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Tici MIPI config (#20205)

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* remove non-default mipi timings and preamble lengths

* actual correct settle count
old-commit-hash: 491309b639
This commit is contained in:
robbederks
2021-03-02 14:10:32 +01:00
committed by GitHub
parent 66e22fe9b3
commit 3ca728b1f4
2 changed files with 5 additions and 11 deletions
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selfdrive/camerad/cameras/camera_qcom2.cc
+3 -2
View File
@@ -29,6 +29,7 @@
//#define FRAME_STRIDE 1936 // for 8 bit output
#define FRAME_STRIDE 2416 // for 10 bit output
#define MIPI_SETTLE_CNT 33 // Calculated by camera_freqs.py
extern ExitHandler do_exit;
@@ -749,8 +750,8 @@ static void camera_open(CameraState *s) {
csiphy_info->combo_mode = 0x0;
csiphy_info->lane_cnt = 0x4;
csiphy_info->secure_mode = 0x0;
csiphy_info->settle_time = 2800000000;
csiphy_info->data_rate = 44000000;
csiphy_info->settle_time = MIPI_SETTLE_CNT * 200000000ULL;
csiphy_info->data_rate = 48000000; // Calculated by camera_freqs.py
static struct cam_config_dev_cmd config_dev_cmd = {};
config_dev_cmd.session_handle = s->session_handle;
selfdrive/camerad/cameras/sensor2_i2c.h
+2 -9
View File
@@ -45,14 +45,12 @@ struct i2c_random_wr_payload init_array_ar0231[] = {
{0x32D4, 0x3702}, // RESERVED_MFR_32D4
{0x32D6, 0x3C04}, // RESERVED_MFR_32D6
{0x32DC, 0x370A}, // RESERVED_MFR_32DC
{0x30B0, 0x0800}, // DIGITAL_TEST
{0x302A, 0x0006}, // VT_PIX_CLK_DIV
{0x302C, 0x0001}, // VT_SYS_CLK_DIV
{0x302E, 0x0002}, // PRE_PLL_CLK_DIV
{0x3030, 0x0028}, // PLL_MULTIPLIER
{0x3036, 0x000A}, // OP_WORD_CLK_DIV
{0x3038, 0x0001}, // OP_SYS_CLK_DIV
{0x30B0, 0x0800}, // DIGITAL_TEST
{0x30A2, 0x0001}, // X_ODD_INC_
{0x30A6, 0x0001}, // Y_ODD_INC_
{0x3040, 0xC000}, // READ_MODE C000
@@ -97,13 +95,8 @@ struct i2c_random_wr_payload init_array_ar0231[] = {
{0x3348, 0x0111}, // MIPI_F2_VDT_VC
{0x334C, 0x0211}, // MIPI_F3_VDT_VC
{0x3350, 0x0311}, // MIPI_F4_VDT_VC
{0x31B0, 0x0049}, // FRAME_PREAMBLE
{0x31B2, 0x0033}, // LINE_PREAMBLE
{0x31B4, 0x2185}, // RESERVED_MFR_31B4
{0x31B6, 0x1146}, // RESERVED_MFR_31B6
{0x31B8, 0x3047}, // RESERVED_MFR_31B8
{0x31BA, 0x0186}, // RESERVED_MFR_31BA
{0x31BC, 0x0805}, // RESERVED_MFR_31BC
{0x31B0, 0x0053}, // FRAME_PREAMBLE
{0x31B2, 0x003B}, // LINE_PREAMBLE
{0x301A, 0x01C}, // RESET_REGISTER
// HDR Settings