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arm64: Potential rollover condition for timer counter

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There is potential rollover condition for CNTVCT and
CNTPCT counters. So on any architecture timer counter
read, if the least significant 32 bits are set,
reread counter.

CRs-Fixed: 1074621
Change-Id: I136a5f0ee04deeb74c03800d591e44fbd9b4dd39
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Biao long <blong@codeaurora.org>
This commit is contained in:
blong
2018-05-25 16:37:37 +08:00
committed by Gerrit - the friendly Code Review server
parent e592971056
commit b01f3d75bb
2 changed files with 19 additions and 1 deletions
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11
arch/arm64/include/asm/arch_timer.h
View File

@@ -148,8 +148,17 @@ static inline u64 arch_counter_get_cntpct(void)
static inline u64 arch_counter_get_cntvct(void)
{
u64 cval;
isb();
return arch_timer_reg_read_stable(cntvct_el0);
#if IS_ENABLED(CONFIG_MSM_TIMER_LEAP)
#define L32_BITS 0x00000000FFFFFFFF
do {
cval = arch_timer_reg_read_stable(cntvct_el0);
} while ((cval & L32_BITS) == L32_BITS);
#else
cval = arch_timer_reg_read_stable(cntvct_el0);
#endif
return cval;
}
static inline int arch_timer_arch_init(void)

9
drivers/clocksource/Kconfig
View File

@@ -331,6 +331,15 @@ config ARM_ARCH_TIMER_VCT_ACCESS
This option enables support for reading the ARM architected timer's
virtual counter in userspace.
config MSM_TIMER_LEAP
bool "ARCH TIMER counter rollover"
default n
depends on ARM_ARCH_TIMER && ARM64
help
This option enables a check for least significant 32 bits of
counter rollover. On every counter read if least significant
32 bits are set, reread counter.
config ARM_GLOBAL_TIMER
bool "Support for the ARM global timer" if COMPILE_TEST
select CLKSRC_OF if OF