mirror of
https://github.com/firestar5683/StarPilot.git
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firestar5683
22a8575199
Keep official openpilot ancestry and dependency licenses. Store resources directly in Git, remove LFS setup requirements, and leave the downloadable big model outside the source tree.
69 lines
2.8 KiB
C
69 lines
2.8 KiB
C
#pragma once
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#include "board/drivers/drivers.h"
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#define CLOCK_SOURCE_PERIOD_MS 50U
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#define CLOCK_SOURCE_PULSE_LEN_MS 2U
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void clock_source_set_timer_params(uint16_t param1, uint16_t param2) {
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// Pulse length of each channel
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register_set(&(TIM1->CCR1), (((param1 & 0xFF00U) >> 8U)*10U), 0xFFFFU);
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register_set(&(TIM1->CCR2), ((param1 & 0x00FFU)*10U), 0xFFFFU);
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register_set(&(TIM8->CCR3), (((param2 & 0xFF00U) >> 8U)*10U), 0xFFFFU);
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// Timer period
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register_set(&(TIM1->ARR), (((param2 & 0x00FFU)*10U) - 1U), 0xFFFFU);
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register_set(&(TIM1->CCR4), ((TIM1->ARR + 1U) / 2U), 0xFFFFU);
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}
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void clock_source_init(bool enable_channel1) {
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// Setup timer
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register_set(&(TIM1->PSC), ((APB2_TIMER_FREQ*100U)-1U), 0xFFFFU); // Tick on 0.1 ms
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register_set(&(TIM1->ARR), ((CLOCK_SOURCE_PERIOD_MS*10U) - 1U), 0xFFFFU); // Period
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register_set(&(TIM1->CCMR1), 0U, 0xFFFFU); // No output on compare
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register_set(&(TIM1->CCER), TIM_CCER_CC1E | TIM_CCER_CC2NE, 0xFFFFU); // Enable compares
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register_set(&(TIM1->CCR1), (CLOCK_SOURCE_PULSE_LEN_MS*10U), 0xFFFFU); // Compare 1 value
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register_set(&(TIM1->CCR2), (CLOCK_SOURCE_PULSE_LEN_MS*10U), 0xFFFFU); // Compare 2 value
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register_set(&(TIM1->CCR4), (CLOCK_SOURCE_PERIOD_MS*5U), 0xFFFFU); // For slave timer
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register_set_bits(&(TIM1->DIER), TIM_DIER_UIE | TIM_DIER_CC1IE); // Enable interrupts
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// No interrupts
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NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);
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NVIC_DisableIRQ(TIM1_CC_IRQn);
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// Set GPIO as timer channels
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if (enable_channel1) {
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set_gpio_alternate(GPIOA, 8, GPIO_AF1_TIM1);
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}
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set_gpio_alternate(GPIOB, 14, GPIO_AF1_TIM1);
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// Set PWM mode
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register_set(&(TIM1->CCMR1), (0b110UL << TIM_CCMR1_OC1M_Pos) | (0b110UL << TIM_CCMR1_OC2M_Pos), 0xFFFFU);
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register_set(&(TIM1->CCMR2), (0b110UL << TIM_CCMR2_OC3M_Pos) | (0b111UL << TIM_CCMR2_OC4M_Pos), 0xFFFFU);
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// Enable output
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register_set(&(TIM1->BDTR), TIM_BDTR_MOE, 0xFFFFU);
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// Sync with slave
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register_set(&(TIM1->SMCR), TIM_SMCR_MSM , 0xFFFFU);
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register_set(&(TIM1->CR2), (0b0111U << TIM_CR2_MMS_Pos), 0xFFFFU);
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register_set(&(TIM8->SMCR), (0b0100U << TIM_SMCR_SMS_Pos) | (0b000U << TIM_SMCR_TS_Pos), 0xFFFFU);
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// Setup slave timer (TIM8)
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register_set(&(TIM8->PSC), TIM1->PSC, 0xFFFFU);
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register_set(&(TIM8->ARR), TIM1->ARR, 0xFFFFU);
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register_set(&(TIM8->CCMR2), (0b110UL << TIM_CCMR2_OC3M_Pos), 0xFFFFU);
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register_set(&(TIM8->CCR3), (CLOCK_SOURCE_PULSE_LEN_MS * 10U), 0xFFFFU);
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register_set(&(TIM8->CCER), TIM_CCER_CC3NE, 0xFFFFU);
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// MOE for TIM8 as well
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register_set(&(TIM8->BDTR), TIM_BDTR_MOE, 0xFFFFU);
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// Set GPIO
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set_gpio_alternate(GPIOB, 15, GPIO_AF3_TIM8);
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// Enable timers
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register_set(&(TIM1->CR1), TIM_CR1_CEN, 0x3FU);
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register_set(&(TIM8->CR1), TIM_CR1_CEN, 0x3FU);
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}
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