Allow Bluetooth DAC estimate settling during silent clock calibration

roadscore/prototype/stream_clock_bridge.py

@@ -25,7 +25,9 @@ class StreamClockBridge:
       if (not all(type(value) in (int,float) and math.isfinite(value) for value in (wall,current,dac))
           or current<=0 or dac<=0 or not -.02<=dac-current<=5):
         raise ValueError('Invalid callback clock sample')
-      if previous is not None and (wall<previous[0] or current<previous[1] or dac<=previous[2]):
+      # DAC timestamps are device-delay estimates and may move a few ms during
+      # Bluetooth queue priming. The offset uses the advancing current clock.
+      if previous is not None and (wall<previous[0] or current<previous[1]):
         raise ValueError('Output callback clock did not advance')
       previous=(wall,current,dac)
       offsets.append(wall-current)

roadscore/prototype/test_stream_clock_bridge.py

@@ -53,5 +53,11 @@ class StreamClockBridgeTests(unittest.TestCase):
     self.assertAlmostEqual(bridge.offset,-400.)
     self.assertAlmostEqual(bridge.dac_wall(501.),101.)
 
+  def test_bluetooth_dac_estimate_can_adjust_during_silent_priming(self):
+    samples=[(100.+i*.015,500.+i*.015,500.+i*.015+.06) for i in range(8)]
+    samples[4]=(samples[4][0],samples[4][1],samples[3][2]-.002235)
+    bridge=StreamClockBridge.from_callbacks(samples)
+    self.assertAlmostEqual(bridge.offset,-400.)
+
 
 if __name__=='__main__':unittest.main()