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85dee83f5d
* amd flash attention cleanups * simpler * params * fix emulator bugs * fix idiv bug * remove that test * more emu fixes
202 lines
8.7 KiB
Python
202 lines
8.7 KiB
Python
"""Tests for VOPD instructions - dual-issue vector operations.
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VOPD executes two operations simultaneously. Key behavior:
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- Both ops read their sources BEFORE either writes (dual-issue semantics)
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- This means if X writes to a register that Y reads, Y sees the OLD value
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- Op X can use ops 0-15 (FMAC, MUL, ADD, MOV, etc.)
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- Op Y can use ops 0-18 (includes ADD_NC_U32, LSHLREV, AND)
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"""
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import unittest
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from test.amd.hw.helpers import run_program, v, v_mov_b32_e32
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from tinygrad.runtime.autogen.amd.rdna3.ins import VOPD, VOPD_LIT, VOPDOp
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class TestVOPDBasic(unittest.TestCase):
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"""Basic VOPD functionality tests."""
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def test_vopd_dual_mov(self):
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"""VOPD with two MOV operations to different registers."""
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instructions = [
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v_mov_b32_e32(v[0], 0x12345678),
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v_mov_b32_e32(v[1], 0xDEADBEEF),
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# X: v[2] = v[0], Y: v[3] = v[1]
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VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_MOV_B32, v[2], v[3], v[0], v[1], v[0], v[0]),
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]
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st = run_program(instructions, n_lanes=1)
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self.assertEqual(st.vgpr[0][2], 0x12345678)
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self.assertEqual(st.vgpr[0][3], 0xDEADBEEF)
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def test_vopd_mov_and_add(self):
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"""VOPD with MOV (X) and ADD_NC_U32 (Y) - ADD_NC_U32 can only be Y op."""
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instructions = [
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v_mov_b32_e32(v[0], 10),
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v_mov_b32_e32(v[1], 5),
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# X: v[2] = 100 (literal), Y: v[3] = v[0] + v[1] = 15
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VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_ADD_NC_U32, v[2], v[3], 100, v[0], v[0], v[1]),
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]
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st = run_program(instructions, n_lanes=1)
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self.assertEqual(st.vgpr[0][2], 100)
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self.assertEqual(st.vgpr[0][3], 15)
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class TestVOPDReadBeforeWrite(unittest.TestCase):
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"""Tests for VOPD dual-issue read-before-write semantics.
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In VOPD, both X and Y operations read their sources BEFORE either writes.
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This is critical when X's destination is Y's source.
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"""
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def test_vopd_x_writes_y_reads_same_reg(self):
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"""VOPD where X writes to a register that Y reads.
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X: v[2] = 0 (overwrites v[2])
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Y: v[1] = v[2] + v[0] (srcy0=v[2], vsrcy1=v[0])
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If reads happen before writes: v[1] = OLD_v[2] + v[0] = 0xFFFFFFFF + 1 = 0
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If writes happen before reads: v[1] = 0 + v[0] = 0 + 1 = 1
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Hardware does reads-before-writes, so v[1] should be 0.
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"""
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instructions = [
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v_mov_b32_e32(v[0], 1), # v[0] = 1
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v_mov_b32_e32(v[1], 0x99999999), # v[1] = placeholder (will be overwritten)
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v_mov_b32_e32(v[2], 0xFFFFFFFF), # v[2] = 0xFFFFFFFF
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# X: v[2] = 0 (literal), srcx0=0, vsrcx1=v[0] (unused for MOV)
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# Y: v[1] = srcy0 + vsrcy1 = v[2] + v[0] (should read OLD v[2] = 0xFFFFFFFF)
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# vdsty encoding: (vdsty << 1) | ((vdstx & 1) ^ 1) where vdsty field = 0, vdstx = v[2]
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# So vdsty_reg = (0 << 1) | ((2 & 1) ^ 1) = 0 | 1 = 1 = v[1]
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VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_ADD_NC_U32, v[2], v[0], 0, v[2], v[0], v[0]),
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]
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st = run_program(instructions, n_lanes=1)
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# X should have written 0 to v[2]
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self.assertEqual(st.vgpr[0][2], 0, "X should write 0 to v[2]")
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# Y should have read OLD v[2] (0xFFFFFFFF) and added v[0] (1)
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# 0xFFFFFFFF + 1 = 0 (wrap around)
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self.assertEqual(st.vgpr[0][1], 0, "Y should read OLD v[2]=0xFFFFFFFF, compute 0xFFFFFFFF+1=0")
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def test_vopd_x_writes_y_reads_same_reg_v2(self):
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"""VOPD where X writes to a register that Y reads - cleaner test case.
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X: v[2] = 0 (MOV)
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Y: v[1] = v[2] + v[2] (ADD_NC_U32 with both sources from v[2])
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If reads happen before writes: v[1] = OLD_v[2] + OLD_v[2] = 100 + 100 = 200
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If writes happen before reads: v[1] = 0 + 0 = 0
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Hardware does reads-before-writes, so v[1] should be 200.
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"""
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instructions = [
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v_mov_b32_e32(v[0], 0x88888888), # v[0] = unused placeholder
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v_mov_b32_e32(v[1], 0x99999999), # v[1] = placeholder (will be overwritten)
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v_mov_b32_e32(v[2], 100), # v[2] = 100
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# X: v[2] = 0 (literal)
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# Y: v[1] = srcy0 + vsrcy1 = v[2] + v[2] (should read OLD v[2] = 100)
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VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_ADD_NC_U32, v[2], v[0], 0, v[2], v[0], v[2]),
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]
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st = run_program(instructions, n_lanes=1)
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# X should have written 0 to v[2]
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self.assertEqual(st.vgpr[0][2], 0, "X should write 0 to v[2]")
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# Y should have read OLD v[2] (100) twice and added them
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self.assertEqual(st.vgpr[0][1], 200, "Y should read OLD v[2]=100 twice, compute 100+100=200")
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class TestVOPDLiterals(unittest.TestCase):
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"""Tests for VOPD instructions that use SIMM32 literals (FMAAK, FMAMK)."""
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def test_vopd_fmaak_f32(self):
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"""VOPD V_DUAL_FMAAK_F32: D = S0 * S1 + SIMM32 (literal addend).
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Tests that the 32-bit literal (SIMM32) is correctly passed to the instruction.
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fma(2.0, 3.0, 10.0) = 2*3 + 10 = 16.0
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"""
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from test.amd.hw.helpers import f2i, i2f
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instructions = [
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v_mov_b32_e32(v[0], f2i(2.0)), # v[0] = 2.0
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v_mov_b32_e32(v[1], f2i(3.0)), # v[1] = 3.0
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# VOPD args: opx, opy, vdstx, vdsty, srcx0, srcy0, vsrcx1, vsrcy1
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# X: v[2] = fma(srcx0, vsrcx1, SIMM32) = v[0]*v[1]+10.0 = 2*3+10 = 16
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# Y: v[3] = srcy0 (MOV) = v[0] = 2.0
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VOPD_LIT(VOPDOp.V_DUAL_FMAAK_F32, VOPDOp.V_DUAL_MOV_B32, v[2], v[3], v[0], v[0], v[1], v[0], literal=f2i(10.0)),
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]
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st = run_program(instructions, n_lanes=1)
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self.assertAlmostEqual(i2f(st.vgpr[0][2]), 16.0, places=5, msg="fma(2.0, 3.0, 10.0) should be 16.0")
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def test_vopd_fmamk_f32(self):
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"""VOPD V_DUAL_FMAMK_F32: D = S0 * SIMM32 + S1 (literal multiplier).
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Tests that the 32-bit literal (SIMM32) is correctly used as the multiplier.
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fma(2.0, 5.0, 3.0) = 2*5 + 3 = 13.0
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"""
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from test.amd.hw.helpers import f2i, i2f
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instructions = [
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v_mov_b32_e32(v[0], f2i(2.0)), # v[0] = 2.0
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v_mov_b32_e32(v[1], f2i(3.0)), # v[1] = 3.0
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# X: v[2] = fma(srcx0, SIMM32, vsrcx1) = v[0]*5.0+v[1] = 2*5+3 = 13
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# Y: v[3] = srcy0 (MOV) = v[0] = 2.0
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VOPD_LIT(VOPDOp.V_DUAL_FMAMK_F32, VOPDOp.V_DUAL_MOV_B32, v[2], v[3], v[0], v[0], v[1], v[0], literal=f2i(5.0)),
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]
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st = run_program(instructions, n_lanes=1)
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self.assertAlmostEqual(i2f(st.vgpr[0][2]), 13.0, places=5, msg="fma(2.0, 5.0, 3.0) should be 13.0")
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class TestVOPDDot2Acc(unittest.TestCase):
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"""Tests for V_DUAL_DOT2ACC_F32_F16 - packed f16 dot product accumulate."""
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def test_vopd_dot2acc_f32_f16_basic(self):
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"""V_DUAL_DOT2ACC_F32_F16: D += lo(S0)*lo(S1) + hi(S0)*hi(S1).
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S0 = pack(1.0h, 2.0h), S1 = pack(3.0h, 4.0h), D = 10.0f
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result = 10.0 + 1.0*3.0 + 2.0*4.0 = 10.0 + 3.0 + 8.0 = 21.0
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"""
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from test.amd.hw.helpers import f2i, i2f, f32_to_f16
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pk_s0 = f32_to_f16(1.0) | (f32_to_f16(2.0) << 16) # lo=1.0h, hi=2.0h
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pk_s1 = f32_to_f16(3.0) | (f32_to_f16(4.0) << 16) # lo=3.0h, hi=4.0h
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instructions = [
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v_mov_b32_e32(v[0], pk_s0),
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v_mov_b32_e32(v[1], pk_s1),
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v_mov_b32_e32(v[3], f2i(10.0)), # accumulator in v[3] (vdsty with vdstx=v[4])
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# X: v[4] = MOV v[0] (don't care), Y: v[3] += dot2(v[0], v[1])
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VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_DOT2ACC_F32_F16, v[4], v[3], v[0], v[0], v[0], v[1]),
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]
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st = run_program(instructions, n_lanes=1)
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self.assertAlmostEqual(i2f(st.vgpr[0][3]), 21.0, places=2, msg="10.0 + 1.0*3.0 + 2.0*4.0 = 21.0")
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def test_vopd_dot2acc_f32_f16_zero_accum(self):
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"""V_DUAL_DOT2ACC_F32_F16 with zero accumulator — pure dot product.
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S0 = pack(0.5h, -1.0h), S1 = pack(2.0h, 3.0h), D = 0.0f
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result = 0.0 + 0.5*2.0 + (-1.0)*3.0 = 1.0 - 3.0 = -2.0
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"""
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from test.amd.hw.helpers import f2i, i2f, f32_to_f16
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pk_s0 = f32_to_f16(0.5) | (f32_to_f16(-1.0) << 16)
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pk_s1 = f32_to_f16(2.0) | (f32_to_f16(3.0) << 16)
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instructions = [
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v_mov_b32_e32(v[0], pk_s0),
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v_mov_b32_e32(v[1], pk_s1),
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v_mov_b32_e32(v[3], f2i(0.0)), # zero accumulator in v[3]
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VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_DOT2ACC_F32_F16, v[4], v[3], v[0], v[0], v[0], v[1]),
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]
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st = run_program(instructions, n_lanes=1)
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self.assertAlmostEqual(i2f(st.vgpr[0][3]), -2.0, places=2, msg="0.5*2.0 + (-1.0)*3.0 = -2.0")
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class TestVOPDMultilane(unittest.TestCase):
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"""Tests for VOPD with multiple lanes."""
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def test_vopd_multilane_mov_add(self):
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"""VOPD MOV and ADD with multiple active lanes - no register conflict."""
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instructions = [
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v_mov_b32_e32(v[0], 5),
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v_mov_b32_e32(v[1], 10),
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# X: v[2] = 100 (constant), Y: v[1] = v[0] + v[1] = 5 + 10 = 15
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# vdsty_reg = (vdsty << 1) | ((vdstx.offset & 1) ^ 1) = (0 << 1) | ((258 & 1) ^ 1) = 0 | 1 = 1
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VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_ADD_NC_U32, v[2], v[0], 100, v[0], v[2], v[1]),
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]
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st = run_program(instructions, n_lanes=4)
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for lane in range(4):
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self.assertEqual(st.vgpr[lane][2], 100, f"Lane {lane}: v[2] should be 100")
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self.assertEqual(st.vgpr[lane][1], 15, f"Lane {lane}: v[1] should be 15 (5+10)")
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if __name__ == '__main__':
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unittest.main()
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