From 993ef42bd55c67f0aa40d867bb59a5e248f53ca3 Mon Sep 17 00:00:00 2001 From: nimlgen <138685161+nimlgen@users.noreply.github.com> Date: Tue, 4 Mar 2025 20:44:09 +0300 Subject: [PATCH] am: hdp cg (#9346) --- autogen_stubs.sh | 6 + extra/amdpci/headers/hdp_6_0_0_offset.h | 209 ++++ extra/amdpci/headers/hdp_6_0_0_sh_mask.h | 646 +++++++++++ tinygrad/runtime/autogen/am/hdp_6_0_0.py | 1319 ++++++++++++++++++++++ tinygrad/runtime/support/am/amdev.py | 6 +- tinygrad/runtime/support/am/ip.py | 2 + 6 files changed, 2186 insertions(+), 2 deletions(-) create mode 100644 extra/amdpci/headers/hdp_6_0_0_offset.h create mode 100644 extra/amdpci/headers/hdp_6_0_0_sh_mask.h create mode 100644 tinygrad/runtime/autogen/am/hdp_6_0_0.py diff --git a/autogen_stubs.sh b/autogen_stubs.sh index 60010312eb..23dee4a756 100755 --- a/autogen_stubs.sh +++ b/autogen_stubs.sh @@ -353,6 +353,12 @@ generate_am() { extra/amdpci/headers/amdgpu_smu.h \ -o $BASE/am/smu_v13_0_0.py fixup $BASE/am/smu_v13_0_0.py + + clang2py -k cdefstum \ + extra/amdpci/headers/hdp_6_0_0_offset.h \ + extra/amdpci/headers/hdp_6_0_0_sh_mask.h \ + -o $BASE/am/hdp_6_0_0.py + fixup $BASE/am/hdp_6_0_0.py } generate_webgpu() { diff --git a/extra/amdpci/headers/hdp_6_0_0_offset.h b/extra/amdpci/headers/hdp_6_0_0_offset.h new file mode 100644 index 0000000000..b2dc63d28b --- /dev/null +++ b/extra/amdpci/headers/hdp_6_0_0_offset.h @@ -0,0 +1,209 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _hdp_6_0_0_OFFSET_HEADER +#define _hdp_6_0_0_OFFSET_HEADER + + + +// addressBlock: hdp_hdpdec +// base address: 0x3c80 +#define regHDP_NONSURFACE_BASE 0x0040 +#define regHDP_NONSURFACE_BASE_BASE_IDX 0 +#define regHDP_NONSURFACE_INFO 0x0041 +#define regHDP_NONSURFACE_INFO_BASE_IDX 0 +#define regHDP_NONSURFACE_BASE_HI 0x0042 +#define regHDP_NONSURFACE_BASE_HI_BASE_IDX 0 +#define regHDP_SURFACE_WRITE_FLAGS 0x00c4 +#define regHDP_SURFACE_WRITE_FLAGS_BASE_IDX 0 +#define regHDP_SURFACE_READ_FLAGS 0x00c5 +#define regHDP_SURFACE_READ_FLAGS_BASE_IDX 0 +#define regHDP_SURFACE_WRITE_FLAGS_CLR 0x00c6 +#define regHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX 0 +#define regHDP_SURFACE_READ_FLAGS_CLR 0x00c7 +#define regHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX 0 +#define regHDP_NONSURF_FLAGS 0x00c8 +#define regHDP_NONSURF_FLAGS_BASE_IDX 0 +#define regHDP_NONSURF_FLAGS_CLR 0x00c9 +#define regHDP_NONSURF_FLAGS_CLR_BASE_IDX 0 +#define regHDP_HOST_PATH_CNTL 0x00cc +#define regHDP_HOST_PATH_CNTL_BASE_IDX 0 +#define regHDP_SW_SEMAPHORE 0x00cd +#define regHDP_SW_SEMAPHORE_BASE_IDX 0 +#define regHDP_DEBUG0 0x00ce +#define regHDP_DEBUG0_BASE_IDX 0 +#define regHDP_LAST_SURFACE_HIT 0x00d0 +#define regHDP_LAST_SURFACE_HIT_BASE_IDX 0 +#define regHDP_OUTSTANDING_REQ 0x00d2 +#define regHDP_OUTSTANDING_REQ_BASE_IDX 0 +#define regHDP_MISC_CNTL 0x00d3 +#define regHDP_MISC_CNTL_BASE_IDX 0 +#define regHDP_MEM_POWER_CTRL 0x00d4 +#define regHDP_MEM_POWER_CTRL_BASE_IDX 0 +#define regHDP_MMHUB_CNTL 0x00d5 +#define regHDP_MMHUB_CNTL_BASE_IDX 0 +#define regHDP_VERSION 0x00d7 +#define regHDP_VERSION_BASE_IDX 0 +#define regHDP_CLK_CNTL 0x00d8 +#define regHDP_CLK_CNTL_BASE_IDX 0 +#define regHDP_MEMIO_CNTL 0x00f6 +#define regHDP_MEMIO_CNTL_BASE_IDX 0 +#define regHDP_MEMIO_ADDR 0x00f7 +#define regHDP_MEMIO_ADDR_BASE_IDX 0 +#define regHDP_MEMIO_STATUS 0x00f8 +#define regHDP_MEMIO_STATUS_BASE_IDX 0 +#define regHDP_MEMIO_WR_DATA 0x00f9 +#define regHDP_MEMIO_WR_DATA_BASE_IDX 0 +#define regHDP_MEMIO_RD_DATA 0x00fa +#define regHDP_MEMIO_RD_DATA_BASE_IDX 0 +#define regHDP_XDP_DIRECT2HDP_FIRST 0x0100 +#define regHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0 +#define regHDP_XDP_D2H_FLUSH 0x0101 +#define regHDP_XDP_D2H_FLUSH_BASE_IDX 0 +#define regHDP_XDP_D2H_BAR_UPDATE 0x0102 +#define regHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_3 0x0103 +#define regHDP_XDP_D2H_RSVD_3_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_4 0x0104 +#define regHDP_XDP_D2H_RSVD_4_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_5 0x0105 +#define regHDP_XDP_D2H_RSVD_5_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_6 0x0106 +#define regHDP_XDP_D2H_RSVD_6_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_7 0x0107 +#define regHDP_XDP_D2H_RSVD_7_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_8 0x0108 +#define regHDP_XDP_D2H_RSVD_8_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_9 0x0109 +#define regHDP_XDP_D2H_RSVD_9_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_10 0x010a +#define regHDP_XDP_D2H_RSVD_10_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_11 0x010b +#define regHDP_XDP_D2H_RSVD_11_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_12 0x010c +#define regHDP_XDP_D2H_RSVD_12_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_13 0x010d +#define regHDP_XDP_D2H_RSVD_13_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_14 0x010e +#define regHDP_XDP_D2H_RSVD_14_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_15 0x010f +#define regHDP_XDP_D2H_RSVD_15_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_16 0x0110 +#define regHDP_XDP_D2H_RSVD_16_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_17 0x0111 +#define regHDP_XDP_D2H_RSVD_17_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_18 0x0112 +#define regHDP_XDP_D2H_RSVD_18_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_19 0x0113 +#define regHDP_XDP_D2H_RSVD_19_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_20 0x0114 +#define regHDP_XDP_D2H_RSVD_20_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_21 0x0115 +#define regHDP_XDP_D2H_RSVD_21_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_22 0x0116 +#define regHDP_XDP_D2H_RSVD_22_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_23 0x0117 +#define regHDP_XDP_D2H_RSVD_23_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_24 0x0118 +#define regHDP_XDP_D2H_RSVD_24_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_25 0x0119 +#define regHDP_XDP_D2H_RSVD_25_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_26 0x011a +#define regHDP_XDP_D2H_RSVD_26_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_27 0x011b +#define regHDP_XDP_D2H_RSVD_27_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_28 0x011c +#define regHDP_XDP_D2H_RSVD_28_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_29 0x011d +#define regHDP_XDP_D2H_RSVD_29_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_30 0x011e +#define regHDP_XDP_D2H_RSVD_30_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_31 0x011f +#define regHDP_XDP_D2H_RSVD_31_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_32 0x0120 +#define regHDP_XDP_D2H_RSVD_32_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_33 0x0121 +#define regHDP_XDP_D2H_RSVD_33_BASE_IDX 0 +#define regHDP_XDP_D2H_RSVD_34 0x0122 +#define regHDP_XDP_D2H_RSVD_34_BASE_IDX 0 +#define regHDP_XDP_DIRECT2HDP_LAST 0x0123 +#define regHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0 +#define regHDP_XDP_P2P_BAR_CFG 0x0124 +#define regHDP_XDP_P2P_BAR_CFG_BASE_IDX 0 +#define regHDP_XDP_P2P_MBX_OFFSET 0x0125 +#define regHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0 +#define regHDP_XDP_P2P_MBX_ADDR0 0x0126 +#define regHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0 +#define regHDP_XDP_P2P_MBX_ADDR1 0x0127 +#define regHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0 +#define regHDP_XDP_P2P_MBX_ADDR2 0x0128 +#define regHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0 +#define regHDP_XDP_P2P_MBX_ADDR3 0x0129 +#define regHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0 +#define regHDP_XDP_P2P_MBX_ADDR4 0x012a +#define regHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0 +#define regHDP_XDP_P2P_MBX_ADDR5 0x012b +#define regHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0 +#define regHDP_XDP_P2P_MBX_ADDR6 0x012c +#define regHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0 +#define regHDP_XDP_HDP_MBX_MC_CFG 0x012d +#define regHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0 +#define regHDP_XDP_HDP_MC_CFG 0x012e +#define regHDP_XDP_HDP_MC_CFG_BASE_IDX 0 +#define regHDP_XDP_HST_CFG 0x012f +#define regHDP_XDP_HST_CFG_BASE_IDX 0 +#define regHDP_XDP_HDP_IPH_CFG 0x0131 +#define regHDP_XDP_HDP_IPH_CFG_BASE_IDX 0 +#define regHDP_XDP_P2P_BAR0 0x0134 +#define regHDP_XDP_P2P_BAR0_BASE_IDX 0 +#define regHDP_XDP_P2P_BAR1 0x0135 +#define regHDP_XDP_P2P_BAR1_BASE_IDX 0 +#define regHDP_XDP_P2P_BAR2 0x0136 +#define regHDP_XDP_P2P_BAR2_BASE_IDX 0 +#define regHDP_XDP_P2P_BAR3 0x0137 +#define regHDP_XDP_P2P_BAR3_BASE_IDX 0 +#define regHDP_XDP_P2P_BAR4 0x0138 +#define regHDP_XDP_P2P_BAR4_BASE_IDX 0 +#define regHDP_XDP_P2P_BAR5 0x0139 +#define regHDP_XDP_P2P_BAR5_BASE_IDX 0 +#define regHDP_XDP_P2P_BAR6 0x013a +#define regHDP_XDP_P2P_BAR6_BASE_IDX 0 +#define regHDP_XDP_P2P_BAR7 0x013b +#define regHDP_XDP_P2P_BAR7_BASE_IDX 0 +#define regHDP_XDP_FLUSH_ARMED_STS 0x013c +#define regHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0 +#define regHDP_XDP_FLUSH_CNTR0_STS 0x013d +#define regHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0 +#define regHDP_XDP_BUSY_STS 0x013e +#define regHDP_XDP_BUSY_STS_BASE_IDX 0 +#define regHDP_XDP_STICKY 0x013f +#define regHDP_XDP_STICKY_BASE_IDX 0 +#define regHDP_XDP_CHKN 0x0140 +#define regHDP_XDP_CHKN_BASE_IDX 0 +#define regHDP_XDP_BARS_ADDR_39_36 0x0144 +#define regHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0 +#define regHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145 +#define regHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0 +#define regHDP_XDP_MMHUB_ERROR 0x014a +#define regHDP_XDP_MMHUB_ERROR_BASE_IDX 0 + +#endif diff --git a/extra/amdpci/headers/hdp_6_0_0_sh_mask.h b/extra/amdpci/headers/hdp_6_0_0_sh_mask.h new file mode 100644 index 0000000000..e1905a114c --- /dev/null +++ b/extra/amdpci/headers/hdp_6_0_0_sh_mask.h @@ -0,0 +1,646 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _hdp_6_0_0_SH_MASK_HEADER +#define _hdp_6_0_0_SH_MASK_HEADER + + +// addressBlock: hdp_hdpdec +//HDP_NONSURFACE_BASE +#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0 +#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL +//HDP_NONSURFACE_INFO +#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4 +#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8 +#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L +#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L +//HDP_NONSURFACE_BASE_HI +#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0 +#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL +//HDP_SURFACE_WRITE_FLAGS +#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT 0x0 +#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT 0x1 +#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK 0x00000001L +#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK 0x00000002L +//HDP_SURFACE_READ_FLAGS +#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT 0x0 +#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT 0x1 +#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK 0x00000001L +#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK 0x00000002L +//HDP_SURFACE_WRITE_FLAGS_CLR +#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT 0x0 +#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT 0x1 +#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK 0x00000001L +#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK 0x00000002L +//HDP_SURFACE_READ_FLAGS_CLR +#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT 0x0 +#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT 0x1 +#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK 0x00000001L +#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK 0x00000002L +//HDP_NONSURF_FLAGS +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L +//HDP_NONSURF_FLAGS_CLR +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L +//HDP_HOST_PATH_CNTL +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L +//HDP_SW_SEMAPHORE +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL +//HDP_DEBUG0 +#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 +#define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL +//HDP_LAST_SURFACE_HIT +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L +//HDP_OUTSTANDING_REQ +#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 +#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 +#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL +#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L +//HDP_MISC_CNTL +#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2 +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 +#define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT 0x8 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb +#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe +#define HDP_MISC_CNTL__NACK_ENABLE__SHIFT 0x13 +#define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT 0x14 +#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 +#define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT 0x16 +#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 +#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e +#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L +#define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK 0x00000100L +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L +#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK 0x0000C000L +#define HDP_MISC_CNTL__NACK_ENABLE_MASK 0x00080000L +#define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE_MASK 0x00100000L +#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L +#define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK 0x00400000L +#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L +#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L +//HDP_MEM_POWER_CTRL +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN__SHIFT 0x0 +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN__SHIFT 0x1 +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN__SHIFT 0x2 +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN__SHIFT 0x3 +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS__SHIFT 0x4 +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10 +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT 0x11 +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT 0x12 +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT 0x13 +#define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14 +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18 +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0x1e +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN_MASK 0x00000001L +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK 0x00000002L +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK 0x00000004L +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK 0x00000008L +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS_MASK 0x00000070L +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L +#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK 0x00040000L +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK 0x00080000L +#define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK 0x00700000L +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY_MASK 0xC0000000L +//HDP_MMHUB_CNTL +#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0 +#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1 +#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2 +#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L +#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L +#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L +//HDP_VERSION +#define HDP_VERSION__MINVER__SHIFT 0x0 +#define HDP_VERSION__MAJVER__SHIFT 0x8 +#define HDP_VERSION__REV__SHIFT 0x10 +#define HDP_VERSION__MINVER_MASK 0x000000FFL +#define HDP_VERSION__MAJVER_MASK 0x0000FF00L +#define HDP_VERSION__REV_MASK 0x00FF0000L +//HDP_CLK_CNTL +#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0 +#define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a +#define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1b +#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c +#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d +#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e +#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f +#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL +#define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L +#define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK 0x08000000L +#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L +#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L +#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L +#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L +//HDP_MEMIO_CNTL +#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 +#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 +#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf +#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 +#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 +#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L +#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L +#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L +#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L +#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L +//HDP_MEMIO_ADDR +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL +//HDP_MEMIO_STATUS +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L +//HDP_MEMIO_WR_DATA +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL +//HDP_MEMIO_RD_DATA +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL +//HDP_XDP_DIRECT2HDP_FIRST +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_FLUSH +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L +//HDP_XDP_D2H_BAR_UPDATE +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L +//HDP_XDP_D2H_RSVD_3 +#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_4 +#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_5 +#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_6 +#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_7 +#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_8 +#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_9 +#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_10 +#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_11 +#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_12 +#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_13 +#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_14 +#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_15 +#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_16 +#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_17 +#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_18 +#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_19 +#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_20 +#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_21 +#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_22 +#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_23 +#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_24 +#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_25 +#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_26 +#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_27 +#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_28 +#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_29 +#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_30 +#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_31 +#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_32 +#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_33 +#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_34 +#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_DIRECT2HDP_LAST +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_P2P_BAR_CFG +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L +//HDP_XDP_P2P_MBX_OFFSET +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL +//HDP_XDP_P2P_MBX_ADDR0 +#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR1 +#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR2 +#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR3 +#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR4 +#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR5 +#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR6 +#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_HDP_MBX_MC_CFG +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L +//HDP_XDP_HDP_MC_CFG +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L +//HDP_XDP_HST_CFG +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 +#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L +#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L +//HDP_XDP_HDP_IPH_CFG +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L +//HDP_XDP_P2P_BAR0 +#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR1 +#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR2 +#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR3 +#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR4 +#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR5 +#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR6 +#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR7 +#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L +//HDP_XDP_FLUSH_ARMED_STS +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL +//HDP_XDP_FLUSH_CNTR0_STS +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL +//HDP_XDP_BUSY_STS +#define HDP_XDP_BUSY_STS__BUSY_BITS_0__SHIFT 0x0 +#define HDP_XDP_BUSY_STS__BUSY_BITS_1__SHIFT 0x1 +#define HDP_XDP_BUSY_STS__BUSY_BITS_2__SHIFT 0x2 +#define HDP_XDP_BUSY_STS__BUSY_BITS_3__SHIFT 0x3 +#define HDP_XDP_BUSY_STS__BUSY_BITS_4__SHIFT 0x4 +#define HDP_XDP_BUSY_STS__BUSY_BITS_5__SHIFT 0x5 +#define HDP_XDP_BUSY_STS__BUSY_BITS_6__SHIFT 0x6 +#define HDP_XDP_BUSY_STS__BUSY_BITS_7__SHIFT 0x7 +#define HDP_XDP_BUSY_STS__BUSY_BITS_8__SHIFT 0x8 +#define HDP_XDP_BUSY_STS__BUSY_BITS_9__SHIFT 0x9 +#define HDP_XDP_BUSY_STS__BUSY_BITS_10__SHIFT 0xa +#define HDP_XDP_BUSY_STS__BUSY_BITS_11__SHIFT 0xb +#define HDP_XDP_BUSY_STS__BUSY_BITS_12__SHIFT 0xc +#define HDP_XDP_BUSY_STS__BUSY_BITS_13__SHIFT 0xd +#define HDP_XDP_BUSY_STS__BUSY_BITS_14__SHIFT 0xe +#define HDP_XDP_BUSY_STS__BUSY_BITS_15__SHIFT 0xf +#define HDP_XDP_BUSY_STS__BUSY_BITS_16__SHIFT 0x10 +#define HDP_XDP_BUSY_STS__BUSY_BITS_17__SHIFT 0x11 +#define HDP_XDP_BUSY_STS__BUSY_BITS_18__SHIFT 0x12 +#define HDP_XDP_BUSY_STS__BUSY_BITS_19__SHIFT 0x13 +#define HDP_XDP_BUSY_STS__BUSY_BITS_20__SHIFT 0x14 +#define HDP_XDP_BUSY_STS__BUSY_BITS_21__SHIFT 0x15 +#define HDP_XDP_BUSY_STS__BUSY_BITS_22__SHIFT 0x16 +#define HDP_XDP_BUSY_STS__BUSY_BITS_23__SHIFT 0x17 +#define HDP_XDP_BUSY_STS__Z_FENCE_BIT__SHIFT 0x18 +#define HDP_XDP_BUSY_STS__BUSY_BITS_0_MASK 0x00000001L +#define HDP_XDP_BUSY_STS__BUSY_BITS_1_MASK 0x00000002L +#define HDP_XDP_BUSY_STS__BUSY_BITS_2_MASK 0x00000004L +#define HDP_XDP_BUSY_STS__BUSY_BITS_3_MASK 0x00000008L +#define HDP_XDP_BUSY_STS__BUSY_BITS_4_MASK 0x00000010L +#define HDP_XDP_BUSY_STS__BUSY_BITS_5_MASK 0x00000020L +#define HDP_XDP_BUSY_STS__BUSY_BITS_6_MASK 0x00000040L +#define HDP_XDP_BUSY_STS__BUSY_BITS_7_MASK 0x00000080L +#define HDP_XDP_BUSY_STS__BUSY_BITS_8_MASK 0x00000100L +#define HDP_XDP_BUSY_STS__BUSY_BITS_9_MASK 0x00000200L +#define HDP_XDP_BUSY_STS__BUSY_BITS_10_MASK 0x00000400L +#define HDP_XDP_BUSY_STS__BUSY_BITS_11_MASK 0x00000800L +#define HDP_XDP_BUSY_STS__BUSY_BITS_12_MASK 0x00001000L +#define HDP_XDP_BUSY_STS__BUSY_BITS_13_MASK 0x00002000L +#define HDP_XDP_BUSY_STS__BUSY_BITS_14_MASK 0x00004000L +#define HDP_XDP_BUSY_STS__BUSY_BITS_15_MASK 0x00008000L +#define HDP_XDP_BUSY_STS__BUSY_BITS_16_MASK 0x00010000L +#define HDP_XDP_BUSY_STS__BUSY_BITS_17_MASK 0x00020000L +#define HDP_XDP_BUSY_STS__BUSY_BITS_18_MASK 0x00040000L +#define HDP_XDP_BUSY_STS__BUSY_BITS_19_MASK 0x00080000L +#define HDP_XDP_BUSY_STS__BUSY_BITS_20_MASK 0x00100000L +#define HDP_XDP_BUSY_STS__BUSY_BITS_21_MASK 0x00200000L +#define HDP_XDP_BUSY_STS__BUSY_BITS_22_MASK 0x00400000L +#define HDP_XDP_BUSY_STS__BUSY_BITS_23_MASK 0x00800000L +#define HDP_XDP_BUSY_STS__Z_FENCE_BIT_MASK 0x01000000L +//HDP_XDP_STICKY +#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 +#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 +#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL +#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L +//HDP_XDP_CHKN +#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 +#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 +#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 +#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 +#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL +#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L +#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L +#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L +//HDP_XDP_BARS_ADDR_39_36 +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L +//HDP_XDP_MC_VM_FB_LOCATION_BASE +#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL +//HDP_XDP_MMHUB_ERROR +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1 +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2 +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3 +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED__SHIFT 0x4 +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5 +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6 +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7 +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9 +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED__SHIFT 0xc +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11 +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12 +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13 +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15 +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16 +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17 +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED_MASK 0x00000010L +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED_MASK 0x00001000L +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L + +#endif diff --git a/tinygrad/runtime/autogen/am/hdp_6_0_0.py b/tinygrad/runtime/autogen/am/hdp_6_0_0.py new file mode 100644 index 0000000000..42d4d53214 --- /dev/null +++ b/tinygrad/runtime/autogen/am/hdp_6_0_0.py @@ -0,0 +1,1319 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_hdp_6_0_0_OFFSET_HEADER = True # macro +regHDP_NONSURFACE_BASE = 0x0040 # macro +regHDP_NONSURFACE_BASE_BASE_IDX = 0 # macro +regHDP_NONSURFACE_INFO = 0x0041 # macro +regHDP_NONSURFACE_INFO_BASE_IDX = 0 # macro +regHDP_NONSURFACE_BASE_HI = 0x0042 # macro +regHDP_NONSURFACE_BASE_HI_BASE_IDX = 0 # macro +regHDP_SURFACE_WRITE_FLAGS = 0x00c4 # macro +regHDP_SURFACE_WRITE_FLAGS_BASE_IDX = 0 # macro +regHDP_SURFACE_READ_FLAGS = 0x00c5 # macro +regHDP_SURFACE_READ_FLAGS_BASE_IDX = 0 # macro +regHDP_SURFACE_WRITE_FLAGS_CLR = 0x00c6 # macro +regHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX = 0 # macro +regHDP_SURFACE_READ_FLAGS_CLR = 0x00c7 # macro +regHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX = 0 # macro +regHDP_NONSURF_FLAGS = 0x00c8 # macro +regHDP_NONSURF_FLAGS_BASE_IDX = 0 # macro +regHDP_NONSURF_FLAGS_CLR = 0x00c9 # macro +regHDP_NONSURF_FLAGS_CLR_BASE_IDX = 0 # macro +regHDP_HOST_PATH_CNTL = 0x00cc # macro +regHDP_HOST_PATH_CNTL_BASE_IDX = 0 # macro +regHDP_SW_SEMAPHORE = 0x00cd # macro +regHDP_SW_SEMAPHORE_BASE_IDX = 0 # macro +regHDP_DEBUG0 = 0x00ce # macro +regHDP_DEBUG0_BASE_IDX = 0 # macro +regHDP_LAST_SURFACE_HIT = 0x00d0 # macro +regHDP_LAST_SURFACE_HIT_BASE_IDX = 0 # macro +regHDP_OUTSTANDING_REQ = 0x00d2 # macro +regHDP_OUTSTANDING_REQ_BASE_IDX = 0 # macro +regHDP_MISC_CNTL = 0x00d3 # macro +regHDP_MISC_CNTL_BASE_IDX = 0 # macro +regHDP_MEM_POWER_CTRL = 0x00d4 # macro +regHDP_MEM_POWER_CTRL_BASE_IDX = 0 # macro +regHDP_MMHUB_CNTL = 0x00d5 # macro +regHDP_MMHUB_CNTL_BASE_IDX = 0 # macro +regHDP_VERSION = 0x00d7 # macro +regHDP_VERSION_BASE_IDX = 0 # macro +regHDP_CLK_CNTL = 0x00d8 # macro +regHDP_CLK_CNTL_BASE_IDX = 0 # macro +regHDP_MEMIO_CNTL = 0x00f6 # macro +regHDP_MEMIO_CNTL_BASE_IDX = 0 # macro +regHDP_MEMIO_ADDR = 0x00f7 # macro +regHDP_MEMIO_ADDR_BASE_IDX = 0 # macro +regHDP_MEMIO_STATUS = 0x00f8 # macro +regHDP_MEMIO_STATUS_BASE_IDX = 0 # macro +regHDP_MEMIO_WR_DATA = 0x00f9 # macro +regHDP_MEMIO_WR_DATA_BASE_IDX = 0 # macro +regHDP_MEMIO_RD_DATA = 0x00fa # macro +regHDP_MEMIO_RD_DATA_BASE_IDX = 0 # macro +regHDP_XDP_DIRECT2HDP_FIRST = 0x0100 # macro +regHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX = 0 # macro +regHDP_XDP_D2H_FLUSH = 0x0101 # macro +regHDP_XDP_D2H_FLUSH_BASE_IDX = 0 # macro +regHDP_XDP_D2H_BAR_UPDATE = 0x0102 # macro +regHDP_XDP_D2H_BAR_UPDATE_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_3 = 0x0103 # macro +regHDP_XDP_D2H_RSVD_3_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_4 = 0x0104 # macro +regHDP_XDP_D2H_RSVD_4_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_5 = 0x0105 # macro +regHDP_XDP_D2H_RSVD_5_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_6 = 0x0106 # macro +regHDP_XDP_D2H_RSVD_6_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_7 = 0x0107 # macro +regHDP_XDP_D2H_RSVD_7_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_8 = 0x0108 # macro +regHDP_XDP_D2H_RSVD_8_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_9 = 0x0109 # macro +regHDP_XDP_D2H_RSVD_9_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_10 = 0x010a # macro +regHDP_XDP_D2H_RSVD_10_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_11 = 0x010b # macro +regHDP_XDP_D2H_RSVD_11_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_12 = 0x010c # macro +regHDP_XDP_D2H_RSVD_12_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_13 = 0x010d # macro +regHDP_XDP_D2H_RSVD_13_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_14 = 0x010e # macro +regHDP_XDP_D2H_RSVD_14_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_15 = 0x010f # macro +regHDP_XDP_D2H_RSVD_15_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_16 = 0x0110 # macro +regHDP_XDP_D2H_RSVD_16_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_17 = 0x0111 # macro +regHDP_XDP_D2H_RSVD_17_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_18 = 0x0112 # macro +regHDP_XDP_D2H_RSVD_18_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_19 = 0x0113 # macro +regHDP_XDP_D2H_RSVD_19_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_20 = 0x0114 # macro +regHDP_XDP_D2H_RSVD_20_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_21 = 0x0115 # macro +regHDP_XDP_D2H_RSVD_21_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_22 = 0x0116 # macro +regHDP_XDP_D2H_RSVD_22_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_23 = 0x0117 # macro +regHDP_XDP_D2H_RSVD_23_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_24 = 0x0118 # macro +regHDP_XDP_D2H_RSVD_24_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_25 = 0x0119 # macro +regHDP_XDP_D2H_RSVD_25_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_26 = 0x011a # macro +regHDP_XDP_D2H_RSVD_26_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_27 = 0x011b # macro +regHDP_XDP_D2H_RSVD_27_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_28 = 0x011c # macro +regHDP_XDP_D2H_RSVD_28_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_29 = 0x011d # macro +regHDP_XDP_D2H_RSVD_29_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_30 = 0x011e # macro +regHDP_XDP_D2H_RSVD_30_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_31 = 0x011f # macro +regHDP_XDP_D2H_RSVD_31_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_32 = 0x0120 # macro +regHDP_XDP_D2H_RSVD_32_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_33 = 0x0121 # macro +regHDP_XDP_D2H_RSVD_33_BASE_IDX = 0 # macro +regHDP_XDP_D2H_RSVD_34 = 0x0122 # macro +regHDP_XDP_D2H_RSVD_34_BASE_IDX = 0 # macro +regHDP_XDP_DIRECT2HDP_LAST = 0x0123 # macro +regHDP_XDP_DIRECT2HDP_LAST_BASE_IDX = 0 # macro +regHDP_XDP_P2P_BAR_CFG = 0x0124 # macro +regHDP_XDP_P2P_BAR_CFG_BASE_IDX = 0 # macro +regHDP_XDP_P2P_MBX_OFFSET = 0x0125 # macro +regHDP_XDP_P2P_MBX_OFFSET_BASE_IDX = 0 # macro +regHDP_XDP_P2P_MBX_ADDR0 = 0x0126 # macro +regHDP_XDP_P2P_MBX_ADDR0_BASE_IDX = 0 # macro +regHDP_XDP_P2P_MBX_ADDR1 = 0x0127 # macro +regHDP_XDP_P2P_MBX_ADDR1_BASE_IDX = 0 # macro +regHDP_XDP_P2P_MBX_ADDR2 = 0x0128 # macro +regHDP_XDP_P2P_MBX_ADDR2_BASE_IDX = 0 # macro +regHDP_XDP_P2P_MBX_ADDR3 = 0x0129 # macro +regHDP_XDP_P2P_MBX_ADDR3_BASE_IDX = 0 # macro +regHDP_XDP_P2P_MBX_ADDR4 = 0x012a # macro +regHDP_XDP_P2P_MBX_ADDR4_BASE_IDX = 0 # macro +regHDP_XDP_P2P_MBX_ADDR5 = 0x012b # macro +regHDP_XDP_P2P_MBX_ADDR5_BASE_IDX = 0 # macro +regHDP_XDP_P2P_MBX_ADDR6 = 0x012c # macro +regHDP_XDP_P2P_MBX_ADDR6_BASE_IDX = 0 # macro +regHDP_XDP_HDP_MBX_MC_CFG = 0x012d # macro +regHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX = 0 # macro +regHDP_XDP_HDP_MC_CFG = 0x012e # macro +regHDP_XDP_HDP_MC_CFG_BASE_IDX = 0 # macro +regHDP_XDP_HST_CFG = 0x012f # macro +regHDP_XDP_HST_CFG_BASE_IDX = 0 # macro +regHDP_XDP_HDP_IPH_CFG = 0x0131 # macro +regHDP_XDP_HDP_IPH_CFG_BASE_IDX = 0 # macro +regHDP_XDP_P2P_BAR0 = 0x0134 # macro +regHDP_XDP_P2P_BAR0_BASE_IDX = 0 # macro +regHDP_XDP_P2P_BAR1 = 0x0135 # macro +regHDP_XDP_P2P_BAR1_BASE_IDX = 0 # macro +regHDP_XDP_P2P_BAR2 = 0x0136 # macro +regHDP_XDP_P2P_BAR2_BASE_IDX = 0 # macro +regHDP_XDP_P2P_BAR3 = 0x0137 # macro +regHDP_XDP_P2P_BAR3_BASE_IDX = 0 # macro +regHDP_XDP_P2P_BAR4 = 0x0138 # macro +regHDP_XDP_P2P_BAR4_BASE_IDX = 0 # macro +regHDP_XDP_P2P_BAR5 = 0x0139 # macro +regHDP_XDP_P2P_BAR5_BASE_IDX = 0 # macro +regHDP_XDP_P2P_BAR6 = 0x013a # macro +regHDP_XDP_P2P_BAR6_BASE_IDX = 0 # macro +regHDP_XDP_P2P_BAR7 = 0x013b # macro +regHDP_XDP_P2P_BAR7_BASE_IDX = 0 # macro +regHDP_XDP_FLUSH_ARMED_STS = 0x013c # macro +regHDP_XDP_FLUSH_ARMED_STS_BASE_IDX = 0 # macro +regHDP_XDP_FLUSH_CNTR0_STS = 0x013d # macro +regHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX = 0 # macro +regHDP_XDP_BUSY_STS = 0x013e # macro +regHDP_XDP_BUSY_STS_BASE_IDX = 0 # macro +regHDP_XDP_STICKY = 0x013f # macro +regHDP_XDP_STICKY_BASE_IDX = 0 # macro +regHDP_XDP_CHKN = 0x0140 # macro +regHDP_XDP_CHKN_BASE_IDX = 0 # macro +regHDP_XDP_BARS_ADDR_39_36 = 0x0144 # macro +regHDP_XDP_BARS_ADDR_39_36_BASE_IDX = 0 # macro +regHDP_XDP_MC_VM_FB_LOCATION_BASE = 0x0145 # macro +regHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX = 0 # macro +regHDP_XDP_MMHUB_ERROR = 0x014a # macro +regHDP_XDP_MMHUB_ERROR_BASE_IDX = 0 # macro +_hdp_6_0_0_SH_MASK_HEADER = True # macro +HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT = 0x0 # macro +HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK = 0xFFFFFFFF # macro +HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT = 0x4 # macro +HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT = 0x8 # macro +HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK = 0x00000030 # macro +HDP_NONSURFACE_INFO__NONSURF_VMID_MASK = 0x00000F00 # macro +HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT = 0x0 # macro +HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK = 0x000000FF # macro +HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT = 0x0 # macro +HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT = 0x1 # macro +HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK = 0x00000001 # macro +HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK = 0x00000002 # macro +HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT = 0x0 # macro +HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT = 0x1 # macro +HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK = 0x00000001 # macro +HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK = 0x00000002 # macro +HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT = 0x0 # macro +HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT = 0x1 # macro +HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK = 0x00000001 # macro +HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK = 0x00000002 # macro +HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT = 0x0 # macro +HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT = 0x1 # macro +HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK = 0x00000001 # macro +HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK = 0x00000002 # macro +HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT = 0x0 # macro +HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT = 0x1 # macro +HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK = 0x00000001 # macro +HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK = 0x00000002 # macro +HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT = 0x0 # macro +HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT = 0x1 # macro +HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK = 0x00000001 # macro +HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK = 0x00000002 # macro +HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT = 0x9 # macro +HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT = 0xb # macro +HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT = 0x12 # macro +HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT = 0x13 # macro +HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT = 0x15 # macro +HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT = 0x16 # macro +HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT = 0x1d # macro +HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK = 0x00000600 # macro +HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK = 0x00001800 # macro +HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK = 0x00040000 # macro +HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK = 0x00180000 # macro +HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK = 0x00200000 # macro +HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK = 0x00400000 # macro +HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK = 0x20000000 # macro +HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT = 0x0 # macro +HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK = 0xFFFFFFFF # macro +HDP_DEBUG0__HDP_DEBUG__SHIFT = 0x0 # macro +HDP_DEBUG0__HDP_DEBUG_MASK = 0xFFFFFFFF # macro +HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT = 0x0 # macro +HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK = 0x00000003 # macro +HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT = 0x0 # macro +HDP_OUTSTANDING_REQ__READ_REQ__SHIFT = 0x8 # macro +HDP_OUTSTANDING_REQ__WRITE_REQ_MASK = 0x000000FF # macro +HDP_OUTSTANDING_REQ__READ_REQ_MASK = 0x0000FF00 # macro +HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT = 0x2 # macro +HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT = 0x5 # macro +HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT = 0x8 # macro +HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT = 0xb # macro +HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT = 0xe # macro +HDP_MISC_CNTL__NACK_ENABLE__SHIFT = 0x13 # macro +HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT = 0x14 # macro +HDP_MISC_CNTL__FED_ENABLE__SHIFT = 0x15 # macro +HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT = 0x16 # macro +HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT = 0x18 # macro +HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT = 0x1e # macro +HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK = 0x0000000C # macro +HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK = 0x00000020 # macro +HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK = 0x00000100 # macro +HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK = 0x00000800 # macro +HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK = 0x0000C000 # macro +HDP_MISC_CNTL__NACK_ENABLE_MASK = 0x00080000 # macro +HDP_MISC_CNTL__ATOMIC_NACK_ENABLE_MASK = 0x00100000 # macro +HDP_MISC_CNTL__FED_ENABLE_MASK = 0x00200000 # macro +HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK = 0x00400000 # macro +HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK = 0x01000000 # macro +HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK = 0x40000000 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN__SHIFT = 0x0 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN__SHIFT = 0x1 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN__SHIFT = 0x2 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN__SHIFT = 0x3 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS__SHIFT = 0x4 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY__SHIFT = 0x8 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT = 0xe # macro +HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT = 0x10 # macro +HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT = 0x11 # macro +HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT = 0x12 # macro +HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT = 0x13 # macro +HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT = 0x14 # macro +HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT = 0x18 # macro +HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT = 0x1e # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN_MASK = 0x00000001 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK = 0x00000002 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK = 0x00000004 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK = 0x00000008 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS_MASK = 0x00000070 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY_MASK = 0x00003F00 # macro +HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY_MASK = 0x0000C000 # macro +HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK = 0x00010000 # macro +HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK = 0x00020000 # macro +HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK = 0x00040000 # macro +HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK = 0x00080000 # macro +HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK = 0x00700000 # macro +HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK = 0x3F000000 # macro +HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY_MASK = 0xC0000000 # macro +HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT = 0x0 # macro +HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT = 0x1 # macro +HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT = 0x2 # macro +HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK = 0x00000001 # macro +HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK = 0x00000002 # macro +HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK = 0x00000004 # macro +HDP_VERSION__MINVER__SHIFT = 0x0 # macro +HDP_VERSION__MAJVER__SHIFT = 0x8 # macro +HDP_VERSION__REV__SHIFT = 0x10 # macro +HDP_VERSION__MINVER_MASK = 0x000000FF # macro +HDP_VERSION__MAJVER_MASK = 0x0000FF00 # macro +HDP_VERSION__REV_MASK = 0x00FF0000 # macro +HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT = 0x0 # macro +HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE__SHIFT = 0x1a # macro +HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT = 0x1b # macro +HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT = 0x1c # macro +HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT = 0x1d # macro +HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT = 0x1e # macro +HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT = 0x1f # macro +HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK = 0x0000000F # macro +HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK = 0x04000000 # macro +HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK = 0x08000000 # macro +HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK = 0x10000000 # macro +HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK = 0x20000000 # macro +HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK = 0x40000000 # macro +HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK = 0x80000000 # macro +HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT = 0x0 # macro +HDP_MEMIO_CNTL__MEMIO_OP__SHIFT = 0x1 # macro +HDP_MEMIO_CNTL__MEMIO_BE__SHIFT = 0x2 # macro +HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT = 0x6 # macro +HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT = 0x7 # macro +HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT = 0x8 # macro +HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT = 0xe # macro +HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT = 0xf # macro +HDP_MEMIO_CNTL__MEMIO_VF__SHIFT = 0x10 # macro +HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT = 0x11 # macro +HDP_MEMIO_CNTL__MEMIO_SEND_MASK = 0x00000001 # macro +HDP_MEMIO_CNTL__MEMIO_OP_MASK = 0x00000002 # macro +HDP_MEMIO_CNTL__MEMIO_BE_MASK = 0x0000003C # macro +HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK = 0x00000040 # macro +HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK = 0x00000080 # macro +HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK = 0x00003F00 # macro +HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK = 0x00004000 # macro +HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK = 0x00008000 # macro +HDP_MEMIO_CNTL__MEMIO_VF_MASK = 0x00010000 # macro +HDP_MEMIO_CNTL__MEMIO_VFID_MASK = 0x003E0000 # macro +HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT = 0x0 # macro +HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK = 0xFFFFFFFF # macro +HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT = 0x0 # macro +HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT = 0x1 # macro +HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT = 0x2 # macro +HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT = 0x3 # macro +HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK = 0x00000001 # macro +HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK = 0x00000002 # macro +HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK = 0x00000004 # macro +HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK = 0x00000008 # macro +HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT = 0x0 # macro +HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK = 0xFFFFFFFF # macro +HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT = 0x0 # macro +HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK = 0xFFFFFFFF # macro +HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT = 0x0 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT = 0x4 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT = 0x8 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT = 0xb # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT = 0x10 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT = 0x12 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT = 0x13 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT = 0x14 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK = 0x0000000F # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK = 0x000000F0 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK = 0x00000700 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK = 0x0000F800 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK = 0x00010000 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK = 0x00040000 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK = 0x00080000 # macro +HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK = 0x00100000 # macro +HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT = 0x0 # macro +HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT = 0x10 # macro +HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT = 0x14 # macro +HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK = 0x0000FFFF # macro +HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK = 0x000F0000 # macro +HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK = 0x00700000 # macro +HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_3__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_4__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_5__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_6__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_7__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_8__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_9__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_10__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_11__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_12__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_13__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_14__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_15__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_16__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_17__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_18__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_19__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_20__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_21__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_22__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_23__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_24__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_25__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_26__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_27__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_28__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_29__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_30__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_31__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_32__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_33__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_D2H_RSVD_34__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT = 0x0 # macro +HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK = 0xFFFFFFFF # macro +HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT = 0x0 # macro +HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT = 0x4 # macro +HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK = 0x0000000F # macro +HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK = 0x00000030 # macro +HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT = 0x0 # macro +HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK = 0x0001FFFF # macro +HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT = 0x0 # macro +HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT = 0x3 # macro +HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT = 0x14 # macro +HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT = 0x18 # macro +HDP_XDP_P2P_MBX_ADDR0__VALID_MASK = 0x00000001 # macro +HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK = 0x000FFFF8 # macro +HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK = 0x00F00000 # macro +HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK = 0xFF000000 # macro +HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT = 0x0 # macro +HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT = 0x3 # macro +HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT = 0x14 # macro +HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT = 0x18 # macro +HDP_XDP_P2P_MBX_ADDR1__VALID_MASK = 0x00000001 # macro +HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK = 0x000FFFF8 # macro +HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK = 0x00F00000 # macro +HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK = 0xFF000000 # macro +HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT = 0x0 # macro +HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT = 0x3 # macro +HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT = 0x14 # macro +HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT = 0x18 # macro +HDP_XDP_P2P_MBX_ADDR2__VALID_MASK = 0x00000001 # macro +HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK = 0x000FFFF8 # macro +HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK = 0x00F00000 # macro +HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK = 0xFF000000 # macro +HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT = 0x0 # macro +HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT = 0x3 # macro +HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT = 0x14 # macro +HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT = 0x18 # macro +HDP_XDP_P2P_MBX_ADDR3__VALID_MASK = 0x00000001 # macro +HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK = 0x000FFFF8 # macro +HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK = 0x00F00000 # macro +HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK = 0xFF000000 # macro +HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT = 0x0 # macro +HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT = 0x3 # macro +HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT = 0x14 # macro +HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT = 0x18 # macro +HDP_XDP_P2P_MBX_ADDR4__VALID_MASK = 0x00000001 # macro +HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK = 0x000FFFF8 # macro +HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK = 0x00F00000 # macro +HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK = 0xFF000000 # macro +HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT = 0x0 # macro +HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT = 0x3 # macro +HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT = 0x14 # macro +HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT = 0x18 # macro +HDP_XDP_P2P_MBX_ADDR5__VALID_MASK = 0x00000001 # macro +HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK = 0x000FFFF8 # macro +HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK = 0x00F00000 # macro +HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK = 0xFF000000 # macro +HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT = 0x0 # macro +HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT = 0x3 # macro +HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT = 0x14 # macro +HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT = 0x18 # macro +HDP_XDP_P2P_MBX_ADDR6__VALID_MASK = 0x00000001 # macro +HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK = 0x000FFFF8 # macro +HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK = 0x00F00000 # macro +HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK = 0xFF000000 # macro +HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT = 0x0 # macro +HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT = 0x4 # macro +HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT = 0x8 # macro +HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT = 0xc # macro +HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT = 0xd # macro +HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT = 0xe # macro +HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK = 0x0000000F # macro +HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK = 0x00000030 # macro +HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK = 0x00000F00 # macro +HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK = 0x00001000 # macro +HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK = 0x00002000 # macro +HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK = 0x00004000 # macro +HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT = 0x3 # macro +HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT = 0x4 # macro +HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT = 0x8 # macro +HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT = 0xc # macro +HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT = 0xd # macro +HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT = 0xe # macro +HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK = 0x00000008 # macro +HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK = 0x00000030 # macro +HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK = 0x00000F00 # macro +HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK = 0x00001000 # macro +HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK = 0x00002000 # macro +HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK = 0x000FC000 # macro +HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT = 0x0 # macro +HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT = 0x1 # macro +HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT = 0x3 # macro +HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT = 0x4 # macro +HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT = 0x5 # macro +HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK = 0x00000001 # macro +HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK = 0x00000006 # macro +HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK = 0x00000008 # macro +HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK = 0x00000010 # macro +HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK = 0x00000020 # macro +HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT = 0xc # macro +HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT = 0xd # macro +HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK = 0x00001000 # macro +HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK = 0x00002000 # macro +HDP_XDP_P2P_BAR0__ADDR__SHIFT = 0x0 # macro +HDP_XDP_P2P_BAR0__FLUSH__SHIFT = 0x10 # macro +HDP_XDP_P2P_BAR0__VALID__SHIFT = 0x14 # macro +HDP_XDP_P2P_BAR0__ADDR_MASK = 0x0000FFFF # macro +HDP_XDP_P2P_BAR0__FLUSH_MASK = 0x000F0000 # macro +HDP_XDP_P2P_BAR0__VALID_MASK = 0x00100000 # macro +HDP_XDP_P2P_BAR1__ADDR__SHIFT = 0x0 # macro +HDP_XDP_P2P_BAR1__FLUSH__SHIFT = 0x10 # macro +HDP_XDP_P2P_BAR1__VALID__SHIFT = 0x14 # macro +HDP_XDP_P2P_BAR1__ADDR_MASK = 0x0000FFFF # macro +HDP_XDP_P2P_BAR1__FLUSH_MASK = 0x000F0000 # macro +HDP_XDP_P2P_BAR1__VALID_MASK = 0x00100000 # macro +HDP_XDP_P2P_BAR2__ADDR__SHIFT = 0x0 # macro +HDP_XDP_P2P_BAR2__FLUSH__SHIFT = 0x10 # macro +HDP_XDP_P2P_BAR2__VALID__SHIFT = 0x14 # macro +HDP_XDP_P2P_BAR2__ADDR_MASK = 0x0000FFFF # macro +HDP_XDP_P2P_BAR2__FLUSH_MASK = 0x000F0000 # macro +HDP_XDP_P2P_BAR2__VALID_MASK = 0x00100000 # macro +HDP_XDP_P2P_BAR3__ADDR__SHIFT = 0x0 # macro +HDP_XDP_P2P_BAR3__FLUSH__SHIFT = 0x10 # macro +HDP_XDP_P2P_BAR3__VALID__SHIFT = 0x14 # macro +HDP_XDP_P2P_BAR3__ADDR_MASK = 0x0000FFFF # macro +HDP_XDP_P2P_BAR3__FLUSH_MASK = 0x000F0000 # macro +HDP_XDP_P2P_BAR3__VALID_MASK = 0x00100000 # macro +HDP_XDP_P2P_BAR4__ADDR__SHIFT = 0x0 # macro +HDP_XDP_P2P_BAR4__FLUSH__SHIFT = 0x10 # macro +HDP_XDP_P2P_BAR4__VALID__SHIFT = 0x14 # macro +HDP_XDP_P2P_BAR4__ADDR_MASK = 0x0000FFFF # macro +HDP_XDP_P2P_BAR4__FLUSH_MASK = 0x000F0000 # macro +HDP_XDP_P2P_BAR4__VALID_MASK = 0x00100000 # macro +HDP_XDP_P2P_BAR5__ADDR__SHIFT = 0x0 # macro +HDP_XDP_P2P_BAR5__FLUSH__SHIFT = 0x10 # macro +HDP_XDP_P2P_BAR5__VALID__SHIFT = 0x14 # macro +HDP_XDP_P2P_BAR5__ADDR_MASK = 0x0000FFFF # macro +HDP_XDP_P2P_BAR5__FLUSH_MASK = 0x000F0000 # macro +HDP_XDP_P2P_BAR5__VALID_MASK = 0x00100000 # macro +HDP_XDP_P2P_BAR6__ADDR__SHIFT = 0x0 # macro +HDP_XDP_P2P_BAR6__FLUSH__SHIFT = 0x10 # macro +HDP_XDP_P2P_BAR6__VALID__SHIFT = 0x14 # macro +HDP_XDP_P2P_BAR6__ADDR_MASK = 0x0000FFFF # macro +HDP_XDP_P2P_BAR6__FLUSH_MASK = 0x000F0000 # macro +HDP_XDP_P2P_BAR6__VALID_MASK = 0x00100000 # macro +HDP_XDP_P2P_BAR7__ADDR__SHIFT = 0x0 # macro +HDP_XDP_P2P_BAR7__FLUSH__SHIFT = 0x10 # macro +HDP_XDP_P2P_BAR7__VALID__SHIFT = 0x14 # macro +HDP_XDP_P2P_BAR7__ADDR_MASK = 0x0000FFFF # macro +HDP_XDP_P2P_BAR7__FLUSH_MASK = 0x000F0000 # macro +HDP_XDP_P2P_BAR7__VALID_MASK = 0x00100000 # macro +HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT = 0x0 # macro +HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK = 0xFFFFFFFF # macro +HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT = 0x0 # macro +HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK = 0x03FFFFFF # macro +HDP_XDP_BUSY_STS__BUSY_BITS_0__SHIFT = 0x0 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_1__SHIFT = 0x1 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_2__SHIFT = 0x2 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_3__SHIFT = 0x3 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_4__SHIFT = 0x4 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_5__SHIFT = 0x5 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_6__SHIFT = 0x6 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_7__SHIFT = 0x7 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_8__SHIFT = 0x8 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_9__SHIFT = 0x9 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_10__SHIFT = 0xa # macro +HDP_XDP_BUSY_STS__BUSY_BITS_11__SHIFT = 0xb # macro +HDP_XDP_BUSY_STS__BUSY_BITS_12__SHIFT = 0xc # macro +HDP_XDP_BUSY_STS__BUSY_BITS_13__SHIFT = 0xd # macro +HDP_XDP_BUSY_STS__BUSY_BITS_14__SHIFT = 0xe # macro +HDP_XDP_BUSY_STS__BUSY_BITS_15__SHIFT = 0xf # macro +HDP_XDP_BUSY_STS__BUSY_BITS_16__SHIFT = 0x10 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_17__SHIFT = 0x11 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_18__SHIFT = 0x12 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_19__SHIFT = 0x13 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_20__SHIFT = 0x14 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_21__SHIFT = 0x15 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_22__SHIFT = 0x16 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_23__SHIFT = 0x17 # macro +HDP_XDP_BUSY_STS__Z_FENCE_BIT__SHIFT = 0x18 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_0_MASK = 0x00000001 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_1_MASK = 0x00000002 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_2_MASK = 0x00000004 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_3_MASK = 0x00000008 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_4_MASK = 0x00000010 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_5_MASK = 0x00000020 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_6_MASK = 0x00000040 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_7_MASK = 0x00000080 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_8_MASK = 0x00000100 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_9_MASK = 0x00000200 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_10_MASK = 0x00000400 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_11_MASK = 0x00000800 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_12_MASK = 0x00001000 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_13_MASK = 0x00002000 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_14_MASK = 0x00004000 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_15_MASK = 0x00008000 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_16_MASK = 0x00010000 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_17_MASK = 0x00020000 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_18_MASK = 0x00040000 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_19_MASK = 0x00080000 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_20_MASK = 0x00100000 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_21_MASK = 0x00200000 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_22_MASK = 0x00400000 # macro +HDP_XDP_BUSY_STS__BUSY_BITS_23_MASK = 0x00800000 # macro +HDP_XDP_BUSY_STS__Z_FENCE_BIT_MASK = 0x01000000 # macro +HDP_XDP_STICKY__STICKY_STS__SHIFT = 0x0 # macro +HDP_XDP_STICKY__STICKY_W1C__SHIFT = 0x10 # macro +HDP_XDP_STICKY__STICKY_STS_MASK = 0x0000FFFF # macro +HDP_XDP_STICKY__STICKY_W1C_MASK = 0xFFFF0000 # macro +HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT = 0x0 # macro +HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT = 0x8 # macro +HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT = 0x10 # macro +HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT = 0x18 # macro +HDP_XDP_CHKN__CHKN_0_RSVD_MASK = 0x000000FF # macro +HDP_XDP_CHKN__CHKN_1_RSVD_MASK = 0x0000FF00 # macro +HDP_XDP_CHKN__CHKN_2_RSVD_MASK = 0x00FF0000 # macro +HDP_XDP_CHKN__CHKN_3_RSVD_MASK = 0xFF000000 # macro +HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT = 0x0 # macro +HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT = 0x4 # macro +HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT = 0x8 # macro +HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT = 0xc # macro +HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT = 0x10 # macro +HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT = 0x14 # macro +HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT = 0x18 # macro +HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT = 0x1c # macro +HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK = 0x0000000F # macro +HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK = 0x000000F0 # macro +HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK = 0x00000F00 # macro +HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK = 0x0000F000 # macro +HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK = 0x000F0000 # macro +HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK = 0x00F00000 # macro +HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK = 0x0F000000 # macro +HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK = 0xF0000000 # macro +HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT = 0x0 # macro +HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK = 0x03FFFFFF # macro +HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT = 0x1 # macro +HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT = 0x2 # macro +HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT = 0x3 # macro +HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED__SHIFT = 0x4 # macro +HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT = 0x5 # macro +HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT = 0x6 # macro +HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT = 0x7 # macro +HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT = 0x9 # macro +HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT = 0xa # macro +HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT = 0xb # macro +HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED__SHIFT = 0xc # macro +HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT = 0xd # macro +HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT = 0xe # macro +HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT = 0xf # macro +HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT = 0x11 # macro +HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT = 0x12 # macro +HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT = 0x13 # macro +HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT = 0x15 # macro +HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT = 0x16 # macro +HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT = 0x17 # macro +HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK = 0x00000002 # macro +HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK = 0x00000004 # macro +HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK = 0x00000008 # macro +HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED_MASK = 0x00000010 # macro +HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK = 0x00000020 # macro +HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK = 0x00000040 # macro +HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK = 0x00000080 # macro +HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK = 0x00000200 # macro +HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK = 0x00000400 # macro +HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK = 0x00000800 # macro +HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED_MASK = 0x00001000 # macro +HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK = 0x00002000 # macro +HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK = 0x00004000 # macro +HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK = 0x00008000 # macro +HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK = 0x00020000 # macro +HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK = 0x00040000 # macro +HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK = 0x00080000 # macro +HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK = 0x00200000 # macro +HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK = 0x00400000 # macro +HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK = 0x00800000 # macro +__all__ = \ + ['HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK', + 'HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE__SHIFT', + 'HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK', + 'HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT', + 'HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK', + 'HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT', + 'HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK', + 'HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT', + 'HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK', + 'HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT', + 'HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK', + 'HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT', + 'HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK', + 'HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT', + 'HDP_DEBUG0__HDP_DEBUG_MASK', 'HDP_DEBUG0__HDP_DEBUG__SHIFT', + 'HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK', + 'HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT', + 'HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK', + 'HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT', + 'HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK', + 'HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT', + 'HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK', + 'HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT', + 'HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK', + 'HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK', + 'HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT', + 'HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT', + 'HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK', + 'HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT', + 'HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK', + 'HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT', + 'HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK', + 'HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT', + 'HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK', + 'HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT', + 'HDP_MEMIO_CNTL__MEMIO_BE_MASK', + 'HDP_MEMIO_CNTL__MEMIO_BE__SHIFT', + 'HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK', + 'HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT', + 'HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK', + 'HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT', + 'HDP_MEMIO_CNTL__MEMIO_OP_MASK', + 'HDP_MEMIO_CNTL__MEMIO_OP__SHIFT', + 'HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK', + 'HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT', + 'HDP_MEMIO_CNTL__MEMIO_SEND_MASK', + 'HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT', + 'HDP_MEMIO_CNTL__MEMIO_VFID_MASK', + 'HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT', + 'HDP_MEMIO_CNTL__MEMIO_VF_MASK', + 'HDP_MEMIO_CNTL__MEMIO_VF__SHIFT', + 'HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK', + 'HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT', + 'HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK', + 'HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT', + 'HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK', + 'HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT', + 'HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK', + 'HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT', + 'HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK', + 'HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT', + 'HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK', + 'HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT', + 'HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK', + 'HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS_MASK', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS__SHIFT', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN_MASK', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN__SHIFT', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY_MASK', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN__SHIFT', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN__SHIFT', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN__SHIFT', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY_MASK', + 'HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY__SHIFT', + 'HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK', + 'HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT', + 'HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK', + 'HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT', + 'HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY_MASK', + 'HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT', + 'HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK', + 'HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT', + 'HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK', + 'HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT', + 'HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK', + 'HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT', + 'HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK', + 'HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT', + 'HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK', + 'HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT', + 'HDP_MISC_CNTL__ATOMIC_NACK_ENABLE_MASK', + 'HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT', + 'HDP_MISC_CNTL__FED_ENABLE_MASK', + 'HDP_MISC_CNTL__FED_ENABLE__SHIFT', + 'HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK', + 'HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT', + 'HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK', + 'HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT', + 'HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK', + 'HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT', + 'HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK', + 'HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT', + 'HDP_MISC_CNTL__NACK_ENABLE_MASK', + 'HDP_MISC_CNTL__NACK_ENABLE__SHIFT', + 'HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK', + 'HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT', + 'HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK', + 'HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT', + 'HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK', + 'HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT', + 'HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK', + 'HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT', + 'HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK', + 'HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT', + 'HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK', + 'HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT', + 'HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK', + 'HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT', + 'HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK', + 'HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT', + 'HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK', + 'HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT', + 'HDP_NONSURFACE_INFO__NONSURF_VMID_MASK', + 'HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT', + 'HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK', + 'HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT', + 'HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK', + 'HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT', + 'HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK', + 'HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT', + 'HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK', + 'HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT', + 'HDP_OUTSTANDING_REQ__READ_REQ_MASK', + 'HDP_OUTSTANDING_REQ__READ_REQ__SHIFT', + 'HDP_OUTSTANDING_REQ__WRITE_REQ_MASK', + 'HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT', + 'HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK', + 'HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT', + 'HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK', + 'HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT', + 'HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK', + 'HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT', + 'HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK', + 'HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT', + 'HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK', + 'HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT', + 'HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK', + 'HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT', + 'HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK', + 'HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT', + 'HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK', + 'HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT', + 'HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK', + 'HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT', + 'HDP_VERSION__MAJVER_MASK', 'HDP_VERSION__MAJVER__SHIFT', + 'HDP_VERSION__MINVER_MASK', 'HDP_VERSION__MINVER__SHIFT', + 'HDP_VERSION__REV_MASK', 'HDP_VERSION__REV__SHIFT', + 'HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK', + 'HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT', + 'HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK', + 'HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT', + 'HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK', + 'HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT', + 'HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK', + 'HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT', + 'HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK', + 'HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT', + 'HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK', + 'HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT', + 'HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK', + 'HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT', + 'HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK', + 'HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_0_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_0__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_10_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_10__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_11_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_11__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_12_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_12__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_13_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_13__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_14_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_14__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_15_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_15__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_16_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_16__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_17_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_17__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_18_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_18__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_19_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_19__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_1_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_1__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_20_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_20__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_21_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_21__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_22_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_22__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_23_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_23__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_2_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_2__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_3_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_3__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_4_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_4__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_5_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_5__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_6_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_6__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_7_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_7__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_8_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_8__SHIFT', + 'HDP_XDP_BUSY_STS__BUSY_BITS_9_MASK', + 'HDP_XDP_BUSY_STS__BUSY_BITS_9__SHIFT', + 'HDP_XDP_BUSY_STS__Z_FENCE_BIT_MASK', + 'HDP_XDP_BUSY_STS__Z_FENCE_BIT__SHIFT', + 'HDP_XDP_CHKN__CHKN_0_RSVD_MASK', + 'HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT', + 'HDP_XDP_CHKN__CHKN_1_RSVD_MASK', + 'HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT', + 'HDP_XDP_CHKN__CHKN_2_RSVD_MASK', + 'HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT', + 'HDP_XDP_CHKN__CHKN_3_RSVD_MASK', + 'HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT', + 'HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK', + 'HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT', + 'HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK', + 'HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT', + 'HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK', + 'HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK', + 'HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT', + 'HDP_XDP_D2H_RSVD_10__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_11__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_12__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_13__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_14__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_15__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_16__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_17__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_18__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_19__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_20__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_21__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_22__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_23__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_24__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_25__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_26__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_27__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_28__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_29__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_30__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_31__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_32__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_33__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_34__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_3__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_4__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_5__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_6__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_7__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_8__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT', + 'HDP_XDP_D2H_RSVD_9__RESERVED_MASK', + 'HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT', + 'HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK', + 'HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT', + 'HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK', + 'HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT', + 'HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK', + 'HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT', + 'HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK', + 'HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT', + 'HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK', + 'HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT', + 'HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK', + 'HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT', + 'HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK', + 'HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT', + 'HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK', + 'HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT', + 'HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK', + 'HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT', + 'HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK', + 'HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT', + 'HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK', + 'HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT', + 'HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK', + 'HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT', + 'HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK', + 'HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT', + 'HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK', + 'HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT', + 'HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK', + 'HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT', + 'HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK', + 'HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT', + 'HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK', + 'HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT', + 'HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK', + 'HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT', + 'HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK', + 'HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT', + 'HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK', + 'HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT', + 'HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK', + 'HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT', + 'HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK', + 'HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK', + 'HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT', + 'HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT', + 'HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK', + 'HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT', + 'HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK', + 'HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT', + 'HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK', + 'HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT', + 'HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK', + 'HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT', + 'HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK', + 'HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT', + 'HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK', + 'HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT', + 'HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK', + 'HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT', + 'HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK', + 'HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT', + 'HDP_XDP_P2P_BAR0__ADDR_MASK', 'HDP_XDP_P2P_BAR0__ADDR__SHIFT', + 'HDP_XDP_P2P_BAR0__FLUSH_MASK', 'HDP_XDP_P2P_BAR0__FLUSH__SHIFT', + 'HDP_XDP_P2P_BAR0__VALID_MASK', 'HDP_XDP_P2P_BAR0__VALID__SHIFT', + 'HDP_XDP_P2P_BAR1__ADDR_MASK', 'HDP_XDP_P2P_BAR1__ADDR__SHIFT', + 'HDP_XDP_P2P_BAR1__FLUSH_MASK', 'HDP_XDP_P2P_BAR1__FLUSH__SHIFT', + 'HDP_XDP_P2P_BAR1__VALID_MASK', 'HDP_XDP_P2P_BAR1__VALID__SHIFT', + 'HDP_XDP_P2P_BAR2__ADDR_MASK', 'HDP_XDP_P2P_BAR2__ADDR__SHIFT', + 'HDP_XDP_P2P_BAR2__FLUSH_MASK', 'HDP_XDP_P2P_BAR2__FLUSH__SHIFT', + 'HDP_XDP_P2P_BAR2__VALID_MASK', 'HDP_XDP_P2P_BAR2__VALID__SHIFT', + 'HDP_XDP_P2P_BAR3__ADDR_MASK', 'HDP_XDP_P2P_BAR3__ADDR__SHIFT', + 'HDP_XDP_P2P_BAR3__FLUSH_MASK', 'HDP_XDP_P2P_BAR3__FLUSH__SHIFT', + 'HDP_XDP_P2P_BAR3__VALID_MASK', 'HDP_XDP_P2P_BAR3__VALID__SHIFT', + 'HDP_XDP_P2P_BAR4__ADDR_MASK', 'HDP_XDP_P2P_BAR4__ADDR__SHIFT', + 'HDP_XDP_P2P_BAR4__FLUSH_MASK', 'HDP_XDP_P2P_BAR4__FLUSH__SHIFT', + 'HDP_XDP_P2P_BAR4__VALID_MASK', 'HDP_XDP_P2P_BAR4__VALID__SHIFT', + 'HDP_XDP_P2P_BAR5__ADDR_MASK', 'HDP_XDP_P2P_BAR5__ADDR__SHIFT', + 'HDP_XDP_P2P_BAR5__FLUSH_MASK', 'HDP_XDP_P2P_BAR5__FLUSH__SHIFT', + 'HDP_XDP_P2P_BAR5__VALID_MASK', 'HDP_XDP_P2P_BAR5__VALID__SHIFT', + 'HDP_XDP_P2P_BAR6__ADDR_MASK', 'HDP_XDP_P2P_BAR6__ADDR__SHIFT', + 'HDP_XDP_P2P_BAR6__FLUSH_MASK', 'HDP_XDP_P2P_BAR6__FLUSH__SHIFT', + 'HDP_XDP_P2P_BAR6__VALID_MASK', 'HDP_XDP_P2P_BAR6__VALID__SHIFT', + 'HDP_XDP_P2P_BAR7__ADDR_MASK', 'HDP_XDP_P2P_BAR7__ADDR__SHIFT', + 'HDP_XDP_P2P_BAR7__FLUSH_MASK', 'HDP_XDP_P2P_BAR7__FLUSH__SHIFT', + 'HDP_XDP_P2P_BAR7__VALID_MASK', 'HDP_XDP_P2P_BAR7__VALID__SHIFT', + 'HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK', + 'HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT', + 'HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK', + 'HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK', + 'HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK', + 'HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK', + 'HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR0__VALID_MASK', + 'HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK', + 'HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK', + 'HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK', + 'HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR1__VALID_MASK', + 'HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK', + 'HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK', + 'HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK', + 'HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR2__VALID_MASK', + 'HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK', + 'HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK', + 'HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK', + 'HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR3__VALID_MASK', + 'HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK', + 'HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK', + 'HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK', + 'HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR4__VALID_MASK', + 'HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK', + 'HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK', + 'HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK', + 'HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR5__VALID_MASK', + 'HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK', + 'HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK', + 'HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK', + 'HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT', + 'HDP_XDP_P2P_MBX_ADDR6__VALID_MASK', + 'HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT', + 'HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK', + 'HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT', + 'HDP_XDP_STICKY__STICKY_STS_MASK', + 'HDP_XDP_STICKY__STICKY_STS__SHIFT', + 'HDP_XDP_STICKY__STICKY_W1C_MASK', + 'HDP_XDP_STICKY__STICKY_W1C__SHIFT', '_hdp_6_0_0_OFFSET_HEADER', + '_hdp_6_0_0_SH_MASK_HEADER', 'regHDP_CLK_CNTL', + 'regHDP_CLK_CNTL_BASE_IDX', 'regHDP_DEBUG0', + 'regHDP_DEBUG0_BASE_IDX', 'regHDP_HOST_PATH_CNTL', + 'regHDP_HOST_PATH_CNTL_BASE_IDX', 'regHDP_LAST_SURFACE_HIT', + 'regHDP_LAST_SURFACE_HIT_BASE_IDX', 'regHDP_MEMIO_ADDR', + 'regHDP_MEMIO_ADDR_BASE_IDX', 'regHDP_MEMIO_CNTL', + 'regHDP_MEMIO_CNTL_BASE_IDX', 'regHDP_MEMIO_RD_DATA', + 'regHDP_MEMIO_RD_DATA_BASE_IDX', 'regHDP_MEMIO_STATUS', + 'regHDP_MEMIO_STATUS_BASE_IDX', 'regHDP_MEMIO_WR_DATA', + 'regHDP_MEMIO_WR_DATA_BASE_IDX', 'regHDP_MEM_POWER_CTRL', + 'regHDP_MEM_POWER_CTRL_BASE_IDX', 'regHDP_MISC_CNTL', + 'regHDP_MISC_CNTL_BASE_IDX', 'regHDP_MMHUB_CNTL', + 'regHDP_MMHUB_CNTL_BASE_IDX', 'regHDP_NONSURFACE_BASE', + 'regHDP_NONSURFACE_BASE_BASE_IDX', 'regHDP_NONSURFACE_BASE_HI', + 'regHDP_NONSURFACE_BASE_HI_BASE_IDX', 'regHDP_NONSURFACE_INFO', + 'regHDP_NONSURFACE_INFO_BASE_IDX', 'regHDP_NONSURF_FLAGS', + 'regHDP_NONSURF_FLAGS_BASE_IDX', 'regHDP_NONSURF_FLAGS_CLR', + 'regHDP_NONSURF_FLAGS_CLR_BASE_IDX', 'regHDP_OUTSTANDING_REQ', + 'regHDP_OUTSTANDING_REQ_BASE_IDX', 'regHDP_SURFACE_READ_FLAGS', + 'regHDP_SURFACE_READ_FLAGS_BASE_IDX', + 'regHDP_SURFACE_READ_FLAGS_CLR', + 'regHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX', + 'regHDP_SURFACE_WRITE_FLAGS', + 'regHDP_SURFACE_WRITE_FLAGS_BASE_IDX', + 'regHDP_SURFACE_WRITE_FLAGS_CLR', + 'regHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX', 'regHDP_SW_SEMAPHORE', + 'regHDP_SW_SEMAPHORE_BASE_IDX', 'regHDP_VERSION', + 'regHDP_VERSION_BASE_IDX', 'regHDP_XDP_BARS_ADDR_39_36', + 'regHDP_XDP_BARS_ADDR_39_36_BASE_IDX', 'regHDP_XDP_BUSY_STS', + 'regHDP_XDP_BUSY_STS_BASE_IDX', 'regHDP_XDP_CHKN', + 'regHDP_XDP_CHKN_BASE_IDX', 'regHDP_XDP_D2H_BAR_UPDATE', + 'regHDP_XDP_D2H_BAR_UPDATE_BASE_IDX', 'regHDP_XDP_D2H_FLUSH', + 'regHDP_XDP_D2H_FLUSH_BASE_IDX', 'regHDP_XDP_D2H_RSVD_10', + 'regHDP_XDP_D2H_RSVD_10_BASE_IDX', 'regHDP_XDP_D2H_RSVD_11', + 'regHDP_XDP_D2H_RSVD_11_BASE_IDX', 'regHDP_XDP_D2H_RSVD_12', + 'regHDP_XDP_D2H_RSVD_12_BASE_IDX', 'regHDP_XDP_D2H_RSVD_13', + 'regHDP_XDP_D2H_RSVD_13_BASE_IDX', 'regHDP_XDP_D2H_RSVD_14', + 'regHDP_XDP_D2H_RSVD_14_BASE_IDX', 'regHDP_XDP_D2H_RSVD_15', + 'regHDP_XDP_D2H_RSVD_15_BASE_IDX', 'regHDP_XDP_D2H_RSVD_16', + 'regHDP_XDP_D2H_RSVD_16_BASE_IDX', 'regHDP_XDP_D2H_RSVD_17', + 'regHDP_XDP_D2H_RSVD_17_BASE_IDX', 'regHDP_XDP_D2H_RSVD_18', + 'regHDP_XDP_D2H_RSVD_18_BASE_IDX', 'regHDP_XDP_D2H_RSVD_19', + 'regHDP_XDP_D2H_RSVD_19_BASE_IDX', 'regHDP_XDP_D2H_RSVD_20', + 'regHDP_XDP_D2H_RSVD_20_BASE_IDX', 'regHDP_XDP_D2H_RSVD_21', + 'regHDP_XDP_D2H_RSVD_21_BASE_IDX', 'regHDP_XDP_D2H_RSVD_22', + 'regHDP_XDP_D2H_RSVD_22_BASE_IDX', 'regHDP_XDP_D2H_RSVD_23', + 'regHDP_XDP_D2H_RSVD_23_BASE_IDX', 'regHDP_XDP_D2H_RSVD_24', + 'regHDP_XDP_D2H_RSVD_24_BASE_IDX', 'regHDP_XDP_D2H_RSVD_25', + 'regHDP_XDP_D2H_RSVD_25_BASE_IDX', 'regHDP_XDP_D2H_RSVD_26', + 'regHDP_XDP_D2H_RSVD_26_BASE_IDX', 'regHDP_XDP_D2H_RSVD_27', + 'regHDP_XDP_D2H_RSVD_27_BASE_IDX', 'regHDP_XDP_D2H_RSVD_28', + 'regHDP_XDP_D2H_RSVD_28_BASE_IDX', 'regHDP_XDP_D2H_RSVD_29', + 'regHDP_XDP_D2H_RSVD_29_BASE_IDX', 'regHDP_XDP_D2H_RSVD_3', + 'regHDP_XDP_D2H_RSVD_30', 'regHDP_XDP_D2H_RSVD_30_BASE_IDX', + 'regHDP_XDP_D2H_RSVD_31', 'regHDP_XDP_D2H_RSVD_31_BASE_IDX', + 'regHDP_XDP_D2H_RSVD_32', 'regHDP_XDP_D2H_RSVD_32_BASE_IDX', + 'regHDP_XDP_D2H_RSVD_33', 'regHDP_XDP_D2H_RSVD_33_BASE_IDX', + 'regHDP_XDP_D2H_RSVD_34', 'regHDP_XDP_D2H_RSVD_34_BASE_IDX', + 'regHDP_XDP_D2H_RSVD_3_BASE_IDX', 'regHDP_XDP_D2H_RSVD_4', + 'regHDP_XDP_D2H_RSVD_4_BASE_IDX', 'regHDP_XDP_D2H_RSVD_5', + 'regHDP_XDP_D2H_RSVD_5_BASE_IDX', 'regHDP_XDP_D2H_RSVD_6', + 'regHDP_XDP_D2H_RSVD_6_BASE_IDX', 'regHDP_XDP_D2H_RSVD_7', + 'regHDP_XDP_D2H_RSVD_7_BASE_IDX', 'regHDP_XDP_D2H_RSVD_8', + 'regHDP_XDP_D2H_RSVD_8_BASE_IDX', 'regHDP_XDP_D2H_RSVD_9', + 'regHDP_XDP_D2H_RSVD_9_BASE_IDX', 'regHDP_XDP_DIRECT2HDP_FIRST', + 'regHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX', + 'regHDP_XDP_DIRECT2HDP_LAST', + 'regHDP_XDP_DIRECT2HDP_LAST_BASE_IDX', + 'regHDP_XDP_FLUSH_ARMED_STS', + 'regHDP_XDP_FLUSH_ARMED_STS_BASE_IDX', + 'regHDP_XDP_FLUSH_CNTR0_STS', + 'regHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX', 'regHDP_XDP_HDP_IPH_CFG', + 'regHDP_XDP_HDP_IPH_CFG_BASE_IDX', 'regHDP_XDP_HDP_MBX_MC_CFG', + 'regHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX', 'regHDP_XDP_HDP_MC_CFG', + 'regHDP_XDP_HDP_MC_CFG_BASE_IDX', 'regHDP_XDP_HST_CFG', + 'regHDP_XDP_HST_CFG_BASE_IDX', + 'regHDP_XDP_MC_VM_FB_LOCATION_BASE', + 'regHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX', + 'regHDP_XDP_MMHUB_ERROR', 'regHDP_XDP_MMHUB_ERROR_BASE_IDX', + 'regHDP_XDP_P2P_BAR0', 'regHDP_XDP_P2P_BAR0_BASE_IDX', + 'regHDP_XDP_P2P_BAR1', 'regHDP_XDP_P2P_BAR1_BASE_IDX', + 'regHDP_XDP_P2P_BAR2', 'regHDP_XDP_P2P_BAR2_BASE_IDX', + 'regHDP_XDP_P2P_BAR3', 'regHDP_XDP_P2P_BAR3_BASE_IDX', + 'regHDP_XDP_P2P_BAR4', 'regHDP_XDP_P2P_BAR4_BASE_IDX', + 'regHDP_XDP_P2P_BAR5', 'regHDP_XDP_P2P_BAR5_BASE_IDX', + 'regHDP_XDP_P2P_BAR6', 'regHDP_XDP_P2P_BAR6_BASE_IDX', + 'regHDP_XDP_P2P_BAR7', 'regHDP_XDP_P2P_BAR7_BASE_IDX', + 'regHDP_XDP_P2P_BAR_CFG', 'regHDP_XDP_P2P_BAR_CFG_BASE_IDX', + 'regHDP_XDP_P2P_MBX_ADDR0', 'regHDP_XDP_P2P_MBX_ADDR0_BASE_IDX', + 'regHDP_XDP_P2P_MBX_ADDR1', 'regHDP_XDP_P2P_MBX_ADDR1_BASE_IDX', + 'regHDP_XDP_P2P_MBX_ADDR2', 'regHDP_XDP_P2P_MBX_ADDR2_BASE_IDX', + 'regHDP_XDP_P2P_MBX_ADDR3', 'regHDP_XDP_P2P_MBX_ADDR3_BASE_IDX', + 'regHDP_XDP_P2P_MBX_ADDR4', 'regHDP_XDP_P2P_MBX_ADDR4_BASE_IDX', + 'regHDP_XDP_P2P_MBX_ADDR5', 'regHDP_XDP_P2P_MBX_ADDR5_BASE_IDX', + 'regHDP_XDP_P2P_MBX_ADDR6', 'regHDP_XDP_P2P_MBX_ADDR6_BASE_IDX', + 'regHDP_XDP_P2P_MBX_OFFSET', 'regHDP_XDP_P2P_MBX_OFFSET_BASE_IDX', + 'regHDP_XDP_STICKY', 'regHDP_XDP_STICKY_BASE_IDX'] diff --git a/tinygrad/runtime/support/am/amdev.py b/tinygrad/runtime/support/am/amdev.py index c410f6156c..325b8f02dc 100644 --- a/tinygrad/runtime/support/am/amdev.py +++ b/tinygrad/runtime/support/am/amdev.py @@ -295,7 +295,7 @@ class AMDev: if DEBUG >= 2: print(f"am {self.devfmt}: {ip.__class__.__name__} initialized") self.smu.set_clocks(level=-1) # last level, max perf. - self.gfx.set_clockgating_state() + for ip in [self.soc21, self.gfx]: ip.set_clockgating_state() self.reg("regSCRATCH_REG7").write(am_version) if DEBUG >= 2: print(f"am {self.devfmt}: boot done") @@ -382,7 +382,9 @@ class AMDev: def _build_regs(self): mods = [("MP0", self._ip_module("mp", am.MP0_HWIP)), ("NBIO", self._ip_module("nbio", am.NBIO_HWIP)), ("GC", self._ip_module("gc", am.GC_HWIP)), - ("MP1", mp_11_0), ("MMHUB", self._ip_module("mmhub", am.MMHUB_HWIP)), ("OSSSYS", self._ip_module("osssys", am.OSSSYS_HWIP))] + ("MP1", mp_11_0), ("MMHUB", self._ip_module("mmhub", am.MMHUB_HWIP)), ("OSSSYS", self._ip_module("osssys", am.OSSSYS_HWIP)), + ("HDP", self._ip_module("hdp", am.HDP_HWIP))] + for base, module in mods: rpref = "mm" if base == "MP1" else "reg" # MP1 regs starts with mm reg_names: set[str] = set(k[len(rpref):] for k in module.__dict__.keys() if k.startswith(rpref) and not k.endswith("_BASE_IDX")) diff --git a/tinygrad/runtime/support/am/ip.py b/tinygrad/runtime/support/am/ip.py index c597f798fd..51ebcf9430 100644 --- a/tinygrad/runtime/support/am/ip.py +++ b/tinygrad/runtime/support/am/ip.py @@ -7,11 +7,13 @@ class AM_IP: def __init__(self, adev): self.adev = adev def init(self): raise NotImplementedError("IP block init must be implemeted") def fini(self): pass + def set_clockgating_state(self): pass class AM_SOC21(AM_IP): def init(self): self.adev.regRCC_DEV0_EPF2_STRAP2.update(strap_no_soft_reset_dev0_f2=0x0) self.adev.regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN.write(0x1) + def set_clockgating_state(self): self.adev.regHDP_MEM_POWER_CTRL.update(atomic_mem_power_ctrl_en=1, atomic_mem_power_ds_en=1) class AM_GMC(AM_IP): def __init__(self, adev):