A common software error when it comes to page table code is missing TLB
maintenance. Add some checks to the io-pgtable-fast code to detect when
an address that might be stale in the TLB is being re-used. This can be
accomplished by writing a "stale TLB" flag value to the reserved bits of
the PTE during unmap and then removing the flag value when the TLBs are
invalidated (by sweeping the entire page table). That way, whenever we
map we can know that there might be a stale TLB in the location being
mapped into if it contains the "stale TLB" flag value.
CRs-Fixed: 997751
Change-Id: Icf9c1e41977cb71e8b137190adb3b4a201c339da
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Certain use cases require performance that can't be achieved with the
general-purpose SMMU page table code. By limiting ourselves to 4K page
mappings (no block mappings) and pre-populating the first and second
levels of the page tables up front, we can eliminate a lot of the work
needed for page table mapping and unmapping.
Add a performance-tuned io-pgtable implementation for ARMv8L page tables
that only supports 4K page mappings. Any size can be mapped, but only
4K page mappings will be installed in the page tables.
CRs-Fixed: 997751
Change-Id: I5861270709675016988052360d196e0a16a0d103
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
