mirror of
https://github.com/firestar5683/StarPilot.git
synced 2026-08-21 16:23:46 +08:00
firestar5683
3350 lines
78 KiB
Python
3350 lines
78 KiB
Python
counters = {
|
|
'CPC_CPC_STAT_BUSY': {
|
|
'gfx90a': ('CPC', 25),
|
|
'gfx908': ('CPC', 25),
|
|
'gfx940': ('CPC', 25),
|
|
'gfx941': ('CPC', 25),
|
|
'gfx942': ('CPC', 25),
|
|
'gfx950': ('CPC', 25),
|
|
},
|
|
'CPC_CPC_STAT_IDLE': {
|
|
'gfx90a': ('CPC', 26),
|
|
'gfx908': ('CPC', 26),
|
|
'gfx940': ('CPC', 26),
|
|
'gfx941': ('CPC', 26),
|
|
'gfx942': ('CPC', 26),
|
|
'gfx950': ('CPC', 26),
|
|
},
|
|
'CPC_CPC_STAT_STALL': {
|
|
'gfx90a': ('CPC', 27),
|
|
'gfx908': ('CPC', 27),
|
|
'gfx940': ('CPC', 27),
|
|
'gfx941': ('CPC', 27),
|
|
'gfx942': ('CPC', 27),
|
|
'gfx950': ('CPC', 27),
|
|
},
|
|
'CPC_CPC_TCIU_BUSY': {
|
|
'gfx90a': ('CPC', 28),
|
|
'gfx908': ('CPC', 28),
|
|
'gfx940': ('CPC', 28),
|
|
'gfx941': ('CPC', 28),
|
|
'gfx942': ('CPC', 28),
|
|
'gfx950': ('CPC', 28),
|
|
},
|
|
'CPC_CPC_TCIU_IDLE': {
|
|
'gfx90a': ('CPC', 29),
|
|
'gfx908': ('CPC', 29),
|
|
'gfx940': ('CPC', 29),
|
|
'gfx941': ('CPC', 29),
|
|
'gfx942': ('CPC', 29),
|
|
'gfx950': ('CPC', 29),
|
|
},
|
|
'CPC_CPC_UTCL2IU_BUSY': {
|
|
'gfx90a': ('CPC', 30),
|
|
'gfx908': ('CPC', 30),
|
|
'gfx940': ('CPC', 30),
|
|
'gfx941': ('CPC', 30),
|
|
'gfx942': ('CPC', 30),
|
|
'gfx950': ('CPC', 30),
|
|
},
|
|
'CPC_CPC_UTCL2IU_IDLE': {
|
|
'gfx90a': ('CPC', 31),
|
|
'gfx908': ('CPC', 31),
|
|
'gfx940': ('CPC', 31),
|
|
'gfx941': ('CPC', 31),
|
|
'gfx942': ('CPC', 31),
|
|
'gfx950': ('CPC', 31),
|
|
},
|
|
'CPC_CPC_UTCL2IU_STALL': {
|
|
'gfx90a': ('CPC', 32),
|
|
'gfx908': ('CPC', 32),
|
|
'gfx940': ('CPC', 32),
|
|
'gfx941': ('CPC', 32),
|
|
'gfx942': ('CPC', 32),
|
|
'gfx950': ('CPC', 32),
|
|
},
|
|
'CPC_ME1_BUSY_FOR_PACKET_DECODE': {
|
|
'gfx90a': ('CPC', 13),
|
|
'gfx908': ('CPC', 13),
|
|
'gfx940': ('CPC', 13),
|
|
'gfx941': ('CPC', 13),
|
|
'gfx942': ('CPC', 13),
|
|
'gfx950': ('CPC', 13),
|
|
},
|
|
'CPC_ME1_DC0_SPI_BUSY': {
|
|
'gfx90a': ('CPC', 33),
|
|
'gfx908': ('CPC', 33),
|
|
'gfx940': ('CPC', 33),
|
|
'gfx941': ('CPC', 33),
|
|
'gfx942': ('CPC', 33),
|
|
'gfx950': ('CPC', 33),
|
|
},
|
|
'CPC_UTCL1_STALL_ON_TRANSLATION': {
|
|
'gfx90a': ('CPC', 24),
|
|
'gfx908': ('CPC', 24),
|
|
'gfx940': ('CPC', 24),
|
|
'gfx941': ('CPC', 24),
|
|
'gfx942': ('CPC', 24),
|
|
'gfx950': ('CPC', 24),
|
|
},
|
|
'CPC_ALWAYS_COUNT': {
|
|
'gfx950': ('CPC', 0),
|
|
},
|
|
'CPC_ADC_VALID_CHUNK_NOT_AVAIL': {
|
|
'gfx950': ('CPC', 3),
|
|
},
|
|
'CPC_ADC_DISPATCH_ALLOC_DONE': {
|
|
'gfx950': ('CPC', 4),
|
|
},
|
|
'CPC_ADC_VALID_CHUNK_END': {
|
|
'gfx950': ('CPC', 9),
|
|
},
|
|
'CPC_SYNC_FIFO_FULL_LEVEL': {
|
|
'gfx950': ('CPC', 43),
|
|
},
|
|
'CPC_SYNC_FIFO_FULL': {
|
|
'gfx950': ('CPC', 44),
|
|
},
|
|
'CPC_GD_BUSY': {
|
|
'gfx950': ('CPC', 61),
|
|
},
|
|
'CPC_TG_SEND': {
|
|
'gfx950': ('CPC', 62),
|
|
},
|
|
'CPC_WALK_NEXT_CHUNK': {
|
|
'gfx950': ('CPC', 63),
|
|
},
|
|
'CPC_STALLED_BY_SE0_SPI': {
|
|
'gfx950': ('CPC', 64),
|
|
},
|
|
'CPC_STALLED_BY_SE1_SPI': {
|
|
'gfx950': ('CPC', 65),
|
|
},
|
|
'CPC_STALLED_BY_SE2_SPI': {
|
|
'gfx950': ('CPC', 66),
|
|
},
|
|
'CPC_STALLED_BY_SE3_SPI': {
|
|
'gfx950': ('CPC', 67),
|
|
},
|
|
'CPC_LTE_ALL': {
|
|
'gfx950': ('CPC', 68),
|
|
},
|
|
'CPC_SYNC_WRREQ_FIFO_BUSY': {
|
|
'gfx950': ('CPC', 69),
|
|
},
|
|
'CPC_CANE_BUSY': {
|
|
'gfx950': ('CPC', 70),
|
|
},
|
|
'CPC_CANE_STALL': {
|
|
'gfx950': ('CPC', 71),
|
|
},
|
|
'CPF_CMP_UTCL1_STALL_ON_TRANSLATION': {
|
|
'gfx90a': ('CPF', 20),
|
|
'gfx908': ('CPF', 20),
|
|
'gfx940': ('CPF', 20),
|
|
'gfx941': ('CPF', 20),
|
|
'gfx942': ('CPF', 20),
|
|
'gfx950': ('CPF', 20),
|
|
},
|
|
'CPF_CPF_STAT_BUSY': {
|
|
'gfx90a': ('CPF', 23),
|
|
'gfx908': ('CPF', 23),
|
|
'gfx940': ('CPF', 23),
|
|
'gfx941': ('CPF', 23),
|
|
'gfx942': ('CPF', 23),
|
|
'gfx950': ('CPF', 23),
|
|
},
|
|
'CPF_CPF_STAT_IDLE': {
|
|
'gfx90a': ('CPF', 24),
|
|
'gfx908': ('CPF', 24),
|
|
'gfx940': ('CPF', 24),
|
|
'gfx941': ('CPF', 24),
|
|
'gfx942': ('CPF', 24),
|
|
'gfx950': ('CPF', 24),
|
|
},
|
|
'CPF_CPF_STAT_STALL': {
|
|
'gfx90a': ('CPF', 25),
|
|
'gfx908': ('CPF', 25),
|
|
'gfx940': ('CPF', 25),
|
|
'gfx941': ('CPF', 25),
|
|
'gfx942': ('CPF', 25),
|
|
'gfx950': ('CPF', 25),
|
|
},
|
|
'CPF_CPF_TCIU_BUSY': {
|
|
'gfx90a': ('CPF', 26),
|
|
'gfx908': ('CPF', 26),
|
|
'gfx940': ('CPF', 26),
|
|
'gfx941': ('CPF', 26),
|
|
'gfx942': ('CPF', 26),
|
|
'gfx950': ('CPF', 26),
|
|
},
|
|
'CPF_CPF_TCIU_IDLE': {
|
|
'gfx90a': ('CPF', 27),
|
|
'gfx908': ('CPF', 27),
|
|
'gfx940': ('CPF', 27),
|
|
'gfx941': ('CPF', 27),
|
|
'gfx942': ('CPF', 27),
|
|
'gfx950': ('CPF', 27),
|
|
},
|
|
'CPF_CPF_TCIU_STALL': {
|
|
'gfx90a': ('CPF', 28),
|
|
'gfx908': ('CPF', 28),
|
|
'gfx940': ('CPF', 28),
|
|
'gfx941': ('CPF', 28),
|
|
'gfx942': ('CPF', 28),
|
|
'gfx950': ('CPF', 28),
|
|
},
|
|
'GL2C_EA_RDREQ': {
|
|
'gfx12': ('GL2C', 140),
|
|
'gfx1200': ('GL2C', 140),
|
|
'gfx1201': ('GL2C', 140),
|
|
},
|
|
'GL2C_EA_RDREQ_128B': {
|
|
'gfx10': ('GL2C', 102),
|
|
'gfx1010': ('GL2C', 102),
|
|
'gfx1030': ('GL2C', 102),
|
|
'gfx1031': ('GL2C', 102),
|
|
'gfx1032': ('GL2C', 102),
|
|
'gfx11': ('GL2C', 102),
|
|
'gfx1100': ('GL2C', 102),
|
|
'gfx1101': ('GL2C', 102),
|
|
'gfx1102': ('GL2C', 102),
|
|
'gfx12': ('GL2C', 148),
|
|
'gfx1200': ('GL2C', 148),
|
|
'gfx1201': ('GL2C', 148),
|
|
},
|
|
'GL2C_EA_RDREQ_32B': {
|
|
'gfx10': ('GL2C', 99),
|
|
'gfx1010': ('GL2C', 99),
|
|
'gfx1030': ('GL2C', 99),
|
|
'gfx1031': ('GL2C', 99),
|
|
'gfx1032': ('GL2C', 99),
|
|
'gfx11': ('GL2C', 99),
|
|
'gfx1100': ('GL2C', 99),
|
|
'gfx1101': ('GL2C', 99),
|
|
'gfx1102': ('GL2C', 99),
|
|
'gfx12': ('GL2C', 146),
|
|
'gfx1200': ('GL2C', 146),
|
|
'gfx1201': ('GL2C', 146),
|
|
},
|
|
'GL2C_EA_RDREQ_64B': {
|
|
'gfx10': ('GL2C', 100),
|
|
'gfx1010': ('GL2C', 100),
|
|
'gfx1030': ('GL2C', 100),
|
|
'gfx1031': ('GL2C', 100),
|
|
'gfx1032': ('GL2C', 100),
|
|
'gfx11': ('GL2C', 100),
|
|
'gfx1100': ('GL2C', 100),
|
|
'gfx1101': ('GL2C', 100),
|
|
'gfx1102': ('GL2C', 100),
|
|
'gfx12': ('GL2C', 147),
|
|
'gfx1200': ('GL2C', 147),
|
|
'gfx1201': ('GL2C', 147),
|
|
},
|
|
'GL2C_EA_RDREQ_96B': {
|
|
'gfx10': ('GL2C', 101),
|
|
'gfx1010': ('GL2C', 101),
|
|
'gfx1030': ('GL2C', 101),
|
|
'gfx1031': ('GL2C', 101),
|
|
'gfx1032': ('GL2C', 101),
|
|
'gfx11': ('GL2C', 101),
|
|
'gfx1100': ('GL2C', 101),
|
|
'gfx1101': ('GL2C', 101),
|
|
'gfx1102': ('GL2C', 101),
|
|
},
|
|
'GL2C_EA_WRREQ': {
|
|
'gfx12': ('GL2C', 108),
|
|
'gfx1200': ('GL2C', 108),
|
|
'gfx1201': ('GL2C', 108),
|
|
},
|
|
'GL2C_EA_WRREQ_STALL': {
|
|
'gfx12': ('GL2C', 122),
|
|
'gfx1200': ('GL2C', 122),
|
|
'gfx1201': ('GL2C', 122),
|
|
},
|
|
'GL2C_EA_WRREQ_64B': {
|
|
'gfx10': ('GL2C', 85),
|
|
'gfx1010': ('GL2C', 85),
|
|
'gfx1030': ('GL2C', 85),
|
|
'gfx1031': ('GL2C', 85),
|
|
'gfx1032': ('GL2C', 85),
|
|
'gfx11': ('GL2C', 85),
|
|
'gfx1100': ('GL2C', 85),
|
|
'gfx1101': ('GL2C', 85),
|
|
'gfx1102': ('GL2C', 85),
|
|
'gfx12': ('GL2C', 114),
|
|
'gfx1200': ('GL2C', 114),
|
|
'gfx1201': ('GL2C', 114),
|
|
},
|
|
'GL2C_HIT': {
|
|
'gfx10': ('GL2C', 42),
|
|
'gfx1010': ('GL2C', 42),
|
|
'gfx1030': ('GL2C', 42),
|
|
'gfx1031': ('GL2C', 42),
|
|
'gfx1032': ('GL2C', 42),
|
|
'gfx11': ('GL2C', 42),
|
|
'gfx1100': ('GL2C', 42),
|
|
'gfx1101': ('GL2C', 42),
|
|
'gfx1102': ('GL2C', 42),
|
|
'gfx12': ('GL2C', 41),
|
|
'gfx1200': ('GL2C', 41),
|
|
'gfx1201': ('GL2C', 41),
|
|
},
|
|
'GL2C_MC_RDREQ': {
|
|
'gfx10': ('GL2C', 96),
|
|
'gfx1010': ('GL2C', 96),
|
|
'gfx1030': ('GL2C', 96),
|
|
'gfx1031': ('GL2C', 96),
|
|
'gfx1032': ('GL2C', 96),
|
|
'gfx11': ('GL2C', 96),
|
|
'gfx1100': ('GL2C', 96),
|
|
'gfx1101': ('GL2C', 96),
|
|
'gfx1102': ('GL2C', 96),
|
|
},
|
|
'GL2C_MC_WRREQ': {
|
|
'gfx10': ('GL2C', 83),
|
|
'gfx1010': ('GL2C', 83),
|
|
'gfx1030': ('GL2C', 83),
|
|
'gfx1031': ('GL2C', 83),
|
|
'gfx1032': ('GL2C', 83),
|
|
'gfx11': ('GL2C', 83),
|
|
'gfx1100': ('GL2C', 83),
|
|
'gfx1101': ('GL2C', 83),
|
|
'gfx1102': ('GL2C', 83),
|
|
},
|
|
'GL2C_MC_WRREQ_STALL': {
|
|
'gfx10': ('GL2C', 88),
|
|
'gfx1010': ('GL2C', 88),
|
|
'gfx1030': ('GL2C', 88),
|
|
'gfx1031': ('GL2C', 88),
|
|
'gfx1032': ('GL2C', 88),
|
|
'gfx11': ('GL2C', 88),
|
|
'gfx1100': ('GL2C', 88),
|
|
'gfx1101': ('GL2C', 88),
|
|
'gfx1102': ('GL2C', 88),
|
|
},
|
|
'GL2C_MISS': {
|
|
'gfx10': ('GL2C', 43),
|
|
'gfx1010': ('GL2C', 43),
|
|
'gfx1030': ('GL2C', 43),
|
|
'gfx1031': ('GL2C', 43),
|
|
'gfx1032': ('GL2C', 43),
|
|
'gfx11': ('GL2C', 43),
|
|
'gfx1100': ('GL2C', 43),
|
|
'gfx1101': ('GL2C', 43),
|
|
'gfx1102': ('GL2C', 43),
|
|
'gfx12': ('GL2C', 42),
|
|
'gfx1200': ('GL2C', 42),
|
|
'gfx1201': ('GL2C', 42),
|
|
},
|
|
'GRBM_COUNT': {
|
|
'gfx10': ('GRBM', 0),
|
|
'gfx1010': ('GRBM', 0),
|
|
'gfx1030': ('GRBM', 0),
|
|
'gfx1031': ('GRBM', 0),
|
|
'gfx1032': ('GRBM', 0),
|
|
'gfx11': ('GRBM', 0),
|
|
'gfx1100': ('GRBM', 0),
|
|
'gfx1101': ('GRBM', 0),
|
|
'gfx1102': ('GRBM', 0),
|
|
'gfx12': ('GRBM', 0),
|
|
'gfx1200': ('GRBM', 0),
|
|
'gfx1201': ('GRBM', 0),
|
|
'gfx9': ('GRBM', 0),
|
|
'gfx900': ('GRBM', 0),
|
|
'gfx906': ('GRBM', 0),
|
|
'gfx908': ('GRBM', 0),
|
|
'gfx90a': ('GRBM', 0),
|
|
'gfx940': ('GRBM', 0),
|
|
'gfx941': ('GRBM', 0),
|
|
'gfx942': ('GRBM', 0),
|
|
'gfx950': ('GRBM', 0),
|
|
},
|
|
'GRBM_CPC_BUSY': {
|
|
'gfx90a': ('GRBM', 30),
|
|
'gfx908': ('GRBM', 30),
|
|
'gfx940': ('GRBM', 30),
|
|
'gfx941': ('GRBM', 30),
|
|
'gfx942': ('GRBM', 30),
|
|
'gfx950': ('GRBM', 30),
|
|
},
|
|
'GRBM_CPF_BUSY': {
|
|
'gfx90a': ('GRBM', 31),
|
|
'gfx908': ('GRBM', 31),
|
|
'gfx940': ('GRBM', 31),
|
|
'gfx941': ('GRBM', 31),
|
|
'gfx942': ('GRBM', 31),
|
|
'gfx950': ('GRBM', 31),
|
|
},
|
|
'GRBM_CP_BUSY': {
|
|
'gfx10': ('GRBM', 3),
|
|
'gfx1010': ('GRBM', 3),
|
|
'gfx1030': ('GRBM', 3),
|
|
'gfx1031': ('GRBM', 3),
|
|
'gfx1032': ('GRBM', 3),
|
|
'gfx90a': ('GRBM', 3),
|
|
'gfx908': ('GRBM', 3),
|
|
'gfx940': ('GRBM', 3),
|
|
'gfx941': ('GRBM', 3),
|
|
'gfx942': ('GRBM', 3),
|
|
'gfx950': ('GRBM', 3),
|
|
},
|
|
'GRBM_EA_BUSY': {
|
|
'gfx10': ('GRBM', 35),
|
|
'gfx1010': ('GRBM', 35),
|
|
'gfx1030': ('GRBM', 35),
|
|
'gfx1031': ('GRBM', 35),
|
|
'gfx1032': ('GRBM', 35),
|
|
'gfx90a': ('GRBM', 35),
|
|
'gfx908': ('GRBM', 35),
|
|
'gfx940': ('GRBM', 35),
|
|
'gfx941': ('GRBM', 35),
|
|
'gfx942': ('GRBM', 35),
|
|
'gfx950': ('GRBM', 35),
|
|
},
|
|
'GRBM_GDS_BUSY': {
|
|
'gfx10': ('GRBM', 25),
|
|
'gfx1010': ('GRBM', 25),
|
|
'gfx1030': ('GRBM', 25),
|
|
'gfx1031': ('GRBM', 25),
|
|
'gfx1032': ('GRBM', 25),
|
|
},
|
|
'GRBM_GL2CC_BUSY': {
|
|
'gfx10': ('GRBM', 40),
|
|
'gfx1010': ('GRBM', 40),
|
|
'gfx1030': ('GRBM', 40),
|
|
'gfx1031': ('GRBM', 40),
|
|
'gfx1032': ('GRBM', 40),
|
|
},
|
|
'GRBM_GUI_ACTIVE': {
|
|
'gfx10': ('GRBM', 2),
|
|
'gfx1010': ('GRBM', 2),
|
|
'gfx1030': ('GRBM', 2),
|
|
'gfx1031': ('GRBM', 2),
|
|
'gfx1032': ('GRBM', 2),
|
|
'gfx11': ('GRBM', 2),
|
|
'gfx1100': ('GRBM', 2),
|
|
'gfx1101': ('GRBM', 2),
|
|
'gfx1102': ('GRBM', 2),
|
|
'gfx12': ('GRBM', 2),
|
|
'gfx1200': ('GRBM', 2),
|
|
'gfx1201': ('GRBM', 2),
|
|
'gfx9': ('GRBM', 2),
|
|
'gfx900': ('GRBM', 2),
|
|
'gfx906': ('GRBM', 2),
|
|
'gfx908': ('GRBM', 2),
|
|
'gfx90a': ('GRBM', 2),
|
|
'gfx940': ('GRBM', 2),
|
|
'gfx941': ('GRBM', 2),
|
|
'gfx942': ('GRBM', 2),
|
|
'gfx950': ('GRBM', 2),
|
|
},
|
|
'GRBM_SPI_BUSY': {
|
|
'gfx10': ('GRBM', 11),
|
|
'gfx1010': ('GRBM', 11),
|
|
'gfx1030': ('GRBM', 11),
|
|
'gfx1031': ('GRBM', 11),
|
|
'gfx1032': ('GRBM', 11),
|
|
'gfx90a': ('GRBM', 11),
|
|
'gfx908': ('GRBM', 11),
|
|
'gfx940': ('GRBM', 11),
|
|
'gfx941': ('GRBM', 11),
|
|
'gfx942': ('GRBM', 11),
|
|
'gfx950': ('GRBM', 11),
|
|
},
|
|
'GRBM_TA_BUSY': {
|
|
'gfx10': ('GRBM', 13),
|
|
'gfx1010': ('GRBM', 13),
|
|
'gfx1030': ('GRBM', 13),
|
|
'gfx1031': ('GRBM', 13),
|
|
'gfx1032': ('GRBM', 13),
|
|
'gfx90a': ('GRBM', 13),
|
|
'gfx908': ('GRBM', 13),
|
|
'gfx940': ('GRBM', 13),
|
|
'gfx941': ('GRBM', 13),
|
|
'gfx942': ('GRBM', 13),
|
|
'gfx950': ('GRBM', 13),
|
|
},
|
|
'GRBM_TC_BUSY': {
|
|
'gfx90a': ('GRBM', 28),
|
|
'gfx908': ('GRBM', 28),
|
|
'gfx940': ('GRBM', 28),
|
|
'gfx941': ('GRBM', 28),
|
|
'gfx942': ('GRBM', 28),
|
|
'gfx950': ('GRBM', 28),
|
|
},
|
|
'GRBM_UTCL2_BUSY': {
|
|
'gfx90a': ('GRBM', 34),
|
|
'gfx908': ('GRBM', 34),
|
|
'gfx940': ('GRBM', 34),
|
|
'gfx941': ('GRBM', 34),
|
|
'gfx942': ('GRBM', 34),
|
|
'gfx950': ('GRBM', 34),
|
|
},
|
|
'SPI_CSN_BUSY': {
|
|
'gfx90a': ('SPI', 48),
|
|
'gfx908': ('SPI', 48),
|
|
'gfx940': ('SPI', 48),
|
|
'gfx941': ('SPI', 48),
|
|
'gfx942': ('SPI', 48),
|
|
'gfx950': ('SPI', 48),
|
|
},
|
|
'SPI_CSN_NUM_THREADGROUPS': {
|
|
'gfx90a': ('SPI', 49),
|
|
'gfx908': ('SPI', 49),
|
|
'gfx940': ('SPI', 49),
|
|
'gfx941': ('SPI', 49),
|
|
'gfx942': ('SPI', 49),
|
|
'gfx950': ('SPI', 49),
|
|
},
|
|
'SPI_CSN_WAVE': {
|
|
'gfx90a': ('SPI', 52),
|
|
'gfx908': ('SPI', 52),
|
|
'gfx940': ('SPI', 52),
|
|
'gfx941': ('SPI', 52),
|
|
'gfx942': ('SPI', 52),
|
|
'gfx950': ('SPI', 52),
|
|
},
|
|
'SPI_CSN_WINDOW_VALID': {
|
|
'gfx90a': ('SPI', 47),
|
|
'gfx908': ('SPI', 47),
|
|
'gfx940': ('SPI', 47),
|
|
'gfx941': ('SPI', 47),
|
|
'gfx942': ('SPI', 47),
|
|
'gfx950': ('SPI', 47),
|
|
},
|
|
'SPI_RA_BAR_CU_FULL_CSN': {
|
|
'gfx90a': ('SPI', 123),
|
|
'gfx908': ('SPI', 123),
|
|
'gfx940': ('SPI', 123),
|
|
'gfx941': ('SPI', 123),
|
|
'gfx942': ('SPI', 123),
|
|
'gfx950': ('SPI', 123),
|
|
},
|
|
'SPI_RA_BULKY_CU_FULL_CSN': {
|
|
'gfx90a': ('SPI', 125),
|
|
'gfx908': ('SPI', 125),
|
|
'gfx940': ('SPI', 125),
|
|
'gfx941': ('SPI', 125),
|
|
'gfx942': ('SPI', 125),
|
|
'gfx950': ('SPI', 125),
|
|
},
|
|
'SPI_RA_LDS_CU_FULL_CSN': {
|
|
'gfx90a': ('SPI', 120),
|
|
'gfx908': ('SPI', 120),
|
|
'gfx940': ('SPI', 120),
|
|
'gfx941': ('SPI', 120),
|
|
'gfx942': ('SPI', 120),
|
|
'gfx950': ('SPI', 120),
|
|
},
|
|
'SPI_RA_REQ_NO_ALLOC': {
|
|
'gfx90a': ('SPI', 79),
|
|
'gfx908': ('SPI', 79),
|
|
'gfx940': ('SPI', 79),
|
|
'gfx941': ('SPI', 79),
|
|
'gfx942': ('SPI', 79),
|
|
'gfx950': ('SPI', 79),
|
|
},
|
|
'SPI_RA_REQ_NO_ALLOC_CSN': {
|
|
'gfx90a': ('SPI', 85),
|
|
'gfx908': ('SPI', 85),
|
|
'gfx940': ('SPI', 85),
|
|
'gfx941': ('SPI', 85),
|
|
'gfx942': ('SPI', 85),
|
|
'gfx950': ('SPI', 85),
|
|
},
|
|
'SPI_RA_RES_STALL_CSN': {
|
|
'gfx90a': ('SPI', 91),
|
|
'gfx908': ('SPI', 91),
|
|
'gfx940': ('SPI', 91),
|
|
'gfx941': ('SPI', 91),
|
|
'gfx942': ('SPI', 91),
|
|
'gfx950': ('SPI', 91),
|
|
},
|
|
'SPI_RA_SGPR_SIMD_FULL_CSN': {
|
|
'gfx90a': ('SPI', 115),
|
|
'gfx908': ('SPI', 115),
|
|
'gfx940': ('SPI', 115),
|
|
'gfx941': ('SPI', 115),
|
|
'gfx942': ('SPI', 115),
|
|
'gfx950': ('SPI', 115),
|
|
},
|
|
'SPI_RA_TGLIM_CU_FULL_CSN': {
|
|
'gfx90a': ('SPI', 127),
|
|
'gfx908': ('SPI', 127),
|
|
'gfx940': ('SPI', 127),
|
|
'gfx941': ('SPI', 127),
|
|
'gfx942': ('SPI', 127),
|
|
'gfx950': ('SPI', 127),
|
|
},
|
|
'SPI_RA_TMP_STALL_CSN': {
|
|
'gfx90a': ('SPI', 97),
|
|
'gfx908': ('SPI', 97),
|
|
'gfx940': ('SPI', 97),
|
|
'gfx941': ('SPI', 97),
|
|
'gfx942': ('SPI', 97),
|
|
'gfx950': ('SPI', 97),
|
|
},
|
|
'SPI_RA_VGPR_SIMD_FULL_CSN': {
|
|
'gfx90a': ('SPI', 109),
|
|
'gfx908': ('SPI', 109),
|
|
'gfx940': ('SPI', 109),
|
|
'gfx941': ('SPI', 109),
|
|
'gfx942': ('SPI', 109),
|
|
'gfx950': ('SPI', 109),
|
|
},
|
|
'SPI_RA_WAVE_SIMD_FULL_CSN': {
|
|
'gfx90a': ('SPI', 103),
|
|
'gfx908': ('SPI', 103),
|
|
'gfx940': ('SPI', 103),
|
|
'gfx941': ('SPI', 103),
|
|
'gfx942': ('SPI', 103),
|
|
'gfx950': ('SPI', 103),
|
|
},
|
|
'SPI_RA_WVLIM_STALL_CSN': {
|
|
'gfx90a': ('SPI', 133),
|
|
'gfx908': ('SPI', 133),
|
|
'gfx940': ('SPI', 133),
|
|
'gfx941': ('SPI', 133),
|
|
'gfx942': ('SPI', 133),
|
|
'gfx950': ('SPI', 133),
|
|
},
|
|
'SPI_SWC_CSC_WR': {
|
|
'gfx90a': ('SPI', 189),
|
|
'gfx908': ('SPI', 189),
|
|
'gfx940': ('SPI', 189),
|
|
'gfx941': ('SPI', 189),
|
|
'gfx942': ('SPI', 189),
|
|
'gfx950': ('SPI', 189),
|
|
},
|
|
'SPI_VWC_CSC_WR': {
|
|
'gfx90a': ('SPI', 195),
|
|
'gfx908': ('SPI', 195),
|
|
'gfx940': ('SPI', 195),
|
|
'gfx941': ('SPI', 195),
|
|
'gfx942': ('SPI', 195),
|
|
'gfx950': ('SPI', 195),
|
|
},
|
|
'SPI_CS0_WINDOW_VALID': {
|
|
'gfx950': ('SPI', 0),
|
|
},
|
|
'SPI_CS0_BUSY': {
|
|
'gfx950': ('SPI', 1),
|
|
},
|
|
'SPI_CS0_NUM_THREADGROUPS': {
|
|
'gfx950': ('SPI', 2),
|
|
},
|
|
'SPI_CS0_CRAWLER_STALL': {
|
|
'gfx950': ('SPI', 3),
|
|
},
|
|
'SPI_CS0_EVENT_WAVE': {
|
|
'gfx950': ('SPI', 4),
|
|
},
|
|
'SPI_CS0_WAVE': {
|
|
'gfx950': ('SPI', 5),
|
|
},
|
|
'SPI_CS1_WINDOW_VALID': {
|
|
'gfx950': ('SPI', 6),
|
|
},
|
|
'SPI_CS1_BUSY': {
|
|
'gfx950': ('SPI', 7),
|
|
},
|
|
'SPI_CS1_NUM_THREADGROUPS': {
|
|
'gfx950': ('SPI', 8),
|
|
},
|
|
'SPI_CS1_CRAWLER_STALL': {
|
|
'gfx950': ('SPI', 9),
|
|
},
|
|
'SPI_CS1_EVENT_WAVE': {
|
|
'gfx950': ('SPI', 10),
|
|
},
|
|
'SPI_CS1_WAVE': {
|
|
'gfx950': ('SPI', 11),
|
|
},
|
|
'SPI_CS2_WINDOW_VALID': {
|
|
'gfx950': ('SPI', 12),
|
|
},
|
|
'SPI_CS2_BUSY': {
|
|
'gfx950': ('SPI', 13),
|
|
},
|
|
'SPI_CS2_NUM_THREADGROUPS': {
|
|
'gfx950': ('SPI', 14),
|
|
},
|
|
'SPI_CS2_CRAWLER_STALL': {
|
|
'gfx950': ('SPI', 15),
|
|
},
|
|
'SPI_CS2_EVENT_WAVE': {
|
|
'gfx950': ('SPI', 16),
|
|
},
|
|
'SPI_CS2_WAVE': {
|
|
'gfx950': ('SPI', 17),
|
|
},
|
|
'SPI_CS3_WINDOW_VALID': {
|
|
'gfx950': ('SPI', 18),
|
|
},
|
|
'SPI_CS3_BUSY': {
|
|
'gfx950': ('SPI', 19),
|
|
},
|
|
'SPI_CS3_NUM_THREADGROUPS': {
|
|
'gfx950': ('SPI', 20),
|
|
},
|
|
'SPI_CS3_CRAWLER_STALL': {
|
|
'gfx950': ('SPI', 21),
|
|
},
|
|
'SPI_CS3_EVENT_WAVE': {
|
|
'gfx950': ('SPI', 22),
|
|
},
|
|
'SPI_CS3_WAVE': {
|
|
'gfx950': ('SPI', 23),
|
|
},
|
|
'SPI_CSQ_P0_Q0_OCCUPANCY': {
|
|
'gfx950': ('SPI', 140),
|
|
},
|
|
'SPI_CSQ_P0_Q1_OCCUPANCY': {
|
|
'gfx950': ('SPI', 141),
|
|
},
|
|
'SPI_CSQ_P0_Q2_OCCUPANCY': {
|
|
'gfx950': ('SPI', 142),
|
|
},
|
|
'SPI_CSQ_P0_Q3_OCCUPANCY': {
|
|
'gfx950': ('SPI', 143),
|
|
},
|
|
'SPI_CSQ_P0_Q4_OCCUPANCY': {
|
|
'gfx950': ('SPI', 144),
|
|
},
|
|
'SPI_CSQ_P0_Q5_OCCUPANCY': {
|
|
'gfx950': ('SPI', 145),
|
|
},
|
|
'SPI_CSQ_P0_Q6_OCCUPANCY': {
|
|
'gfx950': ('SPI', 146),
|
|
},
|
|
'SPI_CSQ_P0_Q7_OCCUPANCY': {
|
|
'gfx950': ('SPI', 147),
|
|
},
|
|
'SPI_CSQ_P1_Q0_OCCUPANCY': {
|
|
'gfx950': ('SPI', 148),
|
|
},
|
|
'SPI_CSQ_P1_Q1_OCCUPANCY': {
|
|
'gfx950': ('SPI', 149),
|
|
},
|
|
'SPI_CSQ_P1_Q2_OCCUPANCY': {
|
|
'gfx950': ('SPI', 150),
|
|
},
|
|
'SPI_CSQ_P1_Q3_OCCUPANCY': {
|
|
'gfx950': ('SPI', 151),
|
|
},
|
|
'SPI_CSQ_P1_Q4_OCCUPANCY': {
|
|
'gfx950': ('SPI', 152),
|
|
},
|
|
'SPI_CSQ_P1_Q5_OCCUPANCY': {
|
|
'gfx950': ('SPI', 153),
|
|
},
|
|
'SPI_CSQ_P1_Q6_OCCUPANCY': {
|
|
'gfx950': ('SPI', 154),
|
|
},
|
|
'SPI_CSQ_P1_Q7_OCCUPANCY': {
|
|
'gfx950': ('SPI', 155),
|
|
},
|
|
'SPI_CSQ_P2_Q0_OCCUPANCY': {
|
|
'gfx950': ('SPI', 156),
|
|
},
|
|
'SPI_CSQ_P2_Q1_OCCUPANCY': {
|
|
'gfx950': ('SPI', 157),
|
|
},
|
|
'SPI_CSQ_P2_Q2_OCCUPANCY': {
|
|
'gfx950': ('SPI', 158),
|
|
},
|
|
'SPI_CSQ_P2_Q3_OCCUPANCY': {
|
|
'gfx950': ('SPI', 159),
|
|
},
|
|
'SPI_CSQ_P2_Q4_OCCUPANCY': {
|
|
'gfx950': ('SPI', 160),
|
|
},
|
|
'SPI_CSQ_P2_Q5_OCCUPANCY': {
|
|
'gfx950': ('SPI', 161),
|
|
},
|
|
'SPI_CSQ_P2_Q6_OCCUPANCY': {
|
|
'gfx950': ('SPI', 162),
|
|
},
|
|
'SPI_CSQ_P2_Q7_OCCUPANCY': {
|
|
'gfx950': ('SPI', 163),
|
|
},
|
|
'SPI_CSQ_P3_Q0_OCCUPANCY': {
|
|
'gfx950': ('SPI', 164),
|
|
},
|
|
'SPI_CSQ_P3_Q1_OCCUPANCY': {
|
|
'gfx950': ('SPI', 165),
|
|
},
|
|
'SPI_CSQ_P3_Q2_OCCUPANCY': {
|
|
'gfx950': ('SPI', 166),
|
|
},
|
|
'SPI_CSQ_P3_Q3_OCCUPANCY': {
|
|
'gfx950': ('SPI', 167),
|
|
},
|
|
'SPI_CSQ_P3_Q4_OCCUPANCY': {
|
|
'gfx950': ('SPI', 168),
|
|
},
|
|
'SPI_CSQ_P3_Q5_OCCUPANCY': {
|
|
'gfx950': ('SPI', 169),
|
|
},
|
|
'SPI_CSQ_P3_Q6_OCCUPANCY': {
|
|
'gfx950': ('SPI', 170),
|
|
},
|
|
'SPI_CSQ_P3_Q7_OCCUPANCY': {
|
|
'gfx950': ('SPI', 171),
|
|
},
|
|
'SPI_CSQ_P0_OCCUPANCY': {
|
|
'gfx950': ('SPI', 172),
|
|
},
|
|
'SPI_CSQ_P1_OCCUPANCY': {
|
|
'gfx950': ('SPI', 173),
|
|
},
|
|
'SPI_CSQ_P2_OCCUPANCY': {
|
|
'gfx950': ('SPI', 174),
|
|
},
|
|
'SPI_CSQ_P3_OCCUPANCY': {
|
|
'gfx950': ('SPI', 175),
|
|
},
|
|
'SPI_VWC0_VDATA_VALID_WR': {
|
|
'gfx950': ('SPI', 193),
|
|
},
|
|
'SPI_VWC1_VDATA_VALID_WR': {
|
|
'gfx950': ('SPI', 194),
|
|
},
|
|
'SPI_CSC_WAVE_CNT_BUSY': {
|
|
'gfx950': ('SPI', 225),
|
|
},
|
|
'SQC_DCACHE_ATOMIC': {
|
|
'gfx90a': ('SQ', 298),
|
|
'gfx908': ('SQ', 298),
|
|
'gfx940': ('SQ', 298),
|
|
'gfx941': ('SQ', 298),
|
|
'gfx942': ('SQ', 298),
|
|
'gfx950': ('SQ', 298),
|
|
},
|
|
'SQC_DCACHE_BUSY_CYCLES': {
|
|
'gfx940': ('SQ', 289),
|
|
'gfx941': ('SQ', 289),
|
|
'gfx942': ('SQ', 289),
|
|
'gfx950': ('SQ', 289),
|
|
},
|
|
'SQC_DCACHE_HITS': {
|
|
'gfx90a': ('SQ', 291),
|
|
'gfx908': ('SQ', 291),
|
|
'gfx940': ('SQ', 291),
|
|
'gfx941': ('SQ', 291),
|
|
'gfx942': ('SQ', 291),
|
|
'gfx950': ('SQ', 291),
|
|
},
|
|
'SQC_DCACHE_INPUT_VALID_READYB': {
|
|
'gfx90a': ('SQ', 260),
|
|
'gfx908': ('SQ', 260),
|
|
'gfx940': ('SQ', 260),
|
|
'gfx941': ('SQ', 260),
|
|
'gfx942': ('SQ', 260),
|
|
'gfx950': ('SQ', 260),
|
|
},
|
|
'SQC_DCACHE_MISSES': {
|
|
'gfx90a': ('SQ', 292),
|
|
'gfx908': ('SQ', 292),
|
|
'gfx940': ('SQ', 292),
|
|
'gfx941': ('SQ', 292),
|
|
'gfx942': ('SQ', 292),
|
|
'gfx950': ('SQ', 292),
|
|
},
|
|
'SQC_DCACHE_MISSES_DUPLICATE': {
|
|
'gfx90a': ('SQ', 293),
|
|
'gfx908': ('SQ', 293),
|
|
'gfx940': ('SQ', 293),
|
|
'gfx941': ('SQ', 293),
|
|
'gfx942': ('SQ', 293),
|
|
'gfx950': ('SQ', 293),
|
|
},
|
|
'SQC_DCACHE_REQ': {
|
|
'gfx90a': ('SQ', 290),
|
|
'gfx908': ('SQ', 290),
|
|
'gfx940': ('SQ', 290),
|
|
'gfx941': ('SQ', 290),
|
|
'gfx942': ('SQ', 290),
|
|
'gfx950': ('SQ', 290),
|
|
},
|
|
'SQC_DCACHE_REQ_READ_1': {
|
|
'gfx90a': ('SQ', 323),
|
|
'gfx908': ('SQ', 323),
|
|
'gfx940': ('SQ', 323),
|
|
'gfx941': ('SQ', 323),
|
|
'gfx942': ('SQ', 323),
|
|
'gfx950': ('SQ', 323),
|
|
},
|
|
'SQC_DCACHE_REQ_READ_16': {
|
|
'gfx90a': ('SQ', 327),
|
|
'gfx908': ('SQ', 327),
|
|
'gfx940': ('SQ', 327),
|
|
'gfx941': ('SQ', 327),
|
|
'gfx942': ('SQ', 327),
|
|
'gfx950': ('SQ', 327),
|
|
},
|
|
'SQC_DCACHE_REQ_READ_2': {
|
|
'gfx90a': ('SQ', 324),
|
|
'gfx908': ('SQ', 324),
|
|
'gfx940': ('SQ', 324),
|
|
'gfx941': ('SQ', 324),
|
|
'gfx942': ('SQ', 324),
|
|
'gfx950': ('SQ', 324),
|
|
},
|
|
'SQC_DCACHE_REQ_READ_4': {
|
|
'gfx90a': ('SQ', 325),
|
|
'gfx908': ('SQ', 325),
|
|
'gfx940': ('SQ', 325),
|
|
'gfx941': ('SQ', 325),
|
|
'gfx942': ('SQ', 325),
|
|
'gfx950': ('SQ', 325),
|
|
},
|
|
'SQC_DCACHE_REQ_READ_8': {
|
|
'gfx90a': ('SQ', 326),
|
|
'gfx908': ('SQ', 326),
|
|
'gfx940': ('SQ', 326),
|
|
'gfx941': ('SQ', 326),
|
|
'gfx942': ('SQ', 326),
|
|
'gfx950': ('SQ', 326),
|
|
},
|
|
'SQC_ICACHE_BUSY_CYCLES': {
|
|
'gfx940': ('SQ', 269),
|
|
'gfx941': ('SQ', 269),
|
|
'gfx942': ('SQ', 269),
|
|
'gfx950': ('SQ', 269),
|
|
},
|
|
'SQC_ICACHE_HITS': {
|
|
'gfx90a': ('SQ', 271),
|
|
'gfx908': ('SQ', 271),
|
|
'gfx940': ('SQ', 271),
|
|
'gfx941': ('SQ', 271),
|
|
'gfx942': ('SQ', 271),
|
|
'gfx950': ('SQ', 271),
|
|
'gfx12': ('SQ', 302),
|
|
'gfx1200': ('SQ', 302),
|
|
'gfx1201': ('SQ', 302),
|
|
},
|
|
'SQC_ICACHE_INPUT_VALID_READYB': {
|
|
'gfx940': ('SQ', 257),
|
|
'gfx941': ('SQ', 257),
|
|
'gfx942': ('SQ', 257),
|
|
'gfx950': ('SQ', 257),
|
|
},
|
|
'SQC_ICACHE_MISSES': {
|
|
'gfx90a': ('SQ', 272),
|
|
'gfx908': ('SQ', 272),
|
|
'gfx940': ('SQ', 272),
|
|
'gfx941': ('SQ', 272),
|
|
'gfx942': ('SQ', 272),
|
|
'gfx950': ('SQ', 272),
|
|
'gfx12': ('SQ', 303),
|
|
'gfx1200': ('SQ', 303),
|
|
'gfx1201': ('SQ', 303),
|
|
},
|
|
'SQC_ICACHE_MISSES_DUPLICATE': {
|
|
'gfx90a': ('SQ', 273),
|
|
'gfx908': ('SQ', 273),
|
|
'gfx940': ('SQ', 273),
|
|
'gfx941': ('SQ', 273),
|
|
'gfx942': ('SQ', 273),
|
|
'gfx950': ('SQ', 273),
|
|
},
|
|
'SQC_ICACHE_REQ': {
|
|
'gfx90a': ('SQ', 270),
|
|
'gfx908': ('SQ', 270),
|
|
'gfx940': ('SQ', 270),
|
|
'gfx941': ('SQ', 270),
|
|
'gfx942': ('SQ', 270),
|
|
'gfx950': ('SQ', 270),
|
|
'gfx12': ('SQ', 301),
|
|
'gfx1200': ('SQ', 301),
|
|
'gfx1201': ('SQ', 301),
|
|
},
|
|
'SQC_LDS_BANK_CONFLICT': {
|
|
'gfx10': ('SQ', 285),
|
|
'gfx1010': ('SQ', 285),
|
|
'gfx1030': ('SQ', 285),
|
|
'gfx1031': ('SQ', 285),
|
|
'gfx1032': ('SQ', 285),
|
|
'gfx11': ('SQ', 256),
|
|
'gfx1100': ('SQ', 256),
|
|
'gfx1101': ('SQ', 256),
|
|
'gfx1102': ('SQ', 256),
|
|
'gfx12': ('SQ', 288),
|
|
'gfx1200': ('SQ', 288),
|
|
'gfx1201': ('SQ', 288),
|
|
},
|
|
'SQC_LDS_IDX_ACTIVE': {
|
|
'gfx10': ('SQ', 290),
|
|
'gfx1010': ('SQ', 290),
|
|
'gfx1030': ('SQ', 290),
|
|
'gfx1031': ('SQ', 290),
|
|
'gfx1032': ('SQ', 290),
|
|
'gfx11': ('SQ', 261),
|
|
'gfx1100': ('SQ', 261),
|
|
'gfx1101': ('SQ', 261),
|
|
'gfx1102': ('SQ', 261),
|
|
'gfx12': ('SQ', 293),
|
|
'gfx1200': ('SQ', 293),
|
|
'gfx1201': ('SQ', 293),
|
|
},
|
|
'SQC_TC_DATA_ATOMIC_REQ': {
|
|
'gfx90a': ('SQ', 266),
|
|
'gfx908': ('SQ', 266),
|
|
'gfx940': ('SQ', 266),
|
|
'gfx941': ('SQ', 266),
|
|
'gfx942': ('SQ', 266),
|
|
'gfx950': ('SQ', 266),
|
|
},
|
|
'SQC_TC_DATA_READ_REQ': {
|
|
'gfx90a': ('SQ', 264),
|
|
'gfx908': ('SQ', 264),
|
|
'gfx940': ('SQ', 264),
|
|
'gfx941': ('SQ', 264),
|
|
'gfx942': ('SQ', 264),
|
|
'gfx950': ('SQ', 264),
|
|
},
|
|
'SQC_TC_DATA_WRITE_REQ': {
|
|
'gfx90a': ('SQ', 265),
|
|
'gfx908': ('SQ', 265),
|
|
'gfx940': ('SQ', 265),
|
|
'gfx941': ('SQ', 265),
|
|
'gfx942': ('SQ', 265),
|
|
'gfx950': ('SQ', 265),
|
|
},
|
|
'SQC_TC_INST_REQ': {
|
|
'gfx90a': ('SQ', 263),
|
|
'gfx908': ('SQ', 263),
|
|
'gfx940': ('SQ', 263),
|
|
'gfx941': ('SQ', 263),
|
|
'gfx942': ('SQ', 263),
|
|
'gfx950': ('SQ', 263),
|
|
},
|
|
'SQC_TC_REQ': {
|
|
'gfx90a': ('SQ', 262),
|
|
'gfx908': ('SQ', 262),
|
|
'gfx940': ('SQ', 262),
|
|
'gfx941': ('SQ', 262),
|
|
'gfx942': ('SQ', 262),
|
|
'gfx950': ('SQ', 262),
|
|
},
|
|
'SQC_TC_STALL': {
|
|
'gfx90a': ('SQ', 267),
|
|
'gfx908': ('SQ', 267),
|
|
'gfx940': ('SQ', 267),
|
|
'gfx941': ('SQ', 267),
|
|
'gfx942': ('SQ', 267),
|
|
'gfx950': ('SQ', 267),
|
|
},
|
|
'SQ_ACCUM_PREV': {
|
|
'gfx10': ('SQ', 1),
|
|
'gfx1010': ('SQ', 1),
|
|
'gfx1030': ('SQ', 1),
|
|
'gfx1031': ('SQ', 1),
|
|
'gfx1032': ('SQ', 1),
|
|
'gfx11': ('SQ', 1),
|
|
'gfx1100': ('SQ', 1),
|
|
'gfx1101': ('SQ', 1),
|
|
'gfx1102': ('SQ', 1),
|
|
'gfx12': ('SQ', 1),
|
|
'gfx1200': ('SQ', 1),
|
|
'gfx1201': ('SQ', 1),
|
|
'gfx90a': ('SQ', 1),
|
|
'gfx908': ('SQ', 1),
|
|
'gfx940': ('SQ', 1),
|
|
'gfx941': ('SQ', 1),
|
|
'gfx942': ('SQ', 1),
|
|
'gfx950': ('SQ', 1),
|
|
},
|
|
'SQ_ACCUM_PREV_HIRES': {
|
|
'gfx90a': ('SQ', 185),
|
|
'gfx908': ('SQ', 158),
|
|
'gfx940': ('SQ', 184),
|
|
'gfx941': ('SQ', 184),
|
|
'gfx942': ('SQ', 184),
|
|
'gfx950': ('SQ', 200),
|
|
},
|
|
'SQ_ACTIVE_INST_ANY': {
|
|
'gfx90a': ('SQ', 96),
|
|
'gfx908': ('SQ', 69),
|
|
'gfx940': ('SQ', 101),
|
|
'gfx941': ('SQ', 101),
|
|
'gfx942': ('SQ', 101),
|
|
'gfx950': ('SQ', 117),
|
|
},
|
|
'SQ_ACTIVE_INST_EXP_GDS': {
|
|
'gfx90a': ('SQ', 101),
|
|
'gfx908': ('SQ', 74),
|
|
'gfx940': ('SQ', 106),
|
|
'gfx941': ('SQ', 106),
|
|
'gfx942': ('SQ', 106),
|
|
'gfx950': ('SQ', 122),
|
|
},
|
|
'SQ_ACTIVE_INST_FLAT': {
|
|
'gfx90a': ('SQ', 103),
|
|
'gfx908': ('SQ', 76),
|
|
'gfx940': ('SQ', 108),
|
|
'gfx941': ('SQ', 108),
|
|
'gfx942': ('SQ', 108),
|
|
'gfx950': ('SQ', 124),
|
|
},
|
|
'SQ_ACTIVE_INST_LDS': {
|
|
'gfx90a': ('SQ', 98),
|
|
'gfx908': ('SQ', 71),
|
|
'gfx940': ('SQ', 103),
|
|
'gfx941': ('SQ', 103),
|
|
'gfx942': ('SQ', 103),
|
|
'gfx950': ('SQ', 119),
|
|
},
|
|
'SQ_ACTIVE_INST_MISC': {
|
|
'gfx90a': ('SQ', 102),
|
|
'gfx908': ('SQ', 75),
|
|
'gfx940': ('SQ', 107),
|
|
'gfx941': ('SQ', 107),
|
|
'gfx942': ('SQ', 107),
|
|
'gfx950': ('SQ', 123),
|
|
},
|
|
'SQ_ACTIVE_INST_SCA': {
|
|
'gfx90a': ('SQ', 100),
|
|
'gfx908': ('SQ', 73),
|
|
'gfx940': ('SQ', 105),
|
|
'gfx941': ('SQ', 105),
|
|
'gfx942': ('SQ', 105),
|
|
'gfx950': ('SQ', 121),
|
|
},
|
|
'SQ_ACTIVE_INST_VALU': {
|
|
'gfx9': ('SQ', 71),
|
|
'gfx900': ('SQ', 71),
|
|
'gfx906': ('SQ', 71),
|
|
'gfx908': ('SQ', 72),
|
|
'gfx90a': ('SQ', 99),
|
|
'gfx940': ('SQ', 104),
|
|
'gfx941': ('SQ', 104),
|
|
'gfx942': ('SQ', 104),
|
|
'gfx950': ('SQ', 120),
|
|
},
|
|
'SQ_ACTIVE_INST_VMEM': {
|
|
'gfx90a': ('SQ', 97),
|
|
'gfx908': ('SQ', 70),
|
|
'gfx940': ('SQ', 102),
|
|
'gfx941': ('SQ', 102),
|
|
'gfx942': ('SQ', 102),
|
|
'gfx950': ('SQ', 118),
|
|
},
|
|
'SQ_BUSY_CU_CYCLES': {
|
|
'gfx90a': ('SQ', 13),
|
|
'gfx908': ('SQ', 13),
|
|
'gfx940': ('SQ', 13),
|
|
'gfx941': ('SQ', 13),
|
|
'gfx942': ('SQ', 13),
|
|
'gfx950': ('SQ', 13),
|
|
},
|
|
'SQ_BUSY_CYCLES': {
|
|
'gfx10': ('SQ', 3),
|
|
'gfx1010': ('SQ', 3),
|
|
'gfx1030': ('SQ', 3),
|
|
'gfx1031': ('SQ', 3),
|
|
'gfx1032': ('SQ', 3),
|
|
'gfx11': ('SQ', 3),
|
|
'gfx1100': ('SQ', 3),
|
|
'gfx1101': ('SQ', 3),
|
|
'gfx1102': ('SQ', 3),
|
|
'gfx12': ('SQ', 3),
|
|
'gfx1200': ('SQ', 3),
|
|
'gfx1201': ('SQ', 3),
|
|
'gfx90a': ('SQ', 3),
|
|
'gfx908': ('SQ', 3),
|
|
'gfx940': ('SQ', 3),
|
|
'gfx941': ('SQ', 3),
|
|
'gfx942': ('SQ', 3),
|
|
'gfx950': ('SQ', 3),
|
|
},
|
|
'SQ_CYCLES': {
|
|
'gfx90a': ('SQ', 2),
|
|
'gfx908': ('SQ', 2),
|
|
'gfx940': ('SQ', 2),
|
|
'gfx941': ('SQ', 2),
|
|
'gfx942': ('SQ', 2),
|
|
'gfx950': ('SQ', 2),
|
|
},
|
|
'SQ_IFETCH': {
|
|
'gfx90a': ('SQ', 115),
|
|
'gfx908': ('SQ', 88),
|
|
'gfx940': ('SQ', 120),
|
|
'gfx941': ('SQ', 120),
|
|
'gfx942': ('SQ', 120),
|
|
'gfx950': ('SQ', 136),
|
|
},
|
|
'SQ_IFETCH_LEVEL': {
|
|
'gfx90a': ('SQ', 116),
|
|
'gfx908': ('SQ', 89),
|
|
'gfx940': ('SQ', 121),
|
|
'gfx941': ('SQ', 121),
|
|
'gfx942': ('SQ', 121),
|
|
'gfx950': ('SQ', 137),
|
|
},
|
|
'SQ_INSTS': {
|
|
'gfx90a': ('SQ', 25),
|
|
'gfx908': ('SQ', 25),
|
|
'gfx940': ('SQ', 25),
|
|
'gfx941': ('SQ', 25),
|
|
'gfx942': ('SQ', 25),
|
|
'gfx950': ('SQ', 25),
|
|
},
|
|
'SQ_INSTS_BRANCH': {
|
|
'gfx90a': ('SQ', 64),
|
|
'gfx908': ('SQ', 39),
|
|
'gfx940': ('SQ', 69),
|
|
'gfx941': ('SQ', 69),
|
|
'gfx942': ('SQ', 69),
|
|
'gfx950': ('SQ', 71),
|
|
},
|
|
'SQ_INSTS_EXP_GDS': {
|
|
'gfx90a': ('SQ', 63),
|
|
'gfx908': ('SQ', 38),
|
|
'gfx940': ('SQ', 68),
|
|
'gfx941': ('SQ', 68),
|
|
'gfx942': ('SQ', 68),
|
|
'gfx950': ('SQ', 70),
|
|
},
|
|
'SQ_INSTS_FLAT': {
|
|
'gfx10': ('SQ', 57),
|
|
'gfx1010': ('SQ', 57),
|
|
'gfx1030': ('SQ', 57),
|
|
'gfx1031': ('SQ', 57),
|
|
'gfx1032': ('SQ', 57),
|
|
'gfx9': ('SQ', 32),
|
|
'gfx900': ('SQ', 32),
|
|
'gfx906': ('SQ', 32),
|
|
'gfx908': ('SQ', 33),
|
|
'gfx90a': ('SQ', 58),
|
|
'gfx940': ('SQ', 62),
|
|
'gfx941': ('SQ', 62),
|
|
'gfx942': ('SQ', 62),
|
|
'gfx11': ('SQ', 56),
|
|
'gfx1100': ('SQ', 56),
|
|
'gfx1101': ('SQ', 56),
|
|
'gfx1102': ('SQ', 56),
|
|
'gfx12': ('SQ', 44),
|
|
'gfx1200': ('SQ', 44),
|
|
'gfx1201': ('SQ', 44),
|
|
'gfx950': ('SQ', 64),
|
|
},
|
|
'SQ_INSTS_FLAT_LDS_ONLY': {
|
|
'gfx9': ('SQ', 33),
|
|
'gfx900': ('SQ', 33),
|
|
'gfx906': ('SQ', 33),
|
|
'gfx908': ('SQ', 34),
|
|
'gfx90a': ('SQ', 59),
|
|
},
|
|
'SQ_INSTS_GDS': {
|
|
'gfx10': ('SQ', 55),
|
|
'gfx1010': ('SQ', 55),
|
|
'gfx1030': ('SQ', 55),
|
|
'gfx1031': ('SQ', 55),
|
|
'gfx1032': ('SQ', 55),
|
|
'gfx9': ('SQ', 35),
|
|
'gfx900': ('SQ', 35),
|
|
'gfx906': ('SQ', 35),
|
|
'gfx908': ('SQ', 36),
|
|
'gfx90a': ('SQ', 61),
|
|
'gfx940': ('SQ', 66),
|
|
'gfx941': ('SQ', 66),
|
|
'gfx942': ('SQ', 66),
|
|
'gfx11': ('SQ', 54),
|
|
'gfx1100': ('SQ', 54),
|
|
'gfx1101': ('SQ', 54),
|
|
'gfx1102': ('SQ', 54),
|
|
'gfx950': ('SQ', 68),
|
|
},
|
|
'SQ_INSTS_LDS': {
|
|
'gfx10': ('SQ', 59),
|
|
'gfx1010': ('SQ', 59),
|
|
'gfx1030': ('SQ', 59),
|
|
'gfx1031': ('SQ', 59),
|
|
'gfx1032': ('SQ', 59),
|
|
'gfx9': ('SQ', 34),
|
|
'gfx900': ('SQ', 34),
|
|
'gfx906': ('SQ', 34),
|
|
'gfx908': ('SQ', 35),
|
|
'gfx90a': ('SQ', 60),
|
|
'gfx940': ('SQ', 65),
|
|
'gfx941': ('SQ', 65),
|
|
'gfx942': ('SQ', 65),
|
|
'gfx11': ('SQ', 57),
|
|
'gfx1100': ('SQ', 57),
|
|
'gfx1101': ('SQ', 57),
|
|
'gfx1102': ('SQ', 57),
|
|
'gfx12': ('SQ', 45),
|
|
'gfx1200': ('SQ', 45),
|
|
'gfx1201': ('SQ', 45),
|
|
'gfx950': ('SQ', 67),
|
|
},
|
|
'SQ_INSTS_MFMA': {
|
|
'gfx90a': ('SQ', 52),
|
|
'gfx908': ('SQ', 27),
|
|
'gfx940': ('SQ', 56),
|
|
'gfx941': ('SQ', 56),
|
|
'gfx942': ('SQ', 56),
|
|
'gfx950': ('SQ', 58),
|
|
},
|
|
'SQ_INSTS_SALU': {
|
|
'gfx9': ('SQ', 30),
|
|
'gfx900': ('SQ', 30),
|
|
'gfx906': ('SQ', 30),
|
|
'gfx908': ('SQ', 31),
|
|
'gfx90a': ('SQ', 56),
|
|
'gfx10': ('SQ', 60),
|
|
'gfx1010': ('SQ', 60),
|
|
'gfx1030': ('SQ', 60),
|
|
'gfx1031': ('SQ', 60),
|
|
'gfx1032': ('SQ', 60),
|
|
'gfx940': ('SQ', 60),
|
|
'gfx941': ('SQ', 60),
|
|
'gfx942': ('SQ', 60),
|
|
'gfx11': ('SQ', 58),
|
|
'gfx1100': ('SQ', 58),
|
|
'gfx1101': ('SQ', 58),
|
|
'gfx1102': ('SQ', 58),
|
|
'gfx12': ('SQ', 46),
|
|
'gfx1200': ('SQ', 46),
|
|
'gfx1201': ('SQ', 46),
|
|
'gfx950': ('SQ', 62),
|
|
},
|
|
'SQ_INSTS_SENDMSG': {
|
|
'gfx90a': ('SQ', 65),
|
|
'gfx908': ('SQ', 40),
|
|
'gfx940': ('SQ', 70),
|
|
'gfx941': ('SQ', 70),
|
|
'gfx942': ('SQ', 70),
|
|
'gfx950': ('SQ', 72),
|
|
},
|
|
'SQ_INSTS_SMEM': {
|
|
'gfx9': ('SQ', 31),
|
|
'gfx900': ('SQ', 31),
|
|
'gfx906': ('SQ', 31),
|
|
'gfx908': ('SQ', 32),
|
|
'gfx90a': ('SQ', 57),
|
|
'gfx10': ('SQ', 61),
|
|
'gfx1010': ('SQ', 61),
|
|
'gfx1030': ('SQ', 61),
|
|
'gfx1031': ('SQ', 61),
|
|
'gfx1032': ('SQ', 61),
|
|
'gfx940': ('SQ', 61),
|
|
'gfx941': ('SQ', 61),
|
|
'gfx942': ('SQ', 61),
|
|
'gfx11': ('SQ', 59),
|
|
'gfx1100': ('SQ', 59),
|
|
'gfx1101': ('SQ', 59),
|
|
'gfx1102': ('SQ', 59),
|
|
'gfx12': ('SQ', 47),
|
|
'gfx1200': ('SQ', 47),
|
|
'gfx1201': ('SQ', 47),
|
|
'gfx950': ('SQ', 63),
|
|
},
|
|
'SQ_INSTS_SMEM_NORM': {
|
|
'gfx90a': ('SQ', 188),
|
|
'gfx908': ('SQ', 161),
|
|
'gfx940': ('SQ', 187),
|
|
'gfx941': ('SQ', 187),
|
|
'gfx942': ('SQ', 187),
|
|
'gfx950': ('SQ', 203),
|
|
},
|
|
'SQ_INSTS_TEX_LOAD': {
|
|
'gfx11': ('SQ', 66),
|
|
'gfx1100': ('SQ', 66),
|
|
'gfx1101': ('SQ', 66),
|
|
'gfx1102': ('SQ', 66),
|
|
'gfx12': ('SQ', 54),
|
|
'gfx1200': ('SQ', 54),
|
|
'gfx1201': ('SQ', 54),
|
|
},
|
|
'SQ_INSTS_TEX_STORE': {
|
|
'gfx11': ('SQ', 67),
|
|
'gfx1100': ('SQ', 67),
|
|
'gfx1101': ('SQ', 67),
|
|
'gfx1102': ('SQ', 67),
|
|
'gfx12': ('SQ', 55),
|
|
'gfx1200': ('SQ', 55),
|
|
'gfx1201': ('SQ', 55),
|
|
},
|
|
'SQ_INSTS_VALU': {
|
|
'gfx10': ('SQ', 64),
|
|
'gfx1010': ('SQ', 64),
|
|
'gfx1030': ('SQ', 64),
|
|
'gfx1031': ('SQ', 64),
|
|
'gfx1032': ('SQ', 64),
|
|
'gfx9': ('SQ', 26),
|
|
'gfx900': ('SQ', 26),
|
|
'gfx906': ('SQ', 26),
|
|
'gfx908': ('SQ', 26),
|
|
'gfx90a': ('SQ', 26),
|
|
'gfx940': ('SQ', 26),
|
|
'gfx941': ('SQ', 26),
|
|
'gfx942': ('SQ', 26),
|
|
'gfx950': ('SQ', 26),
|
|
'gfx11': ('SQ', 62),
|
|
'gfx1100': ('SQ', 62),
|
|
'gfx1101': ('SQ', 62),
|
|
'gfx1102': ('SQ', 62),
|
|
'gfx12': ('SQ', 50),
|
|
'gfx1200': ('SQ', 50),
|
|
'gfx1201': ('SQ', 50),
|
|
},
|
|
'SQ_INSTS_VALU_ADD_F16': {
|
|
'gfx90a': ('SQ', 27),
|
|
'gfx940': ('SQ', 27),
|
|
'gfx941': ('SQ', 27),
|
|
'gfx942': ('SQ', 27),
|
|
'gfx950': ('SQ', 27),
|
|
},
|
|
'SQ_INSTS_VALU_ADD_F32': {
|
|
'gfx90a': ('SQ', 31),
|
|
'gfx940': ('SQ', 31),
|
|
'gfx941': ('SQ', 31),
|
|
'gfx942': ('SQ', 31),
|
|
'gfx950': ('SQ', 31),
|
|
},
|
|
'SQ_INSTS_VALU_ADD_F64': {
|
|
'gfx90a': ('SQ', 35),
|
|
'gfx940': ('SQ', 35),
|
|
'gfx941': ('SQ', 35),
|
|
'gfx942': ('SQ', 35),
|
|
'gfx950': ('SQ', 35),
|
|
},
|
|
'SQ_INSTS_VALU_CVT': {
|
|
'gfx90a': ('SQ', 41),
|
|
'gfx940': ('SQ', 41),
|
|
'gfx941': ('SQ', 41),
|
|
'gfx942': ('SQ', 41),
|
|
'gfx950': ('SQ', 41),
|
|
},
|
|
'SQ_INSTS_VALU_FMA_F16': {
|
|
'gfx90a': ('SQ', 29),
|
|
'gfx940': ('SQ', 29),
|
|
'gfx941': ('SQ', 29),
|
|
'gfx942': ('SQ', 29),
|
|
'gfx950': ('SQ', 29),
|
|
},
|
|
'SQ_INSTS_VALU_FMA_F32': {
|
|
'gfx90a': ('SQ', 33),
|
|
'gfx940': ('SQ', 33),
|
|
'gfx941': ('SQ', 33),
|
|
'gfx942': ('SQ', 33),
|
|
'gfx950': ('SQ', 33),
|
|
},
|
|
'SQ_INSTS_VALU_FMA_F64': {
|
|
'gfx90a': ('SQ', 37),
|
|
'gfx940': ('SQ', 37),
|
|
'gfx941': ('SQ', 37),
|
|
'gfx942': ('SQ', 37),
|
|
'gfx950': ('SQ', 37),
|
|
},
|
|
'SQ_INSTS_VALU_INT32': {
|
|
'gfx90a': ('SQ', 39),
|
|
'gfx940': ('SQ', 39),
|
|
'gfx941': ('SQ', 39),
|
|
'gfx942': ('SQ', 39),
|
|
'gfx950': ('SQ', 39),
|
|
},
|
|
'SQ_INSTS_VALU_INT64': {
|
|
'gfx90a': ('SQ', 40),
|
|
'gfx940': ('SQ', 40),
|
|
'gfx941': ('SQ', 40),
|
|
'gfx942': ('SQ', 40),
|
|
'gfx950': ('SQ', 40),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_BF16': {
|
|
'gfx90a': ('SQ', 44),
|
|
'gfx940': ('SQ', 44),
|
|
'gfx941': ('SQ', 44),
|
|
'gfx942': ('SQ', 44),
|
|
'gfx950': ('SQ', 44),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_F16': {
|
|
'gfx90a': ('SQ', 43),
|
|
'gfx940': ('SQ', 43),
|
|
'gfx941': ('SQ', 43),
|
|
'gfx942': ('SQ', 43),
|
|
'gfx950': ('SQ', 43),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_F32': {
|
|
'gfx90a': ('SQ', 45),
|
|
'gfx940': ('SQ', 45),
|
|
'gfx941': ('SQ', 45),
|
|
'gfx942': ('SQ', 45),
|
|
'gfx950': ('SQ', 45),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_F64': {
|
|
'gfx90a': ('SQ', 46),
|
|
'gfx940': ('SQ', 46),
|
|
'gfx941': ('SQ', 46),
|
|
'gfx942': ('SQ', 46),
|
|
'gfx950': ('SQ', 46),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_I8': {
|
|
'gfx90a': ('SQ', 42),
|
|
'gfx940': ('SQ', 42),
|
|
'gfx941': ('SQ', 42),
|
|
'gfx942': ('SQ', 42),
|
|
'gfx950': ('SQ', 42),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_F8': {
|
|
'gfx940': ('SQ', 48),
|
|
'gfx941': ('SQ', 48),
|
|
'gfx942': ('SQ', 48),
|
|
'gfx950': ('SQ', 48),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_XF32': {
|
|
'gfx950': ('SQ', 47),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_MOPS_BF16': {
|
|
'gfx90a': ('SQ', 49),
|
|
'gfx940': ('SQ', 51),
|
|
'gfx941': ('SQ', 51),
|
|
'gfx942': ('SQ', 51),
|
|
'gfx950': ('SQ', 52),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_MOPS_F16': {
|
|
'gfx90a': ('SQ', 48),
|
|
'gfx940': ('SQ', 50),
|
|
'gfx941': ('SQ', 50),
|
|
'gfx942': ('SQ', 50),
|
|
'gfx950': ('SQ', 51),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_MOPS_F32': {
|
|
'gfx90a': ('SQ', 50),
|
|
'gfx940': ('SQ', 52),
|
|
'gfx941': ('SQ', 52),
|
|
'gfx942': ('SQ', 52),
|
|
'gfx950': ('SQ', 53),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_MOPS_F64': {
|
|
'gfx90a': ('SQ', 51),
|
|
'gfx940': ('SQ', 53),
|
|
'gfx941': ('SQ', 53),
|
|
'gfx942': ('SQ', 53),
|
|
'gfx950': ('SQ', 54),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_MOPS_I8': {
|
|
'gfx90a': ('SQ', 47),
|
|
'gfx940': ('SQ', 49),
|
|
'gfx941': ('SQ', 49),
|
|
'gfx942': ('SQ', 49),
|
|
'gfx950': ('SQ', 50),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_MOPS_F8': {
|
|
'gfx940': ('SQ', 55),
|
|
'gfx941': ('SQ', 55),
|
|
'gfx942': ('SQ', 55),
|
|
'gfx950': ('SQ', 56),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_MOPS_XF32': {
|
|
'gfx950': ('SQ', 55),
|
|
},
|
|
'SQ_VALU_MFMA_COEXEC_CYCLES': {
|
|
'gfx950': ('SQ', 94),
|
|
},
|
|
'SQ_INSTS_VALU_MUL_F16': {
|
|
'gfx90a': ('SQ', 28),
|
|
'gfx940': ('SQ', 28),
|
|
'gfx941': ('SQ', 28),
|
|
'gfx942': ('SQ', 28),
|
|
'gfx950': ('SQ', 28),
|
|
},
|
|
'SQ_INSTS_VALU_MUL_F32': {
|
|
'gfx90a': ('SQ', 32),
|
|
'gfx940': ('SQ', 32),
|
|
'gfx941': ('SQ', 32),
|
|
'gfx942': ('SQ', 32),
|
|
'gfx950': ('SQ', 32),
|
|
},
|
|
'SQ_INSTS_VALU_MUL_F64': {
|
|
'gfx90a': ('SQ', 36),
|
|
'gfx940': ('SQ', 36),
|
|
'gfx941': ('SQ', 36),
|
|
'gfx942': ('SQ', 36),
|
|
'gfx950': ('SQ', 36),
|
|
},
|
|
'SQ_INSTS_VALU_TRANS_F16': {
|
|
'gfx90a': ('SQ', 30),
|
|
'gfx940': ('SQ', 30),
|
|
'gfx941': ('SQ', 30),
|
|
'gfx942': ('SQ', 30),
|
|
'gfx950': ('SQ', 30),
|
|
},
|
|
'SQ_INSTS_VALU_TRANS_F32': {
|
|
'gfx90a': ('SQ', 34),
|
|
'gfx940': ('SQ', 34),
|
|
'gfx941': ('SQ', 34),
|
|
'gfx942': ('SQ', 34),
|
|
'gfx950': ('SQ', 34),
|
|
},
|
|
'SQ_INSTS_VALU_TRANS_F64': {
|
|
'gfx90a': ('SQ', 38),
|
|
'gfx940': ('SQ', 38),
|
|
'gfx941': ('SQ', 38),
|
|
'gfx942': ('SQ', 38),
|
|
'gfx950': ('SQ', 38),
|
|
},
|
|
'SQ_INSTS_VMEM': {
|
|
'gfx90a': ('SQ', 55),
|
|
'gfx908': ('SQ', 30),
|
|
'gfx940': ('SQ', 59),
|
|
'gfx941': ('SQ', 59),
|
|
'gfx942': ('SQ', 59),
|
|
'gfx950': ('SQ', 61),
|
|
},
|
|
'SQ_INSTS_VMEM_RD': {
|
|
'gfx9': ('SQ', 28),
|
|
'gfx900': ('SQ', 28),
|
|
'gfx906': ('SQ', 28),
|
|
'gfx908': ('SQ', 29),
|
|
'gfx90a': ('SQ', 54),
|
|
'gfx940': ('SQ', 58),
|
|
'gfx941': ('SQ', 58),
|
|
'gfx942': ('SQ', 58),
|
|
'gfx950': ('SQ', 60),
|
|
},
|
|
'SQ_INSTS_VMEM_WR': {
|
|
'gfx9': ('SQ', 27),
|
|
'gfx900': ('SQ', 27),
|
|
'gfx906': ('SQ', 27),
|
|
'gfx908': ('SQ', 28),
|
|
'gfx90a': ('SQ', 53),
|
|
'gfx940': ('SQ', 57),
|
|
'gfx941': ('SQ', 57),
|
|
'gfx942': ('SQ', 57),
|
|
'gfx950': ('SQ', 59),
|
|
},
|
|
'SQ_INSTS_VSKIPPED': {
|
|
'gfx90a': ('SQ', 66),
|
|
'gfx908': ('SQ', 41),
|
|
'gfx940': ('SQ', 71),
|
|
'gfx941': ('SQ', 71),
|
|
'gfx942': ('SQ', 71),
|
|
'gfx950': ('SQ', 73),
|
|
},
|
|
'SQ_INSTS_WAVE32': {
|
|
'gfx10': ('SQ', 71),
|
|
'gfx1010': ('SQ', 71),
|
|
'gfx1030': ('SQ', 71),
|
|
'gfx1031': ('SQ', 71),
|
|
'gfx1032': ('SQ', 71),
|
|
'gfx11': ('SQ', 70),
|
|
'gfx1100': ('SQ', 70),
|
|
'gfx1101': ('SQ', 70),
|
|
'gfx1102': ('SQ', 70),
|
|
'gfx12': ('SQ', 58),
|
|
'gfx1200': ('SQ', 58),
|
|
'gfx1201': ('SQ', 58),
|
|
},
|
|
'SQ_INSTS_WAVE32_LDS': {
|
|
'gfx10': ('SQ', 74),
|
|
'gfx1010': ('SQ', 74),
|
|
'gfx1030': ('SQ', 74),
|
|
'gfx1031': ('SQ', 74),
|
|
'gfx1032': ('SQ', 74),
|
|
'gfx11': ('SQ', 72),
|
|
'gfx1100': ('SQ', 72),
|
|
'gfx1101': ('SQ', 72),
|
|
'gfx1102': ('SQ', 72),
|
|
'gfx12': ('SQ', 60),
|
|
'gfx1200': ('SQ', 60),
|
|
'gfx1201': ('SQ', 60),
|
|
},
|
|
'SQ_INSTS_WAVE32_VALU': {
|
|
'gfx10': ('SQ', 75),
|
|
'gfx1010': ('SQ', 75),
|
|
'gfx1030': ('SQ', 75),
|
|
'gfx1031': ('SQ', 75),
|
|
'gfx1032': ('SQ', 75),
|
|
'gfx11': ('SQ', 73),
|
|
'gfx1100': ('SQ', 73),
|
|
'gfx1101': ('SQ', 73),
|
|
'gfx1102': ('SQ', 73),
|
|
'gfx12': ('SQ', 61),
|
|
'gfx1200': ('SQ', 61),
|
|
'gfx1201': ('SQ', 61),
|
|
},
|
|
'SQ_INST_CYCLES_VALU': {
|
|
'gfx12': ('SQ', 99),
|
|
'gfx1200': ('SQ', 99),
|
|
'gfx1201': ('SQ', 99),
|
|
},
|
|
'SQ_INST_CYCLES_SALU': {
|
|
'gfx9': ('SQ', 84),
|
|
'gfx900': ('SQ', 84),
|
|
'gfx906': ('SQ', 84),
|
|
'gfx908': ('SQ', 85),
|
|
'gfx90a': ('SQ', 112),
|
|
'gfx940': ('SQ', 117),
|
|
'gfx941': ('SQ', 117),
|
|
'gfx942': ('SQ', 117),
|
|
'gfx950': ('SQ', 133),
|
|
},
|
|
'SQ_INST_CYCLES_SMEM': {
|
|
'gfx90a': ('SQ', 111),
|
|
'gfx908': ('SQ', 84),
|
|
'gfx940': ('SQ', 116),
|
|
'gfx941': ('SQ', 116),
|
|
'gfx942': ('SQ', 116),
|
|
'gfx950': ('SQ', 132),
|
|
},
|
|
'SQ_INST_CYCLES_VMEM': {
|
|
'gfx10': ('SQ', 120),
|
|
'gfx1010': ('SQ', 120),
|
|
'gfx1030': ('SQ', 120),
|
|
'gfx1031': ('SQ', 120),
|
|
'gfx1032': ('SQ', 120),
|
|
'gfx11': ('SQ', 106),
|
|
'gfx1100': ('SQ', 106),
|
|
'gfx1101': ('SQ', 106),
|
|
'gfx1102': ('SQ', 106),
|
|
'gfx12': ('SQ', 102),
|
|
'gfx1200': ('SQ', 102),
|
|
'gfx1201': ('SQ', 102),
|
|
},
|
|
'SQ_INST_CYCLES_VMEM_RD': {
|
|
'gfx90a': ('SQ', 105),
|
|
'gfx908': ('SQ', 78),
|
|
'gfx940': ('SQ', 110),
|
|
'gfx941': ('SQ', 110),
|
|
'gfx942': ('SQ', 110),
|
|
'gfx950': ('SQ', 126),
|
|
},
|
|
'SQ_INST_CYCLES_VMEM_WR': {
|
|
'gfx90a': ('SQ', 104),
|
|
'gfx908': ('SQ', 77),
|
|
'gfx940': ('SQ', 109),
|
|
'gfx941': ('SQ', 109),
|
|
'gfx942': ('SQ', 109),
|
|
'gfx950': ('SQ', 125),
|
|
},
|
|
'SQ_INST_LEVEL_GDS': {
|
|
'gfx10': ('SQ', 98),
|
|
'gfx1010': ('SQ', 98),
|
|
'gfx1030': ('SQ', 98),
|
|
'gfx1031': ('SQ', 98),
|
|
'gfx1032': ('SQ', 98),
|
|
'gfx11': ('SQ', 87),
|
|
'gfx1100': ('SQ', 87),
|
|
'gfx1101': ('SQ', 87),
|
|
'gfx1102': ('SQ', 87),
|
|
},
|
|
'SQ_INST_LEVEL_LDS': {
|
|
'gfx10': ('SQ', 99),
|
|
'gfx1010': ('SQ', 99),
|
|
'gfx1030': ('SQ', 99),
|
|
'gfx1031': ('SQ', 99),
|
|
'gfx1032': ('SQ', 99),
|
|
'gfx90a': ('SQ', 69),
|
|
'gfx908': ('SQ', 44),
|
|
'gfx940': ('SQ', 74),
|
|
'gfx941': ('SQ', 74),
|
|
'gfx942': ('SQ', 74),
|
|
'gfx11': ('SQ', 88),
|
|
'gfx1100': ('SQ', 88),
|
|
'gfx1101': ('SQ', 88),
|
|
'gfx1102': ('SQ', 88),
|
|
'gfx12': ('SQ', 75),
|
|
'gfx1200': ('SQ', 75),
|
|
'gfx1201': ('SQ', 75),
|
|
'gfx950': ('SQ', 90),
|
|
},
|
|
'SQ_INST_LEVEL_SMEM': {
|
|
'gfx90a': ('SQ', 68),
|
|
'gfx908': ('SQ', 43),
|
|
'gfx940': ('SQ', 73),
|
|
'gfx941': ('SQ', 73),
|
|
'gfx942': ('SQ', 73),
|
|
'gfx950': ('SQ', 89),
|
|
},
|
|
'SQ_INST_LEVEL_VMEM': {
|
|
'gfx90a': ('SQ', 67),
|
|
'gfx908': ('SQ', 42),
|
|
'gfx940': ('SQ', 72),
|
|
'gfx941': ('SQ', 72),
|
|
'gfx942': ('SQ', 72),
|
|
'gfx950': ('SQ', 88),
|
|
},
|
|
'SQ_ITEMS': {
|
|
'gfx90a': ('SQ', 14),
|
|
'gfx908': ('SQ', 14),
|
|
'gfx940': ('SQ', 14),
|
|
'gfx941': ('SQ', 14),
|
|
'gfx942': ('SQ', 14),
|
|
'gfx950': ('SQ', 14),
|
|
},
|
|
'SQ_LDS_ADDR_CONFLICT': {
|
|
'gfx90a': ('SQ', 122),
|
|
'gfx908': ('SQ', 95),
|
|
'gfx940': ('SQ', 127),
|
|
'gfx941': ('SQ', 127),
|
|
'gfx942': ('SQ', 127),
|
|
'gfx950': ('SQ', 143),
|
|
},
|
|
'SQ_LDS_ATOMIC_RETURN': {
|
|
'gfx90a': ('SQ', 125),
|
|
'gfx908': ('SQ', 98),
|
|
'gfx940': ('SQ', 130),
|
|
'gfx941': ('SQ', 130),
|
|
'gfx942': ('SQ', 130),
|
|
'gfx950': ('SQ', 146),
|
|
},
|
|
'SQ_LDS_BANK_CONFLICT': {
|
|
'gfx9': ('SQ', 93),
|
|
'gfx900': ('SQ', 93),
|
|
'gfx906': ('SQ', 93),
|
|
'gfx908': ('SQ', 94),
|
|
'gfx90a': ('SQ', 121),
|
|
'gfx940': ('SQ', 126),
|
|
'gfx941': ('SQ', 126),
|
|
'gfx942': ('SQ', 126),
|
|
'gfx950': ('SQ', 142),
|
|
},
|
|
'SQ_LDS_IDX_ACTIVE': {
|
|
'gfx90a': ('SQ', 126),
|
|
'gfx908': ('SQ', 99),
|
|
'gfx940': ('SQ', 131),
|
|
'gfx941': ('SQ', 131),
|
|
'gfx942': ('SQ', 131),
|
|
'gfx950': ('SQ', 147),
|
|
},
|
|
'SQ_LDS_MEM_VIOLATIONS': {
|
|
'gfx90a': ('SQ', 124),
|
|
'gfx908': ('SQ', 97),
|
|
'gfx940': ('SQ', 129),
|
|
'gfx941': ('SQ', 129),
|
|
'gfx942': ('SQ', 129),
|
|
'gfx950': ('SQ', 145),
|
|
},
|
|
'SQ_LDS_UNALIGNED_STALL': {
|
|
'gfx90a': ('SQ', 123),
|
|
'gfx908': ('SQ', 96),
|
|
'gfx940': ('SQ', 128),
|
|
'gfx941': ('SQ', 128),
|
|
'gfx942': ('SQ', 128),
|
|
'gfx950': ('SQ', 144),
|
|
},
|
|
'SQ_LEVEL_WAVES': {
|
|
'gfx10': ('SQ', 7),
|
|
'gfx1010': ('SQ', 7),
|
|
'gfx1030': ('SQ', 7),
|
|
'gfx1031': ('SQ', 7),
|
|
'gfx1032': ('SQ', 7),
|
|
'gfx90a': ('SQ', 5),
|
|
'gfx908': ('SQ', 5),
|
|
'gfx940': ('SQ', 5),
|
|
'gfx941': ('SQ', 5),
|
|
'gfx942': ('SQ', 5),
|
|
'gfx950': ('SQ', 5),
|
|
},
|
|
'SQ_THREAD_CYCLES_VALU': {
|
|
'gfx9': ('SQ', 85),
|
|
'gfx900': ('SQ', 85),
|
|
'gfx906': ('SQ', 85),
|
|
'gfx908': ('SQ', 86),
|
|
'gfx90a': ('SQ', 113),
|
|
'gfx940': ('SQ', 118),
|
|
'gfx941': ('SQ', 118),
|
|
'gfx942': ('SQ', 118),
|
|
'gfx950': ('SQ', 134),
|
|
},
|
|
'SQ_VALU_MFMA_BUSY_CYCLES': {
|
|
'gfx90a': ('SQ', 72),
|
|
'gfx940': ('SQ', 77),
|
|
'gfx941': ('SQ', 77),
|
|
'gfx942': ('SQ', 77),
|
|
'gfx950': ('SQ', 93),
|
|
},
|
|
'SQ_WAIT_ANY': {
|
|
'gfx10': ('SQ', 37),
|
|
'gfx1010': ('SQ', 37),
|
|
'gfx1030': ('SQ', 37),
|
|
'gfx1031': ('SQ', 37),
|
|
'gfx1032': ('SQ', 37),
|
|
'gfx90a': ('SQ', 85),
|
|
'gfx908': ('SQ', 58),
|
|
'gfx940': ('SQ', 90),
|
|
'gfx941': ('SQ', 90),
|
|
'gfx942': ('SQ', 90),
|
|
'gfx11': ('SQ', 35),
|
|
'gfx1100': ('SQ', 35),
|
|
'gfx1101': ('SQ', 35),
|
|
'gfx1102': ('SQ', 35),
|
|
'gfx12': ('SQ', 27),
|
|
'gfx1200': ('SQ', 27),
|
|
'gfx1201': ('SQ', 27),
|
|
'gfx950': ('SQ', 106),
|
|
},
|
|
'SQ_WAIT_INST_ANY': {
|
|
'gfx10': ('SQ', 28),
|
|
'gfx1010': ('SQ', 28),
|
|
'gfx1030': ('SQ', 28),
|
|
'gfx1031': ('SQ', 28),
|
|
'gfx1032': ('SQ', 28),
|
|
'gfx90a': ('SQ', 88),
|
|
'gfx908': ('SQ', 61),
|
|
'gfx940': ('SQ', 93),
|
|
'gfx941': ('SQ', 93),
|
|
'gfx942': ('SQ', 93),
|
|
'gfx11': ('SQ', 26),
|
|
'gfx1100': ('SQ', 26),
|
|
'gfx1101': ('SQ', 26),
|
|
'gfx1102': ('SQ', 26),
|
|
'gfx12': ('SQ', 26),
|
|
'gfx1200': ('SQ', 26),
|
|
'gfx1201': ('SQ', 26),
|
|
'gfx950': ('SQ', 109),
|
|
},
|
|
'SQ_WAIT_INST_LDS': {
|
|
'gfx10': ('SQ', 31),
|
|
'gfx1010': ('SQ', 31),
|
|
'gfx1030': ('SQ', 31),
|
|
'gfx1031': ('SQ', 31),
|
|
'gfx1032': ('SQ', 31),
|
|
'gfx9': ('SQ', 63),
|
|
'gfx900': ('SQ', 63),
|
|
'gfx906': ('SQ', 63),
|
|
'gfx908': ('SQ', 64),
|
|
'gfx90a': ('SQ', 91),
|
|
'gfx940': ('SQ', 96),
|
|
'gfx941': ('SQ', 96),
|
|
'gfx942': ('SQ', 96),
|
|
'gfx11': ('SQ', 29),
|
|
'gfx1100': ('SQ', 29),
|
|
'gfx1101': ('SQ', 29),
|
|
'gfx1102': ('SQ', 29),
|
|
'gfx950': ('SQ', 112),
|
|
},
|
|
'SQ_WAVE32_INSTS': {
|
|
'gfx10': ('SQ', 84),
|
|
'gfx1010': ('SQ', 84),
|
|
'gfx1030': ('SQ', 84),
|
|
'gfx1031': ('SQ', 84),
|
|
'gfx1032': ('SQ', 84),
|
|
'gfx11': ('SQ', 82),
|
|
'gfx1100': ('SQ', 82),
|
|
'gfx1101': ('SQ', 82),
|
|
'gfx1102': ('SQ', 82),
|
|
'gfx12': ('SQ', 70),
|
|
'gfx1200': ('SQ', 70),
|
|
'gfx1201': ('SQ', 70),
|
|
},
|
|
'SQ_WAVE64_INSTS': {
|
|
'gfx10': ('SQ', 85),
|
|
'gfx1010': ('SQ', 85),
|
|
'gfx1030': ('SQ', 85),
|
|
'gfx1031': ('SQ', 85),
|
|
'gfx1032': ('SQ', 85),
|
|
'gfx11': ('SQ', 83),
|
|
'gfx1100': ('SQ', 83),
|
|
'gfx1101': ('SQ', 83),
|
|
'gfx1102': ('SQ', 83),
|
|
'gfx12': ('SQ', 71),
|
|
'gfx1200': ('SQ', 71),
|
|
'gfx1201': ('SQ', 71),
|
|
},
|
|
'SQ_WAVES': {
|
|
'gfx10': ('SQ', 4),
|
|
'gfx1010': ('SQ', 4),
|
|
'gfx1030': ('SQ', 4),
|
|
'gfx1031': ('SQ', 4),
|
|
'gfx1032': ('SQ', 4),
|
|
'gfx11': ('SQ', 4),
|
|
'gfx1100': ('SQ', 4),
|
|
'gfx1101': ('SQ', 4),
|
|
'gfx1102': ('SQ', 4),
|
|
'gfx12': ('SQ', 4),
|
|
'gfx1200': ('SQ', 4),
|
|
'gfx1201': ('SQ', 4),
|
|
'gfx9': ('SQ', 4),
|
|
'gfx900': ('SQ', 4),
|
|
'gfx906': ('SQ', 4),
|
|
'gfx908': ('SQ', 4),
|
|
'gfx90a': ('SQ', 4),
|
|
'gfx940': ('SQ', 4),
|
|
'gfx941': ('SQ', 4),
|
|
'gfx942': ('SQ', 4),
|
|
'gfx950': ('SQ', 4),
|
|
},
|
|
'SQ_WAVES_EQ_64': {
|
|
'gfx90a': ('SQ', 6),
|
|
'gfx908': ('SQ', 6),
|
|
'gfx940': ('SQ', 6),
|
|
'gfx941': ('SQ', 6),
|
|
'gfx942': ('SQ', 6),
|
|
'gfx950': ('SQ', 6),
|
|
},
|
|
'SQ_WAVES_LT_16': {
|
|
'gfx90a': ('SQ', 10),
|
|
'gfx908': ('SQ', 10),
|
|
'gfx940': ('SQ', 10),
|
|
'gfx941': ('SQ', 10),
|
|
'gfx942': ('SQ', 10),
|
|
'gfx950': ('SQ', 10),
|
|
},
|
|
'SQ_WAVES_LT_32': {
|
|
'gfx90a': ('SQ', 9),
|
|
'gfx908': ('SQ', 9),
|
|
'gfx940': ('SQ', 9),
|
|
'gfx941': ('SQ', 9),
|
|
'gfx942': ('SQ', 9),
|
|
'gfx950': ('SQ', 9),
|
|
},
|
|
'SQ_WAVES_LT_48': {
|
|
'gfx90a': ('SQ', 8),
|
|
'gfx908': ('SQ', 8),
|
|
'gfx940': ('SQ', 8),
|
|
'gfx941': ('SQ', 8),
|
|
'gfx942': ('SQ', 8),
|
|
'gfx950': ('SQ', 8),
|
|
},
|
|
'SQ_WAVES_LT_64': {
|
|
'gfx90a': ('SQ', 7),
|
|
'gfx908': ('SQ', 7),
|
|
'gfx940': ('SQ', 7),
|
|
'gfx941': ('SQ', 7),
|
|
'gfx942': ('SQ', 7),
|
|
'gfx950': ('SQ', 7),
|
|
},
|
|
'SQ_WAVES_RESTORED': {
|
|
'gfx90a': ('SQ', 186),
|
|
'gfx908': ('SQ', 159),
|
|
'gfx940': ('SQ', 185),
|
|
'gfx941': ('SQ', 185),
|
|
'gfx942': ('SQ', 185),
|
|
'gfx950': ('SQ', 201),
|
|
},
|
|
'SQ_WAVES_SAVED': {
|
|
'gfx90a': ('SQ', 187),
|
|
'gfx908': ('SQ', 160),
|
|
'gfx940': ('SQ', 186),
|
|
'gfx941': ('SQ', 186),
|
|
'gfx942': ('SQ', 186),
|
|
'gfx950': ('SQ', 202),
|
|
},
|
|
'SQ_WAVE_CYCLES': {
|
|
'gfx10': ('SQ', 26),
|
|
'gfx1010': ('SQ', 26),
|
|
'gfx1030': ('SQ', 26),
|
|
'gfx1031': ('SQ', 26),
|
|
'gfx1032': ('SQ', 26),
|
|
'gfx90a': ('SQ', 74),
|
|
'gfx908': ('SQ', 47),
|
|
'gfx940': ('SQ', 79),
|
|
'gfx941': ('SQ', 79),
|
|
'gfx942': ('SQ', 79),
|
|
'gfx11': ('SQ', 24),
|
|
'gfx1100': ('SQ', 24),
|
|
'gfx1101': ('SQ', 24),
|
|
'gfx1102': ('SQ', 24),
|
|
'gfx12': ('SQ', 24),
|
|
'gfx1200': ('SQ', 24),
|
|
'gfx1201': ('SQ', 24),
|
|
'gfx950': ('SQ', 95),
|
|
},
|
|
'SQ_INSTS_VEC32_LEVEL_LDS': {
|
|
'gfx12': ('SQ', 250),
|
|
'gfx1200': ('SQ', 250),
|
|
'gfx1201': ('SQ', 250),
|
|
},
|
|
'SQ_INSTS_VALU_FLOPS_FP16': {
|
|
'gfx950': ('SQ', 81),
|
|
},
|
|
'SQ_INSTS_VALU_FLOPS_FP32': {
|
|
'gfx950': ('SQ', 82),
|
|
},
|
|
'SQ_INSTS_VALU_FLOPS_FP64': {
|
|
'gfx950': ('SQ', 83),
|
|
},
|
|
'SQ_INSTS_VALU_FLOPS_FP16_TRANS': {
|
|
'gfx950': ('SQ', 84),
|
|
},
|
|
'SQ_INSTS_VALU_FLOPS_FP32_TRANS': {
|
|
'gfx950': ('SQ', 85),
|
|
},
|
|
'SQ_INSTS_VALU_FLOPS_FP64_TRANS': {
|
|
'gfx950': ('SQ', 86),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_F6F4': {
|
|
'gfx950': ('SQ', 49),
|
|
},
|
|
'SQ_INSTS_VALU_MFMA_MOPS_F6F4': {
|
|
'gfx950': ('SQ', 57),
|
|
},
|
|
'SQ_ACTIVE_INST_VALU2': {
|
|
'gfx950': ('SQ', 74),
|
|
},
|
|
'SQ_INSTS_LDS_LOAD': {
|
|
'gfx950': ('SQ', 75),
|
|
},
|
|
'SQ_INSTS_LDS_STORE': {
|
|
'gfx950': ('SQ', 76),
|
|
},
|
|
'SQ_INSTS_LDS_ATOMIC': {
|
|
'gfx950': ('SQ', 77),
|
|
},
|
|
'SQ_INSTS_LDS_LOAD_BANDWIDTH': {
|
|
'gfx950': ('SQ', 78),
|
|
},
|
|
'SQ_INSTS_LDS_STORE_BANDWIDTH': {
|
|
'gfx950': ('SQ', 79),
|
|
},
|
|
'SQ_INSTS_LDS_ATOMIC_BANDWIDTH': {
|
|
'gfx950': ('SQ', 80),
|
|
},
|
|
'SQ_INSTS_VALU_IOPS': {
|
|
'gfx950': ('SQ', 87),
|
|
},
|
|
'SQ_LDS_DATA_FIFO_FULL': {
|
|
'gfx950': ('SQ', 152),
|
|
},
|
|
'SQ_LDS_CMD_FIFO_FULL': {
|
|
'gfx950': ('SQ', 153),
|
|
},
|
|
'SQ_VMEM_TA_ADDR_FIFO_FULL': {
|
|
'gfx90a': ('SQ', 133),
|
|
'gfx942': ('SQ', 138),
|
|
'gfx950': ('SQ', 154),
|
|
},
|
|
'SQ_VMEM_TA_CMD_FIFO_FULL': {
|
|
'gfx90a': ('SQ', 134),
|
|
'gfx942': ('SQ', 139),
|
|
'gfx950': ('SQ', 155),
|
|
},
|
|
'SQ_VMEM_WR_TA_DATA_FIFO_FULL': {
|
|
'gfx90a': ('SQ', 136),
|
|
'gfx942': ('SQ', 141),
|
|
'gfx950': ('SQ', 157),
|
|
},
|
|
'SQ_INSTS_FLAT_FLATSEG': {
|
|
'gfx950': ('SQ', 65),
|
|
},
|
|
'SQ_INSTS_FLAT_NO_LDS': {
|
|
'gfx950': ('SQ', 66),
|
|
},
|
|
'SQ_INSTS_EXP': {
|
|
'gfx950': ('SQ', 69),
|
|
},
|
|
'SQ_EVENTS': {
|
|
'gfx950': ('SQ', 16),
|
|
},
|
|
'TA_ADDR_STALLED_BY_TC_CYCLES': {
|
|
'gfx90a': ('TA', 54),
|
|
'gfx908': ('TA', 54),
|
|
'gfx940': ('TA', 42),
|
|
'gfx941': ('TA', 42),
|
|
'gfx942': ('TA', 42),
|
|
'gfx950': ('TA', 42),
|
|
},
|
|
'TA_ADDR_STALLED_BY_TD_CYCLES': {
|
|
'gfx90a': ('TA', 55),
|
|
'gfx908': ('TA', 55),
|
|
'gfx940': ('TA', 43),
|
|
'gfx941': ('TA', 43),
|
|
'gfx942': ('TA', 43),
|
|
'gfx950': ('TA', 43),
|
|
},
|
|
'TA_BUFFER_ATOMIC_WAVEFRONTS': {
|
|
'gfx90a': ('TA', 47),
|
|
'gfx908': ('TA', 47),
|
|
'gfx940': ('TA', 35),
|
|
'gfx941': ('TA', 35),
|
|
'gfx942': ('TA', 35),
|
|
'gfx950': ('TA', 35),
|
|
},
|
|
'TA_BUFFER_COALESCED_READ_CYCLES': {
|
|
'gfx90a': ('TA', 52),
|
|
'gfx908': ('TA', 52),
|
|
'gfx940': ('TA', 40),
|
|
'gfx941': ('TA', 40),
|
|
'gfx942': ('TA', 40),
|
|
'gfx950': ('TA', 40),
|
|
},
|
|
'TA_BUFFER_COALESCED_WRITE_CYCLES': {
|
|
'gfx90a': ('TA', 53),
|
|
'gfx908': ('TA', 53),
|
|
'gfx940': ('TA', 41),
|
|
'gfx941': ('TA', 41),
|
|
'gfx942': ('TA', 41),
|
|
'gfx950': ('TA', 41),
|
|
},
|
|
'TA_BUFFER_LOAD_WAVEFRONTS': {
|
|
'gfx11': ('TA', 45),
|
|
'gfx1100': ('TA', 45),
|
|
'gfx1101': ('TA', 45),
|
|
'gfx1102': ('TA', 45),
|
|
'gfx12': ('TA', 45),
|
|
'gfx1200': ('TA', 45),
|
|
'gfx1201': ('TA', 45),
|
|
},
|
|
'TA_BUFFER_READ_WAVEFRONTS': {
|
|
'gfx90a': ('TA', 45),
|
|
'gfx908': ('TA', 45),
|
|
'gfx940': ('TA', 33),
|
|
'gfx941': ('TA', 33),
|
|
'gfx942': ('TA', 33),
|
|
'gfx950': ('TA', 33),
|
|
},
|
|
'TA_BUFFER_STORE_WAVEFRONTS': {
|
|
'gfx11': ('TA', 46),
|
|
'gfx1100': ('TA', 46),
|
|
'gfx1101': ('TA', 46),
|
|
'gfx1102': ('TA', 46),
|
|
'gfx12': ('TA', 46),
|
|
'gfx1200': ('TA', 46),
|
|
'gfx1201': ('TA', 46),
|
|
},
|
|
'TA_BUFFER_TOTAL_CYCLES': {
|
|
'gfx90a': ('TA', 49),
|
|
'gfx908': ('TA', 49),
|
|
'gfx940': ('TA', 37),
|
|
'gfx941': ('TA', 37),
|
|
'gfx942': ('TA', 37),
|
|
'gfx950': ('TA', 37),
|
|
},
|
|
'TA_BUFFER_WAVEFRONTS': {
|
|
'gfx90a': ('TA', 44),
|
|
'gfx908': ('TA', 44),
|
|
'gfx940': ('TA', 32),
|
|
'gfx941': ('TA', 32),
|
|
'gfx942': ('TA', 32),
|
|
'gfx950': ('TA', 32),
|
|
},
|
|
'TA_BUFFER_WRITE_WAVEFRONTS': {
|
|
'gfx90a': ('TA', 46),
|
|
'gfx908': ('TA', 46),
|
|
'gfx940': ('TA', 34),
|
|
'gfx941': ('TA', 34),
|
|
'gfx942': ('TA', 34),
|
|
'gfx950': ('TA', 34),
|
|
},
|
|
'TA_DATA_STALLED_BY_TC_CYCLES': {
|
|
'gfx90a': ('TA', 56),
|
|
'gfx908': ('TA', 56),
|
|
'gfx940': ('TA', 44),
|
|
'gfx941': ('TA', 44),
|
|
'gfx942': ('TA', 44),
|
|
'gfx950': ('TA', 44),
|
|
},
|
|
'TA_FLAT_ATOMIC_WAVEFRONTS': {
|
|
'gfx90a': ('TA', 103),
|
|
'gfx908': ('TA', 103),
|
|
'gfx940': ('TA', 54),
|
|
'gfx941': ('TA', 54),
|
|
'gfx942': ('TA', 54),
|
|
'gfx950': ('TA', 54),
|
|
},
|
|
'TA_FLAT_LOAD_WAVEFRONTS': {
|
|
'gfx10': ('TA', 101),
|
|
'gfx1010': ('TA', 101),
|
|
'gfx1030': ('TA', 101),
|
|
'gfx1031': ('TA', 101),
|
|
'gfx1032': ('TA', 101),
|
|
},
|
|
'TA_FLAT_READ_WAVEFRONTS': {
|
|
'gfx9': ('TA', 101),
|
|
'gfx900': ('TA', 101),
|
|
'gfx906': ('TA', 101),
|
|
'gfx908': ('TA', 101),
|
|
'gfx90a': ('TA', 101),
|
|
'gfx940': ('TA', 52),
|
|
'gfx941': ('TA', 52),
|
|
'gfx942': ('TA', 52),
|
|
'gfx950': ('TA', 52),
|
|
},
|
|
'TA_FLAT_STORE_WAVEFRONTS': {
|
|
'gfx10': ('TA', 102),
|
|
'gfx1010': ('TA', 102),
|
|
'gfx1030': ('TA', 102),
|
|
'gfx1031': ('TA', 102),
|
|
'gfx1032': ('TA', 102),
|
|
},
|
|
'TA_FLAT_WAVEFRONTS': {
|
|
'gfx90a': ('TA', 100),
|
|
'gfx908': ('TA', 100),
|
|
'gfx940': ('TA', 51),
|
|
'gfx941': ('TA', 51),
|
|
'gfx942': ('TA', 51),
|
|
'gfx950': ('TA', 51),
|
|
},
|
|
'TA_FLAT_WRITE_WAVEFRONTS': {
|
|
'gfx9': ('TA', 102),
|
|
'gfx900': ('TA', 102),
|
|
'gfx906': ('TA', 102),
|
|
'gfx908': ('TA', 102),
|
|
'gfx90a': ('TA', 102),
|
|
'gfx940': ('TA', 53),
|
|
'gfx941': ('TA', 53),
|
|
'gfx942': ('TA', 53),
|
|
'gfx950': ('TA', 53),
|
|
},
|
|
'TA_TA_BUSY': {
|
|
'gfx10': ('TA', 15),
|
|
'gfx1010': ('TA', 15),
|
|
'gfx1030': ('TA', 15),
|
|
'gfx1031': ('TA', 15),
|
|
'gfx1032': ('TA', 15),
|
|
'gfx11': ('TA', 15),
|
|
'gfx1100': ('TA', 15),
|
|
'gfx1101': ('TA', 15),
|
|
'gfx1102': ('TA', 15),
|
|
'gfx12': ('TA', 15),
|
|
'gfx1200': ('TA', 15),
|
|
'gfx1201': ('TA', 15),
|
|
'gfx9': ('TA', 15),
|
|
'gfx900': ('TA', 15),
|
|
'gfx906': ('TA', 15),
|
|
'gfx908': ('TA', 15),
|
|
'gfx90a': ('TA', 15),
|
|
'gfx940': ('TA', 13),
|
|
'gfx941': ('TA', 13),
|
|
'gfx942': ('TA', 13),
|
|
'gfx950': ('TA', 13),
|
|
},
|
|
'TA_TOTAL_WAVEFRONTS': {
|
|
'gfx90a': ('TA', 32),
|
|
'gfx908': ('TA', 32),
|
|
'gfx940': ('TA', 29),
|
|
'gfx941': ('TA', 29),
|
|
'gfx942': ('TA', 29),
|
|
'gfx950': ('TA', 29),
|
|
},
|
|
'TA_BUFFER_READ_LDS_WAVEFRONTS': {
|
|
'gfx950': ('TA', 70),
|
|
},
|
|
'TA_FLAT_READ_LDS_WAVEFRONTS': {
|
|
'gfx950': ('TA', 71),
|
|
},
|
|
'TA_BUFFER_COALESCEABLE_WAVEFRONTS': {
|
|
'gfx950': ('TA', 36),
|
|
},
|
|
'TA_FLAT_COALESCEABLE_WAVEFRONTS': {
|
|
'gfx950': ('TA', 55),
|
|
},
|
|
'TCA_BUSY': {
|
|
'gfx90a': ('TCA', 2),
|
|
'gfx908': ('TCA', 2),
|
|
'gfx940': ('TCA', 2),
|
|
'gfx941': ('TCA', 2),
|
|
'gfx942': ('TCA', 2),
|
|
'gfx950': ('TCA', 2),
|
|
},
|
|
'TCA_CYCLE': {
|
|
'gfx90a': ('TCA', 1),
|
|
'gfx908': ('TCA', 1),
|
|
'gfx940': ('TCA', 1),
|
|
'gfx941': ('TCA', 1),
|
|
'gfx942': ('TCA', 1),
|
|
'gfx950': ('TCA', 1),
|
|
},
|
|
'TCC_ALL_TC_OP_INV_EVICT': {
|
|
'gfx90a': ('TCC', 80),
|
|
'gfx908': ('TCC', 80),
|
|
'gfx940': ('TCC', 80),
|
|
'gfx941': ('TCC', 80),
|
|
'gfx942': ('TCC', 80),
|
|
'gfx950': ('TCC', 86),
|
|
},
|
|
'TCC_ALL_TC_OP_WB_WRITEBACK': {
|
|
'gfx90a': ('TCC', 73),
|
|
'gfx908': ('TCC', 73),
|
|
'gfx940': ('TCC', 73),
|
|
'gfx941': ('TCC', 73),
|
|
'gfx942': ('TCC', 73),
|
|
'gfx950': ('TCC', 79),
|
|
},
|
|
'TCC_ATOMIC': {
|
|
'gfx90a': ('TCC', 14),
|
|
'gfx908': ('TCC', 14),
|
|
'gfx940': ('TCC', 14),
|
|
'gfx941': ('TCC', 14),
|
|
'gfx942': ('TCC', 14),
|
|
'gfx950': ('TCC', 18),
|
|
},
|
|
'TCC_BUSY': {
|
|
'gfx90a': ('TCC', 2),
|
|
'gfx908': ('TCC', 2),
|
|
'gfx940': ('TCC', 2),
|
|
'gfx941': ('TCC', 2),
|
|
'gfx942': ('TCC', 2),
|
|
'gfx950': ('TCC', 2),
|
|
},
|
|
'TCC_CC_REQ': {
|
|
'gfx90a': ('TCC', 7),
|
|
'gfx908': ('TCC', 7),
|
|
'gfx940': ('TCC', 7),
|
|
'gfx941': ('TCC', 7),
|
|
'gfx942': ('TCC', 7),
|
|
'gfx950': ('TCC', 11),
|
|
},
|
|
'TCC_CYCLE': {
|
|
'gfx90a': ('TCC', 1),
|
|
'gfx908': ('TCC', 1),
|
|
'gfx940': ('TCC', 1),
|
|
'gfx941': ('TCC', 1),
|
|
'gfx942': ('TCC', 1),
|
|
'gfx950': ('TCC', 1),
|
|
},
|
|
'TCC_EA0_ATOMIC': {
|
|
'gfx908': ('TCC', 36),
|
|
'gfx940': ('TCC', 36),
|
|
'gfx941': ('TCC', 36),
|
|
'gfx942': ('TCC', 36),
|
|
'gfx950': ('TCC', 40),
|
|
},
|
|
'TCC_EA0_ATOMIC_LEVEL': {
|
|
'gfx908': ('TCC', 37),
|
|
'gfx940': ('TCC', 37),
|
|
'gfx941': ('TCC', 37),
|
|
'gfx942': ('TCC', 37),
|
|
'gfx950': ('TCC', 41),
|
|
},
|
|
'TCC_EA0_RDREQ': {
|
|
'gfx908': ('TCC', 38),
|
|
'gfx940': ('TCC', 38),
|
|
'gfx941': ('TCC', 38),
|
|
'gfx942': ('TCC', 38),
|
|
'gfx950': ('TCC', 42),
|
|
},
|
|
'TCC_EA0_RDREQ_32B': {
|
|
'gfx908': ('TCC', 39),
|
|
'gfx940': ('TCC', 39),
|
|
'gfx941': ('TCC', 39),
|
|
'gfx942': ('TCC', 39),
|
|
'gfx950': ('TCC', 43),
|
|
},
|
|
'TCC_EA0_RDREQ_DRAM': {
|
|
'gfx908': ('TCC', 102),
|
|
'gfx940': ('TCC', 102),
|
|
'gfx941': ('TCC', 102),
|
|
'gfx942': ('TCC', 102),
|
|
'gfx950': ('TCC', 108),
|
|
},
|
|
'TCC_EA0_RDREQ_DRAM_CREDIT_STALL': {
|
|
'gfx908': ('TCC', 43),
|
|
'gfx940': ('TCC', 43),
|
|
'gfx941': ('TCC', 43),
|
|
'gfx942': ('TCC', 43),
|
|
'gfx950': ('TCC', 49),
|
|
},
|
|
'TCC_EA0_RDREQ_GMI_CREDIT_STALL': {
|
|
'gfx908': ('TCC', 42),
|
|
'gfx940': ('TCC', 42),
|
|
'gfx941': ('TCC', 42),
|
|
'gfx942': ('TCC', 42),
|
|
'gfx950': ('TCC', 48),
|
|
},
|
|
'TCC_EA0_RDREQ_IO_CREDIT_STALL': {
|
|
'gfx908': ('TCC', 41),
|
|
'gfx940': ('TCC', 41),
|
|
'gfx941': ('TCC', 41),
|
|
'gfx942': ('TCC', 41),
|
|
'gfx950': ('TCC', 47),
|
|
},
|
|
'TCC_EA0_RDREQ_LEVEL': {
|
|
'gfx908': ('TCC', 44),
|
|
'gfx940': ('TCC', 44),
|
|
'gfx941': ('TCC', 44),
|
|
'gfx942': ('TCC', 44),
|
|
'gfx950': ('TCC', 50),
|
|
},
|
|
'TCC_EA0_RD_UNCACHED_32B': {
|
|
'gfx908': ('TCC', 40),
|
|
'gfx940': ('TCC', 40),
|
|
'gfx941': ('TCC', 40),
|
|
'gfx942': ('TCC', 40),
|
|
'gfx950': ('TCC', 46),
|
|
},
|
|
'TCC_EA0_WRREQ': {
|
|
'gfx908': ('TCC', 26),
|
|
'gfx90a': ('TCC', 26),
|
|
'gfx940': ('TCC', 26),
|
|
'gfx941': ('TCC', 26),
|
|
'gfx942': ('TCC', 26),
|
|
'gfx950': ('TCC', 30),
|
|
},
|
|
'TCC_EA0_WRREQ_64B': {
|
|
'gfx908': ('TCC', 27),
|
|
'gfx90a': ('TCC', 27),
|
|
'gfx940': ('TCC', 27),
|
|
'gfx941': ('TCC', 27),
|
|
'gfx942': ('TCC', 27),
|
|
'gfx950': ('TCC', 31),
|
|
},
|
|
'TCC_EA0_WRREQ_DRAM': {
|
|
'gfx908': ('TCC', 103),
|
|
'gfx940': ('TCC', 103),
|
|
'gfx941': ('TCC', 103),
|
|
'gfx942': ('TCC', 103),
|
|
'gfx950': ('TCC', 109),
|
|
},
|
|
'TCC_EA0_WRREQ_DRAM_CREDIT_STALL': {
|
|
'gfx908': ('TCC', 33),
|
|
'gfx940': ('TCC', 33),
|
|
'gfx941': ('TCC', 33),
|
|
'gfx942': ('TCC', 33),
|
|
'gfx950': ('TCC', 37),
|
|
},
|
|
'TCC_EA0_WRREQ_GMI_CREDIT_STALL': {
|
|
'gfx908': ('TCC', 32),
|
|
'gfx940': ('TCC', 32),
|
|
'gfx941': ('TCC', 32),
|
|
'gfx942': ('TCC', 32),
|
|
'gfx950': ('TCC', 36),
|
|
},
|
|
'TCC_EA0_WRREQ_IO_CREDIT_STALL': {
|
|
'gfx908': ('TCC', 31),
|
|
'gfx940': ('TCC', 31),
|
|
'gfx941': ('TCC', 31),
|
|
'gfx942': ('TCC', 31),
|
|
'gfx950': ('TCC', 35),
|
|
},
|
|
'TCC_EA0_WRREQ_LEVEL': {
|
|
'gfx908': ('TCC', 35),
|
|
'gfx940': ('TCC', 35),
|
|
'gfx941': ('TCC', 35),
|
|
'gfx942': ('TCC', 35),
|
|
'gfx950': ('TCC', 39),
|
|
},
|
|
'TCC_EA0_WRREQ_PROBE_COMMAND': {
|
|
'gfx940': ('TCC', 28),
|
|
'gfx941': ('TCC', 28),
|
|
'gfx942': ('TCC', 28),
|
|
'gfx950': ('TCC', 32),
|
|
},
|
|
'TCC_EA0_WRREQ_STALL': {
|
|
'gfx908': ('TCC', 30),
|
|
'gfx940': ('TCC', 30),
|
|
'gfx941': ('TCC', 30),
|
|
'gfx942': ('TCC', 30),
|
|
'gfx950': ('TCC', 34),
|
|
},
|
|
'TCC_EA0_WR_UNCACHED_32B': {
|
|
'gfx908': ('TCC', 29),
|
|
'gfx940': ('TCC', 29),
|
|
'gfx941': ('TCC', 29),
|
|
'gfx942': ('TCC', 29),
|
|
'gfx950': ('TCC', 33),
|
|
},
|
|
'TCC_EA1_RDREQ': {
|
|
'gfx906': ('TCC', 267),
|
|
},
|
|
'TCC_EA1_RDREQ_32B': {
|
|
'gfx906': ('TCC', 268),
|
|
},
|
|
'TCC_EA1_WRREQ': {
|
|
'gfx906': ('TCC', 256),
|
|
},
|
|
'TCC_EA1_WRREQ_64B': {
|
|
'gfx906': ('TCC', 257),
|
|
},
|
|
'TCC_EA1_WRREQ_STALL': {
|
|
'gfx906': ('TCC', 260),
|
|
},
|
|
'TCC_EA_ATOMIC': {
|
|
'gfx90a': ('TCC', 36),
|
|
},
|
|
'TCC_EA_ATOMIC_LEVEL': {
|
|
'gfx90a': ('TCC', 37),
|
|
},
|
|
'TCC_EA_RDREQ': {
|
|
'gfx9': ('TCC', 41),
|
|
'gfx900': ('TCC', 41),
|
|
'gfx906': ('TCC', 41),
|
|
'gfx908': ('TCC', 38),
|
|
'gfx90a': ('TCC', 38),
|
|
},
|
|
'TCC_EA_RDREQ_32B': {
|
|
'gfx9': ('TCC', 42),
|
|
'gfx900': ('TCC', 42),
|
|
'gfx906': ('TCC', 42),
|
|
'gfx908': ('TCC', 39),
|
|
'gfx90a': ('TCC', 39),
|
|
},
|
|
'TCC_EA_RDREQ_DRAM': {
|
|
'gfx90a': ('TCC', 102),
|
|
},
|
|
'TCC_EA_RDREQ_DRAM_CREDIT_STALL': {
|
|
'gfx90a': ('TCC', 43),
|
|
},
|
|
'TCC_EA_RDREQ_GMI_CREDIT_STALL': {
|
|
'gfx90a': ('TCC', 42),
|
|
},
|
|
'TCC_EA_RDREQ_IO_CREDIT_STALL': {
|
|
'gfx90a': ('TCC', 41),
|
|
},
|
|
'TCC_EA_RDREQ_LEVEL': {
|
|
'gfx90a': ('TCC', 44),
|
|
},
|
|
'TCC_EA_RD_UNCACHED_32B': {
|
|
'gfx90a': ('TCC', 40),
|
|
},
|
|
'TCC_EA_WRREQ': {
|
|
'gfx9': ('TCC', 29),
|
|
'gfx900': ('TCC', 29),
|
|
'gfx906': ('TCC', 29),
|
|
'gfx908': ('TCC', 26),
|
|
'gfx90a': ('TCC', 26),
|
|
},
|
|
'TCC_EA_WRREQ_64B': {
|
|
'gfx9': ('TCC', 30),
|
|
'gfx900': ('TCC', 30),
|
|
'gfx906': ('TCC', 30),
|
|
'gfx908': ('TCC', 27),
|
|
'gfx90a': ('TCC', 27),
|
|
},
|
|
'TCC_EA_WRREQ_DRAM': {
|
|
'gfx90a': ('TCC', 103),
|
|
},
|
|
'TCC_EA_WRREQ_DRAM_CREDIT_STALL': {
|
|
'gfx90a': ('TCC', 33),
|
|
},
|
|
'TCC_EA_WRREQ_GMI_CREDIT_STALL': {
|
|
'gfx90a': ('TCC', 32),
|
|
},
|
|
'TCC_EA_WRREQ_IO_CREDIT_STALL': {
|
|
'gfx90a': ('TCC', 31),
|
|
},
|
|
'TCC_EA_WRREQ_LEVEL': {
|
|
'gfx90a': ('TCC', 35),
|
|
},
|
|
'TCC_EA_WRREQ_STALL': {
|
|
'gfx9': ('TCC', 33),
|
|
'gfx900': ('TCC', 33),
|
|
'gfx906': ('TCC', 33),
|
|
'gfx908': ('TCC', 30),
|
|
'gfx90a': ('TCC', 30),
|
|
},
|
|
'TCC_EA_WR_UNCACHED_32B': {
|
|
'gfx90a': ('TCC', 29),
|
|
},
|
|
'TCC_HIT': {
|
|
'gfx9': ('TCC', 20),
|
|
'gfx900': ('TCC', 20),
|
|
'gfx906': ('TCC', 20),
|
|
'gfx908': ('TCC', 17),
|
|
'gfx90a': ('TCC', 17),
|
|
'gfx940': ('TCC', 17),
|
|
'gfx941': ('TCC', 17),
|
|
'gfx942': ('TCC', 17),
|
|
'gfx950': ('TCC', 21),
|
|
},
|
|
'TCC_INTERNAL_PROBE': {
|
|
'gfx940': ('TCC', 11),
|
|
'gfx941': ('TCC', 11),
|
|
'gfx942': ('TCC', 11),
|
|
'gfx950': ('TCC', 15),
|
|
},
|
|
'TCC_MISS': {
|
|
'gfx9': ('TCC', 22),
|
|
'gfx900': ('TCC', 22),
|
|
'gfx906': ('TCC', 22),
|
|
'gfx908': ('TCC', 19),
|
|
'gfx90a': ('TCC', 19),
|
|
'gfx940': ('TCC', 19),
|
|
'gfx941': ('TCC', 19),
|
|
'gfx942': ('TCC', 19),
|
|
'gfx950': ('TCC', 23),
|
|
},
|
|
'TCC_NC_REQ': {
|
|
'gfx908': ('TCC', 5),
|
|
'gfx90a': ('TCC', 5),
|
|
'gfx940': ('TCC', 5),
|
|
'gfx941': ('TCC', 5),
|
|
'gfx942': ('TCC', 5),
|
|
'gfx950': ('TCC', 9),
|
|
},
|
|
'TCC_NORMAL_EVICT': {
|
|
'gfx90a': ('TCC', 74),
|
|
'gfx908': ('TCC', 74),
|
|
'gfx940': ('TCC', 74),
|
|
'gfx941': ('TCC', 74),
|
|
'gfx942': ('TCC', 74),
|
|
'gfx950': ('TCC', 80),
|
|
},
|
|
'TCC_NORMAL_WRITEBACK': {
|
|
'gfx908': ('TCC', 68),
|
|
'gfx90a': ('TCC', 68),
|
|
'gfx940': ('TCC', 68),
|
|
'gfx941': ('TCC', 68),
|
|
'gfx942': ('TCC', 68),
|
|
'gfx950': ('TCC', 74),
|
|
},
|
|
'TCC_PROBE': {
|
|
'gfx90a': ('TCC', 9),
|
|
'gfx908': ('TCC', 9),
|
|
'gfx940': ('TCC', 9),
|
|
'gfx941': ('TCC', 9),
|
|
'gfx942': ('TCC', 9),
|
|
'gfx950': ('TCC', 13),
|
|
},
|
|
'TCC_PROBE_ALL': {
|
|
'gfx90a': ('TCC', 10),
|
|
'gfx908': ('TCC', 10),
|
|
'gfx940': ('TCC', 10),
|
|
'gfx941': ('TCC', 10),
|
|
'gfx942': ('TCC', 10),
|
|
'gfx950': ('TCC', 14),
|
|
},
|
|
'TCC_PROBE_EVICT': {
|
|
'gfx940': ('TCC', 81),
|
|
'gfx941': ('TCC', 81),
|
|
'gfx942': ('TCC', 81),
|
|
'gfx950': ('TCC', 87),
|
|
},
|
|
'TCC_READ': {
|
|
'gfx90a': ('TCC', 12),
|
|
'gfx908': ('TCC', 12),
|
|
'gfx940': ('TCC', 12),
|
|
'gfx941': ('TCC', 12),
|
|
'gfx942': ('TCC', 12),
|
|
'gfx950': ('TCC', 16),
|
|
},
|
|
'TCC_REQ': {
|
|
'gfx90a': ('TCC', 3),
|
|
'gfx908': ('TCC', 3),
|
|
'gfx940': ('TCC', 3),
|
|
'gfx941': ('TCC', 3),
|
|
'gfx942': ('TCC', 3),
|
|
'gfx950': ('TCC', 6),
|
|
},
|
|
'TCC_RW_REQ': {
|
|
'gfx90a': ('TCC', 8),
|
|
'gfx908': ('TCC', 8),
|
|
'gfx940': ('TCC', 8),
|
|
'gfx941': ('TCC', 8),
|
|
'gfx942': ('TCC', 8),
|
|
'gfx950': ('TCC', 12),
|
|
},
|
|
'TCC_STREAMING_REQ': {
|
|
'gfx90a': ('TCC', 4),
|
|
'gfx908': ('TCC', 4),
|
|
'gfx940': ('TCC', 4),
|
|
'gfx941': ('TCC', 4),
|
|
'gfx942': ('TCC', 4),
|
|
'gfx950': ('TCC', 7),
|
|
},
|
|
'TCC_TAG_STALL': {
|
|
'gfx90a': ('TCC', 45),
|
|
'gfx908': ('TCC', 45),
|
|
'gfx940': ('TCC', 45),
|
|
'gfx941': ('TCC', 45),
|
|
'gfx942': ('TCC', 45),
|
|
'gfx950': ('TCC', 51),
|
|
},
|
|
'TCC_TOO_MANY_EA_WRREQS_STALL': {
|
|
'gfx90a': ('TCC', 34),
|
|
'gfx908': ('TCC', 34),
|
|
'gfx940': ('TCC', 34),
|
|
'gfx941': ('TCC', 34),
|
|
'gfx942': ('TCC', 34),
|
|
'gfx950': ('TCC', 38),
|
|
},
|
|
'TCC_UC_REQ': {
|
|
'gfx90a': ('TCC', 6),
|
|
'gfx908': ('TCC', 6),
|
|
'gfx940': ('TCC', 6),
|
|
'gfx941': ('TCC', 6),
|
|
'gfx942': ('TCC', 6),
|
|
'gfx950': ('TCC', 10),
|
|
},
|
|
'TCC_WRITE': {
|
|
'gfx90a': ('TCC', 13),
|
|
'gfx908': ('TCC', 13),
|
|
'gfx940': ('TCC', 13),
|
|
'gfx941': ('TCC', 13),
|
|
'gfx942': ('TCC', 13),
|
|
'gfx950': ('TCC', 17),
|
|
},
|
|
'TCC_WRITEBACK': {
|
|
'gfx90a': ('TCC', 22),
|
|
'gfx908': ('TCC', 22),
|
|
'gfx940': ('TCC', 22),
|
|
'gfx941': ('TCC', 22),
|
|
'gfx942': ('TCC', 22),
|
|
'gfx950': ('TCC', 26),
|
|
},
|
|
'TCC_BUBBLE': {
|
|
'gfx90a': ('TCC', 56),
|
|
'gfx908': ('TCC', 56),
|
|
'gfx940': ('TCC', 56),
|
|
'gfx941': ('TCC', 56),
|
|
'gfx942': ('TCC', 56),
|
|
'gfx950': ('TCC', 62),
|
|
},
|
|
'TCC_EA0_RDREQ_DRAM_32B': {
|
|
'gfx950': ('TCC', 112),
|
|
},
|
|
'TCC_EA0_RDREQ_GMI_32B': {
|
|
'gfx950': ('TCC', 113),
|
|
},
|
|
'TCC_EA0_RDREQ_IO_32B': {
|
|
'gfx950': ('TCC', 114),
|
|
},
|
|
'TCC_EA0_WRREQ_WRITE_DRAM_32B': {
|
|
'gfx950': ('TCC', 115),
|
|
},
|
|
'TCC_EA0_WRREQ_WRITE_ATOMIC_32B': {
|
|
'gfx950': ('TCC', 116),
|
|
},
|
|
'TCC_EA0_WRREQ_WRITE_GMI_32B': {
|
|
'gfx950': ('TCC', 117),
|
|
},
|
|
'TCC_EA0_WRREQ_ATOMIC_GMI_32B': {
|
|
'gfx950': ('TCC', 118),
|
|
},
|
|
'TCC_EA0_WRREQ_WRITE_IO_32B': {
|
|
'gfx950': ('TCC', 119),
|
|
},
|
|
'TCC_EA0_WRREQ_ATOMIC_IO_32B': {
|
|
'gfx950': ('TCC', 120),
|
|
},
|
|
'TCC_READ_SECTORS': {
|
|
'gfx950': ('TCC', 3),
|
|
},
|
|
'TCC_WRITE_SECTORS': {
|
|
'gfx950': ('TCC', 4),
|
|
},
|
|
'TCC_ATOMIC_SECTORS': {
|
|
'gfx950': ('TCC', 5),
|
|
},
|
|
'TCC_BYPASS_REQ': {
|
|
'gfx950': ('TCC', 8),
|
|
},
|
|
'TCC_LATENCY_FIFO_FULL': {
|
|
'gfx950': ('TCC', 27),
|
|
},
|
|
'TCC_SRC_FIFO_FULL': {
|
|
'gfx950': ('TCC', 28),
|
|
},
|
|
'TCC_EA0_RDREQ_64B': {
|
|
'gfx950': ('TCC', 44),
|
|
},
|
|
'TCC_EA0_RDREQ_128B': {
|
|
'gfx950': ('TCC', 45),
|
|
},
|
|
'TCC_IB_REQ': {
|
|
'gfx950': ('TCC', 67),
|
|
},
|
|
'TCC_IB_STALL': {
|
|
'gfx950': ('TCC', 68),
|
|
},
|
|
'TCC_EA0_WRREQ_ATOMIC_DRAM': {
|
|
'gfx950': ('TCC', 111),
|
|
},
|
|
'TCC_EA0_WRREQ_WRITE_DRAM': {
|
|
'gfx950': ('TCC', 110),
|
|
},
|
|
'TCC_EA0_WRREQ_ATOMIC_DRAM_32B': {
|
|
'gfx950': ('TCC', 116),
|
|
},
|
|
'TCC_CLIENT184_REQ': {
|
|
'gfx908': ('TCC', 312),
|
|
},
|
|
'TCC_CLIENT185_REQ': {
|
|
'gfx908': ('TCC', 313),
|
|
},
|
|
'TCC_CLIENT186_REQ': {
|
|
'gfx908': ('TCC', 314),
|
|
},
|
|
'TCC_CLIENT187_REQ': {
|
|
'gfx908': ('TCC', 315),
|
|
},
|
|
'TCC_CLIENT188_REQ': {
|
|
'gfx908': ('TCC', 316),
|
|
},
|
|
'TCC_CLIENT189_REQ': {
|
|
'gfx908': ('TCC', 317),
|
|
},
|
|
'TCC_CLIENT190_REQ': {
|
|
'gfx908': ('TCC', 318),
|
|
},
|
|
'TCC_CLIENT191_REQ': {
|
|
'gfx908': ('TCC', 319),
|
|
},
|
|
'TCP_REQ': {
|
|
'gfx12': ('TCP', 9),
|
|
'gfx1200': ('TCP', 9),
|
|
'gfx1201': ('TCP', 9),
|
|
},
|
|
'TCP_REQ_MISS': {
|
|
'gfx12': ('TCP', 17),
|
|
'gfx1200': ('TCP', 17),
|
|
'gfx1201': ('TCP', 17),
|
|
},
|
|
'TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES': {
|
|
'gfx90a': ('TCP', 13),
|
|
'gfx908': ('TCP', 13),
|
|
'gfx940': ('TCP', 12),
|
|
'gfx941': ('TCP', 12),
|
|
'gfx942': ('TCP', 12),
|
|
'gfx950': ('TCP', 12),
|
|
},
|
|
'TCP_GATE_EN1': {
|
|
'gfx90a': ('TCP', 0),
|
|
'gfx908': ('TCP', 0),
|
|
'gfx940': ('TCP', 0),
|
|
'gfx941': ('TCP', 0),
|
|
'gfx942': ('TCP', 0),
|
|
'gfx950': ('TCP', 0),
|
|
},
|
|
'TCP_GATE_EN2': {
|
|
'gfx90a': ('TCP', 1),
|
|
'gfx908': ('TCP', 1),
|
|
'gfx940': ('TCP', 1),
|
|
'gfx941': ('TCP', 1),
|
|
'gfx942': ('TCP', 1),
|
|
'gfx950': ('TCP', 1),
|
|
},
|
|
'TCP_PENDING_STALL_CYCLES': {
|
|
'gfx90a': ('TCP', 22),
|
|
'gfx908': ('TCP', 22),
|
|
'gfx940': ('TCP', 21),
|
|
'gfx941': ('TCP', 21),
|
|
'gfx942': ('TCP', 21),
|
|
'gfx950': ('TCP', 21),
|
|
},
|
|
'TCP_READ_TAGCONFLICT_STALL_CYCLES': {
|
|
'gfx90a': ('TCP', 11),
|
|
'gfx908': ('TCP', 11),
|
|
'gfx940': ('TCP', 10),
|
|
'gfx941': ('TCP', 10),
|
|
'gfx942': ('TCP', 10),
|
|
'gfx950': ('TCP', 10),
|
|
},
|
|
'TCP_TA_TCP_STATE_READ': {
|
|
'gfx90a': ('TCP', 27),
|
|
'gfx908': ('TCP', 27),
|
|
'gfx940': ('TCP', 25),
|
|
'gfx941': ('TCP', 25),
|
|
'gfx942': ('TCP', 25),
|
|
'gfx950': ('TCP', 25),
|
|
},
|
|
'TCP_TCC_ATOMIC_WITHOUT_RET_REQ': {
|
|
'gfx90a': ('TCP', 72),
|
|
'gfx908': ('TCP', 72),
|
|
'gfx940': ('TCP', 68),
|
|
'gfx941': ('TCP', 68),
|
|
'gfx942': ('TCP', 68),
|
|
'gfx950': ('TCP', 71),
|
|
},
|
|
'TCP_TCC_ATOMIC_WITH_RET_REQ': {
|
|
'gfx90a': ('TCP', 71),
|
|
'gfx908': ('TCP', 71),
|
|
'gfx940': ('TCP', 67),
|
|
'gfx941': ('TCP', 67),
|
|
'gfx942': ('TCP', 67),
|
|
'gfx950': ('TCP', 70),
|
|
},
|
|
'TCP_TCC_CC_ATOMIC_REQ': {
|
|
'gfx90a': ('TCP', 83),
|
|
'gfx908': ('TCP', 83),
|
|
'gfx940': ('TCP', 79),
|
|
'gfx941': ('TCP', 79),
|
|
'gfx942': ('TCP', 79),
|
|
'gfx950': ('TCP', 82),
|
|
},
|
|
'TCP_TCC_CC_READ_REQ': {
|
|
'gfx90a': ('TCP', 81),
|
|
'gfx908': ('TCP', 81),
|
|
'gfx940': ('TCP', 77),
|
|
'gfx941': ('TCP', 77),
|
|
'gfx942': ('TCP', 77),
|
|
'gfx950': ('TCP', 80),
|
|
},
|
|
'TCP_TCC_CC_WRITE_REQ': {
|
|
'gfx90a': ('TCP', 82),
|
|
'gfx908': ('TCP', 82),
|
|
'gfx940': ('TCP', 78),
|
|
'gfx941': ('TCP', 78),
|
|
'gfx942': ('TCP', 78),
|
|
'gfx950': ('TCP', 81),
|
|
},
|
|
'TCP_TCC_NC_ATOMIC_REQ': {
|
|
'gfx90a': ('TCP', 77),
|
|
'gfx908': ('TCP', 77),
|
|
'gfx940': ('TCP', 73),
|
|
'gfx941': ('TCP', 73),
|
|
'gfx942': ('TCP', 73),
|
|
'gfx950': ('TCP', 76),
|
|
},
|
|
'TCP_TCC_NC_READ_REQ': {
|
|
'gfx90a': ('TCP', 75),
|
|
'gfx908': ('TCP', 75),
|
|
'gfx940': ('TCP', 71),
|
|
'gfx941': ('TCP', 71),
|
|
'gfx942': ('TCP', 71),
|
|
'gfx950': ('TCP', 74),
|
|
},
|
|
'TCP_TCC_NC_WRITE_REQ': {
|
|
'gfx90a': ('TCP', 76),
|
|
'gfx908': ('TCP', 76),
|
|
'gfx940': ('TCP', 72),
|
|
'gfx941': ('TCP', 72),
|
|
'gfx942': ('TCP', 72),
|
|
'gfx950': ('TCP', 75),
|
|
},
|
|
'TCP_TCC_READ_REQ': {
|
|
'gfx90a': ('TCP', 69),
|
|
'gfx908': ('TCP', 69),
|
|
'gfx940': ('TCP', 65),
|
|
'gfx941': ('TCP', 65),
|
|
'gfx942': ('TCP', 65),
|
|
'gfx950': ('TCP', 68),
|
|
},
|
|
'TCP_TCC_READ_REQ_LATENCY': {
|
|
'gfx90a': ('TCP', 66),
|
|
'gfx908': ('TCP', 66),
|
|
'gfx950': ('TCP', 65),
|
|
},
|
|
'TCP_TCC_RW_ATOMIC_REQ': {
|
|
'gfx90a': ('TCP', 87),
|
|
'gfx908': ('TCP', 87),
|
|
'gfx940': ('TCP', 82),
|
|
'gfx941': ('TCP', 82),
|
|
'gfx942': ('TCP', 82),
|
|
'gfx950': ('TCP', 85),
|
|
},
|
|
'TCP_TCC_RW_READ_REQ': {
|
|
'gfx90a': ('TCP', 85),
|
|
'gfx908': ('TCP', 85),
|
|
'gfx940': ('TCP', 80),
|
|
'gfx941': ('TCP', 80),
|
|
'gfx942': ('TCP', 80),
|
|
'gfx950': ('TCP', 83),
|
|
},
|
|
'TCP_TCC_RW_WRITE_REQ': {
|
|
'gfx90a': ('TCP', 86),
|
|
'gfx908': ('TCP', 86),
|
|
'gfx940': ('TCP', 81),
|
|
'gfx941': ('TCP', 81),
|
|
'gfx942': ('TCP', 81),
|
|
'gfx950': ('TCP', 84),
|
|
},
|
|
'TCP_TCC_UC_ATOMIC_REQ': {
|
|
'gfx90a': ('TCP', 80),
|
|
'gfx908': ('TCP', 80),
|
|
'gfx940': ('TCP', 76),
|
|
'gfx941': ('TCP', 76),
|
|
'gfx942': ('TCP', 76),
|
|
'gfx950': ('TCP', 79),
|
|
},
|
|
'TCP_TCC_UC_READ_REQ': {
|
|
'gfx90a': ('TCP', 78),
|
|
'gfx908': ('TCP', 78),
|
|
'gfx940': ('TCP', 74),
|
|
'gfx941': ('TCP', 74),
|
|
'gfx942': ('TCP', 74),
|
|
'gfx950': ('TCP', 77),
|
|
},
|
|
'TCP_TCC_UC_WRITE_REQ': {
|
|
'gfx90a': ('TCP', 79),
|
|
'gfx908': ('TCP', 79),
|
|
'gfx940': ('TCP', 75),
|
|
'gfx941': ('TCP', 75),
|
|
'gfx942': ('TCP', 75),
|
|
'gfx950': ('TCP', 78),
|
|
},
|
|
'TCP_TCC_WRITE_REQ': {
|
|
'gfx90a': ('TCP', 70),
|
|
'gfx908': ('TCP', 70),
|
|
'gfx940': ('TCP', 66),
|
|
'gfx941': ('TCP', 66),
|
|
'gfx942': ('TCP', 66),
|
|
'gfx950': ('TCP', 69),
|
|
},
|
|
'TCP_TCC_WRITE_REQ_LATENCY': {
|
|
'gfx90a': ('TCP', 67),
|
|
'gfx908': ('TCP', 67),
|
|
'gfx950': ('TCP', 66),
|
|
},
|
|
'TCP_TCP_LATENCY': {
|
|
'gfx90a': ('TCP', 65),
|
|
'gfx908': ('TCP', 65),
|
|
'gfx950': ('TCP', 64),
|
|
},
|
|
'TCP_TCP_TA_DATA_STALL_CYCLES': {
|
|
'gfx9': ('TCP', 6),
|
|
'gfx900': ('TCP', 6),
|
|
'gfx906': ('TCP', 6),
|
|
'gfx908': ('TCP', 6),
|
|
'gfx90a': ('TCP', 6),
|
|
'gfx940': ('TCP', 6),
|
|
'gfx941': ('TCP', 6),
|
|
'gfx942': ('TCP', 6),
|
|
'gfx950': ('TCP', 6),
|
|
},
|
|
'TCP_TCR_TCP_STALL_CYCLES': {
|
|
'gfx90a': ('TCP', 8),
|
|
'gfx908': ('TCP', 8),
|
|
'gfx940': ('TCP', 8),
|
|
'gfx941': ('TCP', 8),
|
|
'gfx942': ('TCP', 8),
|
|
'gfx950': ('TCP', 8),
|
|
},
|
|
'TCP_TD_TCP_STALL_CYCLES': {
|
|
'gfx90a': ('TCP', 7),
|
|
'gfx908': ('TCP', 7),
|
|
'gfx940': ('TCP', 7),
|
|
'gfx941': ('TCP', 7),
|
|
'gfx942': ('TCP', 7),
|
|
'gfx950': ('TCP', 7),
|
|
},
|
|
'TCP_TOTAL_ACCESSES': {
|
|
'gfx90a': ('TCP', 29),
|
|
'gfx908': ('TCP', 29),
|
|
'gfx940': ('TCP', 27),
|
|
'gfx941': ('TCP', 27),
|
|
'gfx942': ('TCP', 27),
|
|
'gfx950': ('TCP', 27),
|
|
},
|
|
'TCP_TOTAL_ATOMIC_WITHOUT_RET': {
|
|
'gfx90a': ('TCP', 39),
|
|
'gfx908': ('TCP', 39),
|
|
'gfx940': ('TCP', 37),
|
|
'gfx941': ('TCP', 37),
|
|
'gfx942': ('TCP', 37),
|
|
'gfx950': ('TCP', 37),
|
|
},
|
|
'TCP_TOTAL_ATOMIC_WITH_RET': {
|
|
'gfx90a': ('TCP', 38),
|
|
'gfx908': ('TCP', 38),
|
|
'gfx940': ('TCP', 36),
|
|
'gfx941': ('TCP', 36),
|
|
'gfx942': ('TCP', 36),
|
|
'gfx950': ('TCP', 36),
|
|
},
|
|
'TCP_TOTAL_CACHE_ACCESSES': {
|
|
'gfx90a': ('TCP', 60),
|
|
'gfx908': ('TCP', 60),
|
|
'gfx940': ('TCP', 60),
|
|
'gfx941': ('TCP', 60),
|
|
'gfx942': ('TCP', 60),
|
|
'gfx950': ('TCP', 58),
|
|
},
|
|
'TCP_TOTAL_READ': {
|
|
'gfx90a': ('TCP', 30),
|
|
'gfx908': ('TCP', 30),
|
|
'gfx940': ('TCP', 28),
|
|
'gfx941': ('TCP', 28),
|
|
'gfx942': ('TCP', 28),
|
|
'gfx950': ('TCP', 28),
|
|
},
|
|
'TCP_TOTAL_WRITE': {
|
|
'gfx90a': ('TCP', 32),
|
|
'gfx908': ('TCP', 32),
|
|
'gfx940': ('TCP', 30),
|
|
'gfx941': ('TCP', 30),
|
|
'gfx942': ('TCP', 30),
|
|
'gfx950': ('TCP', 30),
|
|
},
|
|
'TCP_TOTAL_WRITEBACK_INVALIDATES': {
|
|
'gfx90a': ('TCP', 45),
|
|
'gfx908': ('TCP', 45),
|
|
'gfx940': ('TCP', 43),
|
|
'gfx941': ('TCP', 43),
|
|
'gfx942': ('TCP', 43),
|
|
'gfx950': ('TCP', 41),
|
|
},
|
|
'TCP_UTCL1_PERMISSION_MISS': {
|
|
'gfx90a': ('TCP', 50),
|
|
'gfx908': ('TCP', 50),
|
|
'gfx940': ('TCP', 49),
|
|
'gfx941': ('TCP', 49),
|
|
'gfx942': ('TCP', 49),
|
|
'gfx950': ('TCP', 47),
|
|
},
|
|
'TCP_UTCL1_REQUEST': {
|
|
'gfx90a': ('TCP', 47),
|
|
'gfx908': ('TCP', 47),
|
|
'gfx940': ('TCP', 45),
|
|
'gfx941': ('TCP', 45),
|
|
'gfx942': ('TCP', 45),
|
|
'gfx950': ('TCP', 43),
|
|
},
|
|
'TCP_UTCL1_TRANSLATION_HIT': {
|
|
'gfx90a': ('TCP', 49),
|
|
'gfx908': ('TCP', 49),
|
|
'gfx940': ('TCP', 48),
|
|
'gfx941': ('TCP', 48),
|
|
'gfx942': ('TCP', 48),
|
|
'gfx950': ('TCP', 46),
|
|
},
|
|
'TCP_UTCL1_TRANSLATION_MISS': {
|
|
'gfx90a': ('TCP', 48),
|
|
'gfx908': ('TCP', 48),
|
|
'gfx940': ('TCP', 47),
|
|
'gfx941': ('TCP', 47),
|
|
'gfx942': ('TCP', 47),
|
|
'gfx950': ('TCP', 45),
|
|
},
|
|
'TCP_VOLATILE': {
|
|
'gfx90a': ('TCP', 28),
|
|
'gfx908': ('TCP', 28),
|
|
'gfx940': ('TCP', 26),
|
|
'gfx941': ('TCP', 26),
|
|
'gfx942': ('TCP', 26),
|
|
'gfx950': ('TCP', 26),
|
|
},
|
|
'TCP_WRITE_TAGCONFLICT_STALL_CYCLES': {
|
|
'gfx90a': ('TCP', 12),
|
|
'gfx908': ('TCP', 12),
|
|
'gfx940': ('TCP', 11),
|
|
'gfx941': ('TCP', 11),
|
|
'gfx942': ('TCP', 11),
|
|
'gfx950': ('TCP', 11),
|
|
},
|
|
'TCP_CACHE_MISS': {
|
|
'gfx950': ('TCP', 63),
|
|
},
|
|
'TCP_TCP_TA_ADDR_STALL_CYCLES': {
|
|
'gfx950': ('TCP', 5),
|
|
},
|
|
'TCP_LFIFO_STALL_CYCLES': {
|
|
'gfx950': ('TCP', 15),
|
|
},
|
|
'TCP_RFIFO_STALL_CYCLES': {
|
|
'gfx950': ('TCP', 16),
|
|
},
|
|
'TCP_TCR_RDRET_STALL': {
|
|
'gfx950': ('TCP', 17),
|
|
},
|
|
'TCP_UTCL1_SERIALIZATION_STALL': {
|
|
'gfx950': ('TCP', 23),
|
|
},
|
|
'TCP_UTCL1_THRASHING_STALL': {
|
|
'gfx950': ('TCP', 44),
|
|
},
|
|
'TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS': {
|
|
'gfx950': ('TCP', 48),
|
|
},
|
|
'TCP_UTCL1_STALL_INFLIGHT_MAX': {
|
|
'gfx950': ('TCP', 49),
|
|
},
|
|
'TCP_UTCL1_STALL_LRU_INFLIGHT': {
|
|
'gfx950': ('TCP', 50),
|
|
},
|
|
'TCP_UTCL1_STALL_MULTI_MISS': {
|
|
'gfx950': ('TCP', 51),
|
|
},
|
|
'TCP_UTCL1_LFIFO_FULL': {
|
|
'gfx950': ('TCP', 52),
|
|
},
|
|
'TCP_UTCL1_STALL_LFIFO_NOT_RES': {
|
|
'gfx950': ('TCP', 53),
|
|
},
|
|
'TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS': {
|
|
'gfx950': ('TCP', 54),
|
|
},
|
|
'TCP_CLIENT_UTCL1_INFLIGHT': {
|
|
'gfx950': ('TCP', 55),
|
|
},
|
|
'TCP_TAGRAM0_REQ': {
|
|
'gfx950': ('TCP', 59),
|
|
},
|
|
'TCP_TAGRAM1_REQ': {
|
|
'gfx950': ('TCP', 60),
|
|
},
|
|
'TCP_TAGRAM2_REQ': {
|
|
'gfx950': ('TCP', 61),
|
|
},
|
|
'TCP_TAGRAM3_REQ': {
|
|
'gfx950': ('TCP', 62),
|
|
},
|
|
'TCP_TCC_WRITE_REQ_HOLE_LATENCY': {
|
|
'gfx950': ('TCP', 67),
|
|
},
|
|
'TCP_TOTAL_WBINVL1_VOL': {
|
|
'gfx950': ('TCP', 38),
|
|
},
|
|
'TCP_SQ_TCP_INVALIDATE_VOL': {
|
|
'gfx950': ('TCP', 39),
|
|
},
|
|
'TCP_CP_TCP_INVALIDATE_VOL': {
|
|
'gfx950': ('TCP', 40),
|
|
},
|
|
'TCP_UTCL1_STALL_LFIFO_NO_RES': {
|
|
'gfx950': ('TCP', 53),
|
|
},
|
|
'TD_ATOMIC_WAVEFRONT': {
|
|
'gfx90a': ('TD', 26),
|
|
'gfx908': ('TD', 26),
|
|
'gfx940': ('TD', 17),
|
|
'gfx941': ('TD', 17),
|
|
'gfx942': ('TD', 17),
|
|
'gfx950': ('TD', 17),
|
|
},
|
|
'TD_COALESCABLE_WAVEFRONT': {
|
|
'gfx90a': ('TD', 32),
|
|
'gfx908': ('TD', 32),
|
|
'gfx940': ('TD', 21),
|
|
'gfx941': ('TD', 21),
|
|
'gfx942': ('TD', 21),
|
|
'gfx950': ('TD', 21),
|
|
},
|
|
'TD_LOAD_WAVEFRONT': {
|
|
'gfx90a': ('TD', 25),
|
|
'gfx908': ('TD', 25),
|
|
'gfx940': ('TD', 16),
|
|
'gfx941': ('TD', 16),
|
|
'gfx942': ('TD', 16),
|
|
'gfx950': ('TD', 16),
|
|
},
|
|
'TD_SPI_STALL': {
|
|
'gfx90a': ('TD', 18),
|
|
'gfx940': ('TD', 15),
|
|
'gfx941': ('TD', 15),
|
|
'gfx942': ('TD', 15),
|
|
'gfx950': ('TD', 15),
|
|
},
|
|
'TD_STORE_WAVEFRONT': {
|
|
'gfx90a': ('TD', 27),
|
|
'gfx908': ('TD', 27),
|
|
'gfx940': ('TD', 18),
|
|
'gfx941': ('TD', 18),
|
|
'gfx942': ('TD', 18),
|
|
'gfx950': ('TD', 18),
|
|
},
|
|
'TD_TC_STALL': {
|
|
'gfx90a': ('TD', 15),
|
|
'gfx908': ('TD', 15),
|
|
'gfx940': ('TD', 12),
|
|
'gfx941': ('TD', 12),
|
|
'gfx942': ('TD', 12),
|
|
'gfx950': ('TD', 12),
|
|
},
|
|
'TD_TD_BUSY': {
|
|
'gfx90a': ('TD', 1),
|
|
'gfx908': ('TD', 1),
|
|
'gfx940': ('TD', 1),
|
|
'gfx941': ('TD', 1),
|
|
'gfx942': ('TD', 1),
|
|
'gfx950': ('TD', 1),
|
|
},
|
|
'TD_WRITE_ACKT_WAVEFRONT': {
|
|
'gfx950': ('TD', 27),
|
|
},
|
|
'TD_TD_SP_TRAFFIC': {
|
|
'gfx950': ('TD', 29),
|
|
},
|
|
'SQC_DCACHE_INFLIGHT_LEVEL': {
|
|
'gfx90a': ('SQ', 337),
|
|
'gfx908': ('SQ', 337),
|
|
'gfx940': ('SQ', 337),
|
|
'gfx941': ('SQ', 337),
|
|
'gfx942': ('SQ', 337),
|
|
'gfx950': ('SQ', 337),
|
|
},
|
|
'SQC_ICACHE_INFLIGHT_LEVEL': {
|
|
'gfx90a': ('SQ', 336),
|
|
'gfx908': ('SQ', 336),
|
|
'gfx940': ('SQ', 336),
|
|
'gfx941': ('SQ', 336),
|
|
'gfx942': ('SQ', 336),
|
|
'gfx950': ('SQ', 336),
|
|
},
|
|
} |