mirror of
https://github.com/firestar5683/StarPilot.git
synced 2026-11-06 20:43:46 +08:00
Daniel Koepping
102 lines
3.1 KiB
C
102 lines
3.1 KiB
C
#pragma once
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#include "lladc_declarations.h"
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static uint32_t adc_avdd_mV = 0U;
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void adc_init(ADC_TypeDef *adc) {
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adc->CR &= ~(ADC_CR_ADEN); // Disable ADC
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adc->CR &= ~(ADC_CR_DEEPPWD); // Reset deep-power-down mode
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adc->CR |= ADC_CR_ADVREGEN; // Enable ADC regulator
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while(!(adc->ISR & ADC_ISR_LDORDY) && (adc != ADC3));
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if (adc != ADC3) {
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adc->CR &= ~(ADC_CR_ADCALDIF); // Choose single-ended calibration
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adc->CR |= ADC_CR_ADCALLIN; // Lineriality calibration
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}
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adc->CR |= ADC_CR_ADCAL; // Start calibration
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while((adc->CR & ADC_CR_ADCAL) != 0U);
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adc->ISR |= ADC_ISR_ADRDY;
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adc->CR |= ADC_CR_ADEN;
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while(!(adc->ISR & ADC_ISR_ADRDY));
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}
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uint16_t adc_get_raw(const adc_signal_t *signal) {
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signal->adc->SQR1 &= ~(ADC_SQR1_L);
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signal->adc->SQR1 = ((uint32_t) signal->channel << 6U);
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// sample time
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if (signal->channel < 10U) {
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signal->adc->SMPR1 = ((uint32_t) signal->sample_time << (signal->channel * 3U));
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} else {
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signal->adc->SMPR2 = ((uint32_t) signal->sample_time << ((signal->channel - 10U) * 3U));
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}
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// select channel
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signal->adc->PCSEL_RES0 = (0x1UL << signal->channel);
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// oversampling
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signal->adc->CFGR2 = (((1U << (uint32_t) signal->oversampling) - 1U) << ADC_CFGR2_OVSR_Pos) | ((uint32_t) signal->oversampling << ADC_CFGR2_OVSS_Pos);
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signal->adc->CFGR2 |= (signal->oversampling != OVERSAMPLING_1) ? ADC_CFGR2_ROVSE : 0U;
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// start conversion
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signal->adc->CR |= ADC_CR_ADSTART;
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// a stuck ADC reads 0
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uint32_t timeout = 1000000U;
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while (((signal->adc->ISR & ADC_ISR_EOS) == 0U) && (timeout > 0U)) {
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timeout--;
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}
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uint16_t res = (timeout > 0U) ? (uint16_t)signal->adc->DR : 0U;
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signal->adc->ISR = ADC_ISR_EOC | ADC_ISR_EOS;
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return res;
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}
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static uint32_t adc_measure_avdd_mV(void) {
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uint16_t raw_vrefint = adc_get_raw(&(adc_signal_t){.adc = ADC2, .channel = 17U, .sample_time = SAMPLETIME_810_CYCLES, .oversampling = OVERSAMPLING_256});
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return (raw_vrefint != 0U) ? ((uint32_t) *VREFINT_CAL_ADDR * 16U * 3300U / raw_vrefint) : 0U;
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}
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static void adc_calibrate_vdda(void) {
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// ADC2 used for calibration
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adc_init(ADC2);
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// enable VREFINT channel
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register_set_bits(&(ADC3_COMMON->CCR), ADC_CCR_VREFEN);
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register_set_bits(&(SYSCFG->ADC2ALT), SYSCFG_ADC2ALT_ADC2_ROUT1);
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adc_avdd_mV = adc_measure_avdd_mV();
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print(" AVDD: 0x"); puth(adc_avdd_mV); print(" mV\n");
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}
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// the main loop is using ADC2
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static volatile bool adc2_busy = false;
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// ADC_SM_2, ADC_SM_3: AVDD from VREFINT has to match the board
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void adc_check(uint32_t expected_avdd_mV) {
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adc2_busy = true;
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uint32_t avdd_mV = adc_measure_avdd_mV();
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adc2_busy = false;
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if ((avdd_mV <= ((expected_avdd_mV * 9U) / 10U)) || (avdd_mV >= ((expected_avdd_mV * 11U) / 10U))) {
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ENTER_CRITICAL();
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fault_occurred_value(FAULT_ADC, avdd_mV);
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EXIT_CRITICAL();
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}
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}
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uint16_t adc_get_mV(const adc_signal_t *signal) {
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uint16_t ret = 0;
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if (adc_avdd_mV == 0U) {
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adc_calibrate_vdda();
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}
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if ((signal->adc == ADC1) || (signal->adc == ADC2)) {
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ret = (adc_get_raw(signal) * adc_avdd_mV) / 65535U;
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} else if (signal->adc == ADC3) {
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ret = (adc_get_raw(signal) * adc_avdd_mV) / 4095U;
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} else {}
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return ret;
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}
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