mirror of
https://github.com/firestar5683/StarPilot.git
synced 2026-11-08 13:33:42 +08:00
Daniel Koepping
120 lines
3.2 KiB
C
120 lines
3.2 KiB
C
#pragma once
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// Early bringup
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#define ENTER_BOOTLOADER_MAGIC 0xdeadbeefU
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#define ENTER_SOFTLOADER_MAGIC 0xdeadc0deU
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#define BOOT_NORMAL 0xdeadb111U
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extern void *g_pfnVectors;
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extern uint32_t enter_bootloader_mode;
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typedef void (*bootloader_fcn)(void);
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typedef bootloader_fcn *bootloader_fcn_ptr;
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static void jump_to_bootloader(void) {
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// do enter bootloader
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enter_bootloader_mode = 0;
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bootloader_fcn_ptr bootloader_ptr = (bootloader_fcn_ptr)BOOTLOADER_ADDRESS;
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bootloader_fcn bootloader = *bootloader_ptr;
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// jump to bootloader
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enable_interrupts();
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bootloader();
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// reset on exit
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enter_bootloader_mode = BOOT_NORMAL;
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NVIC_SystemReset();
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}
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void early_initialization(void) {
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// Reset global critical depth
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disable_interrupts();
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global_critical_depth = 0;
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// Init register and interrupt tables
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init_registers();
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// after it's been in the bootloader, things are initted differently, so we reset
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if ((enter_bootloader_mode != BOOT_NORMAL) &&
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(enter_bootloader_mode != ENTER_BOOTLOADER_MAGIC) &&
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(enter_bootloader_mode != ENTER_SOFTLOADER_MAGIC)) {
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enter_bootloader_mode = BOOT_NORMAL;
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NVIC_SystemReset();
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}
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// if wrong chip, reboot
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volatile unsigned int id = DBGMCU->IDCODE;
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if ((id & 0xFFFU) != MCU_IDCODE) {
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enter_bootloader_mode = ENTER_BOOTLOADER_MAGIC;
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}
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// setup interrupt table
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register_set(&(SCB->VTOR), (uint32_t)&g_pfnVectors, SCB_VTOR_TBLOFF_Msk);
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// early GPIOs float everything
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early_gpio_float();
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detect_board_type();
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if (enter_bootloader_mode == ENTER_BOOTLOADER_MAGIC) {
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led_init();
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led_set(LED_GREEN, 1);
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jump_to_bootloader();
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}
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}
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// we might hit NMI / HardFault close to brown-out.
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// we don't want to infinitely loop, so let's set a logging cookie and reset.
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#define NMI_COOKIE 0x4E4D4921U
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#define HARDFAULT_COOKIE 0x48464C54U
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extern uint32_t fault_cookie;
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#ifdef STM32H7
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extern uint32_t fault_cfsr;
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extern uint32_t fault_addr;
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extern uint32_t fault_pc;
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// frame is the stacked r0-r3, r12, lr, pc and xpsr, panda only runs on the MSP
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static void fault_record(uint32_t cookie, const uint32_t *frame) {
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fault_cookie = cookie;
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if (cookie == HARDFAULT_COOKIE) {
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fault_cfsr = SCB->CFSR;
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fault_addr = ((fault_cfsr & SCB_CFSR_MMARVALID_Msk) != 0U) ? SCB->MMFAR : SCB->BFAR;
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}
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// a failed stacking leaves no frame to read
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fault_pc = ((SCB->CFSR & (SCB_CFSR_MSTKERR_Msk | SCB_CFSR_STKERR_Msk)) == 0U) ? frame[6] : 0U;
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NVIC_SystemReset();
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}
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__attribute__((used)) static void nmi_record(const uint32_t *frame) {
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fault_record(NMI_COOKIE, frame);
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}
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__attribute__((used)) static void hardfault_record(const uint32_t *frame) {
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fault_record(HARDFAULT_COOKIE, frame);
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}
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// naked to read the frame before anything is pushed
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__attribute__((naked)) void NMI_Handler(void) {
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// cppcheck-suppress misra-c2012-17.3 ; inline asm
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__asm volatile ("mrs r0, msp\n b nmi_record");
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}
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__attribute__((naked)) void HardFault_Handler(void) {
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// cppcheck-suppress misra-c2012-17.3 ; inline asm
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__asm volatile ("mrs r0, msp\n b hardfault_record");
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}
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#else
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void NMI_Handler(void) {
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fault_cookie = NMI_COOKIE;
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NVIC_SystemReset();
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}
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void HardFault_Handler(void) {
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fault_cookie = HARDFAULT_COOKIE;
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NVIC_SystemReset();
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}
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#endif
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