mirror of
https://github.com/firestar5683/StarPilot.git
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firestar5683
22a8575199
Keep official openpilot ancestry and dependency licenses. Store resources directly in Git, remove LFS setup requirements, and leave the downloadable big model outside the source tree.
227 lines
11 KiB
Python
227 lines
11 KiB
Python
from __future__ import annotations
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import ctypes, mmap, struct, sys
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if sys.platform != "win32": from tinygrad.runtime.autogen import libc
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class MockUSB:
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def __init__(self, mem):
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self.mem = mem
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def read(self, address, size): return bytes(self.mem[address:address+size])
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def write(self, address, data): self.mem[address:address+len(data)] = data
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def pcie_mem_read(self, address, nbytes): return bytes(self.mem[address:address+nbytes])
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def pcie_mem_write(self, address, data): self.mem[address:address+len(data)] = data
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# *** ASM24 Controller Mock ***
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_mock_usb_state: MockASM24State|None = None
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class MockASM24State:
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"""Mock custom ASM24 controller: XRAM, DMA windows, PCI config space, and GPU BARs.
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Memory map (64KB XRAM):
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0xA000-0xAFFF: DMA window -> sys 0x820000
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0xB000-0xB1FF: DMA window -> sys 0x800000
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0xB200-0xB7FF: controller PCI MMIO
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0xF000-0xFFFF: DMA window -> sys 0x200000 (512KB)
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"""
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XRAM_SIZE = 0x10000
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def __init__(self, gpu, driver, vram_size:int, doorbell_size:int, mmio_size:int):
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self.gpu, self.driver = gpu, driver
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self._xram = bytearray(self.XRAM_SIZE)
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self._doorbell_addr = libc.mmap(0, doorbell_size, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED, gpu.doorbell_fd, 0)
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self._doorbell = (ctypes.c_ubyte * doorbell_size).from_address(self._doorbell_addr)
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# DMA windows: ctrl_addr -> (host_addr, size)
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self._dma_regions: dict[int, tuple[int, int]] = {}
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self._add_dma_window(0xF000, 0x200000, 0x80000)
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self._add_dma_window(0xA000, 0x820000, 0x1000)
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self._add_dma_window(0xB000, 0x800000, 0x200)
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# PCI config space: (bus,dev,fn) -> bytearray(4096)
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self._pci_cfg: dict[tuple[int,int,int], bytearray] = {}
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# GPU BAR definitions: reg_offset -> (size, type_bits, is_64bit)
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self._gpu_bars: dict[int, tuple[int, int, bool]] = {
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0x10: (vram_size, 0x0C, True), # BAR0: VRAM, 64-bit prefetchable
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0x18: (doorbell_size, 0x00, False), # BAR2: doorbell, 32-bit
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0x1C: (0, 0x00, False), # BAR3: unused
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0x20: (0, 0x00, False), # BAR4: unused
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0x24: (mmio_size, 0x00, False), # BAR5: MMIO, 32-bit
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}
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self._bar_addrs: dict[int, tuple[int, int]] = {} # reg_offset -> (addr, size)
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# Initialize GPU config space (bus=4, dev=0, fn=0) with BAR type bits and REBAR capability
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gpu_cfg = self._get_cfg(4, 0, 0)
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for reg_off, (sz, type_bits, _) in self._gpu_bars.items():
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if sz > 0: struct.pack_into('<I', gpu_cfg, reg_off, type_bits)
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struct.pack_into('<I', gpu_cfg, 0x100, 0x15 | (1 << 16)) # REBAR cap header: id=0x15, version=1, next=0
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struct.pack_into('<I', gpu_cfg, 0x104, sum(1 << (i + 4) for i in range(10))) # supported sizes up to 512MB
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def _get_cfg(self, bus:int, dev:int, fn:int) -> bytearray:
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if (key:=(bus, dev, fn)) not in self._pci_cfg: self._pci_cfg[key] = bytearray(4096)
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return self._pci_cfg[key]
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def _add_dma_window(self, ctrl_addr:int, sys_addr:int, size:int):
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host_addr = libc.mmap(0, size, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | mmap.MAP_ANONYMOUS, -1, 0)
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self._dma_regions[ctrl_addr] = (host_addr, size)
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for off in range(0, size, 0x1000): self.gpu._sysmem_map[sys_addr + off] = host_addr + off
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# --- XRAM access ---
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def _xram_read(self, addr:int, length:int) -> bytes:
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for ctrl_addr, (host_addr, dma_size) in self._dma_regions.items():
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if ctrl_addr <= addr < ctrl_addr + dma_size:
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return bytes((ctypes.c_ubyte * length).from_address(host_addr + (addr - ctrl_addr)))
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return bytes(self._xram[addr:addr+length])
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def _xram_write_byte(self, addr:int, value:int):
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for ctrl_addr, (host_addr, dma_size) in self._dma_regions.items():
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if ctrl_addr <= addr < ctrl_addr + dma_size:
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(ctypes.c_ubyte * 1).from_address(host_addr + (addr - ctrl_addr))[0] = value
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return
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self._xram[addr] = value
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def _cfg_write(self, bus:int, dev:int, fn:int, byte_addr:int, val:int, size:int):
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cfg = self._get_cfg(bus, dev, fn)
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# Handle BAR register writes for GPU device (bus=4, dev=0, fn=0)
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if (bus, dev, fn) == (4, 0, 0) and 0x10 <= byte_addr < 0x28 and size == 4:
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reg_off = byte_addr & ~0x3
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if (bar_def:=self._gpu_bars.get(reg_off)) is not None:
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bar_size, type_bits, is_64 = bar_def
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if bar_size == 0: return # unused BAR
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if val == 0xFFFFFFFF: # size probe
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struct.pack_into('<I', cfg, reg_off, (~(bar_size - 1)) & 0xFFFFFFF0 | type_bits)
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else:
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struct.pack_into('<I', cfg, reg_off, val)
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hi = struct.unpack_from('<I', cfg, reg_off + 4)[0] if is_64 else 0
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self._bar_addrs[reg_off] = ((hi << 32) | (val & ~0xF), bar_size)
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return
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# Check if upper 32 bits of a 64-bit BAR
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for breg, (bsz, _, b64) in self._gpu_bars.items():
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if b64 and reg_off == breg + 4:
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struct.pack_into('<I', cfg, reg_off, 0xFFFFFFFF if val == 0xFFFFFFFF else val)
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if val != 0xFFFFFFFF:
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self._bar_addrs[breg] = ((val << 32) | (struct.unpack_from('<I', cfg, breg)[0] & ~0xF), bsz)
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return
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# Generic config write
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for i in range(size): cfg[byte_addr + i] = (val >> (8 * i)) & 0xFF
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def _find_bar(self, address:int, size:int) -> tuple[int, int]:
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for reg_off, (bar_addr, bar_size) in self._bar_addrs.items():
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if bar_addr <= address and address + size <= bar_addr + bar_size: return reg_off, address - bar_addr
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raise ValueError(f"PCIe range {address:#x}+{size:#x} not mapped to any BAR")
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def _pcie_read(self, address:int, size:int) -> bytes:
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reg_off, offset = self._find_bar(address, size)
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if reg_off == 0x10: return bytes(self.gpu.vram[offset:offset+size])
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if reg_off == 0x18: return bytes(self._doorbell[offset:offset+size])
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if reg_off == 0x24: return bytes((self.gpu.mmio[(offset+i)//4] >> (8*((offset+i)&3))) & 0xFF for i in range(size))
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raise RuntimeError(f"unsupported BAR register {reg_off:#x}")
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def _pcie_write(self, address:int, data:bytes):
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reg_off, offset = self._find_bar(address, len(data))
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if reg_off == 0x10: self.gpu.vram[offset:offset+len(data)] = list(data)
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elif reg_off == 0x18:
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self._doorbell[offset:offset+len(data)] = list(data)
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self.driver._emulate_execute()
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elif reg_off == 0x24:
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updates: dict[int, int] = {}
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for i, byte in enumerate(data):
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idx, shift = (offset+i)//4, 8*((offset+i)&3)
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updates[idx] = (updates.get(idx, self.gpu.mmio[idx]) & ~(0xFF << shift)) | (byte << shift)
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for idx, val in updates.items(): self.gpu.mmio[idx] = val
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else: raise RuntimeError(f"unsupported BAR register {reg_off:#x}")
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def _pcie_dispatch(self, address:int, value:int|None, size:int) -> int|None:
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if value is None: return int.from_bytes(self._pcie_read(address, size), 'little')
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self._pcie_write(address, value.to_bytes(size, 'little'))
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return None
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class MockUSB3:
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@classmethod
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def list_devices(cls, vendor, dev): return [(0, "usb:mock")]
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def __init__(self, *args, **kwargs):
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self.product = "custom mock"
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self._bulk_read_op: tuple[str, int, int]|None = None
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self._bulk_write_op: tuple[str, int, int]|None = None
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self._f0_reply = bytes(8)
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@property
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def state(self) -> MockASM24State:
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assert _mock_usb_state is not None
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return _mock_usb_state
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def control_write(self, request:int, value:int=0, index:int=0, data:bytes=b'', timeout:int=1000):
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if request == 0xF3:
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self.state._xram[0xB450] = 0x78 if value else 0
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elif request == 0xE5:
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self.state._xram_write_byte(value, index)
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elif request == 0xF2:
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op = ("sram_read" if value & 0x8000 else "sram_write", 0xF000 + (index & 0xFF) * 0x4000, (value & 0x7FFF) * 512)
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if value & 0x8000: self._bulk_read_op = op
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else: self._bulk_write_op = op
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elif request == 0xF0:
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address_lo, address_hi, payload = struct.unpack('<III', data)
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address, fmt_type, byte_en = address_lo | (address_hi << 32), value & 0xFF, value >> 8
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if index == 1: self._bulk_write_op = ("pcie_write", address, payload * 4)
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elif index == 2: self._bulk_read_op = ("pcie_read", address, payload * 4)
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else:
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assert index == 0 and byte_en
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offset = (byte_en & -byte_en).bit_length() - 1
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size, is_write, is_cfg = byte_en.bit_count(), bool(fmt_type & 0x40), (fmt_type & 0xBE) == 0x04
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if is_cfg:
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bus, dev, fn, byte_addr = (address >> 24) & 0xFF, (address >> 19) & 0x1F, (address >> 16) & 0x7, address & 0xFFC
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if is_write: self.state._cfg_write(bus, dev, fn, byte_addr + offset, (payload >> (8 * offset)) & ((1 << (8 * size))-1), size)
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else: payload = int.from_bytes(self.state._get_cfg(bus, dev, fn)[byte_addr:byte_addr+4], 'little')
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elif is_write:
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self.state._pcie_dispatch(address + offset, (payload >> (8 * offset)) & ((1 << (8 * size))-1), size)
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else: payload = (self.state._pcie_dispatch(address + offset, None, size) or 0) << (8 * offset)
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self._f0_reply = struct.pack('<I', payload & 0xFFFFFFFF) + bytes(4)
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else: raise ValueError(f"unsupported control OUT request 0x{request:02X}")
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def control_read(self, request:int, length:int, value:int=0, index:int=0, timeout:int=1000) -> memoryview:
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if request == 0xE4: data = self.state._xram_read(value, length)
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elif request == 0xF0: data = self._f0_reply
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else: raise ValueError(f"unsupported control IN request 0x{request:02X}")
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return memoryview(data[:length])
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def bulk_write(self, data:bytes, timeout:int=1000):
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assert self._bulk_write_op is not None
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op, address, size = self._bulk_write_op
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assert len(data) == size
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if op == "sram_write":
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ctrl, (host_addr, region_size) = next((ca, r) for ca, r in self.state._dma_regions.items() if ca <= address < ca + r[1])
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ctypes.memmove(host_addr + (address - ctrl), data, min(len(data), region_size - (address - ctrl)))
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self.state.driver._emulate_execute() # landed data may un-stall a ring polling on it (e.g. copyin sentinels)
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elif op == "pcie_write": self.state._pcie_write(address, data)
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else: raise RuntimeError(f"cannot bulk write for {op}")
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self._bulk_write_op = None
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def bulk_write_async(self, payload:memoryview, timeout:int=10000) -> int: # the mock completes transfers synchronously
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self.bulk_write(bytes(payload), timeout)
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return 0
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def control_write_async(self, request:int, value:int=0, index:int=0, data:bytes=b"", timeout:int=1000) -> int:
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self.control_write(request, value, index, data, timeout)
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return 0
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def control_read_async(self, request:int, length:int, value:int=0, index:int=0, timeout:int=1000) -> tuple[int, memoryview]:
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return 0, self.control_read(request, length, value, index, timeout)
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def bulk_wait(self, tag:int): pass
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def bulk_read(self, length:int, timeout:int=1000) -> memoryview:
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assert self._bulk_read_op is not None
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op, address, size = self._bulk_read_op
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assert length == size
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if op == "sram_read":
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ctrl, (host_addr, region_size) = next((ca, r) for ca, r in self.state._dma_regions.items() if ca <= address < ca + r[1])
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data = bytes((ctypes.c_ubyte * min(length, region_size - (address - ctrl))).from_address(host_addr + (address - ctrl)))
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elif op == "pcie_read": data = self.state._pcie_read(address, length)
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else: raise RuntimeError(f"cannot bulk read for {op}")
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self._bulk_read_op = None
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return memoryview(data)
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