mirror of
https://github.com/firestar5683/StarPilot.git
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firestar5683
22a8575199
Keep official openpilot ancestry and dependency licenses. Store resources directly in Git, remove LFS setup requirements, and leave the downloadable big model outside the source tree.
452 lines
18 KiB
Python
452 lines
18 KiB
Python
import ctypes, time
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from dataclasses import replace
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from test.mockgpu.gpu import VirtGPU
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from test.mockgpu.helpers import PythonRemu
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from tinygrad.helpers import getbits, to_mv, getenv, DEV
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from tinygrad.runtime.support import c
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MOCKGPU_ARCH = "cdna4" if DEV.arch == "gfx950" else "rdna4" if DEV.arch.startswith("gfx12") else "rdna3"
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assert (ma:=getenv("MOCKGPU_ARCH", "")) == "", "MOCKGPU_ARCH is deprecated, use DEV=" + \
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str(replace(DEV.value, arch={"cdna4":"gfx950", "rdna4":"gfx1201"}.get(ma, "gfx1100"))) # type: ignore
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GFX_TARGET_VERSION = {"rdna3": 110000, "rdna4": 120000, "cdna4": 90500}[MOCKGPU_ARCH]
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import tinygrad.runtime.autogen.amd_gpu as amd_gpu, tinygrad.runtime.autogen.am.pm4_nv as pm4, tinygrad.runtime.autogen.am.sdma_6_0_0 as sdma
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SDMA_MAX_COPY_SIZE = 0x400000
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regCOMPUTE_PGM_LO = 0x1bac + amd_gpu.GC_BASE__INST0_SEG0
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regCOMPUTE_PGM_RSRC2 = 0x1bb3 + amd_gpu.GC_BASE__INST0_SEG0
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regCOMPUTE_TMPRING_SIZE = 0x1bb8 + amd_gpu.GC_BASE__INST0_SEG0
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regCOMPUTE_USER_DATA_0 = 0x1be0 + amd_gpu.GC_BASE__INST0_SEG0
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regCOMPUTE_NUM_THREAD_X = 0x1ba7 + amd_gpu.GC_BASE__INST0_SEG0
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regGRBM_GFX_INDEX = 0x2200 + amd_gpu.GC_BASE__INST0_SEG1
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regSQ_THREAD_TRACE_BUF0_BASE = 0x39e8 + amd_gpu.GC_BASE__INST0_SEG1
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regSQ_THREAD_TRACE_BUF0_SIZE = {"rdna3": 0x39e9, "rdna4": 0x39e6, "cdna4": 0x39e9}[MOCKGPU_ARCH] + amd_gpu.GC_BASE__INST0_SEG1
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regSQ_THREAD_TRACE_WPTR = 0x39ef + amd_gpu.GC_BASE__INST0_SEG1
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regSQ_THREAD_TRACE_STATUS = 0x39f4 + amd_gpu.GC_BASE__INST0_SEG1
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regCP_PERFMON_CNTL = 0x3808 + amd_gpu.GC_BASE__INST0_SEG1
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regCPG_PERFCOUNTER1_LO = 0x3000 + amd_gpu.GC_BASE__INST0_SEG1
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regGUS_PERFCOUNTER_HI = 0x3643 + amd_gpu.GC_BASE__INST0_SEG1
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# RDNA 4
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regSQ_THREAD_TRACE_BUF0_BASE_LO = 0x39e7 + amd_gpu.GC_BASE__INST0_SEG1
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regSQ_THREAD_TRACE_BUF0_BASE_HI = regSQ_THREAD_TRACE_BUF0_BASE
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class SQTT_EVENTS:
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THREAD_TRACE_FINISH = 0x00000037
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CACHE_FLUSH_AND_INV_TS_EVENT = 0x14
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WAIT_REG_MEM_FUNCTION_ALWAYS = 0
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WAIT_REG_MEM_FUNCTION_EQ = 3 # ==
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WAIT_REG_MEM_FUNCTION_NEQ = 4 # !=
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WAIT_REG_MEM_FUNCTION_GEQ = 5 # >=
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remu = PythonRemu()
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def create_sdma_packets():
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# TODO: clean up this, if we want to keep it
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structs = {}
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for name,pkt in [(name,s) for name,s in amd_gpu.__dict__.items() if name.startswith("rocr_AMD_SDMA_PKT_") and name.endswith("_TAG")]:
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names = set()
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fields = []
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for pkt_fields in pkt._real_fields_:
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if not pkt_fields[0].endswith("_UNION"): fields.append(pkt_fields)
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else:
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for union_fields in pkt_fields[1]._real_fields_[:-1]:
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fname = union_fields[0]
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if fname in names: fname = pkt_fields[0]+fname
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names.add(fname)
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# merge together 64-bit fields, otherwise just append them
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if fname.endswith("_63_32") and fields[-1][0].endswith("_31_0"): fields[-1] = (fname[:-6], ctypes.c_ulong, fields[-1][2], 64, 0)
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else: fields.append((fname, union_fields[1], union_fields[2] + pkt_fields[2], *union_fields[3:]))
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new_name = name[18:-4].lower()
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structs[new_name] = c.init_c_struct_t(ctypes.sizeof(pkt), tuple(fields))
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return type("SDMA_PKTS", (object, ), structs)
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sdma_pkts = create_sdma_packets()
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class AMDQueue:
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def __init__(self, base, size, rptr, wptr):
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self.queue, self.size = to_mv(base, size).cast("I"), size
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self.rptr = to_mv(rptr, 8).cast("Q") if isinstance(rptr, int) else rptr
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self.wptr = to_mv(wptr, 8).cast("Q") if isinstance(wptr, int) else wptr
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@property
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def executing(self): return self.rptr[0] < self.wptr[0]
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class PM4Executor(AMDQueue):
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def __init__(self, gpu, base, size, rptr, wptr):
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self.gpu = gpu
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self.ib_executor: PM4Executor|None = None
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super().__init__(base, size, rptr, wptr)
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def _next_dword(self):
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x = self.queue[self.rptr[0] % (self.size // 4)]
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self.rptr[0] += 1
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return x
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@property
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def executing(self): return self.rptr[0] < self.wptr[0] or self.ib_executor is not None
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def execute(self):
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prev_rptr, executed_in_ib, cont = self.rptr[0], 0, True
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while self.executing and cont:
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if self.ib_executor is not None:
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executed_in_ib += self.ib_executor.execute()
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if self.ib_executor.executing: break
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self.ib_executor = None
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continue # this continue is needed if PACKET3_INDIRECT_BUFFER is the last packet and rptr == wptr
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header = self._next_dword()
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packet_type = header >> 30
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op = (header >> 8) & 0xFF
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n = (header >> 16) & 0x3FFF
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assert packet_type == 3, "Can parse only packet3"
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if op == amd_gpu.PACKET3_SET_SH_REG: self._exec_set_reg(n, pm4.PACKET3_SET_SH_REG_START)
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elif op == amd_gpu.PACKET3_SET_UCONFIG_REG: self._exec_set_reg(n, pm4.PACKET3_SET_UCONFIG_REG_START)
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elif op == amd_gpu.PACKET3_ACQUIRE_MEM: self._exec_acquire_mem(n)
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elif op == amd_gpu.PACKET3_RELEASE_MEM: self._exec_release_mem(n)
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elif op == amd_gpu.PACKET3_COPY_DATA: self._exec_copy_data(n)
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elif op == amd_gpu.PACKET3_WAIT_REG_MEM: cont = self._exec_wait_reg_mem(n)
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elif op == amd_gpu.PACKET3_DISPATCH_DIRECT: self._exec_dispatch_direct(n)
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elif op == amd_gpu.PACKET3_INDIRECT_BUFFER: self._exec_indirect_buffer(n)
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elif op == amd_gpu.PACKET3_EVENT_WRITE: self._exec_event_write(n)
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else: raise RuntimeError(f"PM4: Unknown opcode: {op}")
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return (self.rptr[0] - prev_rptr) + executed_in_ib
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def _exec_acquire_mem(self, n):
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assert n in (5, 6)
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for _ in range(n + 1): self._next_dword() # TODO: implement
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def _exec_release_mem(self, n):
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assert n == 6
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mem_event_type = (self._next_dword() >> 0) & 0xff
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selectors = self._next_dword()
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mem_data_sel = (selectors >> 29) & 0b111
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# int_sel = (selectors >> 24) & 0b11
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# mem_dst_sel = (selectors >> 16) & 0b1
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addr_lo = self._next_dword()
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addr_hi = self._next_dword()
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val_lo = self._next_dword()
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val_hi = self._next_dword()
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val = val_lo + (val_hi << 32)
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_ = self._next_dword() # ev
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ptr = to_mv(self.gpu.translate_addr(addr_lo + (addr_hi << 32)), 8)
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if mem_data_sel == 1: ptr.cast('I')[0] = val & 0xffffffff
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elif mem_data_sel == 2: ptr.cast('Q')[0] = val
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elif mem_data_sel == 3:
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if mem_event_type == CACHE_FLUSH_AND_INV_TS_EVENT: ptr.cast('Q')[0] = int(time.perf_counter() * 1e8)
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else: raise RuntimeError(f"Unknown {mem_data_sel=} {mem_event_type=}")
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elif mem_data_sel == 0: pass # no write
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else: raise RuntimeError(f"Unknown {mem_data_sel=}")
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def _exec_copy_data(self, n):
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assert n == 4
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copy_data_flags = self._next_dword()
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src_addr_lo = self._next_dword()
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_src_addr_hi = self._next_dword()
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dst_addr_lo = self._next_dword()
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dst_addr_hi = self._next_dword()
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assert copy_data_flags in {0x100204, 0x000204}, hex(copy_data_flags) # better fail than silently do the wrong thing
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to_mv(self.gpu.translate_addr(dst_addr_hi<<32|dst_addr_lo), 4).cast('I')[0] = self.gpu.regs[src_addr_lo]
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def _exec_wait_reg_mem(self, n):
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assert n == 5
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info = self._next_dword()
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addr_lo = self._next_dword()
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addr_hi = self._next_dword()
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val = self._next_dword()
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mask = self._next_dword()
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_ = self._next_dword() # timeout
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mem_function = (info >> 0) & 0b111
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mem_space = (info >> 4) & 0b1
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mem_op = (info >> 6) & 0b1
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_ = (info >> 8) & 0b1 # mem_engine
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if mem_space == 0 and mem_op == 1: mval = val # hack for memory barrier, should properly handle (req_req, reg_done)
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elif mem_space == 0: mval = self.gpu.regs[addr_hi<<32|addr_lo]
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elif mem_space == 1: mval = to_mv(self.gpu.translate_addr(addr_lo + (addr_hi << 32)), 4).cast('I')[0]
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mval &= mask
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if mem_function == WAIT_REG_MEM_FUNCTION_GEQ: can_cont = bool(mval >= val)
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elif mem_function == WAIT_REG_MEM_FUNCTION_NEQ: can_cont = bool(mval != val)
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elif mem_function == WAIT_REG_MEM_FUNCTION_EQ: can_cont = bool(mval == val)
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else: raise RuntimeError(f"Do not support {mem_function=}")
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if not can_cont: self.rptr[0] = self.rptr[0] - 7 # revert this packet, need to wait again
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return can_cont
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def _exec_set_reg(self, n, off):
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reg = off + self._next_dword()
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for i in range(n):
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self.gpu.regs[reg] = self._next_dword()
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reg += 1
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def _exec_dispatch_direct(self, n):
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assert n == 3
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gl = [self._next_dword() for _ in range(3)]
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_ = self._next_dword() # flags
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prg_addr = (self.gpu.regs[regCOMPUTE_PGM_LO] + (self.gpu.regs[regCOMPUTE_PGM_LO + 1] << 32)) << 8
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args_addr = self.gpu.regs[regCOMPUTE_USER_DATA_0] + (self.gpu.regs[regCOMPUTE_USER_DATA_0 + 1] << 32)
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lc = [self.gpu.regs[i] for i in range(regCOMPUTE_NUM_THREAD_X, regCOMPUTE_NUM_THREAD_X+3)]
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rsrc2 = self.gpu.regs[regCOMPUTE_PGM_RSRC2]
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# Read all user data registers (hardware loads these directly into s[0:N])
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user_sgpr_count = (rsrc2 >> 1) & 0x1F # USER_SGPR_COUNT is bits 1:5
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user_data = []
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for i in range(user_sgpr_count):
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try: user_data.append(self.gpu.regs[regCOMPUTE_USER_DATA_0 + i])
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except KeyError: user_data.append(0)
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prg_sz = 0
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for st,sz in self.gpu.mapped_ranges:
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if st <= prg_addr < st+sz: prg_sz = sz - (prg_addr - st)
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# Get scratch size from COMPUTE_TMPRING_SIZE register
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# WAVESIZE = ceildiv(lanes * size_per_thread, mem_alignment_size)
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# GFX11+: mem_alignment_size=256, so size_per_thread = WAVESIZE * 256 / 64 = WAVESIZE * 4
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# GFX9: mem_alignment_size=1024, so size_per_thread = WAVESIZE * 1024 / 64 = WAVESIZE * 16
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try: tmpring_size = self.gpu.regs[regCOMPUTE_TMPRING_SIZE]
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except KeyError: tmpring_size = 0
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wavesize = (tmpring_size >> 12) & 0x3FFF # WAVESIZE field is bits 12:25
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scratch_size = wavesize * (16 if self.gpu.arch == "cdna" else 4) # per-thread scratch size in bytes
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assert prg_sz > 0, "Invalid prg ptr (not found in mapped ranges)"
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# Pass valid memory ranges, rsrc2, scratch_size, arch, and user data registers to the emulator
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remu.valid_mem_ranges = self.gpu.mapped_ranges
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remu.rsrc2 = rsrc2
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remu.scratch_size = scratch_size
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remu.arch = self.gpu.arch
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remu.user_data = user_data
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err = remu.run_asm(prg_addr, prg_sz, gl[0], gl[1], gl[2], lc[0], lc[1], lc[2], args_addr)
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if err != 0: raise RuntimeError("remu does not support the new instruction introduced in this kernel")
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def _exec_indirect_buffer(self, n):
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addr_lo = self._next_dword()
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addr_hi = self._next_dword()
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buf_sz = self._next_dword() & (0x7fffff)
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rptr = memoryview(bytearray(8)).cast('Q')
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wptr = memoryview(bytearray(8)).cast('Q')
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rptr[0] = 0
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wptr[0] = buf_sz
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self.ib_executor = PM4Executor(self.gpu, self.gpu.translate_addr((addr_hi << 32) | addr_lo), buf_sz * 4, rptr, wptr)
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def _exec_event_write(self, n):
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assert n == 0
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event_dw = self._next_dword()
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match (event_dw & 0xFF): # event type
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case SQTT_EVENTS.THREAD_TRACE_FINISH:
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# Get the most recent trace from the emulator (if available)
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from test.mockgpu.amd.emu import sqtt_traces
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blob = sqtt_traces.pop(0) if sqtt_traces else b''
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old_idx = self.gpu.regs.grbm_index
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for se in range(self.gpu.regs.n_se):
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self.gpu.regs.grbm_index = 0b011 << 29 | se << 16 # select se, broadcast sa and instance
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self.gpu.regs[regSQ_THREAD_TRACE_STATUS] = 1 << 12 # FINISH_PENDING==0 FINISH_DONE==1 BUSY==0
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if MOCKGPU_ARCH == "rdna3":
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buf_addr = ((self.gpu.regs[regSQ_THREAD_TRACE_BUF0_SIZE]&0xf)<<32|self.gpu.regs[regSQ_THREAD_TRACE_BUF0_BASE])<<12
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else:
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buf_addr = ((self.gpu.regs[regSQ_THREAD_TRACE_BUF0_BASE_HI])<<32|self.gpu.regs[regSQ_THREAD_TRACE_BUF0_BASE_LO])<<12
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# Use real trace blob for SE 0 (which has itrace enabled), empty blob for other SEs
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se_blob = blob if se == 0 else b''
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# Write blob to trace buffer
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if se_blob: ctypes.memmove(buf_addr, se_blob, len(se_blob))
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# RDNA3 has absolute address for wptr, RDNA4 has relative
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wptr_val = (((buf_addr if MOCKGPU_ARCH == "rdna3" else 0) + len(se_blob)) // 32) & 0x1FFFFFFF
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self.gpu.regs[regSQ_THREAD_TRACE_WPTR] = wptr_val
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self.gpu.regs.grbm_index = old_idx
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case _: pass # NOTE: for now most events aren't emulated
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class SDMAExecutor(AMDQueue):
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def __init__(self, gpu, base, size, rptr, wptr):
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self.gpu, self.base = gpu, base
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super().__init__(base, size, rptr, wptr)
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def execute(self):
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prev_rptr, cont = self.rptr[0], True
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while self.executing and cont:
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header = self.queue[(self.rptr[0] // 4) % (self.size // 4)]
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op = (header >> 0) & 0xff
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if op == 0: self.rptr[0] += 4
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elif op == amd_gpu.SDMA_OP_FENCE: self._execute_fence()
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elif op == amd_gpu.SDMA_OP_TRAP: self._execute_trap()
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elif op == amd_gpu.SDMA_OP_POLL_REGMEM: cont = self._execute_poll_regmem()
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elif op == amd_gpu.SDMA_OP_GCR: self._execute_gcr()
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elif op == amd_gpu.SDMA_OP_COPY: self._execute_copy()
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elif op == sdma.SDMA_OP_WRITE: self._execute_write()
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elif op == amd_gpu.SDMA_OP_TIMESTAMP: self._execute_timestamp()
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elif op == 32: self.rptr[0] += 4 # SDMA_OP_DUMMY_TRAP: pipeline flush, no interrupt
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else: raise RuntimeError(f"Unknown SDMA op {op}")
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return self.rptr[0] - prev_rptr
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def _execute_fence(self):
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struct = sdma_pkts.fence.from_address(self.base + self.rptr[0] % self.size)
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to_mv(self.gpu.translate_addr(struct.addr), 8).cast('Q')[0] = struct.data
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self.rptr[0] += ctypes.sizeof(struct)
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def _execute_trap(self):
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struct = sdma_pkts.trap.from_address(self.base + self.rptr[0] % self.size)
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self.rptr[0] += ctypes.sizeof(struct)
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def _execute_write(self):
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packet = to_mv(self.base + self.rptr[0] % self.size, 16).cast('I')
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addr, count = packet[1] | packet[2] << 32, packet[3] + 1
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ctypes.memmove(self.gpu.translate_addr(addr), self.base + self.rptr[0] % self.size + 16, count * 4)
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self.rptr[0] += (4 + count) * 4
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def _execute_poll_regmem(self):
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struct = sdma_pkts.poll_regmem.from_address(self.base + self.rptr[0] % self.size)
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if struct.mem_poll == 0: mval = struct.value & struct.mask
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elif struct.mem_poll == 1: mval = to_mv(self.gpu.translate_addr(struct.addr), 4).cast('I')[0] & struct.mask
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if struct.func == WAIT_REG_MEM_FUNCTION_GEQ: can_cont = bool(mval >= struct.value)
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elif struct.func == WAIT_REG_MEM_FUNCTION_EQ: can_cont = bool(mval == struct.value)
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elif struct.func == WAIT_REG_MEM_FUNCTION_ALWAYS: can_cont = True
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else: raise RuntimeError(f"Do not support {struct.func=}")
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if not can_cont: return False
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self.rptr[0] += ctypes.sizeof(struct)
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return True
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def _execute_timestamp(self):
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struct = sdma_pkts.timestamp.from_address(self.base + self.rptr[0] % self.size)
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mem = to_mv(self.gpu.translate_addr(struct.addr), 8).cast('Q')
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mem[0] = int(time.perf_counter() * 1e8)
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self.rptr[0] += ctypes.sizeof(struct)
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def _execute_gcr(self):
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struct = sdma_pkts.gcr.from_address(self.base + self.rptr[0] % self.size)
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self.rptr[0] += ctypes.sizeof(struct)
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def _execute_copy(self):
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struct = sdma_pkts.copy_linear.from_address(self.base + self.rptr[0] % self.size)
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count, off = (to_mv(self.base + self.rptr[0] % self.size + 4, 4).cast('I')[0] & 0x3FFFFFFF) + 1, 0
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while off < count: # a page at a time: the physical pages of a range needn't be contiguous
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n = min(count - off, 0x1000 - ((struct.src_addr + off) & 0xfff), 0x1000 - ((struct.dst_addr + off) & 0xfff))
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ctypes.memmove(self.gpu.translate_addr(struct.dst_addr + off), self.gpu.translate_addr(struct.src_addr + off), n)
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off += n
|
|
self.rptr[0] += ctypes.sizeof(struct)
|
|
|
|
class AMDGPURegisters:
|
|
def __init__(self, n_se:int=6):
|
|
self.n_se = n_se
|
|
self.grbm_index = 0b111 << 0x1d # all broadcast. NOTE: only per-se register emulation is currently supported
|
|
self.regs: dict[tuple[int, int], int] = {}
|
|
def __getitem__(self, addr:int) -> int:
|
|
if addr == regGRBM_GFX_INDEX: return self.grbm_index
|
|
if regCPG_PERFCOUNTER1_LO < addr < regGUS_PERFCOUNTER_HI:
|
|
assert self.regs[(regCP_PERFMON_CNTL, 0)] == 0x401, "read mode should be enabled"
|
|
return addr << 16 | self.grbm_index
|
|
return self.regs[(addr, getbits(self.grbm_index, 16, 23))]
|
|
def __setitem__(self, addr:int, val:int):
|
|
if addr == regGRBM_GFX_INDEX: self.grbm_index = val
|
|
if getbits(self.grbm_index, 31, 31):
|
|
for se in range(self.n_se): self.regs[(addr, se)] = val
|
|
else:
|
|
self.regs[(addr, getbits(self.grbm_index, 16, 23))] = val
|
|
|
|
class AMDGPU(VirtGPU):
|
|
def __init__(self, gpuid):
|
|
super().__init__(gpuid)
|
|
self.regs = AMDGPURegisters()
|
|
self.mapped_ranges = set()
|
|
self.queues = []
|
|
self.arch = "cdna" if MOCKGPU_ARCH == "cdna4" else MOCKGPU_ARCH
|
|
|
|
def translate_addr(self, addr:int) -> int: return addr
|
|
def map_range(self, vaddr, size): self.mapped_ranges.add((vaddr, size))
|
|
def unmap_range(self, vaddr, size): self.mapped_ranges.remove((vaddr, size))
|
|
def add_pm4_queue(self, base, size, rptr, wptr):
|
|
self.queues.append(PM4Executor(self, base, size, rptr, wptr))
|
|
return len(self.queues) - 1
|
|
def add_sdma_queue(self, base, size, rptr, wptr):
|
|
self.queues.append(SDMAExecutor(self, base, size, rptr, wptr))
|
|
return len(self.queues) - 1
|
|
|
|
_gpu_props_rdna = """cpu_cores_count 0
|
|
simd_count 192
|
|
mem_banks_count 1
|
|
caches_count 206
|
|
io_links_count 1
|
|
p2p_links_count 5
|
|
cpu_core_id_base 0
|
|
simd_id_base 2147488032
|
|
max_waves_per_simd 16
|
|
lds_size_in_kb 64
|
|
gds_size_in_kb 0
|
|
num_gws 64
|
|
wave_front_size 32
|
|
array_count 12
|
|
simd_arrays_per_engine 2
|
|
cu_per_simd_array 8
|
|
simd_per_cu 2
|
|
max_slots_scratch_cu 32
|
|
gfx_target_version {gfx_target_version}
|
|
vendor_id 4098
|
|
device_id 29772
|
|
location_id 34304
|
|
domain 0
|
|
drm_render_minor {drm_render_minor}
|
|
hive_id 0
|
|
num_sdma_engines 2
|
|
num_sdma_xgmi_engines 0
|
|
num_sdma_queues_per_engine 6
|
|
num_cp_queues 8
|
|
max_engine_clk_fcompute 2482
|
|
local_mem_size 0
|
|
fw_version 2140
|
|
capability 671588992
|
|
debug_prop 1495
|
|
sdma_fw_version 20
|
|
unique_id 11673270660693242239
|
|
num_xcc 1
|
|
max_engine_clk_ccompute 2400"""
|
|
|
|
_gpu_props_cdna = """cpu_cores_count 0
|
|
simd_count 304
|
|
mem_banks_count 1
|
|
caches_count 206
|
|
io_links_count 1
|
|
p2p_links_count 5
|
|
cpu_core_id_base 0
|
|
simd_id_base 2147488032
|
|
max_waves_per_simd 16
|
|
lds_size_in_kb 160
|
|
gds_size_in_kb 0
|
|
num_gws 64
|
|
wave_front_size 64
|
|
array_count 16
|
|
simd_arrays_per_engine 4
|
|
cu_per_simd_array 19
|
|
simd_per_cu 2
|
|
max_slots_scratch_cu 32
|
|
gfx_target_version {gfx_target_version}
|
|
vendor_id 4098
|
|
device_id 29772
|
|
location_id 34304
|
|
domain 0
|
|
drm_render_minor {drm_render_minor}
|
|
hive_id 0
|
|
num_sdma_engines 2
|
|
num_sdma_xgmi_engines 0
|
|
num_sdma_queues_per_engine 6
|
|
num_cp_queues 8
|
|
max_engine_clk_fcompute 2100
|
|
local_mem_size 0
|
|
fw_version 2140
|
|
capability 671588992
|
|
debug_prop 1495
|
|
sdma_fw_version 20
|
|
unique_id 11673270660693242239
|
|
num_xcc 1
|
|
max_engine_clk_ccompute 2100"""
|
|
|
|
gpu_props = _gpu_props_cdna if MOCKGPU_ARCH == "cdna4" else _gpu_props_rdna
|