mirror of
https://github.com/firestar5683/StarPilot.git
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firestar5683
22a8575199
Keep official openpilot ancestry and dependency licenses. Store resources directly in Git, remove LFS setup requirements, and leave the downloadable big model outside the source tree.
26569 lines
1.5 MiB
Plaintext
26569 lines
1.5 MiB
Plaintext
# mypy: disable-error-code="empty-body"
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from __future__ import annotations
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import ctypes
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from typing import Literal, TypeAlias
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from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
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from tinygrad.runtime.support import c
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_anonenum0: dict[int, str] = {(AES128_NONE:=0): 'AES128_NONE', (AES128_CTR:=1): 'AES128_CTR', (AES128_CBC:=2): 'AES128_CBC', (AES128_ECB:=3): 'AES128_ECB', (AES128_OFB:=4): 'AES128_OFB', (AES128_CTR_LSB16B:=5): 'AES128_CTR_LSB16B', (AES128_CLR_AS_ENCRYPT:=6): 'AES128_CLR_AS_ENCRYPT', (AES128_RESERVED:=7): 'AES128_RESERVED'}
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_anonenum1: dict[int, str] = {(AES128_CTS_DISABLE:=0): 'AES128_CTS_DISABLE', (AES128_CTS_ENABLE:=1): 'AES128_CTS_ENABLE'}
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_anonenum2: dict[int, str] = {(AES128_PADDING_NONE:=0): 'AES128_PADDING_NONE', (AES128_PADDING_CARRY_OVER:=1): 'AES128_PADDING_CARRY_OVER', (AES128_PADDING_RFC2630:=2): 'AES128_PADDING_RFC2630', (AES128_PADDING_RESERVED:=7): 'AES128_PADDING_RESERVED'}
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ENCR_MODE: dict[int, str] = {(ENCR_MODE_CTR64:=0): 'ENCR_MODE_CTR64', (ENCR_MODE_CBC:=1): 'ENCR_MODE_CBC', (ENCR_MODE_ECB:=2): 'ENCR_MODE_ECB', (ENCR_MODE_ECB_PARTIAL:=3): 'ENCR_MODE_ECB_PARTIAL', (ENCR_MODE_CBC_PARTIAL:=4): 'ENCR_MODE_CBC_PARTIAL', (ENCR_MODE_CLEAR_INTO_VPR:=5): 'ENCR_MODE_CLEAR_INTO_VPR', (ENCR_MODE_FORCE_INTO_VPR:=6): 'ENCR_MODE_FORCE_INTO_VPR'}
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_anonenum3: dict[int, str] = {(DRM_MS_PIFF_CTR:=17): 'DRM_MS_PIFF_CTR'}
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_anonenum4: dict[int, str] = {(DRM_MS_PIFF_CBC:=2): 'DRM_MS_PIFF_CBC'}
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_anonenum5: dict[int, str] = {(DRM_MARLIN_CTR:=1): 'DRM_MARLIN_CTR'}
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_anonenum6: dict[int, str] = {(DRM_MARLIN_CBC:=34): 'DRM_MARLIN_CBC'}
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_anonenum7: dict[int, str] = {(DRM_WIDEVINE:=10): 'DRM_WIDEVINE'}
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_anonenum8: dict[int, str] = {(DRM_WIDEVINE_CTR:=17): 'DRM_WIDEVINE_CTR'}
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_anonenum9: dict[int, str] = {(DRM_ULTRA_VIOLET:=5): 'DRM_ULTRA_VIOLET'}
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_anonenum10: dict[int, str] = {(DRM_NONE:=0): 'DRM_NONE'}
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_anonenum11: dict[int, str] = {(DRM_CLR_AS_ENCRYPT:=6): 'DRM_CLR_AS_ENCRYPT'}
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@c.record
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class struct__nvdec_ssm_s(c.Struct):
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SIZE = 8
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bytes_of_protected_data: int
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bytes_of_clear_data: int
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skip_byte_blk: int
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crypt_byte_blk: int
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skip: int
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last: int
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pad: int
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mode: int
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entry_type: int
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reserved: int
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struct__nvdec_ssm_s.register_fields([('bytes_of_protected_data', ctypes.c_uint32, 0), ('bytes_of_clear_data', ctypes.c_uint32, 4, 16, 0), ('skip_byte_blk', ctypes.c_uint32, 6, 4, 0), ('crypt_byte_blk', ctypes.c_uint32, 6, 4, 4), ('skip', ctypes.c_uint32, 7, 1, 0), ('last', ctypes.c_uint32, 7, 1, 1), ('pad', ctypes.c_uint32, 7, 1, 2), ('mode', ctypes.c_uint32, 7, 1, 3), ('entry_type', ctypes.c_uint32, 7, 1, 4), ('reserved', ctypes.c_uint32, 7, 3, 5)])
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nvdec_ssm_s: TypeAlias = struct__nvdec_ssm_s
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@c.record
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class struct__nvdec_pass2_otf_ext_s(c.Struct):
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SIZE = 12
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ssm_entry_num: int
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ssm_iv_num: int
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real_stream_length: int
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non_slice_data: int
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drm_mode: int
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reserved: int
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struct__nvdec_pass2_otf_ext_s.register_fields([('ssm_entry_num', ctypes.c_uint32, 0, 16, 0), ('ssm_iv_num', ctypes.c_uint32, 2, 16, 0), ('real_stream_length', ctypes.c_uint32, 4), ('non_slice_data', ctypes.c_uint32, 8, 16, 0), ('drm_mode', ctypes.c_uint32, 10, 7, 0), ('reserved', ctypes.c_uint32, 10, 9, 7)])
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nvdec_pass2_otf_ext_s: TypeAlias = struct__nvdec_pass2_otf_ext_s
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@c.record
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class struct__nvdec_substream_entry_s(c.Struct):
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SIZE = 12
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substream_start_offset: int
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substream_length: int
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substream_first_tile_idx: int
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substream_last_tile_idx: int
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last_substream_entry_in_frame: int
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reserved: int
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struct__nvdec_substream_entry_s.register_fields([('substream_start_offset', ctypes.c_uint32, 0), ('substream_length', ctypes.c_uint32, 4), ('substream_first_tile_idx', ctypes.c_uint32, 8, 8, 0), ('substream_last_tile_idx', ctypes.c_uint32, 9, 8, 0), ('last_substream_entry_in_frame', ctypes.c_uint32, 10, 1, 0), ('reserved', ctypes.c_uint32, 10, 15, 1)])
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nvdec_substream_entry_s: TypeAlias = struct__nvdec_substream_entry_s
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@c.record
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class struct__nvdec_ecdma_config_s(c.Struct):
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SIZE = 24
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ecdma_enable: int
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ecdma_blk_x_src: int
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ecdma_blk_y_src: int
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ecdma_blk_x_dst: int
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ecdma_blk_y_dst: int
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ref_pic_idx: int
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boundary0_top: int
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boundary0_bottom: int
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boundary1_left: int
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boundary1_right: int
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blk_copy_flag: int
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ctb_size: int
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struct__nvdec_ecdma_config_s.register_fields([('ecdma_enable', ctypes.c_uint32, 0), ('ecdma_blk_x_src', ctypes.c_uint16, 4), ('ecdma_blk_y_src', ctypes.c_uint16, 6), ('ecdma_blk_x_dst', ctypes.c_uint16, 8), ('ecdma_blk_y_dst', ctypes.c_uint16, 10), ('ref_pic_idx', ctypes.c_uint16, 12), ('boundary0_top', ctypes.c_uint16, 14), ('boundary0_bottom', ctypes.c_uint16, 16), ('boundary1_left', ctypes.c_uint16, 18), ('boundary1_right', ctypes.c_uint16, 20), ('blk_copy_flag', ctypes.c_ubyte, 22), ('ctb_size', ctypes.c_ubyte, 23)])
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nvdec_ecdma_config_s: TypeAlias = struct__nvdec_ecdma_config_s
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@c.record
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class struct__nvdec_status_hevc_s(c.Struct):
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SIZE = 36
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frame_status_intra_cnt: int
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frame_status_inter_cnt: int
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frame_status_skip_cnt: int
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frame_status_fwd_mvx_cnt: int
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frame_status_fwd_mvy_cnt: int
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frame_status_bwd_mvx_cnt: int
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frame_status_bwd_mvy_cnt: int
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error_ctb_pos: int
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error_slice_pos: int
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struct__nvdec_status_hevc_s.register_fields([('frame_status_intra_cnt', ctypes.c_uint32, 0), ('frame_status_inter_cnt', ctypes.c_uint32, 4), ('frame_status_skip_cnt', ctypes.c_uint32, 8), ('frame_status_fwd_mvx_cnt', ctypes.c_uint32, 12), ('frame_status_fwd_mvy_cnt', ctypes.c_uint32, 16), ('frame_status_bwd_mvx_cnt', ctypes.c_uint32, 20), ('frame_status_bwd_mvy_cnt', ctypes.c_uint32, 24), ('error_ctb_pos', ctypes.c_uint32, 28), ('error_slice_pos', ctypes.c_uint32, 32)])
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nvdec_status_hevc_s: TypeAlias = struct__nvdec_status_hevc_s
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@c.record
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class struct__nvdec_status_vp9_s(c.Struct):
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SIZE = 36
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frame_status_intra_cnt: int
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frame_status_inter_cnt: int
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frame_status_skip_cnt: int
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frame_status_fwd_mvx_cnt: int
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frame_status_fwd_mvy_cnt: int
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frame_status_bwd_mvx_cnt: int
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frame_status_bwd_mvy_cnt: int
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error_ctb_pos: int
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error_slice_pos: int
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struct__nvdec_status_vp9_s.register_fields([('frame_status_intra_cnt', ctypes.c_uint32, 0), ('frame_status_inter_cnt', ctypes.c_uint32, 4), ('frame_status_skip_cnt', ctypes.c_uint32, 8), ('frame_status_fwd_mvx_cnt', ctypes.c_uint32, 12), ('frame_status_fwd_mvy_cnt', ctypes.c_uint32, 16), ('frame_status_bwd_mvx_cnt', ctypes.c_uint32, 20), ('frame_status_bwd_mvy_cnt', ctypes.c_uint32, 24), ('error_ctb_pos', ctypes.c_uint32, 28), ('error_slice_pos', ctypes.c_uint32, 32)])
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nvdec_status_vp9_s: TypeAlias = struct__nvdec_status_vp9_s
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@c.record
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class struct__nvdec_status_s(c.Struct):
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SIZE = 56
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mbs_correctly_decoded: int
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mbs_in_error: int
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cycle_count: int
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error_status: int
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hevc: struct__nvdec_status_hevc_s
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vp9: struct__nvdec_status_vp9_s
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slice_header_error_code: int
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struct__nvdec_status_s.register_fields([('mbs_correctly_decoded', ctypes.c_uint32, 0), ('mbs_in_error', ctypes.c_uint32, 4), ('cycle_count', ctypes.c_uint32, 8), ('error_status', ctypes.c_uint32, 12), ('hevc', nvdec_status_hevc_s, 16), ('vp9', nvdec_status_vp9_s, 16), ('slice_header_error_code', ctypes.c_uint32, 52)])
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nvdec_status_s: TypeAlias = struct__nvdec_status_s
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@c.record
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class struct__external_mv_s(c.Struct):
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SIZE = 4
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mvx: int
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mvy: int
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refidx: int
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struct__external_mv_s.register_fields([('mvx', ctypes.c_int32, 0, 14, 0), ('mvy', ctypes.c_int32, 1, 14, 6), ('refidx', ctypes.c_uint32, 3, 4, 4)])
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external_mv_s: TypeAlias = struct__external_mv_s
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@c.record
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class struct__nvdec_hevc_main10_444_ext_s(c.Struct):
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SIZE = 28
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transformSkipRotationEnableFlag: int
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transformSkipContextEnableFlag: int
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intraBlockCopyEnableFlag: int
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implicitRdpcmEnableFlag: int
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explicitRdpcmEnableFlag: int
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extendedPrecisionProcessingFlag: int
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intraSmoothingDisabledFlag: int
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highPrecisionOffsetsEnableFlag: int
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fastRiceAdaptationEnableFlag: int
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cabacBypassAlignmentEnableFlag: int
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sps_444_extension_reserved: int
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log2MaxTransformSkipSize: int
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crossComponentPredictionEnableFlag: int
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chromaQpAdjustmentEnableFlag: int
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diffCuChromaQpAdjustmentDepth: int
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chromaQpAdjustmentTableSize: int
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log2SaoOffsetScaleLuma: int
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log2SaoOffsetScaleChroma: int
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pps_444_extension_reserved: int
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cb_qp_adjustment: c.Array[ctypes.c_char, Literal[6]]
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cr_qp_adjustment: c.Array[ctypes.c_char, Literal[6]]
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HevcFltAboveOffset: int
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HevcSaoAboveOffset: int
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struct__nvdec_hevc_main10_444_ext_s.register_fields([('transformSkipRotationEnableFlag', ctypes.c_uint32, 0, 1, 0), ('transformSkipContextEnableFlag', ctypes.c_uint32, 0, 1, 1), ('intraBlockCopyEnableFlag', ctypes.c_uint32, 0, 1, 2), ('implicitRdpcmEnableFlag', ctypes.c_uint32, 0, 1, 3), ('explicitRdpcmEnableFlag', ctypes.c_uint32, 0, 1, 4), ('extendedPrecisionProcessingFlag', ctypes.c_uint32, 0, 1, 5), ('intraSmoothingDisabledFlag', ctypes.c_uint32, 0, 1, 6), ('highPrecisionOffsetsEnableFlag', ctypes.c_uint32, 0, 1, 7), ('fastRiceAdaptationEnableFlag', ctypes.c_uint32, 1, 1, 0), ('cabacBypassAlignmentEnableFlag', ctypes.c_uint32, 1, 1, 1), ('sps_444_extension_reserved', ctypes.c_uint32, 1, 22, 2), ('log2MaxTransformSkipSize', ctypes.c_uint32, 4, 4, 0), ('crossComponentPredictionEnableFlag', ctypes.c_uint32, 4, 1, 4), ('chromaQpAdjustmentEnableFlag', ctypes.c_uint32, 4, 1, 5), ('diffCuChromaQpAdjustmentDepth', ctypes.c_uint32, 4, 2, 6), ('chromaQpAdjustmentTableSize', ctypes.c_uint32, 5, 3, 0), ('log2SaoOffsetScaleLuma', ctypes.c_uint32, 5, 3, 3), ('log2SaoOffsetScaleChroma', ctypes.c_uint32, 5, 3, 6), ('pps_444_extension_reserved', ctypes.c_uint32, 6, 15, 1), ('cb_qp_adjustment', c.Array[ctypes.c_char, Literal[6]], 8), ('cr_qp_adjustment', c.Array[ctypes.c_char, Literal[6]], 14), ('HevcFltAboveOffset', ctypes.c_uint32, 20), ('HevcSaoAboveOffset', ctypes.c_uint32, 24)])
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nvdec_hevc_main10_444_ext_s: TypeAlias = struct__nvdec_hevc_main10_444_ext_s
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@c.record
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class struct__nvdec_hevc_pic_v1_s(c.Struct):
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SIZE = 32
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hevc_main10_444_ext: struct__nvdec_hevc_main10_444_ext_s
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sw_skip_start_length: int
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external_ref_mem_dis: int
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error_recovery_start_pos: int
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error_external_mv_en: int
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reserved0: int
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struct__nvdec_hevc_pic_v1_s.register_fields([('hevc_main10_444_ext', nvdec_hevc_main10_444_ext_s, 0), ('sw_skip_start_length', ctypes.c_uint32, 28, 14, 0), ('external_ref_mem_dis', ctypes.c_uint32, 29, 1, 6), ('error_recovery_start_pos', ctypes.c_uint32, 29, 2, 7), ('error_external_mv_en', ctypes.c_uint32, 30, 1, 1), ('reserved0', ctypes.c_uint32, 30, 14, 2)])
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nvdec_hevc_pic_v1_s: TypeAlias = struct__nvdec_hevc_pic_v1_s
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@c.record
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class struct__nvdec_hevc_pic_v2_s(c.Struct):
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SIZE = 4
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mv_hevc_enable: int
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nuh_layer_id: int
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default_ref_layers_active_flag: int
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NumDirectRefLayers: int
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max_one_active_ref_layer_flag: int
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NumActiveRefLayerPics: int
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poc_lsb_not_present_flag: int
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reserved0: int
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struct__nvdec_hevc_pic_v2_s.register_fields([('mv_hevc_enable', ctypes.c_uint32, 0, 1, 0), ('nuh_layer_id', ctypes.c_uint32, 0, 6, 1), ('default_ref_layers_active_flag', ctypes.c_uint32, 0, 1, 7), ('NumDirectRefLayers', ctypes.c_uint32, 1, 6, 0), ('max_one_active_ref_layer_flag', ctypes.c_uint32, 1, 1, 6), ('NumActiveRefLayerPics', ctypes.c_uint32, 1, 6, 7), ('poc_lsb_not_present_flag', ctypes.c_uint32, 2, 1, 5), ('reserved0', ctypes.c_uint32, 2, 10, 6)])
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nvdec_hevc_pic_v2_s: TypeAlias = struct__nvdec_hevc_pic_v2_s
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@c.record
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class struct__nvdec_hevc_pic_v3_s(c.Struct):
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SIZE = 8
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slice_decoding_enable: int
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slice_ec_enable: int
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slice_ec_mv_type: int
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err_detected_sw: int
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slice_ec_slice_type: int
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slice_strm_recfg_en: int
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reserved: int
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HevcSliceEdgeOffset: int
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struct__nvdec_hevc_pic_v3_s.register_fields([('slice_decoding_enable', ctypes.c_uint32, 0, 1, 0), ('slice_ec_enable', ctypes.c_uint32, 0, 1, 1), ('slice_ec_mv_type', ctypes.c_uint32, 0, 2, 2), ('err_detected_sw', ctypes.c_uint32, 0, 1, 4), ('slice_ec_slice_type', ctypes.c_uint32, 0, 2, 5), ('slice_strm_recfg_en', ctypes.c_uint32, 0, 1, 7), ('reserved', ctypes.c_uint32, 1, 24, 0), ('HevcSliceEdgeOffset', ctypes.c_uint32, 4)])
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nvdec_hevc_pic_v3_s: TypeAlias = struct__nvdec_hevc_pic_v3_s
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@c.record
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class struct__nvdec_hevc_pic_s(c.Struct):
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SIZE = 276
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wrapped_session_key: c.Array[ctypes.c_uint32, Literal[4]]
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wrapped_content_key: c.Array[ctypes.c_uint32, Literal[4]]
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initialization_vector: c.Array[ctypes.c_uint32, Literal[4]]
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stream_len: int
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enable_encryption: int
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key_increment: int
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encryption_mode: int
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key_slot_index: int
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ssm_en: int
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enable_histogram: int
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enable_substream_decoding: int
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reserved0: int
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gptimer_timeout_value: int
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tileformat: int
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gob_height: int
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reserverd_surface_format: int
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sw_start_code_e: int
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disp_output_mode: int
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reserved1: int
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framestride: c.Array[ctypes.c_uint32, Literal[2]]
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colMvBuffersize: int
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HevcSaoBufferOffset: int
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HevcBsdCtrlOffset: int
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pic_width_in_luma_samples: int
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pic_height_in_luma_samples: int
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chroma_format_idc: int
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bit_depth_luma: int
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bit_depth_chroma: int
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log2_min_luma_coding_block_size: int
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log2_max_luma_coding_block_size: int
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log2_min_transform_block_size: int
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log2_max_transform_block_size: int
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reserved2: int
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max_transform_hierarchy_depth_inter: int
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max_transform_hierarchy_depth_intra: int
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scalingListEnable: int
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amp_enable_flag: int
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sample_adaptive_offset_enabled_flag: int
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pcm_enabled_flag: int
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pcm_sample_bit_depth_luma: int
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pcm_sample_bit_depth_chroma: int
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log2_min_pcm_luma_coding_block_size: int
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log2_max_pcm_luma_coding_block_size: int
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pcm_loop_filter_disabled_flag: int
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sps_temporal_mvp_enabled_flag: int
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strong_intra_smoothing_enabled_flag: int
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reserved3: int
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dependent_slice_segments_enabled_flag: int
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output_flag_present_flag: int
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num_extra_slice_header_bits: int
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sign_data_hiding_enabled_flag: int
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cabac_init_present_flag: int
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num_ref_idx_l0_default_active: int
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num_ref_idx_l1_default_active: int
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init_qp: int
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constrained_intra_pred_flag: int
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transform_skip_enabled_flag: int
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cu_qp_delta_enabled_flag: int
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diff_cu_qp_delta_depth: int
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reserved4: int
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pps_cb_qp_offset: bytes
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pps_cr_qp_offset: bytes
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pps_beta_offset: bytes
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pps_tc_offset: bytes
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pps_slice_chroma_qp_offsets_present_flag: int
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weighted_pred_flag: int
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weighted_bipred_flag: int
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transquant_bypass_enabled_flag: int
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tiles_enabled_flag: int
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entropy_coding_sync_enabled_flag: int
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num_tile_columns: int
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num_tile_rows: int
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loop_filter_across_tiles_enabled_flag: int
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loop_filter_across_slices_enabled_flag: int
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deblocking_filter_control_present_flag: int
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deblocking_filter_override_enabled_flag: int
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pps_deblocking_filter_disabled_flag: int
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lists_modification_present_flag: int
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log2_parallel_merge_level: int
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slice_segment_header_extension_present_flag: int
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reserved5: int
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num_ref_frames: int
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reserved6: int
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longtermflag: int
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initreflistidxl0: c.Array[ctypes.c_ubyte, Literal[16]]
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initreflistidxl1: c.Array[ctypes.c_ubyte, Literal[16]]
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RefDiffPicOrderCnts: c.Array[ctypes.c_int16, Literal[16]]
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IDR_picture_flag: int
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RAP_picture_flag: int
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curr_pic_idx: int
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pattern_id: int
|
|
sw_hdr_skip_length: int
|
|
reserved7: int
|
|
ecdma_cfg: struct__nvdec_ecdma_config_s
|
|
separate_colour_plane_flag: int
|
|
log2_max_pic_order_cnt_lsb_minus4: int
|
|
num_short_term_ref_pic_sets: int
|
|
num_long_term_ref_pics_sps: int
|
|
bBitParsingDisable: int
|
|
num_delta_pocs_of_rps_idx: int
|
|
long_term_ref_pics_present_flag: int
|
|
reserved_dxva: int
|
|
num_bits_short_term_ref_pics_in_slice: int
|
|
v1: struct__nvdec_hevc_pic_v1_s
|
|
v2: struct__nvdec_hevc_pic_v2_s
|
|
v3: struct__nvdec_hevc_pic_v3_s
|
|
ssm: struct__nvdec_pass2_otf_ext_s
|
|
struct__nvdec_hevc_pic_s.register_fields([('wrapped_session_key', c.Array[ctypes.c_uint32, Literal[4]], 0), ('wrapped_content_key', c.Array[ctypes.c_uint32, Literal[4]], 16), ('initialization_vector', c.Array[ctypes.c_uint32, Literal[4]], 32), ('stream_len', ctypes.c_uint32, 48), ('enable_encryption', ctypes.c_uint32, 52), ('key_increment', ctypes.c_uint32, 56, 6, 0), ('encryption_mode', ctypes.c_uint32, 56, 4, 6), ('key_slot_index', ctypes.c_uint32, 57, 4, 2), ('ssm_en', ctypes.c_uint32, 57, 1, 6), ('enable_histogram', ctypes.c_uint32, 57, 1, 7), ('enable_substream_decoding', ctypes.c_uint32, 58, 1, 0), ('reserved0', ctypes.c_uint32, 58, 15, 1), ('gptimer_timeout_value', ctypes.c_uint32, 60), ('tileformat', ctypes.c_ubyte, 64, 2, 0), ('gob_height', ctypes.c_ubyte, 64, 3, 2), ('reserverd_surface_format', ctypes.c_ubyte, 64, 3, 5), ('sw_start_code_e', ctypes.c_ubyte, 65), ('disp_output_mode', ctypes.c_ubyte, 66), ('reserved1', ctypes.c_ubyte, 67), ('framestride', c.Array[ctypes.c_uint32, Literal[2]], 68), ('colMvBuffersize', ctypes.c_uint32, 76), ('HevcSaoBufferOffset', ctypes.c_uint32, 80), ('HevcBsdCtrlOffset', ctypes.c_uint32, 84), ('pic_width_in_luma_samples', ctypes.c_uint16, 88), ('pic_height_in_luma_samples', ctypes.c_uint16, 90), ('chroma_format_idc', ctypes.c_uint32, 92, 4, 0), ('bit_depth_luma', ctypes.c_uint32, 92, 4, 4), ('bit_depth_chroma', ctypes.c_uint32, 93, 4, 0), ('log2_min_luma_coding_block_size', ctypes.c_uint32, 93, 4, 4), ('log2_max_luma_coding_block_size', ctypes.c_uint32, 94, 4, 0), ('log2_min_transform_block_size', ctypes.c_uint32, 94, 4, 4), ('log2_max_transform_block_size', ctypes.c_uint32, 95, 4, 0), ('reserved2', ctypes.c_uint32, 95, 4, 4), ('max_transform_hierarchy_depth_inter', ctypes.c_uint32, 96, 3, 0), ('max_transform_hierarchy_depth_intra', ctypes.c_uint32, 96, 3, 3), ('scalingListEnable', ctypes.c_uint32, 96, 1, 6), ('amp_enable_flag', ctypes.c_uint32, 96, 1, 7), ('sample_adaptive_offset_enabled_flag', ctypes.c_uint32, 97, 1, 0), ('pcm_enabled_flag', ctypes.c_uint32, 97, 1, 1), ('pcm_sample_bit_depth_luma', ctypes.c_uint32, 97, 4, 2), ('pcm_sample_bit_depth_chroma', ctypes.c_uint32, 97, 4, 6), ('log2_min_pcm_luma_coding_block_size', ctypes.c_uint32, 98, 4, 2), ('log2_max_pcm_luma_coding_block_size', ctypes.c_uint32, 98, 4, 6), ('pcm_loop_filter_disabled_flag', ctypes.c_uint32, 99, 1, 2), ('sps_temporal_mvp_enabled_flag', ctypes.c_uint32, 99, 1, 3), ('strong_intra_smoothing_enabled_flag', ctypes.c_uint32, 99, 1, 4), ('reserved3', ctypes.c_uint32, 99, 3, 5), ('dependent_slice_segments_enabled_flag', ctypes.c_uint32, 100, 1, 0), ('output_flag_present_flag', ctypes.c_uint32, 100, 1, 1), ('num_extra_slice_header_bits', ctypes.c_uint32, 100, 3, 2), ('sign_data_hiding_enabled_flag', ctypes.c_uint32, 100, 1, 5), ('cabac_init_present_flag', ctypes.c_uint32, 100, 1, 6), ('num_ref_idx_l0_default_active', ctypes.c_uint32, 100, 4, 7), ('num_ref_idx_l1_default_active', ctypes.c_uint32, 101, 4, 3), ('init_qp', ctypes.c_uint32, 101, 7, 7), ('constrained_intra_pred_flag', ctypes.c_uint32, 102, 1, 6), ('transform_skip_enabled_flag', ctypes.c_uint32, 102, 1, 7), ('cu_qp_delta_enabled_flag', ctypes.c_uint32, 103, 1, 0), ('diff_cu_qp_delta_depth', ctypes.c_uint32, 103, 2, 1), ('reserved4', ctypes.c_uint32, 103, 5, 3), ('pps_cb_qp_offset', ctypes.c_char, 104), ('pps_cr_qp_offset', ctypes.c_char, 105), ('pps_beta_offset', ctypes.c_char, 106), ('pps_tc_offset', ctypes.c_char, 107), ('pps_slice_chroma_qp_offsets_present_flag', ctypes.c_uint32, 108, 1, 0), ('weighted_pred_flag', ctypes.c_uint32, 108, 1, 1), ('weighted_bipred_flag', ctypes.c_uint32, 108, 1, 2), ('transquant_bypass_enabled_flag', ctypes.c_uint32, 108, 1, 3), ('tiles_enabled_flag', ctypes.c_uint32, 108, 1, 4), ('entropy_coding_sync_enabled_flag', ctypes.c_uint32, 108, 1, 5), ('num_tile_columns', ctypes.c_uint32, 108, 5, 6), ('num_tile_rows', ctypes.c_uint32, 109, 5, 3), ('loop_filter_across_tiles_enabled_flag', ctypes.c_uint32, 110, 1, 0), ('loop_filter_across_slices_enabled_flag', ctypes.c_uint32, 110, 1, 1), ('deblocking_filter_control_present_flag', ctypes.c_uint32, 110, 1, 2), ('deblocking_filter_override_enabled_flag', ctypes.c_uint32, 110, 1, 3), ('pps_deblocking_filter_disabled_flag', ctypes.c_uint32, 110, 1, 4), ('lists_modification_present_flag', ctypes.c_uint32, 110, 1, 5), ('log2_parallel_merge_level', ctypes.c_uint32, 110, 3, 6), ('slice_segment_header_extension_present_flag', ctypes.c_uint32, 111, 1, 1), ('reserved5', ctypes.c_uint32, 111, 6, 2), ('num_ref_frames', ctypes.c_ubyte, 112), ('reserved6', ctypes.c_ubyte, 113), ('longtermflag', ctypes.c_uint16, 114), ('initreflistidxl0', c.Array[ctypes.c_ubyte, Literal[16]], 116), ('initreflistidxl1', c.Array[ctypes.c_ubyte, Literal[16]], 132), ('RefDiffPicOrderCnts', c.Array[ctypes.c_int16, Literal[16]], 148), ('IDR_picture_flag', ctypes.c_ubyte, 180), ('RAP_picture_flag', ctypes.c_ubyte, 181), ('curr_pic_idx', ctypes.c_ubyte, 182), ('pattern_id', ctypes.c_ubyte, 183), ('sw_hdr_skip_length', ctypes.c_uint16, 184), ('reserved7', ctypes.c_uint16, 186), ('ecdma_cfg', nvdec_ecdma_config_s, 188), ('separate_colour_plane_flag', ctypes.c_uint32, 212, 1, 0), ('log2_max_pic_order_cnt_lsb_minus4', ctypes.c_uint32, 212, 4, 1), ('num_short_term_ref_pic_sets', ctypes.c_uint32, 212, 7, 5), ('num_long_term_ref_pics_sps', ctypes.c_uint32, 213, 6, 4), ('bBitParsingDisable', ctypes.c_uint32, 214, 1, 2), ('num_delta_pocs_of_rps_idx', ctypes.c_uint32, 214, 8, 3), ('long_term_ref_pics_present_flag', ctypes.c_uint32, 215, 1, 3), ('reserved_dxva', ctypes.c_uint32, 215, 4, 4), ('num_bits_short_term_ref_pics_in_slice', ctypes.c_uint32, 216), ('v1', nvdec_hevc_pic_v1_s, 220), ('v2', nvdec_hevc_pic_v2_s, 252), ('v3', nvdec_hevc_pic_v3_s, 256), ('ssm', nvdec_pass2_otf_ext_s, 264)])
|
|
nvdec_hevc_pic_s: TypeAlias = struct__nvdec_hevc_pic_s
|
|
@c.record
|
|
class struct__hevc_slice_info_s(c.Struct):
|
|
SIZE = 16
|
|
first_flag: int
|
|
err_flag: int
|
|
last_flag: int
|
|
conceal_partial_slice: int
|
|
available: int
|
|
reserved0: int
|
|
ctb_count: int
|
|
bs_offset: int
|
|
bs_length: int
|
|
start_ctbx: int
|
|
start_ctby: int
|
|
struct__hevc_slice_info_s.register_fields([('first_flag', ctypes.c_uint32, 0, 1, 0), ('err_flag', ctypes.c_uint32, 0, 1, 1), ('last_flag', ctypes.c_uint32, 0, 1, 2), ('conceal_partial_slice', ctypes.c_uint32, 0, 1, 3), ('available', ctypes.c_uint32, 0, 1, 4), ('reserved0', ctypes.c_uint32, 0, 7, 5), ('ctb_count', ctypes.c_uint32, 1, 20, 4), ('bs_offset', ctypes.c_uint32, 4), ('bs_length', ctypes.c_uint32, 8), ('start_ctbx', ctypes.c_uint16, 12), ('start_ctby', ctypes.c_uint16, 14)])
|
|
hevc_slice_info_s: TypeAlias = struct__hevc_slice_info_s
|
|
@c.record
|
|
class struct__slice_edge_ctb_pos_ctx_s(c.Struct):
|
|
SIZE = 8
|
|
next_slice_pos_ctbxy: int
|
|
next_slice_segment_addr: int
|
|
struct__slice_edge_ctb_pos_ctx_s.register_fields([('next_slice_pos_ctbxy', ctypes.c_uint32, 0), ('next_slice_segment_addr', ctypes.c_uint32, 4)])
|
|
slice_edge_ctb_pos_ctx_s: TypeAlias = struct__slice_edge_ctb_pos_ctx_s
|
|
@c.record
|
|
class struct__slice_edge_tile_ctx_s(c.Struct):
|
|
SIZE = 12
|
|
tileInfo1: int
|
|
tileInfo2: int
|
|
tileInfo3: int
|
|
struct__slice_edge_tile_ctx_s.register_fields([('tileInfo1', ctypes.c_uint32, 0), ('tileInfo2', ctypes.c_uint32, 4), ('tileInfo3', ctypes.c_uint32, 8)])
|
|
slice_edge_tile_ctx_s: TypeAlias = struct__slice_edge_tile_ctx_s
|
|
@c.record
|
|
class struct__slice_edge_stats_ctx_s(c.Struct):
|
|
SIZE = 32
|
|
frame_status_intra_cnt: int
|
|
frame_status_inter_cnt: int
|
|
frame_status_skip_cnt: int
|
|
frame_status_fwd_mvx_cnt: int
|
|
frame_status_fwd_mvy_cnt: int
|
|
frame_status_bwd_mvx_cnt: int
|
|
frame_status_bwd_mvy_cnt: int
|
|
frame_status_mv_cnt_ext: int
|
|
struct__slice_edge_stats_ctx_s.register_fields([('frame_status_intra_cnt', ctypes.c_uint32, 0), ('frame_status_inter_cnt', ctypes.c_uint32, 4), ('frame_status_skip_cnt', ctypes.c_uint32, 8), ('frame_status_fwd_mvx_cnt', ctypes.c_uint32, 12), ('frame_status_fwd_mvy_cnt', ctypes.c_uint32, 16), ('frame_status_bwd_mvx_cnt', ctypes.c_uint32, 20), ('frame_status_bwd_mvy_cnt', ctypes.c_uint32, 24), ('frame_status_mv_cnt_ext', ctypes.c_uint32, 28)])
|
|
slice_edge_stats_ctx_s: TypeAlias = struct__slice_edge_stats_ctx_s
|
|
@c.record
|
|
class struct__slice_vpc_edge_ctx_s(c.Struct):
|
|
SIZE = 4
|
|
reserved: int
|
|
struct__slice_vpc_edge_ctx_s.register_fields([('reserved', ctypes.c_uint32, 0)])
|
|
slice_vpc_edge_ctx_s: TypeAlias = struct__slice_vpc_edge_ctx_s
|
|
@c.record
|
|
class struct__slice_vpc_main_ctx_s(c.Struct):
|
|
SIZE = 4
|
|
reserved: int
|
|
struct__slice_vpc_main_ctx_s.register_fields([('reserved', ctypes.c_uint32, 0)])
|
|
slice_vpc_main_ctx_s: TypeAlias = struct__slice_vpc_main_ctx_s
|
|
@c.record
|
|
class struct__slice_edge_ctx_s(c.Struct):
|
|
SIZE = 60
|
|
slice_ctb_pos_ctx: struct__slice_edge_ctb_pos_ctx_s
|
|
slice_stats_ctx: struct__slice_edge_stats_ctx_s
|
|
slice_tile_ctx: struct__slice_edge_tile_ctx_s
|
|
slice_vpc_edge_ctx: struct__slice_vpc_edge_ctx_s
|
|
slice_vpc_main_ctx: struct__slice_vpc_main_ctx_s
|
|
struct__slice_edge_ctx_s.register_fields([('slice_ctb_pos_ctx', slice_edge_ctb_pos_ctx_s, 0), ('slice_stats_ctx', slice_edge_stats_ctx_s, 8), ('slice_tile_ctx', slice_edge_tile_ctx_s, 40), ('slice_vpc_edge_ctx', slice_vpc_edge_ctx_s, 52), ('slice_vpc_main_ctx', slice_vpc_main_ctx_s, 56)])
|
|
slice_edge_ctx_s: TypeAlias = struct__slice_edge_ctx_s
|
|
@c.record
|
|
class struct__nvdec_vp9_pic_v1_s(c.Struct):
|
|
SIZE = 8
|
|
Vp9FltAboveOffset: int
|
|
external_ref_mem_dis: int
|
|
bit_depth: int
|
|
error_recovery_start_pos: int
|
|
error_external_mv_en: int
|
|
Reserved0: int
|
|
struct__nvdec_vp9_pic_v1_s.register_fields([('Vp9FltAboveOffset', ctypes.c_uint32, 0), ('external_ref_mem_dis', ctypes.c_uint32, 4, 1, 0), ('bit_depth', ctypes.c_uint32, 4, 4, 1), ('error_recovery_start_pos', ctypes.c_uint32, 4, 2, 5), ('error_external_mv_en', ctypes.c_uint32, 4, 1, 7), ('Reserved0', ctypes.c_uint32, 5, 24, 0)])
|
|
nvdec_vp9_pic_v1_s: TypeAlias = struct__nvdec_vp9_pic_v1_s
|
|
enum_VP9_FRAME_SFC_ID: dict[int, str] = {(VP9_LAST_FRAME_SFC:=0): 'VP9_LAST_FRAME_SFC', (VP9_GOLDEN_FRAME_SFC:=1): 'VP9_GOLDEN_FRAME_SFC', (VP9_ALTREF_FRAME_SFC:=2): 'VP9_ALTREF_FRAME_SFC', (VP9_CURR_FRAME_SFC:=3): 'VP9_CURR_FRAME_SFC'}
|
|
@c.record
|
|
class struct__nvdec_vp9_pic_s(c.Struct):
|
|
SIZE = 256
|
|
wrapped_session_key: c.Array[ctypes.c_uint32, Literal[4]]
|
|
wrapped_content_key: c.Array[ctypes.c_uint32, Literal[4]]
|
|
initialization_vector: c.Array[ctypes.c_uint32, Literal[4]]
|
|
stream_len: int
|
|
enable_encryption: int
|
|
key_increment: int
|
|
encryption_mode: int
|
|
sw_hdr_skip_length: int
|
|
key_slot_index: int
|
|
ssm_en: int
|
|
enable_histogram: int
|
|
reserved0: int
|
|
gptimer_timeout_value: int
|
|
tileformat: int
|
|
gob_height: int
|
|
reserverd_surface_format: int
|
|
reserved1: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
Vp9BsdCtrlOffset: int
|
|
ref0_width: int
|
|
ref0_height: int
|
|
ref0_stride: c.Array[ctypes.c_uint16, Literal[2]]
|
|
ref1_width: int
|
|
ref1_height: int
|
|
ref1_stride: c.Array[ctypes.c_uint16, Literal[2]]
|
|
ref2_width: int
|
|
ref2_height: int
|
|
ref2_stride: c.Array[ctypes.c_uint16, Literal[2]]
|
|
width: int
|
|
height: int
|
|
framestride: c.Array[ctypes.c_uint16, Literal[2]]
|
|
keyFrame: int
|
|
prevIsKeyFrame: int
|
|
resolutionChange: int
|
|
errorResilient: int
|
|
prevShowFrame: int
|
|
intraOnly: int
|
|
reserved2: int
|
|
reserved3: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
refFrameSignBias: c.Array[ctypes.c_ubyte, Literal[4]]
|
|
loopFilterLevel: bytes
|
|
loopFilterSharpness: bytes
|
|
qpYAc: int
|
|
qpYDc: bytes
|
|
qpChAc: bytes
|
|
qpChDc: bytes
|
|
lossless: bytes
|
|
transform_mode: bytes
|
|
allow_high_precision_mv: bytes
|
|
mcomp_filter_type: bytes
|
|
comp_pred_mode: bytes
|
|
comp_fixed_ref: bytes
|
|
comp_var_ref: c.Array[ctypes.c_char, Literal[2]]
|
|
log2_tile_columns: bytes
|
|
log2_tile_rows: bytes
|
|
segmentEnabled: int
|
|
segmentMapUpdate: int
|
|
segmentMapTemporalUpdate: int
|
|
segmentFeatureMode: int
|
|
segmentFeatureEnable: c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[8]]
|
|
segmentFeatureData: c.Array[c.Array[ctypes.c_int16, Literal[4]], Literal[8]]
|
|
modeRefLfEnabled: bytes
|
|
mbRefLfDelta: c.Array[ctypes.c_char, Literal[4]]
|
|
mbModeLfDelta: c.Array[ctypes.c_char, Literal[2]]
|
|
reserved5: bytes
|
|
v1: struct__nvdec_vp9_pic_v1_s
|
|
ssm: struct__nvdec_pass2_otf_ext_s
|
|
struct__nvdec_vp9_pic_s.register_fields([('wrapped_session_key', c.Array[ctypes.c_uint32, Literal[4]], 0), ('wrapped_content_key', c.Array[ctypes.c_uint32, Literal[4]], 16), ('initialization_vector', c.Array[ctypes.c_uint32, Literal[4]], 32), ('stream_len', ctypes.c_uint32, 48), ('enable_encryption', ctypes.c_uint32, 52), ('key_increment', ctypes.c_uint32, 56, 6, 0), ('encryption_mode', ctypes.c_uint32, 56, 4, 6), ('sw_hdr_skip_length', ctypes.c_uint32, 57, 14, 2), ('key_slot_index', ctypes.c_uint32, 59, 4, 0), ('ssm_en', ctypes.c_uint32, 59, 1, 4), ('enable_histogram', ctypes.c_uint32, 59, 1, 5), ('reserved0', ctypes.c_uint32, 59, 2, 6), ('gptimer_timeout_value', ctypes.c_uint32, 60), ('tileformat', ctypes.c_ubyte, 64, 2, 0), ('gob_height', ctypes.c_ubyte, 64, 3, 2), ('reserverd_surface_format', ctypes.c_ubyte, 64, 3, 5), ('reserved1', c.Array[ctypes.c_ubyte, Literal[3]], 65), ('Vp9BsdCtrlOffset', ctypes.c_uint32, 68), ('ref0_width', ctypes.c_uint16, 72), ('ref0_height', ctypes.c_uint16, 74), ('ref0_stride', c.Array[ctypes.c_uint16, Literal[2]], 76), ('ref1_width', ctypes.c_uint16, 80), ('ref1_height', ctypes.c_uint16, 82), ('ref1_stride', c.Array[ctypes.c_uint16, Literal[2]], 84), ('ref2_width', ctypes.c_uint16, 88), ('ref2_height', ctypes.c_uint16, 90), ('ref2_stride', c.Array[ctypes.c_uint16, Literal[2]], 92), ('width', ctypes.c_uint16, 96), ('height', ctypes.c_uint16, 98), ('framestride', c.Array[ctypes.c_uint16, Literal[2]], 100), ('keyFrame', ctypes.c_ubyte, 104, 1, 0), ('prevIsKeyFrame', ctypes.c_ubyte, 104, 1, 1), ('resolutionChange', ctypes.c_ubyte, 104, 1, 2), ('errorResilient', ctypes.c_ubyte, 104, 1, 3), ('prevShowFrame', ctypes.c_ubyte, 104, 1, 4), ('intraOnly', ctypes.c_ubyte, 104, 1, 5), ('reserved2', ctypes.c_ubyte, 104, 2, 6), ('reserved3', c.Array[ctypes.c_ubyte, Literal[3]], 105), ('refFrameSignBias', c.Array[ctypes.c_ubyte, Literal[4]], 108), ('loopFilterLevel', ctypes.c_char, 112), ('loopFilterSharpness', ctypes.c_char, 113), ('qpYAc', ctypes.c_ubyte, 114), ('qpYDc', ctypes.c_char, 115), ('qpChAc', ctypes.c_char, 116), ('qpChDc', ctypes.c_char, 117), ('lossless', ctypes.c_char, 118), ('transform_mode', ctypes.c_char, 119), ('allow_high_precision_mv', ctypes.c_char, 120), ('mcomp_filter_type', ctypes.c_char, 121), ('comp_pred_mode', ctypes.c_char, 122), ('comp_fixed_ref', ctypes.c_char, 123), ('comp_var_ref', c.Array[ctypes.c_char, Literal[2]], 124), ('log2_tile_columns', ctypes.c_char, 126), ('log2_tile_rows', ctypes.c_char, 127), ('segmentEnabled', ctypes.c_ubyte, 128), ('segmentMapUpdate', ctypes.c_ubyte, 129), ('segmentMapTemporalUpdate', ctypes.c_ubyte, 130), ('segmentFeatureMode', ctypes.c_ubyte, 131), ('segmentFeatureEnable', c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[8]], 132), ('segmentFeatureData', c.Array[c.Array[ctypes.c_int16, Literal[4]], Literal[8]], 164), ('modeRefLfEnabled', ctypes.c_char, 228), ('mbRefLfDelta', c.Array[ctypes.c_char, Literal[4]], 229), ('mbModeLfDelta', c.Array[ctypes.c_char, Literal[2]], 233), ('reserved5', ctypes.c_char, 235), ('v1', nvdec_vp9_pic_v1_s, 236), ('ssm', nvdec_pass2_otf_ext_s, 244)])
|
|
nvdec_vp9_pic_s: TypeAlias = struct__nvdec_vp9_pic_s
|
|
@c.record
|
|
class nvdec_nmv_context(c.Struct):
|
|
SIZE = 69
|
|
joints: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
sign: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
class0: c.Array[c.Array[ctypes.c_ubyte, Literal[1]], Literal[2]]
|
|
fp: c.Array[c.Array[ctypes.c_ubyte, Literal[3]], Literal[2]]
|
|
class0_hp: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
hp: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
classes: c.Array[c.Array[ctypes.c_ubyte, Literal[10]], Literal[2]]
|
|
class0_fp: c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[3]], Literal[2]], Literal[2]]
|
|
bits: c.Array[c.Array[ctypes.c_ubyte, Literal[10]], Literal[2]]
|
|
nvdec_nmv_context.register_fields([('joints', c.Array[ctypes.c_ubyte, Literal[3]], 0), ('sign', c.Array[ctypes.c_ubyte, Literal[2]], 3), ('class0', c.Array[c.Array[ctypes.c_ubyte, Literal[1]], Literal[2]], 5), ('fp', c.Array[c.Array[ctypes.c_ubyte, Literal[3]], Literal[2]], 7), ('class0_hp', c.Array[ctypes.c_ubyte, Literal[2]], 13), ('hp', c.Array[ctypes.c_ubyte, Literal[2]], 15), ('classes', c.Array[c.Array[ctypes.c_ubyte, Literal[10]], Literal[2]], 17), ('class0_fp', c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[3]], Literal[2]], Literal[2]], 37), ('bits', c.Array[c.Array[ctypes.c_ubyte, Literal[10]], Literal[2]], 49)])
|
|
@c.record
|
|
class nvdec_nmv_context_counts(c.Struct):
|
|
SIZE = 424
|
|
joints: c.Array[ctypes.c_uint32, Literal[4]]
|
|
sign: c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[2]]
|
|
classes: c.Array[c.Array[ctypes.c_uint32, Literal[11]], Literal[2]]
|
|
class0: c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[2]]
|
|
bits: c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[10]], Literal[2]]
|
|
class0_fp: c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[2]], Literal[2]]
|
|
fp: c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[2]]
|
|
class0_hp: c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[2]]
|
|
hp: c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[2]]
|
|
nvdec_nmv_context_counts.register_fields([('joints', c.Array[ctypes.c_uint32, Literal[4]], 0), ('sign', c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[2]], 16), ('classes', c.Array[c.Array[ctypes.c_uint32, Literal[11]], Literal[2]], 32), ('class0', c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[2]], 120), ('bits', c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[10]], Literal[2]], 136), ('class0_fp', c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[2]], Literal[2]], 296), ('fp', c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[2]], 360), ('class0_hp', c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[2]], 392), ('hp', c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[2]], 408)])
|
|
@c.record
|
|
class struct_nvdec_vp9AdaptiveEntropyProbs_s(c.Struct):
|
|
SIZE = 2720
|
|
inter_mode_prob: c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[7]]
|
|
intra_inter_prob: c.Array[ctypes.c_ubyte, Literal[4]]
|
|
uv_mode_prob: c.Array[c.Array[ctypes.c_ubyte, Literal[8]], Literal[10]]
|
|
tx8x8_prob: c.Array[c.Array[ctypes.c_ubyte, Literal[1]], Literal[2]]
|
|
tx16x16_prob: c.Array[c.Array[ctypes.c_ubyte, Literal[2]], Literal[2]]
|
|
tx32x32_prob: c.Array[c.Array[ctypes.c_ubyte, Literal[3]], Literal[2]]
|
|
sb_ymode_probB: c.Array[c.Array[ctypes.c_ubyte, Literal[1]], Literal[4]]
|
|
sb_ymode_prob: c.Array[c.Array[ctypes.c_ubyte, Literal[8]], Literal[4]]
|
|
partition_prob: c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[16]], Literal[2]]
|
|
uv_mode_probB: c.Array[c.Array[ctypes.c_ubyte, Literal[1]], Literal[10]]
|
|
switchable_interp_prob: c.Array[c.Array[ctypes.c_ubyte, Literal[2]], Literal[4]]
|
|
comp_inter_prob: c.Array[ctypes.c_ubyte, Literal[5]]
|
|
mbskip_probs: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
pad1: c.Array[ctypes.c_ubyte, Literal[1]]
|
|
nmvc: nvdec_nmv_context
|
|
single_ref_prob: c.Array[c.Array[ctypes.c_ubyte, Literal[2]], Literal[5]]
|
|
comp_ref_prob: c.Array[ctypes.c_ubyte, Literal[5]]
|
|
pad2: c.Array[ctypes.c_ubyte, Literal[17]]
|
|
probCoeffs: c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]]
|
|
probCoeffs8x8: c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]]
|
|
probCoeffs16x16: c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]]
|
|
probCoeffs32x32: c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]]
|
|
struct_nvdec_vp9AdaptiveEntropyProbs_s.register_fields([('inter_mode_prob', c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[7]], 0), ('intra_inter_prob', c.Array[ctypes.c_ubyte, Literal[4]], 28), ('uv_mode_prob', c.Array[c.Array[ctypes.c_ubyte, Literal[8]], Literal[10]], 32), ('tx8x8_prob', c.Array[c.Array[ctypes.c_ubyte, Literal[1]], Literal[2]], 112), ('tx16x16_prob', c.Array[c.Array[ctypes.c_ubyte, Literal[2]], Literal[2]], 114), ('tx32x32_prob', c.Array[c.Array[ctypes.c_ubyte, Literal[3]], Literal[2]], 118), ('sb_ymode_probB', c.Array[c.Array[ctypes.c_ubyte, Literal[1]], Literal[4]], 124), ('sb_ymode_prob', c.Array[c.Array[ctypes.c_ubyte, Literal[8]], Literal[4]], 128), ('partition_prob', c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[16]], Literal[2]], 160), ('uv_mode_probB', c.Array[c.Array[ctypes.c_ubyte, Literal[1]], Literal[10]], 288), ('switchable_interp_prob', c.Array[c.Array[ctypes.c_ubyte, Literal[2]], Literal[4]], 298), ('comp_inter_prob', c.Array[ctypes.c_ubyte, Literal[5]], 306), ('mbskip_probs', c.Array[ctypes.c_ubyte, Literal[3]], 311), ('pad1', c.Array[ctypes.c_ubyte, Literal[1]], 314), ('nmvc', nvdec_nmv_context, 315), ('single_ref_prob', c.Array[c.Array[ctypes.c_ubyte, Literal[2]], Literal[5]], 384), ('comp_ref_prob', c.Array[ctypes.c_ubyte, Literal[5]], 394), ('pad2', c.Array[ctypes.c_ubyte, Literal[17]], 399), ('probCoeffs', c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 416), ('probCoeffs8x8', c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 992), ('probCoeffs16x16', c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 1568), ('probCoeffs32x32', c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 2144)])
|
|
nvdec_vp9AdaptiveEntropyProbs_t: TypeAlias = struct_nvdec_vp9AdaptiveEntropyProbs_s
|
|
@c.record
|
|
class struct_nvdec_vp9EntropyProbs_s(c.Struct):
|
|
SIZE = 3744
|
|
kf_bmode_prob: c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[8]], Literal[10]], Literal[10]]
|
|
kf_bmode_probB: c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[1]], Literal[10]], Literal[10]]
|
|
ref_pred_probs: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
mb_segment_tree_probs: c.Array[ctypes.c_ubyte, Literal[7]]
|
|
segment_pred_probs: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
ref_scores: c.Array[ctypes.c_ubyte, Literal[4]]
|
|
prob_comppred: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
pad1: c.Array[ctypes.c_ubyte, Literal[9]]
|
|
kf_uv_mode_prob: c.Array[c.Array[ctypes.c_ubyte, Literal[8]], Literal[10]]
|
|
kf_uv_mode_probB: c.Array[c.Array[ctypes.c_ubyte, Literal[1]], Literal[10]]
|
|
pad2: c.Array[ctypes.c_ubyte, Literal[6]]
|
|
a: struct_nvdec_vp9AdaptiveEntropyProbs_s
|
|
struct_nvdec_vp9EntropyProbs_s.register_fields([('kf_bmode_prob', c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[8]], Literal[10]], Literal[10]], 0), ('kf_bmode_probB', c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[1]], Literal[10]], Literal[10]], 800), ('ref_pred_probs', c.Array[ctypes.c_ubyte, Literal[3]], 900), ('mb_segment_tree_probs', c.Array[ctypes.c_ubyte, Literal[7]], 903), ('segment_pred_probs', c.Array[ctypes.c_ubyte, Literal[3]], 910), ('ref_scores', c.Array[ctypes.c_ubyte, Literal[4]], 913), ('prob_comppred', c.Array[ctypes.c_ubyte, Literal[2]], 917), ('pad1', c.Array[ctypes.c_ubyte, Literal[9]], 919), ('kf_uv_mode_prob', c.Array[c.Array[ctypes.c_ubyte, Literal[8]], Literal[10]], 928), ('kf_uv_mode_probB', c.Array[c.Array[ctypes.c_ubyte, Literal[1]], Literal[10]], 1008), ('pad2', c.Array[ctypes.c_ubyte, Literal[6]], 1018), ('a', nvdec_vp9AdaptiveEntropyProbs_t, 1024)])
|
|
nvdec_vp9EntropyProbs_t: TypeAlias = struct_nvdec_vp9EntropyProbs_s
|
|
@c.record
|
|
class struct_nvdec_vp9EntropyCounts_s(c.Struct):
|
|
SIZE = 13264
|
|
inter_mode_counts: c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[3]], Literal[7]]
|
|
sb_ymode_counts: c.Array[c.Array[ctypes.c_uint32, Literal[10]], Literal[4]]
|
|
uv_mode_counts: c.Array[c.Array[ctypes.c_uint32, Literal[10]], Literal[10]]
|
|
partition_counts: c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[16]]
|
|
switchable_interp_counts: c.Array[c.Array[ctypes.c_uint32, Literal[3]], Literal[4]]
|
|
intra_inter_count: c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[4]]
|
|
comp_inter_count: c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[5]]
|
|
single_ref_count: c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[2]], Literal[5]]
|
|
comp_ref_count: c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[5]]
|
|
tx32x32_count: c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[2]]
|
|
tx16x16_count: c.Array[c.Array[ctypes.c_uint32, Literal[3]], Literal[2]]
|
|
tx8x8_count: c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[2]]
|
|
mbskip_count: c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[3]]
|
|
nmvcount: nvdec_nmv_context_counts
|
|
countCoeffs: c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]]
|
|
countCoeffs8x8: c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]]
|
|
countCoeffs16x16: c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]]
|
|
countCoeffs32x32: c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]]
|
|
countEobs: c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[6]], Literal[6]], Literal[2]], Literal[2]], Literal[4]]
|
|
struct_nvdec_vp9EntropyCounts_s.register_fields([('inter_mode_counts', c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[3]], Literal[7]], 0), ('sb_ymode_counts', c.Array[c.Array[ctypes.c_uint32, Literal[10]], Literal[4]], 168), ('uv_mode_counts', c.Array[c.Array[ctypes.c_uint32, Literal[10]], Literal[10]], 328), ('partition_counts', c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[16]], 728), ('switchable_interp_counts', c.Array[c.Array[ctypes.c_uint32, Literal[3]], Literal[4]], 984), ('intra_inter_count', c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[4]], 1032), ('comp_inter_count', c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[5]], 1064), ('single_ref_count', c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[2]], Literal[5]], 1104), ('comp_ref_count', c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[5]], 1184), ('tx32x32_count', c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[2]], 1224), ('tx16x16_count', c.Array[c.Array[ctypes.c_uint32, Literal[3]], Literal[2]], 1256), ('tx8x8_count', c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[2]], 1280), ('mbskip_count', c.Array[c.Array[ctypes.c_uint32, Literal[2]], Literal[3]], 1296), ('nmvcount', nvdec_nmv_context_counts, 1320), ('countCoeffs', c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 1744), ('countCoeffs8x8', c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 4048), ('countCoeffs16x16', c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 6352), ('countCoeffs32x32', c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 8656), ('countEobs', c.Array[c.Array[c.Array[c.Array[c.Array[ctypes.c_uint32, Literal[6]], Literal[6]], Literal[2]], Literal[2]], Literal[4]], 10960)])
|
|
nvdec_vp9EntropyCounts_t: TypeAlias = struct_nvdec_vp9EntropyCounts_s
|
|
@c.record
|
|
class struct__nvdec_pass2_otf_s(c.Struct):
|
|
SIZE = 52
|
|
wrapped_session_key: c.Array[ctypes.c_uint32, Literal[4]]
|
|
wrapped_content_key: c.Array[ctypes.c_uint32, Literal[4]]
|
|
initialization_vector: c.Array[ctypes.c_uint32, Literal[4]]
|
|
enable_encryption: int
|
|
key_increment: int
|
|
encryption_mode: int
|
|
key_slot_index: int
|
|
ssm_en: int
|
|
reserved1: int
|
|
struct__nvdec_pass2_otf_s.register_fields([('wrapped_session_key', c.Array[ctypes.c_uint32, Literal[4]], 0), ('wrapped_content_key', c.Array[ctypes.c_uint32, Literal[4]], 16), ('initialization_vector', c.Array[ctypes.c_uint32, Literal[4]], 32), ('enable_encryption', ctypes.c_uint32, 48, 1, 0), ('key_increment', ctypes.c_uint32, 48, 6, 1), ('encryption_mode', ctypes.c_uint32, 48, 4, 7), ('key_slot_index', ctypes.c_uint32, 49, 4, 3), ('ssm_en', ctypes.c_uint32, 49, 1, 7), ('reserved1', ctypes.c_uint32, 50, 16, 0)])
|
|
nvdec_pass2_otf_s: TypeAlias = struct__nvdec_pass2_otf_s
|
|
@c.record
|
|
class struct__nvdec_display_param_s(c.Struct):
|
|
SIZE = 28
|
|
enableTFOutput: int
|
|
VC1MapYFlag: int
|
|
MapYValue: int
|
|
VC1MapUVFlag: int
|
|
MapUVValue: int
|
|
OutStride: int
|
|
TilingFormat: int
|
|
OutputStructure: int
|
|
reserved0: int
|
|
OutputTop: c.Array[ctypes.c_int32, Literal[2]]
|
|
OutputBottom: c.Array[ctypes.c_int32, Literal[2]]
|
|
enableHistogram: int
|
|
HistogramStartX: int
|
|
HistogramStartY: int
|
|
reserved1: int
|
|
HistogramEndX: int
|
|
HistogramEndY: int
|
|
reserved2: int
|
|
struct__nvdec_display_param_s.register_fields([('enableTFOutput', ctypes.c_uint32, 0, 1, 0), ('VC1MapYFlag', ctypes.c_uint32, 0, 1, 1), ('MapYValue', ctypes.c_uint32, 0, 3, 2), ('VC1MapUVFlag', ctypes.c_uint32, 0, 1, 5), ('MapUVValue', ctypes.c_uint32, 0, 3, 6), ('OutStride', ctypes.c_uint32, 1, 8, 1), ('TilingFormat', ctypes.c_uint32, 2, 3, 1), ('OutputStructure', ctypes.c_uint32, 2, 1, 4), ('reserved0', ctypes.c_uint32, 2, 11, 5), ('OutputTop', c.Array[ctypes.c_int32, Literal[2]], 4), ('OutputBottom', c.Array[ctypes.c_int32, Literal[2]], 12), ('enableHistogram', ctypes.c_uint32, 20, 1, 0), ('HistogramStartX', ctypes.c_uint32, 20, 12, 1), ('HistogramStartY', ctypes.c_uint32, 21, 12, 5), ('reserved1', ctypes.c_uint32, 23, 7, 1), ('HistogramEndX', ctypes.c_uint32, 24, 12, 0), ('HistogramEndY', ctypes.c_uint32, 25, 12, 4), ('reserved2', ctypes.c_uint32, 27, 8, 0)])
|
|
nvdec_display_param_s: TypeAlias = struct__nvdec_display_param_s
|
|
@c.record
|
|
class struct__nvdec_dpb_entry_s(c.Struct):
|
|
SIZE = 16
|
|
index: int
|
|
col_idx: int
|
|
state: int
|
|
is_long_term: int
|
|
not_existing: int
|
|
is_field: int
|
|
top_field_marking: int
|
|
bottom_field_marking: int
|
|
output_memory_layout: int
|
|
reserved: int
|
|
FieldOrderCnt: c.Array[ctypes.c_uint32, Literal[2]]
|
|
FrameIdx: int
|
|
struct__nvdec_dpb_entry_s.register_fields([('index', ctypes.c_uint32, 0, 7, 0), ('col_idx', ctypes.c_uint32, 0, 5, 7), ('state', ctypes.c_uint32, 1, 2, 4), ('is_long_term', ctypes.c_uint32, 1, 1, 6), ('not_existing', ctypes.c_uint32, 1, 1, 7), ('is_field', ctypes.c_uint32, 2, 1, 0), ('top_field_marking', ctypes.c_uint32, 2, 4, 1), ('bottom_field_marking', ctypes.c_uint32, 2, 4, 5), ('output_memory_layout', ctypes.c_uint32, 3, 1, 1), ('reserved', ctypes.c_uint32, 3, 6, 2), ('FieldOrderCnt', c.Array[ctypes.c_uint32, Literal[2]], 4), ('FrameIdx', ctypes.c_int32, 12)])
|
|
nvdec_dpb_entry_s: TypeAlias = struct__nvdec_dpb_entry_s
|
|
@c.record
|
|
class struct__nvdec_h264_pic_s(c.Struct):
|
|
SIZE = 764
|
|
encryption_params: struct__nvdec_pass2_otf_s
|
|
eos: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
explicitEOSPresentFlag: int
|
|
hint_dump_en: int
|
|
reserved0: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
stream_len: int
|
|
slice_count: int
|
|
mbhist_buffer_size: int
|
|
gptimer_timeout_value: int
|
|
log2_max_pic_order_cnt_lsb_minus4: int
|
|
delta_pic_order_always_zero_flag: int
|
|
frame_mbs_only_flag: int
|
|
PicWidthInMbs: int
|
|
FrameHeightInMbs: int
|
|
tileFormat: int
|
|
gob_height: int
|
|
reserverd_surface_format: int
|
|
entropy_coding_mode_flag: int
|
|
pic_order_present_flag: int
|
|
num_ref_idx_l0_active_minus1: int
|
|
num_ref_idx_l1_active_minus1: int
|
|
deblocking_filter_control_present_flag: int
|
|
redundant_pic_cnt_present_flag: int
|
|
transform_8x8_mode_flag: int
|
|
pitch_luma: int
|
|
pitch_chroma: int
|
|
luma_top_offset: int
|
|
luma_bot_offset: int
|
|
luma_frame_offset: int
|
|
chroma_top_offset: int
|
|
chroma_bot_offset: int
|
|
chroma_frame_offset: int
|
|
HistBufferSize: int
|
|
MbaffFrameFlag: int
|
|
direct_8x8_inference_flag: int
|
|
weighted_pred_flag: int
|
|
constrained_intra_pred_flag: int
|
|
ref_pic_flag: int
|
|
field_pic_flag: int
|
|
bottom_field_flag: int
|
|
second_field: int
|
|
log2_max_frame_num_minus4: int
|
|
chroma_format_idc: int
|
|
pic_order_cnt_type: int
|
|
pic_init_qp_minus26: int
|
|
chroma_qp_index_offset: int
|
|
second_chroma_qp_index_offset: int
|
|
weighted_bipred_idc: int
|
|
CurrPicIdx: int
|
|
CurrColIdx: int
|
|
frame_num: int
|
|
frame_surfaces: int
|
|
output_memory_layout: int
|
|
CurrFieldOrderCnt: c.Array[ctypes.c_int32, Literal[2]]
|
|
dpb: c.Array[struct__nvdec_dpb_entry_s, Literal[16]]
|
|
WeightScale: c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[4]], Literal[6]]
|
|
WeightScale8x8: c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[8]], Literal[8]], Literal[2]]
|
|
num_inter_view_refs_lX: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
reserved1: c.Array[ctypes.c_char, Literal[14]]
|
|
inter_view_refidx_lX: c.Array[c.Array[ctypes.c_byte, Literal[16]], Literal[2]]
|
|
lossless_ipred8x8_filter_enable: int
|
|
qpprime_y_zero_transform_bypass_flag: int
|
|
reserved2: int
|
|
displayPara: struct__nvdec_display_param_s
|
|
ssm: struct__nvdec_pass2_otf_ext_s
|
|
struct__nvdec_h264_pic_s.register_fields([('encryption_params', nvdec_pass2_otf_s, 0), ('eos', c.Array[ctypes.c_ubyte, Literal[16]], 52), ('explicitEOSPresentFlag', ctypes.c_ubyte, 68), ('hint_dump_en', ctypes.c_ubyte, 69), ('reserved0', c.Array[ctypes.c_ubyte, Literal[2]], 70), ('stream_len', ctypes.c_uint32, 72), ('slice_count', ctypes.c_uint32, 76), ('mbhist_buffer_size', ctypes.c_uint32, 80), ('gptimer_timeout_value', ctypes.c_uint32, 84), ('log2_max_pic_order_cnt_lsb_minus4', ctypes.c_int32, 88), ('delta_pic_order_always_zero_flag', ctypes.c_int32, 92), ('frame_mbs_only_flag', ctypes.c_int32, 96), ('PicWidthInMbs', ctypes.c_int32, 100), ('FrameHeightInMbs', ctypes.c_int32, 104), ('tileFormat', ctypes.c_uint32, 108, 2, 0), ('gob_height', ctypes.c_uint32, 108, 3, 2), ('reserverd_surface_format', ctypes.c_uint32, 108, 27, 5), ('entropy_coding_mode_flag', ctypes.c_int32, 112), ('pic_order_present_flag', ctypes.c_int32, 116), ('num_ref_idx_l0_active_minus1', ctypes.c_int32, 120), ('num_ref_idx_l1_active_minus1', ctypes.c_int32, 124), ('deblocking_filter_control_present_flag', ctypes.c_int32, 128), ('redundant_pic_cnt_present_flag', ctypes.c_int32, 132), ('transform_8x8_mode_flag', ctypes.c_int32, 136), ('pitch_luma', ctypes.c_uint32, 140), ('pitch_chroma', ctypes.c_uint32, 144), ('luma_top_offset', ctypes.c_uint32, 148), ('luma_bot_offset', ctypes.c_uint32, 152), ('luma_frame_offset', ctypes.c_uint32, 156), ('chroma_top_offset', ctypes.c_uint32, 160), ('chroma_bot_offset', ctypes.c_uint32, 164), ('chroma_frame_offset', ctypes.c_uint32, 168), ('HistBufferSize', ctypes.c_uint32, 172), ('MbaffFrameFlag', ctypes.c_uint32, 176, 1, 0), ('direct_8x8_inference_flag', ctypes.c_uint32, 176, 1, 1), ('weighted_pred_flag', ctypes.c_uint32, 176, 1, 2), ('constrained_intra_pred_flag', ctypes.c_uint32, 176, 1, 3), ('ref_pic_flag', ctypes.c_uint32, 176, 1, 4), ('field_pic_flag', ctypes.c_uint32, 176, 1, 5), ('bottom_field_flag', ctypes.c_uint32, 176, 1, 6), ('second_field', ctypes.c_uint32, 176, 1, 7), ('log2_max_frame_num_minus4', ctypes.c_uint32, 177, 4, 0), ('chroma_format_idc', ctypes.c_uint32, 177, 2, 4), ('pic_order_cnt_type', ctypes.c_uint32, 177, 2, 6), ('pic_init_qp_minus26', ctypes.c_int32, 178, 6, 0), ('chroma_qp_index_offset', ctypes.c_int32, 178, 5, 6), ('second_chroma_qp_index_offset', ctypes.c_int32, 179, 5, 3), ('weighted_bipred_idc', ctypes.c_uint32, 180, 2, 0), ('CurrPicIdx', ctypes.c_uint32, 180, 7, 2), ('CurrColIdx', ctypes.c_uint32, 181, 5, 1), ('frame_num', ctypes.c_uint32, 181, 16, 6), ('frame_surfaces', ctypes.c_uint32, 183, 1, 6), ('output_memory_layout', ctypes.c_uint32, 183, 1, 7), ('CurrFieldOrderCnt', c.Array[ctypes.c_int32, Literal[2]], 184), ('dpb', c.Array[nvdec_dpb_entry_s, Literal[16]], 192), ('WeightScale', c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[4]], Literal[6]], 448), ('WeightScale8x8', c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[8]], Literal[8]], Literal[2]], 544), ('num_inter_view_refs_lX', c.Array[ctypes.c_ubyte, Literal[2]], 672), ('reserved1', c.Array[ctypes.c_char, Literal[14]], 674), ('inter_view_refidx_lX', c.Array[c.Array[ctypes.c_byte, Literal[16]], Literal[2]], 688), ('lossless_ipred8x8_filter_enable', ctypes.c_uint32, 720, 1, 0), ('qpprime_y_zero_transform_bypass_flag', ctypes.c_uint32, 720, 1, 1), ('reserved2', ctypes.c_uint32, 720, 30, 2), ('displayPara', nvdec_display_param_s, 724), ('ssm', nvdec_pass2_otf_ext_s, 752)])
|
|
nvdec_h264_pic_s: TypeAlias = struct__nvdec_h264_pic_s
|
|
enum__vc1_fcm_e: dict[int, str] = {(FCM_PROGRESSIVE:=0): 'FCM_PROGRESSIVE', (FCM_FRAME_INTERLACE:=2): 'FCM_FRAME_INTERLACE', (FCM_FIELD_INTERLACE:=3): 'FCM_FIELD_INTERLACE'}
|
|
vc1_fcm_e: TypeAlias = ctypes.c_uint32
|
|
enum__syntax_vc1_ptype_e: dict[int, str] = {(PTYPE_I:=0): 'PTYPE_I', (PTYPE_P:=1): 'PTYPE_P', (PTYPE_B:=2): 'PTYPE_B', (PTYPE_BI:=3): 'PTYPE_BI', (PTYPE_SKIPPED:=4): 'PTYPE_SKIPPED'}
|
|
syntax_vc1_ptype_e: TypeAlias = ctypes.c_uint32
|
|
enum_vc1_mvmode_e: dict[int, str] = {(MVMODE_MIXEDMV:=0): 'MVMODE_MIXEDMV', (MVMODE_1MV:=1): 'MVMODE_1MV', (MVMODE_1MV_HALFPEL:=2): 'MVMODE_1MV_HALFPEL', (MVMODE_1MV_HALFPEL_BILINEAR:=3): 'MVMODE_1MV_HALFPEL_BILINEAR', (MVMODE_INTENSITY_COMPENSATION:=4): 'MVMODE_INTENSITY_COMPENSATION'}
|
|
enum__vc1_fptype_e: dict[int, str] = {(FPTYPE_I_I:=0): 'FPTYPE_I_I', (FPTYPE_I_P:=1): 'FPTYPE_I_P', (FPTYPE_P_I:=2): 'FPTYPE_P_I', (FPTYPE_P_P:=3): 'FPTYPE_P_P', (FPTYPE_B_B:=4): 'FPTYPE_B_B', (FPTYPE_B_BI:=5): 'FPTYPE_B_BI', (FPTYPE_BI_B:=6): 'FPTYPE_BI_B', (FPTYPE_BI_BI:=7): 'FPTYPE_BI_BI'}
|
|
vc1_fptype_e: TypeAlias = ctypes.c_uint32
|
|
enum__vc1_dqprofile_e: dict[int, str] = {(DQPROFILE_ALL_FOUR_EDGES:=0): 'DQPROFILE_ALL_FOUR_EDGES', (DQPROFILE_DOUBLE_EDGE:=1): 'DQPROFILE_DOUBLE_EDGE', (DQPROFILE_SINGLE_EDGE:=2): 'DQPROFILE_SINGLE_EDGE', (DQPROFILE_ALL_MACROBLOCKS:=3): 'DQPROFILE_ALL_MACROBLOCKS'}
|
|
vc1_dqprofile_e: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct__nvdec_vc1_pic_s(c.Struct):
|
|
SIZE = 404
|
|
encryption_params: struct__nvdec_pass2_otf_s
|
|
eos: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
prefixStartCode: c.Array[ctypes.c_ubyte, Literal[4]]
|
|
bitstream_offset: int
|
|
explicitEOSPresentFlag: int
|
|
reserved0: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
stream_len: int
|
|
slice_count: int
|
|
scratch_pic_buffer_size: int
|
|
gptimer_timeout_value: int
|
|
FrameWidth: int
|
|
FrameHeight: int
|
|
profile: int
|
|
postprocflag: int
|
|
pulldown: int
|
|
interlace: int
|
|
tfcntrflag: int
|
|
finterpflag: int
|
|
psf: int
|
|
tileFormat: int
|
|
gob_height: int
|
|
reserverd_surface_format: int
|
|
multires: int
|
|
syncmarker: int
|
|
rangered: int
|
|
maxbframes: int
|
|
dquant: int
|
|
panscan_flag: int
|
|
refdist_flag: int
|
|
quantizer: int
|
|
extended_mv: int
|
|
extended_dmv: int
|
|
overlap: int
|
|
vstransform: int
|
|
refdist: bytes
|
|
reserved1: c.Array[ctypes.c_char, Literal[3]]
|
|
fcm: int
|
|
ptype: int
|
|
tfcntr: int
|
|
rptfrm: int
|
|
tff: int
|
|
rndctrl: int
|
|
pqindex: int
|
|
halfqp: int
|
|
pquantizer: int
|
|
postproc: int
|
|
condover: int
|
|
transacfrm: int
|
|
transacfrm2: int
|
|
transdctab: int
|
|
pqdiff: int
|
|
abspq: int
|
|
dquantfrm: int
|
|
dqprofile: int
|
|
dqsbedge: int
|
|
dqdbedge: int
|
|
dqbilevel: int
|
|
mvrange: int
|
|
mvmode: int
|
|
mvmode2: int
|
|
lumscale: int
|
|
lumshift: int
|
|
mvtab: int
|
|
cbptab: int
|
|
ttmbf: int
|
|
ttfrm: int
|
|
bfraction: int
|
|
fptype: int
|
|
numref: int
|
|
reffield: int
|
|
dmvrange: int
|
|
intcompfield: int
|
|
lumscale1: int
|
|
lumshift1: int
|
|
lumscale2: int
|
|
lumshift2: int
|
|
mbmodetab: int
|
|
imvtab: int
|
|
icbptab: int
|
|
fourmvbptab: int
|
|
fourmvswitch: int
|
|
intcomp: int
|
|
twomvbptab: int
|
|
rangeredfrm: int
|
|
HistBufferSize: int
|
|
FrameStride: c.Array[ctypes.c_uint32, Literal[2]]
|
|
luma_top_offset: int
|
|
luma_bot_offset: int
|
|
luma_frame_offset: int
|
|
chroma_top_offset: int
|
|
chroma_bot_offset: int
|
|
chroma_frame_offset: int
|
|
CodedWidth: int
|
|
CodedHeight: int
|
|
loopfilter: int
|
|
fastuvmc: int
|
|
output_memory_layout: int
|
|
ref_memory_layout: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
reserved3: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
displayPara: struct__nvdec_display_param_s
|
|
ssm: struct__nvdec_pass2_otf_ext_s
|
|
struct__nvdec_vc1_pic_s.register_fields([('encryption_params', nvdec_pass2_otf_s, 0), ('eos', c.Array[ctypes.c_ubyte, Literal[16]], 52), ('prefixStartCode', c.Array[ctypes.c_ubyte, Literal[4]], 68), ('bitstream_offset', ctypes.c_uint32, 72), ('explicitEOSPresentFlag', ctypes.c_ubyte, 76), ('reserved0', c.Array[ctypes.c_ubyte, Literal[3]], 77), ('stream_len', ctypes.c_uint32, 80), ('slice_count', ctypes.c_uint32, 84), ('scratch_pic_buffer_size', ctypes.c_uint32, 88), ('gptimer_timeout_value', ctypes.c_uint32, 92), ('FrameWidth', ctypes.c_uint16, 96), ('FrameHeight', ctypes.c_uint16, 98), ('profile', ctypes.c_ubyte, 100), ('postprocflag', ctypes.c_ubyte, 101), ('pulldown', ctypes.c_ubyte, 102), ('interlace', ctypes.c_ubyte, 103), ('tfcntrflag', ctypes.c_ubyte, 104), ('finterpflag', ctypes.c_ubyte, 105), ('psf', ctypes.c_ubyte, 106), ('tileFormat', ctypes.c_ubyte, 107, 2, 0), ('gob_height', ctypes.c_ubyte, 107, 3, 2), ('reserverd_surface_format', ctypes.c_ubyte, 107, 3, 5), ('multires', ctypes.c_ubyte, 108), ('syncmarker', ctypes.c_ubyte, 109), ('rangered', ctypes.c_ubyte, 110), ('maxbframes', ctypes.c_ubyte, 111), ('dquant', ctypes.c_ubyte, 112), ('panscan_flag', ctypes.c_ubyte, 113), ('refdist_flag', ctypes.c_ubyte, 114), ('quantizer', ctypes.c_ubyte, 115), ('extended_mv', ctypes.c_ubyte, 116), ('extended_dmv', ctypes.c_ubyte, 117), ('overlap', ctypes.c_ubyte, 118), ('vstransform', ctypes.c_ubyte, 119), ('refdist', ctypes.c_char, 120), ('reserved1', c.Array[ctypes.c_char, Literal[3]], 121), ('fcm', vc1_fcm_e, 124), ('ptype', syntax_vc1_ptype_e, 128), ('tfcntr', ctypes.c_int32, 132), ('rptfrm', ctypes.c_int32, 136), ('tff', ctypes.c_int32, 140), ('rndctrl', ctypes.c_int32, 144), ('pqindex', ctypes.c_int32, 148), ('halfqp', ctypes.c_int32, 152), ('pquantizer', ctypes.c_int32, 156), ('postproc', ctypes.c_int32, 160), ('condover', ctypes.c_int32, 164), ('transacfrm', ctypes.c_int32, 168), ('transacfrm2', ctypes.c_int32, 172), ('transdctab', ctypes.c_int32, 176), ('pqdiff', ctypes.c_int32, 180), ('abspq', ctypes.c_int32, 184), ('dquantfrm', ctypes.c_int32, 188), ('dqprofile', vc1_dqprofile_e, 192), ('dqsbedge', ctypes.c_int32, 196), ('dqdbedge', ctypes.c_int32, 200), ('dqbilevel', ctypes.c_int32, 204), ('mvrange', ctypes.c_int32, 208), ('mvmode', ctypes.c_uint32, 212), ('mvmode2', ctypes.c_uint32, 216), ('lumscale', ctypes.c_int32, 220), ('lumshift', ctypes.c_int32, 224), ('mvtab', ctypes.c_int32, 228), ('cbptab', ctypes.c_int32, 232), ('ttmbf', ctypes.c_int32, 236), ('ttfrm', ctypes.c_int32, 240), ('bfraction', ctypes.c_int32, 244), ('fptype', vc1_fptype_e, 248), ('numref', ctypes.c_int32, 252), ('reffield', ctypes.c_int32, 256), ('dmvrange', ctypes.c_int32, 260), ('intcompfield', ctypes.c_int32, 264), ('lumscale1', ctypes.c_int32, 268), ('lumshift1', ctypes.c_int32, 272), ('lumscale2', ctypes.c_int32, 276), ('lumshift2', ctypes.c_int32, 280), ('mbmodetab', ctypes.c_int32, 284), ('imvtab', ctypes.c_int32, 288), ('icbptab', ctypes.c_int32, 292), ('fourmvbptab', ctypes.c_int32, 296), ('fourmvswitch', ctypes.c_int32, 300), ('intcomp', ctypes.c_int32, 304), ('twomvbptab', ctypes.c_int32, 308), ('rangeredfrm', ctypes.c_int32, 312), ('HistBufferSize', ctypes.c_uint32, 316), ('FrameStride', c.Array[ctypes.c_uint32, Literal[2]], 320), ('luma_top_offset', ctypes.c_uint32, 328), ('luma_bot_offset', ctypes.c_uint32, 332), ('luma_frame_offset', ctypes.c_uint32, 336), ('chroma_top_offset', ctypes.c_uint32, 340), ('chroma_bot_offset', ctypes.c_uint32, 344), ('chroma_frame_offset', ctypes.c_uint32, 348), ('CodedWidth', ctypes.c_uint16, 352), ('CodedHeight', ctypes.c_uint16, 354), ('loopfilter', ctypes.c_ubyte, 356), ('fastuvmc', ctypes.c_ubyte, 357), ('output_memory_layout', ctypes.c_ubyte, 358), ('ref_memory_layout', c.Array[ctypes.c_ubyte, Literal[2]], 359), ('reserved3', c.Array[ctypes.c_ubyte, Literal[3]], 361), ('displayPara', nvdec_display_param_s, 364), ('ssm', nvdec_pass2_otf_ext_s, 392)])
|
|
nvdec_vc1_pic_s: TypeAlias = struct__nvdec_vc1_pic_s
|
|
@c.record
|
|
class struct__nvdec_mpeg2_pic_s(c.Struct):
|
|
SIZE = 344
|
|
encryption_params: struct__nvdec_pass2_otf_s
|
|
eos: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
explicitEOSPresentFlag: int
|
|
reserved0: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
stream_len: int
|
|
slice_count: int
|
|
gptimer_timeout_value: int
|
|
FrameWidth: int
|
|
FrameHeight: int
|
|
picture_structure: int
|
|
picture_coding_type: int
|
|
intra_dc_precision: int
|
|
frame_pred_frame_dct: bytes
|
|
concealment_motion_vectors: bytes
|
|
intra_vlc_format: bytes
|
|
tileFormat: int
|
|
gob_height: int
|
|
reserverd_surface_format: int
|
|
reserved1: bytes
|
|
f_code: c.Array[ctypes.c_char, Literal[4]]
|
|
PicWidthInMbs: int
|
|
FrameHeightInMbs: int
|
|
pitch_luma: int
|
|
pitch_chroma: int
|
|
luma_top_offset: int
|
|
luma_bot_offset: int
|
|
luma_frame_offset: int
|
|
chroma_top_offset: int
|
|
chroma_bot_offset: int
|
|
chroma_frame_offset: int
|
|
HistBufferSize: int
|
|
output_memory_layout: int
|
|
alternate_scan: int
|
|
secondfield: int
|
|
rounding_type: int
|
|
MbInfoSizeInBytes: int
|
|
q_scale_type: int
|
|
top_field_first: int
|
|
full_pel_fwd_vector: int
|
|
full_pel_bwd_vector: int
|
|
quant_mat_8x8intra: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
quant_mat_8x8nonintra: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
ref_memory_layout: c.Array[ctypes.c_uint32, Literal[2]]
|
|
displayPara: struct__nvdec_display_param_s
|
|
ssm: struct__nvdec_pass2_otf_ext_s
|
|
struct__nvdec_mpeg2_pic_s.register_fields([('encryption_params', nvdec_pass2_otf_s, 0), ('eos', c.Array[ctypes.c_ubyte, Literal[16]], 52), ('explicitEOSPresentFlag', ctypes.c_ubyte, 68), ('reserved0', c.Array[ctypes.c_ubyte, Literal[3]], 69), ('stream_len', ctypes.c_uint32, 72), ('slice_count', ctypes.c_uint32, 76), ('gptimer_timeout_value', ctypes.c_uint32, 80), ('FrameWidth', ctypes.c_int16, 84), ('FrameHeight', ctypes.c_int16, 86), ('picture_structure', ctypes.c_ubyte, 88), ('picture_coding_type', ctypes.c_ubyte, 89), ('intra_dc_precision', ctypes.c_ubyte, 90), ('frame_pred_frame_dct', ctypes.c_char, 91), ('concealment_motion_vectors', ctypes.c_char, 92), ('intra_vlc_format', ctypes.c_char, 93), ('tileFormat', ctypes.c_ubyte, 94, 2, 0), ('gob_height', ctypes.c_ubyte, 94, 3, 2), ('reserverd_surface_format', ctypes.c_ubyte, 94, 3, 5), ('reserved1', ctypes.c_char, 95), ('f_code', c.Array[ctypes.c_char, Literal[4]], 96), ('PicWidthInMbs', ctypes.c_uint16, 100), ('FrameHeightInMbs', ctypes.c_uint16, 102), ('pitch_luma', ctypes.c_uint32, 104), ('pitch_chroma', ctypes.c_uint32, 108), ('luma_top_offset', ctypes.c_uint32, 112), ('luma_bot_offset', ctypes.c_uint32, 116), ('luma_frame_offset', ctypes.c_uint32, 120), ('chroma_top_offset', ctypes.c_uint32, 124), ('chroma_bot_offset', ctypes.c_uint32, 128), ('chroma_frame_offset', ctypes.c_uint32, 132), ('HistBufferSize', ctypes.c_uint32, 136), ('output_memory_layout', ctypes.c_uint16, 140), ('alternate_scan', ctypes.c_uint16, 142), ('secondfield', ctypes.c_uint16, 144), ('rounding_type', ctypes.c_uint16, 146), ('MbInfoSizeInBytes', ctypes.c_uint32, 148), ('q_scale_type', ctypes.c_uint32, 152), ('top_field_first', ctypes.c_uint32, 156), ('full_pel_fwd_vector', ctypes.c_uint32, 160), ('full_pel_bwd_vector', ctypes.c_uint32, 164), ('quant_mat_8x8intra', c.Array[ctypes.c_ubyte, Literal[64]], 168), ('quant_mat_8x8nonintra', c.Array[ctypes.c_ubyte, Literal[64]], 232), ('ref_memory_layout', c.Array[ctypes.c_uint32, Literal[2]], 296), ('displayPara', nvdec_display_param_s, 304), ('ssm', nvdec_pass2_otf_ext_s, 332)])
|
|
nvdec_mpeg2_pic_s: TypeAlias = struct__nvdec_mpeg2_pic_s
|
|
@c.record
|
|
class struct__nvdec_mpeg4_pic_s(c.Struct):
|
|
SIZE = 368
|
|
encryption_params: struct__nvdec_pass2_otf_s
|
|
eos: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
explicitEOSPresentFlag: int
|
|
reserved2: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
stream_len: int
|
|
slice_count: int
|
|
scratch_pic_buffer_size: int
|
|
gptimer_timeout_value: int
|
|
FrameWidth: int
|
|
FrameHeight: int
|
|
vop_time_increment_bitcount: bytes
|
|
resync_marker_disable: bytes
|
|
tileFormat: int
|
|
gob_height: int
|
|
reserverd_surface_format: int
|
|
reserved3: bytes
|
|
width: int
|
|
height: int
|
|
FrameStride: c.Array[ctypes.c_uint32, Literal[2]]
|
|
luma_top_offset: int
|
|
luma_bot_offset: int
|
|
luma_frame_offset: int
|
|
chroma_top_offset: int
|
|
chroma_bot_offset: int
|
|
chroma_frame_offset: int
|
|
HistBufferSize: int
|
|
trd: c.Array[ctypes.c_int32, Literal[2]]
|
|
trb: c.Array[ctypes.c_int32, Literal[2]]
|
|
divx_flags: int
|
|
vop_fcode_forward: int
|
|
vop_fcode_backward: int
|
|
interlaced: int
|
|
quant_type: int
|
|
quarter_sample: int
|
|
short_video_header: int
|
|
curr_output_memory_layout: int
|
|
ptype: int
|
|
rnd: int
|
|
alternate_vertical_scan_flag: int
|
|
top_field_flag: int
|
|
reserved0: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
intra_quant_mat: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
nonintra_quant_mat: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
ref_memory_layout: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
reserved1: c.Array[ctypes.c_ubyte, Literal[34]]
|
|
displayPara: struct__nvdec_display_param_s
|
|
struct__nvdec_mpeg4_pic_s.register_fields([('encryption_params', nvdec_pass2_otf_s, 0), ('eos', c.Array[ctypes.c_ubyte, Literal[16]], 52), ('explicitEOSPresentFlag', ctypes.c_ubyte, 68), ('reserved2', c.Array[ctypes.c_ubyte, Literal[3]], 69), ('stream_len', ctypes.c_uint32, 72), ('slice_count', ctypes.c_uint32, 76), ('scratch_pic_buffer_size', ctypes.c_uint32, 80), ('gptimer_timeout_value', ctypes.c_uint32, 84), ('FrameWidth', ctypes.c_int16, 88), ('FrameHeight', ctypes.c_int16, 90), ('vop_time_increment_bitcount', ctypes.c_char, 92), ('resync_marker_disable', ctypes.c_char, 93), ('tileFormat', ctypes.c_ubyte, 94, 2, 0), ('gob_height', ctypes.c_ubyte, 94, 3, 2), ('reserverd_surface_format', ctypes.c_ubyte, 94, 3, 5), ('reserved3', ctypes.c_char, 95), ('width', ctypes.c_int32, 96), ('height', ctypes.c_int32, 100), ('FrameStride', c.Array[ctypes.c_uint32, Literal[2]], 104), ('luma_top_offset', ctypes.c_uint32, 112), ('luma_bot_offset', ctypes.c_uint32, 116), ('luma_frame_offset', ctypes.c_uint32, 120), ('chroma_top_offset', ctypes.c_uint32, 124), ('chroma_bot_offset', ctypes.c_uint32, 128), ('chroma_frame_offset', ctypes.c_uint32, 132), ('HistBufferSize', ctypes.c_uint32, 136), ('trd', c.Array[ctypes.c_int32, Literal[2]], 140), ('trb', c.Array[ctypes.c_int32, Literal[2]], 148), ('divx_flags', ctypes.c_int32, 156), ('vop_fcode_forward', ctypes.c_int16, 160), ('vop_fcode_backward', ctypes.c_int16, 162), ('interlaced', ctypes.c_ubyte, 164), ('quant_type', ctypes.c_ubyte, 165), ('quarter_sample', ctypes.c_ubyte, 166), ('short_video_header', ctypes.c_ubyte, 167), ('curr_output_memory_layout', ctypes.c_ubyte, 168), ('ptype', ctypes.c_ubyte, 169), ('rnd', ctypes.c_ubyte, 170), ('alternate_vertical_scan_flag', ctypes.c_ubyte, 171), ('top_field_flag', ctypes.c_ubyte, 172), ('reserved0', c.Array[ctypes.c_ubyte, Literal[3]], 173), ('intra_quant_mat', c.Array[ctypes.c_ubyte, Literal[64]], 176), ('nonintra_quant_mat', c.Array[ctypes.c_ubyte, Literal[64]], 240), ('ref_memory_layout', c.Array[ctypes.c_ubyte, Literal[2]], 304), ('reserved1', c.Array[ctypes.c_ubyte, Literal[34]], 306), ('displayPara', nvdec_display_param_s, 340)])
|
|
nvdec_mpeg4_pic_s: TypeAlias = struct__nvdec_mpeg4_pic_s
|
|
enum_VP8_FRAME_TYPE: dict[int, str] = {(VP8_KEYFRAME:=0): 'VP8_KEYFRAME', (VP8_INTERFRAME:=1): 'VP8_INTERFRAME'}
|
|
enum_VP8_FRAME_SFC_ID: dict[int, str] = {(VP8_GOLDEN_FRAME_SFC:=0): 'VP8_GOLDEN_FRAME_SFC', (VP8_ALTREF_FRAME_SFC:=1): 'VP8_ALTREF_FRAME_SFC', (VP8_LAST_FRAME_SFC:=2): 'VP8_LAST_FRAME_SFC', (VP8_CURR_FRAME_SFC:=3): 'VP8_CURR_FRAME_SFC'}
|
|
@c.record
|
|
class struct__nvdec_vp8_pic_s(c.Struct):
|
|
SIZE = 192
|
|
encryption_params: struct__nvdec_pass2_otf_s
|
|
gptimer_timeout_value: int
|
|
FrameWidth: int
|
|
FrameHeight: int
|
|
keyFrame: int
|
|
version: int
|
|
tileFormat: int
|
|
gob_height: int
|
|
reserverd_surface_format: int
|
|
errorConcealOn: int
|
|
firstPartSize: int
|
|
HistBufferSize: int
|
|
VLDBufferSize: int
|
|
FrameStride: c.Array[ctypes.c_uint32, Literal[2]]
|
|
luma_top_offset: int
|
|
luma_bot_offset: int
|
|
luma_frame_offset: int
|
|
chroma_top_offset: int
|
|
chroma_bot_offset: int
|
|
chroma_frame_offset: int
|
|
displayPara: struct__nvdec_display_param_s
|
|
current_output_memory_layout: bytes
|
|
output_memory_layout: c.Array[ctypes.c_char, Literal[3]]
|
|
segmentation_feature_data_update: int
|
|
reserved1: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
resultValue: int
|
|
partition_offset: c.Array[ctypes.c_uint32, Literal[8]]
|
|
ssm: struct__nvdec_pass2_otf_ext_s
|
|
struct__nvdec_vp8_pic_s.register_fields([('encryption_params', nvdec_pass2_otf_s, 0), ('gptimer_timeout_value', ctypes.c_uint32, 52), ('FrameWidth', ctypes.c_uint16, 56), ('FrameHeight', ctypes.c_uint16, 58), ('keyFrame', ctypes.c_ubyte, 60), ('version', ctypes.c_ubyte, 61), ('tileFormat', ctypes.c_ubyte, 62, 2, 0), ('gob_height', ctypes.c_ubyte, 62, 3, 2), ('reserverd_surface_format', ctypes.c_ubyte, 62, 3, 5), ('errorConcealOn', ctypes.c_ubyte, 63), ('firstPartSize', ctypes.c_uint32, 64), ('HistBufferSize', ctypes.c_uint32, 68), ('VLDBufferSize', ctypes.c_uint32, 72), ('FrameStride', c.Array[ctypes.c_uint32, Literal[2]], 76), ('luma_top_offset', ctypes.c_uint32, 84), ('luma_bot_offset', ctypes.c_uint32, 88), ('luma_frame_offset', ctypes.c_uint32, 92), ('chroma_top_offset', ctypes.c_uint32, 96), ('chroma_bot_offset', ctypes.c_uint32, 100), ('chroma_frame_offset', ctypes.c_uint32, 104), ('displayPara', nvdec_display_param_s, 108), ('current_output_memory_layout', ctypes.c_char, 136), ('output_memory_layout', c.Array[ctypes.c_char, Literal[3]], 137), ('segmentation_feature_data_update', ctypes.c_ubyte, 140), ('reserved1', c.Array[ctypes.c_ubyte, Literal[3]], 141), ('resultValue', ctypes.c_uint32, 144), ('partition_offset', c.Array[ctypes.c_uint32, Literal[8]], 148), ('ssm', nvdec_pass2_otf_ext_s, 180)])
|
|
nvdec_vp8_pic_s: TypeAlias = struct__nvdec_vp8_pic_s
|
|
@c.record
|
|
class struct__bytes_of_data_s(c.Struct):
|
|
SIZE = 8
|
|
clear_bytes: int
|
|
encypted_bytes: int
|
|
struct__bytes_of_data_s.register_fields([('clear_bytes', ctypes.c_uint32, 0), ('encypted_bytes', ctypes.c_uint32, 4)])
|
|
bytes_of_data_s: TypeAlias = struct__bytes_of_data_s
|
|
@c.record
|
|
class struct__nvdec_pass1_input_data_s(c.Struct):
|
|
SIZE = 836
|
|
sample_size: c.Array[struct__bytes_of_data_s, Literal[32]]
|
|
initialization_vector: c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[32]]
|
|
IvValid: c.Array[ctypes.c_ubyte, Literal[32]]
|
|
stream_len: int
|
|
clearBufferSize: int
|
|
reencryptBufferSize: int
|
|
vp8coeffPartitonBufferSize: int
|
|
PrevWidth: int
|
|
num_nals: int
|
|
drm_mode: int
|
|
key_sel: int
|
|
codec: int
|
|
TotalSizeOfClearData: int
|
|
SliceHdrOffset: int
|
|
EncryptBlkCnt: int
|
|
SkipBlkCnt: int
|
|
struct__nvdec_pass1_input_data_s.register_fields([('sample_size', c.Array[bytes_of_data_s, Literal[32]], 0), ('initialization_vector', c.Array[c.Array[ctypes.c_uint32, Literal[4]], Literal[32]], 256), ('IvValid', c.Array[ctypes.c_ubyte, Literal[32]], 768), ('stream_len', ctypes.c_uint32, 800), ('clearBufferSize', ctypes.c_uint32, 804), ('reencryptBufferSize', ctypes.c_uint32, 808), ('vp8coeffPartitonBufferSize', ctypes.c_uint32, 812), ('PrevWidth', ctypes.c_uint32, 816), ('num_nals', ctypes.c_uint32, 820, 16, 0), ('drm_mode', ctypes.c_uint32, 822, 8, 0), ('key_sel', ctypes.c_uint32, 823, 4, 0), ('codec', ctypes.c_uint32, 823, 4, 4), ('TotalSizeOfClearData', ctypes.c_uint32, 824), ('SliceHdrOffset', ctypes.c_uint32, 828), ('EncryptBlkCnt', ctypes.c_uint32, 832, 16, 0), ('SkipBlkCnt', ctypes.c_uint32, 834, 16, 0)])
|
|
nvdec_pass1_input_data_s: TypeAlias = struct__nvdec_pass1_input_data_s
|
|
@c.record
|
|
class struct__nvdec_pass1_output_data_s(c.Struct):
|
|
SIZE = 128
|
|
clear_header_size: int
|
|
reencrypt_data_size: int
|
|
clear_token_data_size: int
|
|
key_increment: int
|
|
encryption_mode: int
|
|
bReEncrypted: int
|
|
bvp9SuperFrame: int
|
|
vp9NumFramesMinus1: int
|
|
reserved1: int
|
|
wrapped_session_key: c.Array[ctypes.c_uint32, Literal[4]]
|
|
wrapped_content_key: c.Array[ctypes.c_uint32, Literal[4]]
|
|
initialization_vector: c.Array[ctypes.c_uint32, Literal[4]]
|
|
partition_size: c.Array[ctypes.c_uint32, Literal[8]]
|
|
vp9_frame_sizes: c.Array[ctypes.c_uint32, Literal[8]]
|
|
vp9_clear_hdr_size: c.Array[ctypes.c_uint32, Literal[8]]
|
|
struct__nvdec_pass1_output_data_s.register_fields([('clear_header_size', ctypes.c_uint32, 0), ('reencrypt_data_size', ctypes.c_uint32, 4), ('clear_token_data_size', ctypes.c_uint32, 8), ('key_increment', ctypes.c_uint32, 12, 6, 0), ('encryption_mode', ctypes.c_uint32, 12, 4, 6), ('bReEncrypted', ctypes.c_uint32, 13, 1, 2), ('bvp9SuperFrame', ctypes.c_uint32, 13, 1, 3), ('vp9NumFramesMinus1', ctypes.c_uint32, 13, 3, 4), ('reserved1', ctypes.c_uint32, 13, 17, 7), ('wrapped_session_key', c.Array[ctypes.c_uint32, Literal[4]], 16), ('wrapped_content_key', c.Array[ctypes.c_uint32, Literal[4]], 32), ('initialization_vector', c.Array[ctypes.c_uint32, Literal[4]], 48), ('partition_size', c.Array[ctypes.c_uint32, Literal[8]], 64), ('vp9_frame_sizes', c.Array[ctypes.c_uint32, Literal[8]], 64), ('vp9_clear_hdr_size', c.Array[ctypes.c_uint32, Literal[8]], 96)])
|
|
nvdec_pass1_output_data_s: TypeAlias = struct__nvdec_pass1_output_data_s
|
|
@c.record
|
|
class struct__scale_factors_reference_s(c.Struct):
|
|
SIZE = 4
|
|
x_scale_fp: int
|
|
y_scale_fp: int
|
|
struct__scale_factors_reference_s.register_fields([('x_scale_fp', ctypes.c_int16, 0), ('y_scale_fp', ctypes.c_int16, 2)])
|
|
scale_factors_reference_s: TypeAlias = struct__scale_factors_reference_s
|
|
@c.record
|
|
class struct__frame_info_t(c.Struct):
|
|
SIZE = 12
|
|
width: int
|
|
height: int
|
|
stride: c.Array[ctypes.c_uint16, Literal[2]]
|
|
frame_buffer_idx: int
|
|
struct__frame_info_t.register_fields([('width', ctypes.c_uint16, 0), ('height', ctypes.c_uint16, 2), ('stride', c.Array[ctypes.c_uint16, Literal[2]], 4), ('frame_buffer_idx', ctypes.c_uint32, 8)])
|
|
frame_info_t: TypeAlias = struct__frame_info_t
|
|
@c.record
|
|
class struct__ref_frame_struct_s(c.Struct):
|
|
SIZE = 24
|
|
info: struct__frame_info_t
|
|
sf: struct__scale_factors_reference_s
|
|
sign_bias: int
|
|
wmtype: int
|
|
reserved_rf: int
|
|
frame_off: int
|
|
roffset: int
|
|
struct__ref_frame_struct_s.register_fields([('info', frame_info_t, 0), ('sf', scale_factors_reference_s, 12), ('sign_bias', ctypes.c_ubyte, 16, 1, 0), ('wmtype', ctypes.c_ubyte, 16, 2, 1), ('reserved_rf', ctypes.c_ubyte, 16, 5, 3), ('frame_off', ctypes.c_int16, 18), ('roffset', ctypes.c_int16, 20)])
|
|
ref_frame_struct_s: TypeAlias = struct__ref_frame_struct_s
|
|
@c.record
|
|
class struct__av1_fgs_cfg_t(c.Struct):
|
|
SIZE = 12
|
|
apply_grain: int
|
|
overlap_flag: int
|
|
clip_to_restricted_range: int
|
|
chroma_scaling_from_luma: int
|
|
num_y_points_b: int
|
|
num_cb_points_b: int
|
|
num_cr_points_b: int
|
|
scaling_shift: int
|
|
reserved_fgs: int
|
|
sw_random_seed: int
|
|
cb_offset: int
|
|
cr_offset: int
|
|
cb_mult: bytes
|
|
cb_luma_mult: bytes
|
|
cr_mult: bytes
|
|
cr_luma_mult: bytes
|
|
struct__av1_fgs_cfg_t.register_fields([('apply_grain', ctypes.c_uint16, 0, 1, 0), ('overlap_flag', ctypes.c_uint16, 0, 1, 1), ('clip_to_restricted_range', ctypes.c_uint16, 0, 1, 2), ('chroma_scaling_from_luma', ctypes.c_uint16, 0, 1, 3), ('num_y_points_b', ctypes.c_uint16, 0, 1, 4), ('num_cb_points_b', ctypes.c_uint16, 0, 1, 5), ('num_cr_points_b', ctypes.c_uint16, 0, 1, 6), ('scaling_shift', ctypes.c_uint16, 0, 4, 7), ('reserved_fgs', ctypes.c_uint16, 1, 5, 3), ('sw_random_seed', ctypes.c_uint16, 2), ('cb_offset', ctypes.c_int16, 4), ('cr_offset', ctypes.c_int16, 6), ('cb_mult', ctypes.c_char, 8), ('cb_luma_mult', ctypes.c_char, 9), ('cr_mult', ctypes.c_char, 10), ('cr_luma_mult', ctypes.c_char, 11)])
|
|
av1_fgs_cfg_t: TypeAlias = struct__av1_fgs_cfg_t
|
|
@c.record
|
|
class struct__nvdec_av1_pic_s(c.Struct):
|
|
SIZE = 572
|
|
encryption_params: struct__nvdec_pass2_otf_s
|
|
ssm: struct__nvdec_pass2_otf_ext_s
|
|
fgs_cfg: struct__av1_fgs_cfg_t
|
|
gptimer_timeout_value: int
|
|
stream_len: int
|
|
reserved12: int
|
|
use_128x128_superblock: int
|
|
chroma_format: int
|
|
bit_depth: int
|
|
enable_filter_intra: int
|
|
enable_intra_edge_filter: int
|
|
enable_interintra_compound: int
|
|
enable_masked_compound: int
|
|
enable_dual_filter: int
|
|
reserved10: int
|
|
reserved0: int
|
|
enable_jnt_comp: int
|
|
reserved1: int
|
|
enable_cdef: int
|
|
reserved11: int
|
|
enable_fgs: int
|
|
enable_substream_decoding: int
|
|
reserved2: int
|
|
frame_type: int
|
|
show_frame: int
|
|
reserved13: int
|
|
disable_cdf_update: int
|
|
allow_screen_content_tools: int
|
|
cur_frame_force_integer_mv: int
|
|
scale_denom_minus9: int
|
|
allow_intrabc: int
|
|
allow_high_precision_mv: int
|
|
interp_filter: int
|
|
switchable_motion_mode: int
|
|
use_ref_frame_mvs: int
|
|
refresh_frame_context: int
|
|
delta_q_present_flag: int
|
|
delta_q_res: int
|
|
delta_lf_present_flag: int
|
|
delta_lf_res: int
|
|
delta_lf_multi: int
|
|
reserved3: int
|
|
coded_lossless: int
|
|
tile_enabled: int
|
|
reserved4: int
|
|
superres_is_scaled: int
|
|
reserved_fh: int
|
|
tile_cols: int
|
|
tile_rows: int
|
|
context_update_tile_id: int
|
|
cdef_damping_minus_3: int
|
|
cdef_bits: int
|
|
frame_tx_mode: int
|
|
frame_reference_mode: int
|
|
skip_mode_flag: int
|
|
skip_ref0: int
|
|
skip_ref1: int
|
|
allow_warp: int
|
|
reduced_tx_set_used: int
|
|
ref_scaling_enable: int
|
|
reserved5: int
|
|
reserved6: int
|
|
superres_upscaled_width: int
|
|
superres_luma_step: int
|
|
superres_chroma_step: int
|
|
superres_init_luma_subpel_x: int
|
|
superres_init_chroma_subpel_x: int
|
|
base_qindex: int
|
|
y_dc_delta_q: bytes
|
|
u_dc_delta_q: bytes
|
|
v_dc_delta_q: bytes
|
|
u_ac_delta_q: bytes
|
|
v_ac_delta_q: bytes
|
|
qm_y: int
|
|
qm_u: int
|
|
qm_v: int
|
|
cdef_y_pri_strength: int
|
|
cdef_uv_pri_strength: int
|
|
cdef_y_sec_strength: int
|
|
cdef_uv_sec_strength: int
|
|
segment_enabled: int
|
|
segment_update_map: int
|
|
reserved7: int
|
|
segment_temporal_update: int
|
|
segment_feature_data: c.Array[c.Array[ctypes.c_int16, Literal[8]], Literal[8]]
|
|
last_active_segid: int
|
|
segid_preskip: int
|
|
prevsegid_flag: int
|
|
segment_quant_sign: int
|
|
filter_level: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
filter_level_u: int
|
|
filter_level_v: int
|
|
lf_sharpness_level: int
|
|
lf_ref_deltas: c.Array[ctypes.c_char, Literal[8]]
|
|
lf_mode_deltas: c.Array[ctypes.c_char, Literal[2]]
|
|
lr_type: int
|
|
lr_unit_size: int
|
|
current_frame: struct__frame_info_t
|
|
ref_frame: c.Array[struct__ref_frame_struct_s, Literal[7]]
|
|
use_temporal0_mvs: int
|
|
use_temporal1_mvs: int
|
|
use_temporal2_mvs: int
|
|
mf1_type: int
|
|
mf2_type: int
|
|
mf3_type: int
|
|
reserved_mfmv: int
|
|
mfmv_offset: c.Array[c.Array[ctypes.c_int16, Literal[7]], Literal[3]]
|
|
mfmv_side: c.Array[c.Array[ctypes.c_char, Literal[7]], Literal[3]]
|
|
tileformat: int
|
|
gob_height: int
|
|
errorConcealOn: int
|
|
reserver8: int
|
|
stream_error_detection: int
|
|
mv_error_detection: int
|
|
coeff_error_detection: int
|
|
reserved_eh: int
|
|
Av1FltTopOffset: int
|
|
Av1FltVertOffset: int
|
|
Av1CdefVertOffset: int
|
|
Av1LrVertOffset: int
|
|
Av1HusVertOffset: int
|
|
Av1FgsVertOffset: int
|
|
enable_histogram: int
|
|
sw_skip_start_length: int
|
|
reserved_stat: int
|
|
struct__nvdec_av1_pic_s.register_fields([('encryption_params', nvdec_pass2_otf_s, 0), ('ssm', nvdec_pass2_otf_ext_s, 52), ('fgs_cfg', av1_fgs_cfg_t, 64), ('gptimer_timeout_value', ctypes.c_uint32, 76), ('stream_len', ctypes.c_uint32, 80), ('reserved12', ctypes.c_uint32, 84), ('use_128x128_superblock', ctypes.c_uint32, 88, 1, 0), ('chroma_format', ctypes.c_uint32, 88, 2, 1), ('bit_depth', ctypes.c_uint32, 88, 4, 3), ('enable_filter_intra', ctypes.c_uint32, 88, 1, 7), ('enable_intra_edge_filter', ctypes.c_uint32, 89, 1, 0), ('enable_interintra_compound', ctypes.c_uint32, 89, 1, 1), ('enable_masked_compound', ctypes.c_uint32, 89, 1, 2), ('enable_dual_filter', ctypes.c_uint32, 89, 1, 3), ('reserved10', ctypes.c_uint32, 89, 1, 4), ('reserved0', ctypes.c_uint32, 89, 3, 5), ('enable_jnt_comp', ctypes.c_uint32, 90, 1, 0), ('reserved1', ctypes.c_uint32, 90, 1, 1), ('enable_cdef', ctypes.c_uint32, 90, 1, 2), ('reserved11', ctypes.c_uint32, 90, 1, 3), ('enable_fgs', ctypes.c_uint32, 90, 1, 4), ('enable_substream_decoding', ctypes.c_uint32, 90, 1, 5), ('reserved2', ctypes.c_uint32, 90, 10, 6), ('frame_type', ctypes.c_uint32, 92, 2, 0), ('show_frame', ctypes.c_uint32, 92, 1, 2), ('reserved13', ctypes.c_uint32, 92, 1, 3), ('disable_cdf_update', ctypes.c_uint32, 92, 1, 4), ('allow_screen_content_tools', ctypes.c_uint32, 92, 1, 5), ('cur_frame_force_integer_mv', ctypes.c_uint32, 92, 1, 6), ('scale_denom_minus9', ctypes.c_uint32, 92, 3, 7), ('allow_intrabc', ctypes.c_uint32, 93, 1, 2), ('allow_high_precision_mv', ctypes.c_uint32, 93, 1, 3), ('interp_filter', ctypes.c_uint32, 93, 3, 4), ('switchable_motion_mode', ctypes.c_uint32, 93, 1, 7), ('use_ref_frame_mvs', ctypes.c_uint32, 94, 1, 0), ('refresh_frame_context', ctypes.c_uint32, 94, 1, 1), ('delta_q_present_flag', ctypes.c_uint32, 94, 1, 2), ('delta_q_res', ctypes.c_uint32, 94, 2, 3), ('delta_lf_present_flag', ctypes.c_uint32, 94, 1, 5), ('delta_lf_res', ctypes.c_uint32, 94, 2, 6), ('delta_lf_multi', ctypes.c_uint32, 95, 1, 0), ('reserved3', ctypes.c_uint32, 95, 1, 1), ('coded_lossless', ctypes.c_uint32, 95, 1, 2), ('tile_enabled', ctypes.c_uint32, 95, 1, 3), ('reserved4', ctypes.c_uint32, 95, 2, 4), ('superres_is_scaled', ctypes.c_uint32, 95, 1, 6), ('reserved_fh', ctypes.c_uint32, 95, 1, 7), ('tile_cols', ctypes.c_uint32, 96, 8, 0), ('tile_rows', ctypes.c_uint32, 97, 8, 0), ('context_update_tile_id', ctypes.c_uint32, 98, 16, 0), ('cdef_damping_minus_3', ctypes.c_uint32, 100, 2, 0), ('cdef_bits', ctypes.c_uint32, 100, 2, 2), ('frame_tx_mode', ctypes.c_uint32, 100, 3, 4), ('frame_reference_mode', ctypes.c_uint32, 100, 2, 7), ('skip_mode_flag', ctypes.c_uint32, 101, 1, 1), ('skip_ref0', ctypes.c_uint32, 101, 4, 2), ('skip_ref1', ctypes.c_uint32, 101, 4, 6), ('allow_warp', ctypes.c_uint32, 102, 1, 2), ('reduced_tx_set_used', ctypes.c_uint32, 102, 1, 3), ('ref_scaling_enable', ctypes.c_uint32, 102, 1, 4), ('reserved5', ctypes.c_uint32, 102, 1, 5), ('reserved6', ctypes.c_uint32, 102, 10, 6), ('superres_upscaled_width', ctypes.c_uint16, 104), ('superres_luma_step', ctypes.c_uint16, 106), ('superres_chroma_step', ctypes.c_uint16, 108), ('superres_init_luma_subpel_x', ctypes.c_uint16, 110), ('superres_init_chroma_subpel_x', ctypes.c_uint16, 112), ('base_qindex', ctypes.c_ubyte, 114), ('y_dc_delta_q', ctypes.c_char, 115), ('u_dc_delta_q', ctypes.c_char, 116), ('v_dc_delta_q', ctypes.c_char, 117), ('u_ac_delta_q', ctypes.c_char, 118), ('v_ac_delta_q', ctypes.c_char, 119), ('qm_y', ctypes.c_ubyte, 120), ('qm_u', ctypes.c_ubyte, 121), ('qm_v', ctypes.c_ubyte, 122), ('cdef_y_pri_strength', ctypes.c_uint32, 124), ('cdef_uv_pri_strength', ctypes.c_uint32, 128), ('cdef_y_sec_strength', ctypes.c_uint32, 132, 16, 0), ('cdef_uv_sec_strength', ctypes.c_uint32, 134, 16, 0), ('segment_enabled', ctypes.c_ubyte, 136), ('segment_update_map', ctypes.c_ubyte, 137), ('reserved7', ctypes.c_ubyte, 138), ('segment_temporal_update', ctypes.c_ubyte, 139), ('segment_feature_data', c.Array[c.Array[ctypes.c_int16, Literal[8]], Literal[8]], 140), ('last_active_segid', ctypes.c_ubyte, 268), ('segid_preskip', ctypes.c_ubyte, 269), ('prevsegid_flag', ctypes.c_ubyte, 270), ('segment_quant_sign', ctypes.c_ubyte, 271, 8, 0), ('filter_level', c.Array[ctypes.c_ubyte, Literal[2]], 272), ('filter_level_u', ctypes.c_ubyte, 274), ('filter_level_v', ctypes.c_ubyte, 275), ('lf_sharpness_level', ctypes.c_ubyte, 276), ('lf_ref_deltas', c.Array[ctypes.c_char, Literal[8]], 277), ('lf_mode_deltas', c.Array[ctypes.c_char, Literal[2]], 285), ('lr_type', ctypes.c_ubyte, 287), ('lr_unit_size', ctypes.c_ubyte, 288), ('current_frame', frame_info_t, 292), ('ref_frame', c.Array[ref_frame_struct_s, Literal[7]], 304), ('use_temporal0_mvs', ctypes.c_uint32, 472, 1, 0), ('use_temporal1_mvs', ctypes.c_uint32, 472, 1, 1), ('use_temporal2_mvs', ctypes.c_uint32, 472, 1, 2), ('mf1_type', ctypes.c_uint32, 472, 3, 3), ('mf2_type', ctypes.c_uint32, 472, 3, 6), ('mf3_type', ctypes.c_uint32, 473, 3, 1), ('reserved_mfmv', ctypes.c_uint32, 473, 20, 4), ('mfmv_offset', c.Array[c.Array[ctypes.c_int16, Literal[7]], Literal[3]], 476), ('mfmv_side', c.Array[c.Array[ctypes.c_char, Literal[7]], Literal[3]], 518), ('tileformat', ctypes.c_ubyte, 539, 2, 0), ('gob_height', ctypes.c_ubyte, 539, 3, 2), ('errorConcealOn', ctypes.c_ubyte, 539, 1, 5), ('reserver8', ctypes.c_ubyte, 539, 2, 6), ('stream_error_detection', ctypes.c_ubyte, 540, 1, 0), ('mv_error_detection', ctypes.c_ubyte, 540, 1, 1), ('coeff_error_detection', ctypes.c_ubyte, 540, 1, 2), ('reserved_eh', ctypes.c_ubyte, 540, 5, 3), ('Av1FltTopOffset', ctypes.c_uint32, 544), ('Av1FltVertOffset', ctypes.c_uint32, 548), ('Av1CdefVertOffset', ctypes.c_uint32, 552), ('Av1LrVertOffset', ctypes.c_uint32, 556), ('Av1HusVertOffset', ctypes.c_uint32, 560), ('Av1FgsVertOffset', ctypes.c_uint32, 564), ('enable_histogram', ctypes.c_uint32, 568, 1, 0), ('sw_skip_start_length', ctypes.c_uint32, 568, 14, 1), ('reserved_stat', ctypes.c_uint32, 569, 17, 7)])
|
|
nvdec_av1_pic_s: TypeAlias = struct__nvdec_av1_pic_s
|
|
@c.record
|
|
class struct__AV1FilmGrainMemory(c.Struct):
|
|
SIZE = 13056
|
|
scaling_lut_y: c.Array[ctypes.c_ubyte, Literal[256]]
|
|
scaling_lut_cb: c.Array[ctypes.c_ubyte, Literal[256]]
|
|
scaling_lut_cr: c.Array[ctypes.c_ubyte, Literal[256]]
|
|
cropped_luma_grain_block: c.Array[ctypes.c_int16, Literal[4096]]
|
|
cropped_cb_grain_block: c.Array[ctypes.c_int16, Literal[1024]]
|
|
cropped_cr_grain_block: c.Array[ctypes.c_int16, Literal[1024]]
|
|
struct__AV1FilmGrainMemory.register_fields([('scaling_lut_y', c.Array[ctypes.c_ubyte, Literal[256]], 0), ('scaling_lut_cb', c.Array[ctypes.c_ubyte, Literal[256]], 256), ('scaling_lut_cr', c.Array[ctypes.c_ubyte, Literal[256]], 512), ('cropped_luma_grain_block', c.Array[ctypes.c_int16, Literal[4096]], 768), ('cropped_cb_grain_block', c.Array[ctypes.c_int16, Literal[1024]], 8960), ('cropped_cr_grain_block', c.Array[ctypes.c_int16, Literal[1024]], 11008)])
|
|
AV1FilmGrainMemory: TypeAlias = struct__AV1FilmGrainMemory
|
|
@c.record
|
|
class struct__AV1TileInfo_OLD(c.Struct):
|
|
SIZE = 16
|
|
width_in_sb: int
|
|
height_in_sb: int
|
|
tile_start_b0: int
|
|
tile_start_b1: int
|
|
tile_start_b2: int
|
|
tile_start_b3: int
|
|
tile_end_b0: int
|
|
tile_end_b1: int
|
|
tile_end_b2: int
|
|
tile_end_b3: int
|
|
padding: c.Array[ctypes.c_ubyte, Literal[6]]
|
|
struct__AV1TileInfo_OLD.register_fields([('width_in_sb', ctypes.c_ubyte, 0), ('height_in_sb', ctypes.c_ubyte, 1), ('tile_start_b0', ctypes.c_ubyte, 2), ('tile_start_b1', ctypes.c_ubyte, 3), ('tile_start_b2', ctypes.c_ubyte, 4), ('tile_start_b3', ctypes.c_ubyte, 5), ('tile_end_b0', ctypes.c_ubyte, 6), ('tile_end_b1', ctypes.c_ubyte, 7), ('tile_end_b2', ctypes.c_ubyte, 8), ('tile_end_b3', ctypes.c_ubyte, 9), ('padding', c.Array[ctypes.c_ubyte, Literal[6]], 10)])
|
|
AV1TileInfo_OLD: TypeAlias = struct__AV1TileInfo_OLD
|
|
@c.record
|
|
class struct__AV1TileInfo(c.Struct):
|
|
SIZE = 4
|
|
width_in_sb: int
|
|
padding_w: int
|
|
height_in_sb: int
|
|
padding_h: int
|
|
struct__AV1TileInfo.register_fields([('width_in_sb', ctypes.c_ubyte, 0), ('padding_w', ctypes.c_ubyte, 1), ('height_in_sb', ctypes.c_ubyte, 2), ('padding_h', ctypes.c_ubyte, 3)])
|
|
AV1TileInfo: TypeAlias = struct__AV1TileInfo
|
|
@c.record
|
|
class struct__AV1TileStreamInfo(c.Struct):
|
|
SIZE = 16
|
|
tile_start: int
|
|
tile_end: int
|
|
padding: c.Array[ctypes.c_ubyte, Literal[8]]
|
|
struct__AV1TileStreamInfo.register_fields([('tile_start', ctypes.c_uint32, 0), ('tile_end', ctypes.c_uint32, 4), ('padding', c.Array[ctypes.c_ubyte, Literal[8]], 8)])
|
|
AV1TileStreamInfo: TypeAlias = struct__AV1TileStreamInfo
|
|
@c.record
|
|
class struct__nvdec_new_h264_pic_s(c.Struct):
|
|
SIZE = 764
|
|
encryption_params: struct__nvdec_pass2_otf_s
|
|
eos: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
explicitEOSPresentFlag: int
|
|
hint_dump_en: int
|
|
reserved0: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
stream_len: int
|
|
slice_count: int
|
|
mbhist_buffer_size: int
|
|
gptimer_timeout_value: int
|
|
log2_max_pic_order_cnt_lsb_minus4: int
|
|
delta_pic_order_always_zero_flag: int
|
|
frame_mbs_only_flag: int
|
|
PicWidthInMbs: int
|
|
FrameHeightInMbs: int
|
|
tileFormat: int
|
|
gob_height: int
|
|
reserverd_surface_format: int
|
|
entropy_coding_mode_flag: int
|
|
pic_order_present_flag: int
|
|
num_ref_idx_l0_active_minus1: int
|
|
num_ref_idx_l1_active_minus1: int
|
|
deblocking_filter_control_present_flag: int
|
|
redundant_pic_cnt_present_flag: int
|
|
transform_8x8_mode_flag: int
|
|
pitch_luma: int
|
|
pitch_chroma: int
|
|
luma_top_offset: int
|
|
luma_bot_offset: int
|
|
luma_frame_offset: int
|
|
chroma_top_offset: int
|
|
chroma_bot_offset: int
|
|
chroma_frame_offset: int
|
|
HistBufferSize: int
|
|
MbaffFrameFlag: int
|
|
direct_8x8_inference_flag: int
|
|
weighted_pred_flag: int
|
|
constrained_intra_pred_flag: int
|
|
ref_pic_flag: int
|
|
field_pic_flag: int
|
|
bottom_field_flag: int
|
|
second_field: int
|
|
log2_max_frame_num_minus4: int
|
|
chroma_format_idc: int
|
|
pic_order_cnt_type: int
|
|
pic_init_qp_minus26: int
|
|
chroma_qp_index_offset: int
|
|
second_chroma_qp_index_offset: int
|
|
weighted_bipred_idc: int
|
|
CurrPicIdx: int
|
|
CurrColIdx: int
|
|
frame_num: int
|
|
frame_surfaces: int
|
|
output_memory_layout: int
|
|
CurrFieldOrderCnt: c.Array[ctypes.c_int32, Literal[2]]
|
|
dpb: c.Array[struct__nvdec_dpb_entry_s, Literal[16]]
|
|
WeightScale: c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[4]], Literal[6]]
|
|
WeightScale8x8: c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[8]], Literal[8]], Literal[2]]
|
|
num_inter_view_refs_lX: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
reserved1: c.Array[ctypes.c_char, Literal[14]]
|
|
inter_view_refidx_lX: c.Array[c.Array[ctypes.c_byte, Literal[16]], Literal[2]]
|
|
lossless_ipred8x8_filter_enable: int
|
|
qpprime_y_zero_transform_bypass_flag: int
|
|
reserved2: int
|
|
displayPara: struct__nvdec_display_param_s
|
|
ssm: struct__nvdec_pass2_otf_ext_s
|
|
struct__nvdec_new_h264_pic_s.register_fields([('encryption_params', nvdec_pass2_otf_s, 0), ('eos', c.Array[ctypes.c_ubyte, Literal[16]], 52), ('explicitEOSPresentFlag', ctypes.c_ubyte, 68), ('hint_dump_en', ctypes.c_ubyte, 69), ('reserved0', c.Array[ctypes.c_ubyte, Literal[2]], 70), ('stream_len', ctypes.c_uint32, 72), ('slice_count', ctypes.c_uint32, 76), ('mbhist_buffer_size', ctypes.c_uint32, 80), ('gptimer_timeout_value', ctypes.c_uint32, 84), ('log2_max_pic_order_cnt_lsb_minus4', ctypes.c_int32, 88), ('delta_pic_order_always_zero_flag', ctypes.c_int32, 92), ('frame_mbs_only_flag', ctypes.c_int32, 96), ('PicWidthInMbs', ctypes.c_int32, 100), ('FrameHeightInMbs', ctypes.c_int32, 104), ('tileFormat', ctypes.c_uint32, 108, 2, 0), ('gob_height', ctypes.c_uint32, 108, 3, 2), ('reserverd_surface_format', ctypes.c_uint32, 108, 27, 5), ('entropy_coding_mode_flag', ctypes.c_int32, 112), ('pic_order_present_flag', ctypes.c_int32, 116), ('num_ref_idx_l0_active_minus1', ctypes.c_int32, 120), ('num_ref_idx_l1_active_minus1', ctypes.c_int32, 124), ('deblocking_filter_control_present_flag', ctypes.c_int32, 128), ('redundant_pic_cnt_present_flag', ctypes.c_int32, 132), ('transform_8x8_mode_flag', ctypes.c_int32, 136), ('pitch_luma', ctypes.c_uint32, 140), ('pitch_chroma', ctypes.c_uint32, 144), ('luma_top_offset', ctypes.c_uint32, 148), ('luma_bot_offset', ctypes.c_uint32, 152), ('luma_frame_offset', ctypes.c_uint32, 156), ('chroma_top_offset', ctypes.c_uint32, 160), ('chroma_bot_offset', ctypes.c_uint32, 164), ('chroma_frame_offset', ctypes.c_uint32, 168), ('HistBufferSize', ctypes.c_uint32, 172), ('MbaffFrameFlag', ctypes.c_uint32, 176, 1, 0), ('direct_8x8_inference_flag', ctypes.c_uint32, 176, 1, 1), ('weighted_pred_flag', ctypes.c_uint32, 176, 1, 2), ('constrained_intra_pred_flag', ctypes.c_uint32, 176, 1, 3), ('ref_pic_flag', ctypes.c_uint32, 176, 1, 4), ('field_pic_flag', ctypes.c_uint32, 176, 1, 5), ('bottom_field_flag', ctypes.c_uint32, 176, 1, 6), ('second_field', ctypes.c_uint32, 176, 1, 7), ('log2_max_frame_num_minus4', ctypes.c_uint32, 177, 4, 0), ('chroma_format_idc', ctypes.c_uint32, 177, 2, 4), ('pic_order_cnt_type', ctypes.c_uint32, 177, 2, 6), ('pic_init_qp_minus26', ctypes.c_int32, 178, 6, 0), ('chroma_qp_index_offset', ctypes.c_int32, 178, 5, 6), ('second_chroma_qp_index_offset', ctypes.c_int32, 179, 5, 3), ('weighted_bipred_idc', ctypes.c_uint32, 180, 2, 0), ('CurrPicIdx', ctypes.c_uint32, 180, 7, 2), ('CurrColIdx', ctypes.c_uint32, 181, 5, 1), ('frame_num', ctypes.c_uint32, 181, 16, 6), ('frame_surfaces', ctypes.c_uint32, 183, 1, 6), ('output_memory_layout', ctypes.c_uint32, 183, 1, 7), ('CurrFieldOrderCnt', c.Array[ctypes.c_int32, Literal[2]], 184), ('dpb', c.Array[nvdec_dpb_entry_s, Literal[16]], 192), ('WeightScale', c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[4]], Literal[4]], Literal[6]], 448), ('WeightScale8x8', c.Array[c.Array[c.Array[ctypes.c_ubyte, Literal[8]], Literal[8]], Literal[2]], 544), ('num_inter_view_refs_lX', c.Array[ctypes.c_ubyte, Literal[2]], 672), ('reserved1', c.Array[ctypes.c_char, Literal[14]], 674), ('inter_view_refidx_lX', c.Array[c.Array[ctypes.c_byte, Literal[16]], Literal[2]], 688), ('lossless_ipred8x8_filter_enable', ctypes.c_uint32, 720, 1, 0), ('qpprime_y_zero_transform_bypass_flag', ctypes.c_uint32, 720, 1, 1), ('reserved2', ctypes.c_uint32, 720, 30, 2), ('displayPara', nvdec_display_param_s, 724), ('ssm', nvdec_pass2_otf_ext_s, 752)])
|
|
nvdec_new_h264_pic_s: TypeAlias = struct__nvdec_new_h264_pic_s
|
|
@c.record
|
|
class nvdec_crc_s(c.Struct):
|
|
SIZE = 128
|
|
dbg_crc_enable_partb: int
|
|
dbg_crc_enable_partc: int
|
|
dbg_crc_enable_partd: int
|
|
dbg_crc_enable_parte: int
|
|
dbg_crc_intf_partb: int
|
|
dbg_crc_intf_partc: int
|
|
dbg_crc_intf_partd: int
|
|
dbg_crc_intf_parte: int
|
|
reserved0: int
|
|
dbg_crc_partb_golden: c.Array[ctypes.c_uint32, Literal[4]]
|
|
dbg_crc_partc_golden: c.Array[ctypes.c_uint32, Literal[4]]
|
|
dbg_crc_partd_golden: c.Array[ctypes.c_uint32, Literal[4]]
|
|
dbg_crc_parte_golden: c.Array[ctypes.c_uint32, Literal[4]]
|
|
dbg_crc_comp_partb: int
|
|
dbg_crc_comp_partc: int
|
|
dbg_crc_comp_partd: int
|
|
dbg_crc_comp_parte: int
|
|
reserved1: int
|
|
reserved2: c.Array[ctypes.c_ubyte, Literal[56]]
|
|
nvdec_crc_s.register_fields([('dbg_crc_enable_partb', ctypes.c_uint32, 0, 1, 0), ('dbg_crc_enable_partc', ctypes.c_uint32, 0, 1, 1), ('dbg_crc_enable_partd', ctypes.c_uint32, 0, 1, 2), ('dbg_crc_enable_parte', ctypes.c_uint32, 0, 1, 3), ('dbg_crc_intf_partb', ctypes.c_uint32, 0, 6, 4), ('dbg_crc_intf_partc', ctypes.c_uint32, 1, 6, 2), ('dbg_crc_intf_partd', ctypes.c_uint32, 2, 6, 0), ('dbg_crc_intf_parte', ctypes.c_uint32, 2, 6, 6), ('reserved0', ctypes.c_uint32, 3, 4, 4), ('dbg_crc_partb_golden', c.Array[ctypes.c_uint32, Literal[4]], 4), ('dbg_crc_partc_golden', c.Array[ctypes.c_uint32, Literal[4]], 20), ('dbg_crc_partd_golden', c.Array[ctypes.c_uint32, Literal[4]], 36), ('dbg_crc_parte_golden', c.Array[ctypes.c_uint32, Literal[4]], 52), ('dbg_crc_comp_partb', ctypes.c_uint32, 68, 4, 0), ('dbg_crc_comp_partc', ctypes.c_uint32, 68, 4, 4), ('dbg_crc_comp_partd', ctypes.c_uint32, 69, 4, 0), ('dbg_crc_comp_parte', ctypes.c_uint32, 69, 4, 4), ('reserved1', ctypes.c_uint32, 70, 16, 0), ('reserved2', c.Array[ctypes.c_ubyte, Literal[56]], 72)])
|
|
@c.record
|
|
class struct_NV0000_ALLOC_PARAMETERS(c.Struct):
|
|
SIZE = 120
|
|
hClient: int
|
|
processID: int
|
|
processName: c.Array[ctypes.c_char, Literal[100]]
|
|
pOsPidInfo: ctypes.c_void_p
|
|
NvHandle: TypeAlias = ctypes.c_uint32
|
|
NvU32: TypeAlias = ctypes.c_uint32
|
|
NvP64: TypeAlias = ctypes.c_void_p
|
|
struct_NV0000_ALLOC_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('processID', NvU32, 4), ('processName', c.Array[ctypes.c_char, Literal[100]], 8), ('pOsPidInfo', NvP64, 112)])
|
|
NV0000_ALLOC_PARAMETERS: TypeAlias = struct_NV0000_ALLOC_PARAMETERS
|
|
@c.record
|
|
class struct_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
offset: int
|
|
limit: int
|
|
hVASpace: int
|
|
NvU64: TypeAlias = ctypes.c_uint64
|
|
struct_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS.register_fields([('offset', NvU64, 0), ('limit', NvU64, 8), ('hVASpace', NvHandle, 16)])
|
|
NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS: TypeAlias = struct_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS
|
|
@c.record
|
|
class struct_NV0080_ALLOC_PARAMETERS(c.Struct):
|
|
SIZE = 56
|
|
deviceId: int
|
|
hClientShare: int
|
|
hTargetClient: int
|
|
hTargetDevice: int
|
|
flags: int
|
|
vaSpaceSize: int
|
|
vaStartInternal: int
|
|
vaLimitInternal: int
|
|
vaMode: int
|
|
NvV32: TypeAlias = ctypes.c_uint32
|
|
struct_NV0080_ALLOC_PARAMETERS.register_fields([('deviceId', NvU32, 0), ('hClientShare', NvHandle, 4), ('hTargetClient', NvHandle, 8), ('hTargetDevice', NvHandle, 12), ('flags', NvV32, 16), ('vaSpaceSize', NvU64, 24), ('vaStartInternal', NvU64, 32), ('vaLimitInternal', NvU64, 40), ('vaMode', NvV32, 48)])
|
|
NV0080_ALLOC_PARAMETERS: TypeAlias = struct_NV0080_ALLOC_PARAMETERS
|
|
@c.record
|
|
class struct_NV2080_ALLOC_PARAMETERS(c.Struct):
|
|
SIZE = 4
|
|
subDeviceId: int
|
|
struct_NV2080_ALLOC_PARAMETERS.register_fields([('subDeviceId', NvU32, 0)])
|
|
NV2080_ALLOC_PARAMETERS: TypeAlias = struct_NV2080_ALLOC_PARAMETERS
|
|
@c.record
|
|
class struct__cl2080_tag0(c.Struct):
|
|
SIZE = 7936
|
|
Reserved00: c.Array[ctypes.c_uint32, Literal[1984]]
|
|
struct__cl2080_tag0.register_fields([('Reserved00', c.Array[NvV32, Literal[1984]], 0)])
|
|
@c.record
|
|
class volatile_struct__cl2080_tag0(c.Struct):
|
|
SIZE = 7936
|
|
Reserved00: c.Array[ctypes.c_uint32, Literal[1984]]
|
|
Nv2080Typedef: TypeAlias = volatile_struct__cl2080_tag0
|
|
volatile_struct__cl2080_tag0.register_fields([('Reserved00', c.Array[NvV32, Literal[1984]], 0)])
|
|
Nv20Subdevice0: TypeAlias = volatile_struct__cl2080_tag0
|
|
@c.record
|
|
class struct_Nv2080HdcpStatusChangeNotificationRec(c.Struct):
|
|
SIZE = 8
|
|
displayId: int
|
|
hdcpStatusChangeNotif: int
|
|
struct_Nv2080HdcpStatusChangeNotificationRec.register_fields([('displayId', NvU32, 0), ('hdcpStatusChangeNotif', NvU32, 4)])
|
|
Nv2080HdcpStatusChangeNotification: TypeAlias = struct_Nv2080HdcpStatusChangeNotificationRec
|
|
@c.record
|
|
class struct_Nv2080PStateChangeNotificationRec(c.Struct):
|
|
SIZE = 12
|
|
timeStamp: struct_Nv2080PStateChangeNotificationRec_timeStamp
|
|
NewPstate: int
|
|
@c.record
|
|
class struct_Nv2080PStateChangeNotificationRec_timeStamp(c.Struct):
|
|
SIZE = 8
|
|
nanoseconds: c.Array[ctypes.c_uint32, Literal[2]]
|
|
struct_Nv2080PStateChangeNotificationRec_timeStamp.register_fields([('nanoseconds', c.Array[NvU32, Literal[2]], 0)])
|
|
struct_Nv2080PStateChangeNotificationRec.register_fields([('timeStamp', struct_Nv2080PStateChangeNotificationRec_timeStamp, 0), ('NewPstate', NvU32, 8)])
|
|
Nv2080PStateChangeNotification: TypeAlias = struct_Nv2080PStateChangeNotificationRec
|
|
@c.record
|
|
class struct_Nv2080ClocksChangeNotificationRec(c.Struct):
|
|
SIZE = 8
|
|
timeStamp: struct_Nv2080ClocksChangeNotificationRec_timeStamp
|
|
@c.record
|
|
class struct_Nv2080ClocksChangeNotificationRec_timeStamp(c.Struct):
|
|
SIZE = 8
|
|
nanoseconds: c.Array[ctypes.c_uint32, Literal[2]]
|
|
struct_Nv2080ClocksChangeNotificationRec_timeStamp.register_fields([('nanoseconds', c.Array[NvU32, Literal[2]], 0)])
|
|
struct_Nv2080ClocksChangeNotificationRec.register_fields([('timeStamp', struct_Nv2080ClocksChangeNotificationRec_timeStamp, 0)])
|
|
Nv2080ClocksChangeNotification: TypeAlias = struct_Nv2080ClocksChangeNotificationRec
|
|
@c.record
|
|
class struct_Nv2080WorkloadModulationChangeNotificationRec(c.Struct):
|
|
SIZE = 12
|
|
timeStamp: struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp
|
|
WorkloadModulationEnabled: int
|
|
@c.record
|
|
class struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp(c.Struct):
|
|
SIZE = 8
|
|
nanoseconds: c.Array[ctypes.c_uint32, Literal[2]]
|
|
struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp.register_fields([('nanoseconds', c.Array[NvU32, Literal[2]], 0)])
|
|
NvBool: TypeAlias = ctypes.c_ubyte
|
|
struct_Nv2080WorkloadModulationChangeNotificationRec.register_fields([('timeStamp', struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp, 0), ('WorkloadModulationEnabled', NvBool, 8)])
|
|
Nv2080WorkloadModulationChangeNotification: TypeAlias = struct_Nv2080WorkloadModulationChangeNotificationRec
|
|
@c.record
|
|
class Nv2080HotplugNotification(c.Struct):
|
|
SIZE = 8
|
|
plugDisplayMask: int
|
|
unplugDisplayMask: int
|
|
Nv2080HotplugNotification.register_fields([('plugDisplayMask', NvU32, 0), ('unplugDisplayMask', NvU32, 4)])
|
|
@c.record
|
|
class Nv2080PowerEventNotification(c.Struct):
|
|
SIZE = 8
|
|
bSwitchToAC: int
|
|
bGPUCapabilityChanged: int
|
|
displayMaskAffected: int
|
|
Nv2080PowerEventNotification.register_fields([('bSwitchToAC', NvBool, 0), ('bGPUCapabilityChanged', NvBool, 1), ('displayMaskAffected', NvU32, 4)])
|
|
@c.record
|
|
class struct_Nv2080DpIrqNotificationRec(c.Struct):
|
|
SIZE = 4
|
|
displayId: int
|
|
struct_Nv2080DpIrqNotificationRec.register_fields([('displayId', NvU32, 0)])
|
|
Nv2080DpIrqNotification: TypeAlias = struct_Nv2080DpIrqNotificationRec
|
|
@c.record
|
|
class struct_Nv2080DstateXusbPpcNotificationRec(c.Struct):
|
|
SIZE = 8
|
|
dstateXusb: int
|
|
dstatePpc: int
|
|
struct_Nv2080DstateXusbPpcNotificationRec.register_fields([('dstateXusb', NvU32, 0), ('dstatePpc', NvU32, 4)])
|
|
Nv2080DstateXusbPpcNotification: TypeAlias = struct_Nv2080DstateXusbPpcNotificationRec
|
|
@c.record
|
|
class struct_Nv2080XusbPpcConnectStateNotificationRec(c.Struct):
|
|
SIZE = 1
|
|
bConnected: int
|
|
struct_Nv2080XusbPpcConnectStateNotificationRec.register_fields([('bConnected', NvBool, 0)])
|
|
Nv2080XusbPpcConnectStateNotification: TypeAlias = struct_Nv2080XusbPpcConnectStateNotificationRec
|
|
@c.record
|
|
class struct_Nv2080ACPIEvent(c.Struct):
|
|
SIZE = 4
|
|
event: int
|
|
struct_Nv2080ACPIEvent.register_fields([('event', NvU32, 0)])
|
|
Nv2080ACPIEvent: TypeAlias = struct_Nv2080ACPIEvent
|
|
@c.record
|
|
class struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC(c.Struct):
|
|
SIZE = 4
|
|
currentZone: int
|
|
struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC.register_fields([('currentZone', NvU32, 0)])
|
|
NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC: TypeAlias = struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC
|
|
@c.record
|
|
class struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC(c.Struct):
|
|
SIZE = 4
|
|
currentZone: int
|
|
struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC.register_fields([('currentZone', NvU32, 0)])
|
|
NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC: TypeAlias = struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC
|
|
@c.record
|
|
class struct_Nv2080AudioHdcpRequestRec(c.Struct):
|
|
SIZE = 8
|
|
displayId: int
|
|
requestedState: int
|
|
struct_Nv2080AudioHdcpRequestRec.register_fields([('displayId', NvU32, 0), ('requestedState', NvU32, 4)])
|
|
Nv2080AudioHdcpRequest: TypeAlias = struct_Nv2080AudioHdcpRequestRec
|
|
@c.record
|
|
class struct_Nv2080GC5GpuReadyParams(c.Struct):
|
|
SIZE = 12
|
|
event: int
|
|
sciIntr0: int
|
|
sciIntr1: int
|
|
struct_Nv2080GC5GpuReadyParams.register_fields([('event', NvU32, 0), ('sciIntr0', NvU32, 4), ('sciIntr1', NvU32, 8)])
|
|
Nv2080GC5GpuReadyParams: TypeAlias = struct_Nv2080GC5GpuReadyParams
|
|
@c.record
|
|
class Nv2080PrivRegAccessFaultNotification(c.Struct):
|
|
SIZE = 4
|
|
errAddr: int
|
|
Nv2080PrivRegAccessFaultNotification.register_fields([('errAddr', NvU32, 0)])
|
|
@c.record
|
|
class struct_Nv2080DstateHdaCodecNotificationRec(c.Struct):
|
|
SIZE = 4
|
|
dstateHdaCodec: int
|
|
struct_Nv2080DstateHdaCodecNotificationRec.register_fields([('dstateHdaCodec', NvU32, 0)])
|
|
Nv2080DstateHdaCodecNotification: TypeAlias = struct_Nv2080DstateHdaCodecNotificationRec
|
|
@c.record
|
|
class struct_Nv2080HdmiFrlRequestNotificationRec(c.Struct):
|
|
SIZE = 4
|
|
displayId: int
|
|
struct_Nv2080HdmiFrlRequestNotificationRec.register_fields([('displayId', NvU32, 0)])
|
|
Nv2080HdmiFrlRequestNotification: TypeAlias = struct_Nv2080HdmiFrlRequestNotificationRec
|
|
@c.record
|
|
class struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS(c.Struct):
|
|
SIZE = 3
|
|
platformPowerModeIndex: int
|
|
platformPowerModeMask: int
|
|
eventReason: int
|
|
NvU8: TypeAlias = ctypes.c_ubyte
|
|
struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS.register_fields([('platformPowerModeIndex', NvU8, 0), ('platformPowerModeMask', NvU8, 1), ('eventReason', NvU8, 2)])
|
|
NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS: TypeAlias = struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS
|
|
@c.record
|
|
class struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE(c.Struct):
|
|
SIZE = 1
|
|
workloadType: int
|
|
struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE.register_fields([('workloadType', NvU8, 0)])
|
|
NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE: TypeAlias = struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE
|
|
@c.record
|
|
class Nv2080QosIntrNotification(c.Struct):
|
|
SIZE = 4
|
|
engineType: int
|
|
Nv2080QosIntrNotification.register_fields([('engineType', NvU32, 0)])
|
|
@c.record
|
|
class Nv2080EccDbeNotification(c.Struct):
|
|
SIZE = 8
|
|
physAddress: int
|
|
Nv2080EccDbeNotification.register_fields([('physAddress', NvU64, 0)])
|
|
@c.record
|
|
class Nv2080LpwrDifrPrefetchNotification(c.Struct):
|
|
SIZE = 4
|
|
l2CacheSize: int
|
|
Nv2080LpwrDifrPrefetchNotification.register_fields([('l2CacheSize', NvU32, 0)])
|
|
@c.record
|
|
class Nv2080NvlinkLnkChangeNotification(c.Struct):
|
|
SIZE = 8
|
|
GpuId: int
|
|
linkId: int
|
|
Nv2080NvlinkLnkChangeNotification.register_fields([('GpuId', NvU32, 0), ('linkId', NvU32, 4)])
|
|
@c.record
|
|
class struct_Nvc56fControl_struct(c.Struct):
|
|
SIZE = 512
|
|
Ignored00: c.Array[ctypes.c_uint32, Literal[16]]
|
|
Put: int
|
|
Get: int
|
|
Reference: int
|
|
PutHi: int
|
|
Ignored01: c.Array[ctypes.c_uint32, Literal[2]]
|
|
TopLevelGet: int
|
|
TopLevelGetHi: int
|
|
GetHi: int
|
|
Ignored02: c.Array[ctypes.c_uint32, Literal[7]]
|
|
Ignored03: int
|
|
Ignored04: c.Array[ctypes.c_uint32, Literal[1]]
|
|
GPGet: int
|
|
GPPut: int
|
|
Ignored05: c.Array[ctypes.c_uint32, Literal[92]]
|
|
struct_Nvc56fControl_struct.register_fields([('Ignored00', c.Array[NvU32, Literal[16]], 0), ('Put', NvU32, 64), ('Get', NvU32, 68), ('Reference', NvU32, 72), ('PutHi', NvU32, 76), ('Ignored01', c.Array[NvU32, Literal[2]], 80), ('TopLevelGet', NvU32, 88), ('TopLevelGetHi', NvU32, 92), ('GetHi', NvU32, 96), ('Ignored02', c.Array[NvU32, Literal[7]], 100), ('Ignored03', NvU32, 128), ('Ignored04', c.Array[NvU32, Literal[1]], 132), ('GPGet', NvU32, 136), ('GPPut', NvU32, 140), ('Ignored05', c.Array[NvU32, Literal[92]], 144)])
|
|
@c.record
|
|
class volatile_struct_Nvc56fControl_struct(c.Struct):
|
|
SIZE = 512
|
|
Ignored00: c.Array[ctypes.c_uint32, Literal[16]]
|
|
Put: int
|
|
Get: int
|
|
Reference: int
|
|
PutHi: int
|
|
Ignored01: c.Array[ctypes.c_uint32, Literal[2]]
|
|
TopLevelGet: int
|
|
TopLevelGetHi: int
|
|
GetHi: int
|
|
Ignored02: c.Array[ctypes.c_uint32, Literal[7]]
|
|
Ignored03: int
|
|
Ignored04: c.Array[ctypes.c_uint32, Literal[1]]
|
|
GPGet: int
|
|
GPPut: int
|
|
Ignored05: c.Array[ctypes.c_uint32, Literal[92]]
|
|
Nvc56fControl: TypeAlias = volatile_struct_Nvc56fControl_struct
|
|
volatile_struct_Nvc56fControl_struct.register_fields([('Ignored00', c.Array[NvU32, Literal[16]], 0), ('Put', NvU32, 64), ('Get', NvU32, 68), ('Reference', NvU32, 72), ('PutHi', NvU32, 76), ('Ignored01', c.Array[NvU32, Literal[2]], 80), ('TopLevelGet', NvU32, 88), ('TopLevelGetHi', NvU32, 92), ('GetHi', NvU32, 96), ('Ignored02', c.Array[NvU32, Literal[7]], 100), ('Ignored03', NvU32, 128), ('Ignored04', c.Array[NvU32, Literal[1]], 132), ('GPGet', NvU32, 136), ('GPPut', NvU32, 140), ('Ignored05', c.Array[NvU32, Literal[92]], 144)])
|
|
AmpereAControlGPFifo: TypeAlias = volatile_struct_Nvc56fControl_struct
|
|
@c.record
|
|
class struct_Nvc86fControl_struct(c.Struct):
|
|
SIZE = 512
|
|
Ignored00: c.Array[ctypes.c_uint32, Literal[16]]
|
|
Put: int
|
|
Get: int
|
|
Reference: int
|
|
PutHi: int
|
|
Ignored01: c.Array[ctypes.c_uint32, Literal[2]]
|
|
TopLevelGet: int
|
|
TopLevelGetHi: int
|
|
GetHi: int
|
|
Ignored02: c.Array[ctypes.c_uint32, Literal[7]]
|
|
Ignored03: int
|
|
Ignored04: c.Array[ctypes.c_uint32, Literal[1]]
|
|
GPGet: int
|
|
GPPut: int
|
|
Ignored05: c.Array[ctypes.c_uint32, Literal[92]]
|
|
struct_Nvc86fControl_struct.register_fields([('Ignored00', c.Array[NvU32, Literal[16]], 0), ('Put', NvU32, 64), ('Get', NvU32, 68), ('Reference', NvU32, 72), ('PutHi', NvU32, 76), ('Ignored01', c.Array[NvU32, Literal[2]], 80), ('TopLevelGet', NvU32, 88), ('TopLevelGetHi', NvU32, 92), ('GetHi', NvU32, 96), ('Ignored02', c.Array[NvU32, Literal[7]], 100), ('Ignored03', NvU32, 128), ('Ignored04', c.Array[NvU32, Literal[1]], 132), ('GPGet', NvU32, 136), ('GPPut', NvU32, 140), ('Ignored05', c.Array[NvU32, Literal[92]], 144)])
|
|
@c.record
|
|
class volatile_struct_Nvc86fControl_struct(c.Struct):
|
|
SIZE = 512
|
|
Ignored00: c.Array[ctypes.c_uint32, Literal[16]]
|
|
Put: int
|
|
Get: int
|
|
Reference: int
|
|
PutHi: int
|
|
Ignored01: c.Array[ctypes.c_uint32, Literal[2]]
|
|
TopLevelGet: int
|
|
TopLevelGetHi: int
|
|
GetHi: int
|
|
Ignored02: c.Array[ctypes.c_uint32, Literal[7]]
|
|
Ignored03: int
|
|
Ignored04: c.Array[ctypes.c_uint32, Literal[1]]
|
|
GPGet: int
|
|
GPPut: int
|
|
Ignored05: c.Array[ctypes.c_uint32, Literal[92]]
|
|
Nvc86fControl: TypeAlias = volatile_struct_Nvc86fControl_struct
|
|
volatile_struct_Nvc86fControl_struct.register_fields([('Ignored00', c.Array[NvU32, Literal[16]], 0), ('Put', NvU32, 64), ('Get', NvU32, 68), ('Reference', NvU32, 72), ('PutHi', NvU32, 76), ('Ignored01', c.Array[NvU32, Literal[2]], 80), ('TopLevelGet', NvU32, 88), ('TopLevelGetHi', NvU32, 92), ('GetHi', NvU32, 96), ('Ignored02', c.Array[NvU32, Literal[7]], 100), ('Ignored03', NvU32, 128), ('Ignored04', c.Array[NvU32, Literal[1]], 132), ('GPGet', NvU32, 136), ('GPPut', NvU32, 140), ('Ignored05', c.Array[NvU32, Literal[92]], 144)])
|
|
HopperAControlGPFifo: TypeAlias = volatile_struct_Nvc86fControl_struct
|
|
@c.record
|
|
class struct_Nvc96fControl_struct(c.Struct):
|
|
SIZE = 512
|
|
Ignored00: c.Array[ctypes.c_uint32, Literal[35]]
|
|
GPPut: int
|
|
Ignored01: c.Array[ctypes.c_uint32, Literal[92]]
|
|
struct_Nvc96fControl_struct.register_fields([('Ignored00', c.Array[NvU32, Literal[35]], 0), ('GPPut', NvU32, 140), ('Ignored01', c.Array[NvU32, Literal[92]], 144)])
|
|
@c.record
|
|
class volatile_struct_Nvc96fControl_struct(c.Struct):
|
|
SIZE = 512
|
|
Ignored00: c.Array[ctypes.c_uint32, Literal[35]]
|
|
GPPut: int
|
|
Ignored01: c.Array[ctypes.c_uint32, Literal[92]]
|
|
Nvc96fControl: TypeAlias = volatile_struct_Nvc96fControl_struct
|
|
volatile_struct_Nvc96fControl_struct.register_fields([('Ignored00', c.Array[NvU32, Literal[35]], 0), ('GPPut', NvU32, 140), ('Ignored01', c.Array[NvU32, Literal[92]], 144)])
|
|
BlackwellAControlGPFifo: TypeAlias = volatile_struct_Nvc96fControl_struct
|
|
@c.record
|
|
class struct_NV83DE_ALLOC_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
hDebuggerClient_Obsolete: int
|
|
hAppClient: int
|
|
hClass3dObject: int
|
|
struct_NV83DE_ALLOC_PARAMETERS.register_fields([('hDebuggerClient_Obsolete', NvHandle, 0), ('hAppClient', NvHandle, 4), ('hClass3dObject', NvHandle, 8)])
|
|
NV83DE_ALLOC_PARAMETERS: TypeAlias = struct_NV83DE_ALLOC_PARAMETERS
|
|
@c.record
|
|
class struct_NVB2CC_ALLOC_PARAMETERS(c.Struct):
|
|
SIZE = 8
|
|
hClientTarget: int
|
|
hContextTarget: int
|
|
struct_NVB2CC_ALLOC_PARAMETERS.register_fields([('hClientTarget', NvHandle, 0), ('hContextTarget', NvHandle, 4)])
|
|
NVB2CC_ALLOC_PARAMETERS: TypeAlias = struct_NVB2CC_ALLOC_PARAMETERS
|
|
@c.record
|
|
class UVM_RESERVE_VA_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
requestedBase: int
|
|
length: int
|
|
rmStatus: int
|
|
NV_STATUS: TypeAlias = ctypes.c_uint32
|
|
UVM_RESERVE_VA_PARAMS.register_fields([('requestedBase', NvU64, 0), ('length', NvU64, 8), ('rmStatus', NV_STATUS, 16)])
|
|
@c.record
|
|
class UVM_RELEASE_VA_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
requestedBase: int
|
|
length: int
|
|
rmStatus: int
|
|
UVM_RELEASE_VA_PARAMS.register_fields([('requestedBase', NvU64, 0), ('length', NvU64, 8), ('rmStatus', NV_STATUS, 16)])
|
|
@c.record
|
|
class UVM_REGION_COMMIT_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
requestedBase: int
|
|
length: int
|
|
streamId: int
|
|
gpuUuid: struct_nv_uuid
|
|
rmStatus: int
|
|
UvmStream: TypeAlias = ctypes.c_uint64
|
|
@c.record
|
|
class struct_nv_uuid(c.Struct):
|
|
SIZE = 16
|
|
uuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
NvProcessorUuid: TypeAlias = struct_nv_uuid
|
|
struct_nv_uuid.register_fields([('uuid', c.Array[NvU8, Literal[16]], 0)])
|
|
UVM_REGION_COMMIT_PARAMS.register_fields([('requestedBase', NvU64, 0), ('length', NvU64, 8), ('streamId', UvmStream, 16), ('gpuUuid', NvProcessorUuid, 24), ('rmStatus', NV_STATUS, 40)])
|
|
@c.record
|
|
class UVM_REGION_DECOMMIT_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
requestedBase: int
|
|
length: int
|
|
rmStatus: int
|
|
UVM_REGION_DECOMMIT_PARAMS.register_fields([('requestedBase', NvU64, 0), ('length', NvU64, 8), ('rmStatus', NV_STATUS, 16)])
|
|
@c.record
|
|
class UVM_REGION_SET_STREAM_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
requestedBase: int
|
|
length: int
|
|
newStreamId: int
|
|
gpuUuid: struct_nv_uuid
|
|
rmStatus: int
|
|
UVM_REGION_SET_STREAM_PARAMS.register_fields([('requestedBase', NvU64, 0), ('length', NvU64, 8), ('newStreamId', UvmStream, 16), ('gpuUuid', NvProcessorUuid, 24), ('rmStatus', NV_STATUS, 40)])
|
|
@c.record
|
|
class UVM_SET_STREAM_RUNNING_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
streamId: int
|
|
rmStatus: int
|
|
UVM_SET_STREAM_RUNNING_PARAMS.register_fields([('streamId', UvmStream, 0), ('rmStatus', NV_STATUS, 8)])
|
|
@c.record
|
|
class UVM_SET_STREAM_STOPPED_PARAMS(c.Struct):
|
|
SIZE = 272
|
|
streamIdArray: c.Array[ctypes.c_uint64, Literal[32]]
|
|
nStreams: int
|
|
rmStatus: int
|
|
UVM_SET_STREAM_STOPPED_PARAMS.register_fields([('streamIdArray', c.Array[UvmStream, Literal[32]], 0), ('nStreams', NvU64, 256), ('rmStatus', NV_STATUS, 264)])
|
|
@c.record
|
|
class UVM_ADD_SESSION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pidTarget: int
|
|
rmStatus: int
|
|
UVM_ADD_SESSION_PARAMS.register_fields([('pidTarget', NvU32, 0), ('rmStatus', NV_STATUS, 4)])
|
|
@c.record
|
|
class UVM_ENABLE_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 904
|
|
config: c.Array[UvmCounterConfig, Literal[32]]
|
|
count: int
|
|
rmStatus: int
|
|
@c.record
|
|
class UvmCounterConfig(c.Struct):
|
|
SIZE = 28
|
|
scope: int
|
|
name: int
|
|
gpuid: struct_nv_uuid
|
|
state: int
|
|
UvmCounterConfig.register_fields([('scope', NvU32, 0), ('name', NvU32, 4), ('gpuid', NvProcessorUuid, 8), ('state', NvU32, 24)])
|
|
UVM_ENABLE_COUNTERS_PARAMS.register_fields([('config', c.Array[UvmCounterConfig, Literal[32]], 0), ('count', NvU32, 896), ('rmStatus', NV_STATUS, 900)])
|
|
@c.record
|
|
class UVM_MAP_COUNTER_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
scope: int
|
|
counterName: int
|
|
gpuUuid: struct_nv_uuid
|
|
addr: ctypes.c_void_p
|
|
rmStatus: int
|
|
UVM_MAP_COUNTER_PARAMS.register_fields([('scope', NvU32, 0), ('counterName', NvU32, 4), ('gpuUuid', NvProcessorUuid, 8), ('addr', NvP64, 24), ('rmStatus', NV_STATUS, 32)])
|
|
@c.record
|
|
class UVM_CREATE_EVENT_QUEUE_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
eventQueueIndex: int
|
|
queueSize: int
|
|
notificationCount: int
|
|
notificationHandle: int
|
|
timeStampType: int
|
|
rmStatus: int
|
|
UVM_CREATE_EVENT_QUEUE_PARAMS.register_fields([('eventQueueIndex', NvU32, 0), ('queueSize', NvU64, 8), ('notificationCount', NvU64, 16), ('notificationHandle', NvU64, 24), ('timeStampType', NvU32, 32), ('rmStatus', NV_STATUS, 36)])
|
|
@c.record
|
|
class UVM_REMOVE_EVENT_QUEUE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
eventQueueIndex: int
|
|
rmStatus: int
|
|
UVM_REMOVE_EVENT_QUEUE_PARAMS.register_fields([('eventQueueIndex', NvU32, 0), ('rmStatus', NV_STATUS, 4)])
|
|
@c.record
|
|
class UVM_MAP_EVENT_QUEUE_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
eventQueueIndex: int
|
|
userRODataAddr: ctypes.c_void_p
|
|
userRWDataAddr: ctypes.c_void_p
|
|
readIndexAddr: ctypes.c_void_p
|
|
writeIndexAddr: ctypes.c_void_p
|
|
queueBufferAddr: ctypes.c_void_p
|
|
rmStatus: int
|
|
UVM_MAP_EVENT_QUEUE_PARAMS.register_fields([('eventQueueIndex', NvU32, 0), ('userRODataAddr', NvP64, 8), ('userRWDataAddr', NvP64, 16), ('readIndexAddr', NvP64, 24), ('writeIndexAddr', NvP64, 32), ('queueBufferAddr', NvP64, 40), ('rmStatus', NV_STATUS, 48)])
|
|
@c.record
|
|
class UVM_EVENT_CTRL_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
eventQueueIndex: int
|
|
eventType: int
|
|
enable: int
|
|
rmStatus: int
|
|
NvS32: TypeAlias = ctypes.c_int32
|
|
UVM_EVENT_CTRL_PARAMS.register_fields([('eventQueueIndex', NvU32, 0), ('eventType', NvS32, 4), ('enable', NvU32, 8), ('rmStatus', NV_STATUS, 12)])
|
|
@c.record
|
|
class UVM_GET_GPU_UUID_TABLE_PARAMS(c.Struct):
|
|
SIZE = 520
|
|
gpuUuidArray: c.Array[struct_nv_uuid, Literal[32]]
|
|
validCount: int
|
|
rmStatus: int
|
|
UVM_GET_GPU_UUID_TABLE_PARAMS.register_fields([('gpuUuidArray', c.Array[NvProcessorUuid, Literal[32]], 0), ('validCount', NvU32, 512), ('rmStatus', NV_STATUS, 516)])
|
|
@c.record
|
|
class UVM_REGISTER_GPU_VASPACE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
gpuUuid: struct_nv_uuid
|
|
rmCtrlFd: int
|
|
hClient: int
|
|
hVaSpace: int
|
|
rmStatus: int
|
|
UVM_REGISTER_GPU_VASPACE_PARAMS.register_fields([('gpuUuid', NvProcessorUuid, 0), ('rmCtrlFd', NvS32, 16), ('hClient', NvHandle, 20), ('hVaSpace', NvHandle, 24), ('rmStatus', NV_STATUS, 28)])
|
|
@c.record
|
|
class UVM_UNREGISTER_GPU_VASPACE_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
gpuUuid: struct_nv_uuid
|
|
rmStatus: int
|
|
UVM_UNREGISTER_GPU_VASPACE_PARAMS.register_fields([('gpuUuid', NvProcessorUuid, 0), ('rmStatus', NV_STATUS, 16)])
|
|
@c.record
|
|
class UVM_REGISTER_CHANNEL_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
gpuUuid: struct_nv_uuid
|
|
rmCtrlFd: int
|
|
hClient: int
|
|
hChannel: int
|
|
base: int
|
|
length: int
|
|
rmStatus: int
|
|
UVM_REGISTER_CHANNEL_PARAMS.register_fields([('gpuUuid', NvProcessorUuid, 0), ('rmCtrlFd', NvS32, 16), ('hClient', NvHandle, 20), ('hChannel', NvHandle, 24), ('base', NvU64, 32), ('length', NvU64, 40), ('rmStatus', NV_STATUS, 48)])
|
|
@c.record
|
|
class UVM_UNREGISTER_CHANNEL_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hClient: int
|
|
hChannel: int
|
|
rmStatus: int
|
|
UVM_UNREGISTER_CHANNEL_PARAMS.register_fields([('hClient', NvHandle, 0), ('hChannel', NvHandle, 4), ('rmStatus', NV_STATUS, 8)])
|
|
@c.record
|
|
class UVM_ENABLE_PEER_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 36
|
|
gpuUuidA: struct_nv_uuid
|
|
gpuUuidB: struct_nv_uuid
|
|
rmStatus: int
|
|
UVM_ENABLE_PEER_ACCESS_PARAMS.register_fields([('gpuUuidA', NvProcessorUuid, 0), ('gpuUuidB', NvProcessorUuid, 16), ('rmStatus', NV_STATUS, 32)])
|
|
@c.record
|
|
class UVM_DISABLE_PEER_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 36
|
|
gpuUuidA: struct_nv_uuid
|
|
gpuUuidB: struct_nv_uuid
|
|
rmStatus: int
|
|
UVM_DISABLE_PEER_ACCESS_PARAMS.register_fields([('gpuUuidA', NvProcessorUuid, 0), ('gpuUuidB', NvProcessorUuid, 16), ('rmStatus', NV_STATUS, 32)])
|
|
@c.record
|
|
class UVM_MAP_EXTERNAL_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 9264
|
|
base: int
|
|
length: int
|
|
offset: int
|
|
perGpuAttributes: c.Array[UvmGpuMappingAttributes, Literal[256]]
|
|
gpuAttributesCount: int
|
|
rmCtrlFd: int
|
|
hClient: int
|
|
hMemory: int
|
|
rmStatus: int
|
|
@c.record
|
|
class UvmGpuMappingAttributes(c.Struct):
|
|
SIZE = 36
|
|
gpuUuid: struct_nv_uuid
|
|
gpuMappingType: int
|
|
gpuCachingType: int
|
|
gpuFormatType: int
|
|
gpuElementBits: int
|
|
gpuCompressionType: int
|
|
UvmGpuMappingAttributes.register_fields([('gpuUuid', NvProcessorUuid, 0), ('gpuMappingType', NvU32, 16), ('gpuCachingType', NvU32, 20), ('gpuFormatType', NvU32, 24), ('gpuElementBits', NvU32, 28), ('gpuCompressionType', NvU32, 32)])
|
|
UVM_MAP_EXTERNAL_ALLOCATION_PARAMS.register_fields([('base', NvU64, 0), ('length', NvU64, 8), ('offset', NvU64, 16), ('perGpuAttributes', c.Array[UvmGpuMappingAttributes, Literal[256]], 24), ('gpuAttributesCount', NvU64, 9240), ('rmCtrlFd', NvS32, 9248), ('hClient', NvU32, 9252), ('hMemory', NvU32, 9256), ('rmStatus', NV_STATUS, 9260)])
|
|
@c.record
|
|
class UVM_FREE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
base: int
|
|
rmStatus: int
|
|
UVM_FREE_PARAMS.register_fields([('base', NvU64, 0), ('rmStatus', NV_STATUS, 8)])
|
|
@c.record
|
|
class UVM_MEM_MAP_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
regionBase: ctypes.c_void_p
|
|
regionLength: int
|
|
rmStatus: int
|
|
UVM_MEM_MAP_PARAMS.register_fields([('regionBase', NvP64, 0), ('regionLength', NvU64, 8), ('rmStatus', NV_STATUS, 16)])
|
|
@c.record
|
|
class UVM_REGISTER_GPU_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
gpu_uuid: struct_nv_uuid
|
|
numaEnabled: int
|
|
numaNodeId: int
|
|
rmCtrlFd: int
|
|
hClient: int
|
|
hSmcPartRef: int
|
|
rmStatus: int
|
|
UVM_REGISTER_GPU_PARAMS.register_fields([('gpu_uuid', NvProcessorUuid, 0), ('numaEnabled', NvBool, 16), ('numaNodeId', NvS32, 20), ('rmCtrlFd', NvS32, 24), ('hClient', NvHandle, 28), ('hSmcPartRef', NvHandle, 32), ('rmStatus', NV_STATUS, 36)])
|
|
@c.record
|
|
class UVM_UNREGISTER_GPU_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
gpu_uuid: struct_nv_uuid
|
|
rmStatus: int
|
|
UVM_UNREGISTER_GPU_PARAMS.register_fields([('gpu_uuid', NvProcessorUuid, 0), ('rmStatus', NV_STATUS, 16)])
|
|
@c.record
|
|
class UVM_PAGEABLE_MEM_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pageableMemAccess: int
|
|
rmStatus: int
|
|
UVM_PAGEABLE_MEM_ACCESS_PARAMS.register_fields([('pageableMemAccess', NvBool, 0), ('rmStatus', NV_STATUS, 4)])
|
|
@c.record
|
|
class UVM_SET_PREFERRED_LOCATION_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
requestedBase: int
|
|
length: int
|
|
preferredLocation: struct_nv_uuid
|
|
preferredCpuNumaNode: int
|
|
rmStatus: int
|
|
UVM_SET_PREFERRED_LOCATION_PARAMS.register_fields([('requestedBase', NvU64, 0), ('length', NvU64, 8), ('preferredLocation', NvProcessorUuid, 16), ('preferredCpuNumaNode', NvS32, 32), ('rmStatus', NV_STATUS, 36)])
|
|
@c.record
|
|
class UVM_UNSET_PREFERRED_LOCATION_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
requestedBase: int
|
|
length: int
|
|
rmStatus: int
|
|
UVM_UNSET_PREFERRED_LOCATION_PARAMS.register_fields([('requestedBase', NvU64, 0), ('length', NvU64, 8), ('rmStatus', NV_STATUS, 16)])
|
|
@c.record
|
|
class UVM_ENABLE_READ_DUPLICATION_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
requestedBase: int
|
|
length: int
|
|
rmStatus: int
|
|
UVM_ENABLE_READ_DUPLICATION_PARAMS.register_fields([('requestedBase', NvU64, 0), ('length', NvU64, 8), ('rmStatus', NV_STATUS, 16)])
|
|
@c.record
|
|
class UVM_DISABLE_READ_DUPLICATION_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
requestedBase: int
|
|
length: int
|
|
rmStatus: int
|
|
UVM_DISABLE_READ_DUPLICATION_PARAMS.register_fields([('requestedBase', NvU64, 0), ('length', NvU64, 8), ('rmStatus', NV_STATUS, 16)])
|
|
@c.record
|
|
class UVM_SET_ACCESSED_BY_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
requestedBase: int
|
|
length: int
|
|
accessedByUuid: struct_nv_uuid
|
|
rmStatus: int
|
|
UVM_SET_ACCESSED_BY_PARAMS.register_fields([('requestedBase', NvU64, 0), ('length', NvU64, 8), ('accessedByUuid', NvProcessorUuid, 16), ('rmStatus', NV_STATUS, 32)])
|
|
@c.record
|
|
class UVM_UNSET_ACCESSED_BY_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
requestedBase: int
|
|
length: int
|
|
accessedByUuid: struct_nv_uuid
|
|
rmStatus: int
|
|
UVM_UNSET_ACCESSED_BY_PARAMS.register_fields([('requestedBase', NvU64, 0), ('length', NvU64, 8), ('accessedByUuid', NvProcessorUuid, 16), ('rmStatus', NV_STATUS, 32)])
|
|
@c.record
|
|
class UVM_MIGRATE_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
base: int
|
|
length: int
|
|
destinationUuid: struct_nv_uuid
|
|
flags: int
|
|
semaphoreAddress: int
|
|
semaphorePayload: int
|
|
cpuNumaNode: int
|
|
userSpaceStart: int
|
|
userSpaceLength: int
|
|
rmStatus: int
|
|
UVM_MIGRATE_PARAMS.register_fields([('base', NvU64, 0), ('length', NvU64, 8), ('destinationUuid', NvProcessorUuid, 16), ('flags', NvU32, 32), ('semaphoreAddress', NvU64, 40), ('semaphorePayload', NvU32, 48), ('cpuNumaNode', NvS32, 52), ('userSpaceStart', NvU64, 56), ('userSpaceLength', NvU64, 64), ('rmStatus', NV_STATUS, 72)])
|
|
@c.record
|
|
class UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
queueBuffer: int
|
|
queueBufferSize: int
|
|
controlBuffer: int
|
|
processor: struct_nv_uuid
|
|
allProcessors: int
|
|
uvmFd: int
|
|
rmStatus: int
|
|
UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS.register_fields([('queueBuffer', NvU64, 0), ('queueBufferSize', NvU64, 8), ('controlBuffer', NvU64, 16), ('processor', NvProcessorUuid, 24), ('allProcessors', NvU32, 40), ('uvmFd', NvU32, 44), ('rmStatus', NV_STATUS, 48)])
|
|
@c.record
|
|
class UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
notificationThreshold: int
|
|
rmStatus: int
|
|
UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS.register_fields([('notificationThreshold', NvU32, 0), ('rmStatus', NV_STATUS, 4)])
|
|
@c.record
|
|
class UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
eventTypeFlags: int
|
|
rmStatus: int
|
|
UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS.register_fields([('eventTypeFlags', NvU64, 0), ('rmStatus', NV_STATUS, 8)])
|
|
@c.record
|
|
class UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
eventTypeFlags: int
|
|
rmStatus: int
|
|
UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS.register_fields([('eventTypeFlags', NvU64, 0), ('rmStatus', NV_STATUS, 8)])
|
|
@c.record
|
|
class UVM_TOOLS_ENABLE_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
counterTypeFlags: int
|
|
rmStatus: int
|
|
UVM_TOOLS_ENABLE_COUNTERS_PARAMS.register_fields([('counterTypeFlags', NvU64, 0), ('rmStatus', NV_STATUS, 8)])
|
|
@c.record
|
|
class UVM_TOOLS_DISABLE_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
counterTypeFlags: int
|
|
rmStatus: int
|
|
UVM_TOOLS_DISABLE_COUNTERS_PARAMS.register_fields([('counterTypeFlags', NvU64, 0), ('rmStatus', NV_STATUS, 8)])
|
|
@c.record
|
|
class UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
buffer: int
|
|
size: int
|
|
targetVa: int
|
|
bytesRead: int
|
|
rmStatus: int
|
|
UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS.register_fields([('buffer', NvU64, 0), ('size', NvU64, 8), ('targetVa', NvU64, 16), ('bytesRead', NvU64, 24), ('rmStatus', NV_STATUS, 32)])
|
|
@c.record
|
|
class UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
buffer: int
|
|
size: int
|
|
targetVa: int
|
|
bytesWritten: int
|
|
rmStatus: int
|
|
UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS.register_fields([('buffer', NvU64, 0), ('size', NvU64, 8), ('targetVa', NvU64, 16), ('bytesWritten', NvU64, 24), ('rmStatus', NV_STATUS, 32)])
|
|
@c.record
|
|
class UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
tablePtr: int
|
|
rmStatus: int
|
|
UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS.register_fields([('tablePtr', NvU64, 0), ('rmStatus', NV_STATUS, 8)])
|
|
@c.record
|
|
class UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
base: int
|
|
length: int
|
|
gpuUuid: struct_nv_uuid
|
|
rmStatus: int
|
|
UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS.register_fields([('base', NvU64, 0), ('length', NvU64, 8), ('gpuUuid', NvProcessorUuid, 16), ('rmStatus', NV_STATUS, 32)])
|
|
@c.record
|
|
class UVM_UNMAP_EXTERNAL_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
base: int
|
|
length: int
|
|
gpuUuid: struct_nv_uuid
|
|
rmStatus: int
|
|
UVM_UNMAP_EXTERNAL_PARAMS.register_fields([('base', NvU64, 0), ('length', NvU64, 8), ('gpuUuid', NvProcessorUuid, 16), ('rmStatus', NV_STATUS, 32)])
|
|
@c.record
|
|
class UVM_TOOLS_FLUSH_EVENTS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rmStatus: int
|
|
UVM_TOOLS_FLUSH_EVENTS_PARAMS.register_fields([('rmStatus', NV_STATUS, 0)])
|
|
@c.record
|
|
class UVM_ALLOC_SEMAPHORE_POOL_PARAMS(c.Struct):
|
|
SIZE = 9248
|
|
base: int
|
|
length: int
|
|
perGpuAttributes: c.Array[UvmGpuMappingAttributes, Literal[256]]
|
|
gpuAttributesCount: int
|
|
rmStatus: int
|
|
UVM_ALLOC_SEMAPHORE_POOL_PARAMS.register_fields([('base', NvU64, 0), ('length', NvU64, 8), ('perGpuAttributes', c.Array[UvmGpuMappingAttributes, Literal[256]], 16), ('gpuAttributesCount', NvU64, 9232), ('rmStatus', NV_STATUS, 9240)])
|
|
@c.record
|
|
class UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rmStatus: int
|
|
UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS.register_fields([('rmStatus', NV_STATUS, 0)])
|
|
@c.record
|
|
class UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
gpu_uuid: struct_nv_uuid
|
|
pageableMemAccess: int
|
|
rmStatus: int
|
|
UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS.register_fields([('gpu_uuid', NvProcessorUuid, 0), ('pageableMemAccess', NvBool, 16), ('rmStatus', NV_STATUS, 20)])
|
|
@c.record
|
|
class UVM_POPULATE_PAGEABLE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: int
|
|
length: int
|
|
flags: int
|
|
rmStatus: int
|
|
UVM_POPULATE_PAGEABLE_PARAMS.register_fields([('base', NvU64, 0), ('length', NvU64, 8), ('flags', NvU32, 16), ('rmStatus', NV_STATUS, 20)])
|
|
@c.record
|
|
class UVM_VALIDATE_VA_RANGE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: int
|
|
length: int
|
|
rmStatus: int
|
|
UVM_VALIDATE_VA_RANGE_PARAMS.register_fields([('base', NvU64, 0), ('length', NvU64, 8), ('rmStatus', NV_STATUS, 16)])
|
|
@c.record
|
|
class UVM_CREATE_EXTERNAL_RANGE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: int
|
|
length: int
|
|
rmStatus: int
|
|
UVM_CREATE_EXTERNAL_RANGE_PARAMS.register_fields([('base', NvU64, 0), ('length', NvU64, 8), ('rmStatus', NV_STATUS, 16)])
|
|
@c.record
|
|
class UVM_MAP_EXTERNAL_SPARSE_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
base: int
|
|
length: int
|
|
gpuUuid: struct_nv_uuid
|
|
rmStatus: int
|
|
UVM_MAP_EXTERNAL_SPARSE_PARAMS.register_fields([('base', NvU64, 0), ('length', NvU64, 8), ('gpuUuid', NvProcessorUuid, 16), ('rmStatus', NV_STATUS, 32)])
|
|
@c.record
|
|
class UVM_MM_INITIALIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
uvmFd: int
|
|
rmStatus: int
|
|
UVM_MM_INITIALIZE_PARAMS.register_fields([('uvmFd', NvS32, 0), ('rmStatus', NV_STATUS, 4)])
|
|
UVM_TOOLS_INIT_EVENT_TRACKER_V2_PARAMS: TypeAlias = UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS
|
|
UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2_PARAMS: TypeAlias = UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS
|
|
@c.record
|
|
class UVM_ALLOC_DEVICE_P2P_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
base: int
|
|
length: int
|
|
offset: int
|
|
gpuUuid: struct_nv_uuid
|
|
rmCtrlFd: int
|
|
hClient: int
|
|
hMemory: int
|
|
rmStatus: int
|
|
UVM_ALLOC_DEVICE_P2P_PARAMS.register_fields([('base', NvU64, 0), ('length', NvU64, 8), ('offset', NvU64, 16), ('gpuUuid', NvProcessorUuid, 24), ('rmCtrlFd', NvS32, 40), ('hClient', NvU32, 44), ('hMemory', NvU32, 48), ('rmStatus', NV_STATUS, 52)])
|
|
@c.record
|
|
class UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rmStatus: int
|
|
UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS.register_fields([('rmStatus', NV_STATUS, 0)])
|
|
@c.record
|
|
class UVM_DISCARD_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
base: int
|
|
length: int
|
|
flags: int
|
|
rmStatus: int
|
|
UVM_DISCARD_PARAMS.register_fields([('base', NvU64, 0), ('length', NvU64, 8), ('flags', NvU64, 16), ('rmStatus', NV_STATUS, 24)])
|
|
@c.record
|
|
class UVM_QUERY_RESIDENCY_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
base: int
|
|
length: int
|
|
samplingStride: int
|
|
isManagedMemory: int
|
|
numSamples: int
|
|
pageAddresses: int
|
|
pageStatus: int
|
|
residency: struct_nv_uuid
|
|
resident_nid: int
|
|
rmStatus: int
|
|
UVM_QUERY_RESIDENCY_PARAMS.register_fields([('base', NvU64, 0), ('length', NvU64, 8), ('samplingStride', NvU64, 16), ('isManagedMemory', NvBool, 24), ('numSamples', NvU64, 32), ('pageAddresses', NvU64, 40), ('pageStatus', NvU64, 48), ('residency', NvProcessorUuid, 56), ('resident_nid', NvS32, 72), ('rmStatus', NV_STATUS, 76)])
|
|
@c.record
|
|
class UVM_IS_8_SUPPORTED_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
is8Supported: int
|
|
rmStatus: int
|
|
UVM_IS_8_SUPPORTED_PARAMS.register_fields([('is8Supported', NvU32, 0), ('rmStatus', NV_STATUS, 4)])
|
|
@c.record
|
|
class UVM_INITIALIZE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
flags: int
|
|
rmStatus: int
|
|
UVM_INITIALIZE_PARAMS.register_fields([('flags', NvU64, 0), ('rmStatus', NV_STATUS, 8)])
|
|
@c.record
|
|
class nv_pci_info_t(c.Struct):
|
|
SIZE = 12
|
|
domain: int
|
|
bus: int
|
|
slot: int
|
|
function: int
|
|
vendor_id: int
|
|
device_id: int
|
|
NvU16: TypeAlias = ctypes.c_uint16
|
|
nv_pci_info_t.register_fields([('domain', NvU32, 0), ('bus', NvU8, 4), ('slot', NvU8, 5), ('function', NvU8, 6), ('vendor_id', NvU16, 8), ('device_id', NvU16, 10)])
|
|
@c.record
|
|
class struct_nv_ioctl_xfer(c.Struct):
|
|
SIZE = 16
|
|
cmd: int
|
|
size: int
|
|
ptr: ctypes.c_void_p
|
|
struct_nv_ioctl_xfer.register_fields([('cmd', NvU32, 0), ('size', NvU32, 4), ('ptr', NvP64, 8)])
|
|
nv_ioctl_xfer_t: TypeAlias = struct_nv_ioctl_xfer
|
|
@c.record
|
|
class struct_nv_ioctl_card_info(c.Struct):
|
|
SIZE = 72
|
|
valid: int
|
|
pci_info: nv_pci_info_t
|
|
gpu_id: int
|
|
interrupt_line: int
|
|
reg_address: int
|
|
reg_size: int
|
|
fb_address: int
|
|
fb_size: int
|
|
minor_number: int
|
|
dev_name: c.Array[ctypes.c_ubyte, Literal[10]]
|
|
struct_nv_ioctl_card_info.register_fields([('valid', NvBool, 0), ('pci_info', nv_pci_info_t, 4), ('gpu_id', NvU32, 16), ('interrupt_line', NvU16, 20), ('reg_address', NvU64, 24), ('reg_size', NvU64, 32), ('fb_address', NvU64, 40), ('fb_size', NvU64, 48), ('minor_number', NvU32, 56), ('dev_name', c.Array[NvU8, Literal[10]], 60)])
|
|
nv_ioctl_card_info_t: TypeAlias = struct_nv_ioctl_card_info
|
|
@c.record
|
|
class struct_nv_ioctl_alloc_os_event(c.Struct):
|
|
SIZE = 16
|
|
hClient: int
|
|
hDevice: int
|
|
fd: int
|
|
Status: int
|
|
struct_nv_ioctl_alloc_os_event.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('fd', NvU32, 8), ('Status', NvU32, 12)])
|
|
nv_ioctl_alloc_os_event_t: TypeAlias = struct_nv_ioctl_alloc_os_event
|
|
@c.record
|
|
class struct_nv_ioctl_free_os_event(c.Struct):
|
|
SIZE = 16
|
|
hClient: int
|
|
hDevice: int
|
|
fd: int
|
|
Status: int
|
|
struct_nv_ioctl_free_os_event.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('fd', NvU32, 8), ('Status', NvU32, 12)])
|
|
nv_ioctl_free_os_event_t: TypeAlias = struct_nv_ioctl_free_os_event
|
|
@c.record
|
|
class struct_nv_ioctl_status_code(c.Struct):
|
|
SIZE = 12
|
|
domain: int
|
|
bus: int
|
|
slot: int
|
|
status: int
|
|
struct_nv_ioctl_status_code.register_fields([('domain', NvU32, 0), ('bus', NvU8, 4), ('slot', NvU8, 5), ('status', NvU32, 8)])
|
|
nv_ioctl_status_code_t: TypeAlias = struct_nv_ioctl_status_code
|
|
@c.record
|
|
class struct_nv_ioctl_rm_api_version(c.Struct):
|
|
SIZE = 72
|
|
cmd: int
|
|
reply: int
|
|
versionString: c.Array[ctypes.c_char, Literal[64]]
|
|
struct_nv_ioctl_rm_api_version.register_fields([('cmd', NvU32, 0), ('reply', NvU32, 4), ('versionString', c.Array[ctypes.c_char, Literal[64]], 8)])
|
|
nv_ioctl_rm_api_version_t: TypeAlias = struct_nv_ioctl_rm_api_version
|
|
@c.record
|
|
class struct_nv_ioctl_query_device_intr(c.Struct):
|
|
SIZE = 8
|
|
intrStatus: int
|
|
status: int
|
|
struct_nv_ioctl_query_device_intr.register_fields([('intrStatus', NvU32, 0), ('status', NvU32, 4)])
|
|
nv_ioctl_query_device_intr_t: TypeAlias = struct_nv_ioctl_query_device_intr
|
|
@c.record
|
|
class struct_nv_ioctl_sys_params(c.Struct):
|
|
SIZE = 8
|
|
memblock_size: int
|
|
struct_nv_ioctl_sys_params.register_fields([('memblock_size', NvU64, 0)])
|
|
nv_ioctl_sys_params_t: TypeAlias = struct_nv_ioctl_sys_params
|
|
@c.record
|
|
class struct_nv_ioctl_register_fd(c.Struct):
|
|
SIZE = 4
|
|
ctl_fd: int
|
|
struct_nv_ioctl_register_fd.register_fields([('ctl_fd', ctypes.c_int32, 0)])
|
|
nv_ioctl_register_fd_t: TypeAlias = struct_nv_ioctl_register_fd
|
|
@c.record
|
|
class struct_nv_ioctl_export_to_dma_buf_fd(c.Struct):
|
|
SIZE = 2608
|
|
fd: int
|
|
hClient: int
|
|
totalObjects: int
|
|
numObjects: int
|
|
index: int
|
|
totalSize: int
|
|
mappingType: int
|
|
bAllowMmap: int
|
|
handles: c.Array[ctypes.c_uint32, Literal[128]]
|
|
offsets: c.Array[ctypes.c_uint64, Literal[128]]
|
|
sizes: c.Array[ctypes.c_uint64, Literal[128]]
|
|
status: int
|
|
struct_nv_ioctl_export_to_dma_buf_fd.register_fields([('fd', ctypes.c_int32, 0), ('hClient', NvHandle, 4), ('totalObjects', NvU32, 8), ('numObjects', NvU32, 12), ('index', NvU32, 16), ('totalSize', NvU64, 24), ('mappingType', NvU8, 32), ('bAllowMmap', NvBool, 33), ('handles', c.Array[NvHandle, Literal[128]], 36), ('offsets', c.Array[NvU64, Literal[128]], 552), ('sizes', c.Array[NvU64, Literal[128]], 1576), ('status', NvU32, 2600)])
|
|
nv_ioctl_export_to_dma_buf_fd_t: TypeAlias = struct_nv_ioctl_export_to_dma_buf_fd
|
|
@c.record
|
|
class struct_nv_ioctl_wait_open_complete(c.Struct):
|
|
SIZE = 8
|
|
rc: int
|
|
adapterStatus: int
|
|
struct_nv_ioctl_wait_open_complete.register_fields([('rc', ctypes.c_int32, 0), ('adapterStatus', NvU32, 4)])
|
|
nv_ioctl_wait_open_complete_t: TypeAlias = struct_nv_ioctl_wait_open_complete
|
|
@c.record
|
|
class struct_offline_addresses(c.Struct):
|
|
SIZE = 520
|
|
addresses: c.Array[ctypes.c_uint64, Literal[64]]
|
|
numEntries: int
|
|
uint64_t: TypeAlias = ctypes.c_uint64
|
|
uint32_t: TypeAlias = ctypes.c_uint32
|
|
struct_offline_addresses.register_fields([('addresses', c.Array[uint64_t, Literal[64]], 0), ('numEntries', uint32_t, 512)])
|
|
nv_offline_addresses_t: TypeAlias = struct_offline_addresses
|
|
@c.record
|
|
class struct_nv_ioctl_numa_info(c.Struct):
|
|
SIZE = 560
|
|
nid: int
|
|
status: int
|
|
memblock_size: int
|
|
numa_mem_addr: int
|
|
numa_mem_size: int
|
|
use_auto_online: int
|
|
offline_addresses: struct_offline_addresses
|
|
int32_t: TypeAlias = ctypes.c_int32
|
|
uint8_t: TypeAlias = ctypes.c_ubyte
|
|
struct_nv_ioctl_numa_info.register_fields([('nid', int32_t, 0), ('status', int32_t, 4), ('memblock_size', uint64_t, 8), ('numa_mem_addr', uint64_t, 16), ('numa_mem_size', uint64_t, 24), ('use_auto_online', uint8_t, 32), ('offline_addresses', nv_offline_addresses_t, 40)])
|
|
nv_ioctl_numa_info_t: TypeAlias = struct_nv_ioctl_numa_info
|
|
@c.record
|
|
class struct_nv_ioctl_set_numa_status(c.Struct):
|
|
SIZE = 4
|
|
status: int
|
|
struct_nv_ioctl_set_numa_status.register_fields([('status', int32_t, 0)])
|
|
nv_ioctl_set_numa_status_t: TypeAlias = struct_nv_ioctl_set_numa_status
|
|
@c.record
|
|
class nv_ioctl_nvos02_parameters_with_fd(c.Struct):
|
|
SIZE = 56
|
|
params: NVOS02_PARAMETERS
|
|
fd: int
|
|
@c.record
|
|
class NVOS02_PARAMETERS(c.Struct):
|
|
SIZE = 48
|
|
hRoot: int
|
|
hObjectParent: int
|
|
hObjectNew: int
|
|
hClass: int
|
|
flags: int
|
|
pMemory: ctypes.c_void_p
|
|
limit: int
|
|
status: int
|
|
NVOS02_PARAMETERS.register_fields([('hRoot', NvHandle, 0), ('hObjectParent', NvHandle, 4), ('hObjectNew', NvHandle, 8), ('hClass', NvV32, 12), ('flags', NvV32, 16), ('pMemory', NvP64, 24), ('limit', NvU64, 32), ('status', NvV32, 40)])
|
|
nv_ioctl_nvos02_parameters_with_fd.register_fields([('params', NVOS02_PARAMETERS, 0), ('fd', ctypes.c_int32, 48)])
|
|
@c.record
|
|
class nv_ioctl_nvos33_parameters_with_fd(c.Struct):
|
|
SIZE = 56
|
|
params: NVOS33_PARAMETERS
|
|
fd: int
|
|
@c.record
|
|
class NVOS33_PARAMETERS(c.Struct):
|
|
SIZE = 48
|
|
hClient: int
|
|
hDevice: int
|
|
hMemory: int
|
|
offset: int
|
|
length: int
|
|
pLinearAddress: ctypes.c_void_p
|
|
status: int
|
|
flags: int
|
|
NVOS33_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('hMemory', NvHandle, 8), ('offset', NvU64, 16), ('length', NvU64, 24), ('pLinearAddress', NvP64, 32), ('status', NvU32, 40), ('flags', NvU32, 44)])
|
|
nv_ioctl_nvos33_parameters_with_fd.register_fields([('params', NVOS33_PARAMETERS, 0), ('fd', ctypes.c_int32, 48)])
|
|
@c.record
|
|
class struct_NV_MEMORY_DESC_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: int
|
|
size: int
|
|
addressSpace: int
|
|
cacheAttrib: int
|
|
struct_NV_MEMORY_DESC_PARAMS.register_fields([('base', NvU64, 0), ('size', NvU64, 8), ('addressSpace', NvU32, 16), ('cacheAttrib', NvU32, 20)])
|
|
NV_MEMORY_DESC_PARAMS: TypeAlias = struct_NV_MEMORY_DESC_PARAMS
|
|
@c.record
|
|
class struct_NV_CHANNEL_ALLOC_PARAMS(c.Struct):
|
|
SIZE = 376
|
|
hObjectError: int
|
|
hObjectBuffer: int
|
|
gpFifoOffset: int
|
|
gpFifoEntries: int
|
|
flags: int
|
|
hContextShare: int
|
|
hVASpace: int
|
|
hHandleVASpace: int
|
|
hUserdMemory: c.Array[ctypes.c_uint32, Literal[8]]
|
|
userdOffset: c.Array[ctypes.c_uint64, Literal[8]]
|
|
engineType: int
|
|
cid: int
|
|
subDeviceId: int
|
|
hObjectEccError: int
|
|
instanceMem: struct_NV_MEMORY_DESC_PARAMS
|
|
userdMem: struct_NV_MEMORY_DESC_PARAMS
|
|
ramfcMem: struct_NV_MEMORY_DESC_PARAMS
|
|
mthdbufMem: struct_NV_MEMORY_DESC_PARAMS
|
|
hPhysChannelGroup: int
|
|
internalFlags: int
|
|
errorNotifierMem: struct_NV_MEMORY_DESC_PARAMS
|
|
eccErrorNotifierMem: struct_NV_MEMORY_DESC_PARAMS
|
|
ProcessID: int
|
|
SubProcessID: int
|
|
encryptIv: c.Array[ctypes.c_uint32, Literal[3]]
|
|
decryptIv: c.Array[ctypes.c_uint32, Literal[3]]
|
|
hmacNonce: c.Array[ctypes.c_uint32, Literal[8]]
|
|
tpcConfigID: int
|
|
struct_NV_CHANNEL_ALLOC_PARAMS.register_fields([('hObjectError', NvHandle, 0), ('hObjectBuffer', NvHandle, 4), ('gpFifoOffset', NvU64, 8), ('gpFifoEntries', NvU32, 16), ('flags', NvU32, 20), ('hContextShare', NvHandle, 24), ('hVASpace', NvHandle, 28), ('hHandleVASpace', NvHandle, 32), ('hUserdMemory', c.Array[NvHandle, Literal[8]], 36), ('userdOffset', c.Array[NvU64, Literal[8]], 72), ('engineType', NvU32, 136), ('cid', NvU32, 140), ('subDeviceId', NvU32, 144), ('hObjectEccError', NvHandle, 148), ('instanceMem', NV_MEMORY_DESC_PARAMS, 152), ('userdMem', NV_MEMORY_DESC_PARAMS, 176), ('ramfcMem', NV_MEMORY_DESC_PARAMS, 200), ('mthdbufMem', NV_MEMORY_DESC_PARAMS, 224), ('hPhysChannelGroup', NvHandle, 248), ('internalFlags', NvU32, 252), ('errorNotifierMem', NV_MEMORY_DESC_PARAMS, 256), ('eccErrorNotifierMem', NV_MEMORY_DESC_PARAMS, 280), ('ProcessID', NvU32, 304), ('SubProcessID', NvU32, 308), ('encryptIv', c.Array[NvU32, Literal[3]], 312), ('decryptIv', c.Array[NvU32, Literal[3]], 324), ('hmacNonce', c.Array[NvU32, Literal[8]], 336), ('tpcConfigID', NvU32, 368)])
|
|
NV_CHANNEL_ALLOC_PARAMS: TypeAlias = struct_NV_CHANNEL_ALLOC_PARAMS
|
|
NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS: TypeAlias = struct_NV_CHANNEL_ALLOC_PARAMS
|
|
@c.record
|
|
class NVOS00_PARAMETERS(c.Struct):
|
|
SIZE = 16
|
|
hRoot: int
|
|
hObjectParent: int
|
|
hObjectOld: int
|
|
status: int
|
|
NVOS00_PARAMETERS.register_fields([('hRoot', NvHandle, 0), ('hObjectParent', NvHandle, 4), ('hObjectOld', NvHandle, 8), ('status', NvV32, 12)])
|
|
@c.record
|
|
class NVOS05_PARAMETERS(c.Struct):
|
|
SIZE = 20
|
|
hRoot: int
|
|
hObjectParent: int
|
|
hObjectNew: int
|
|
hClass: int
|
|
status: int
|
|
NVOS05_PARAMETERS.register_fields([('hRoot', NvHandle, 0), ('hObjectParent', NvHandle, 4), ('hObjectNew', NvHandle, 8), ('hClass', NvV32, 12), ('status', NvV32, 16)])
|
|
Callback1ArgVoidReturn: TypeAlias = c.CFUNCTYPE[None, [ctypes.c_void_p]]
|
|
Callback5ArgVoidReturn: TypeAlias = c.CFUNCTYPE[None, [ctypes.c_void_p, ctypes.c_void_p, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32]]
|
|
@c.record
|
|
class NVOS10_EVENT_KERNEL_CALLBACK(c.Struct):
|
|
SIZE = 16
|
|
func: c.CFUNCTYPE[None, [ctypes.c_void_p]]
|
|
arg: ctypes.c_void_p
|
|
NVOS10_EVENT_KERNEL_CALLBACK.register_fields([('func', Callback1ArgVoidReturn, 0), ('arg', ctypes.c_void_p, 8)])
|
|
@c.record
|
|
class NVOS10_EVENT_KERNEL_CALLBACK_EX(c.Struct):
|
|
SIZE = 16
|
|
func: c.CFUNCTYPE[None, [ctypes.c_void_p, ctypes.c_void_p, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32]]
|
|
arg: ctypes.c_void_p
|
|
NVOS10_EVENT_KERNEL_CALLBACK_EX.register_fields([('func', Callback5ArgVoidReturn, 0), ('arg', ctypes.c_void_p, 8)])
|
|
@c.record
|
|
class NVOS_I2C_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hClient: int
|
|
hDevice: int
|
|
paramSize: int
|
|
paramStructPtr: ctypes.c_void_p
|
|
status: int
|
|
NVOS_I2C_ACCESS_PARAMS.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('paramSize', NvU32, 8), ('paramStructPtr', NvP64, 16), ('status', NvV32, 24)])
|
|
@c.record
|
|
class NVOS21_PARAMETERS(c.Struct):
|
|
SIZE = 32
|
|
hRoot: int
|
|
hObjectParent: int
|
|
hObjectNew: int
|
|
hClass: int
|
|
pAllocParms: ctypes.c_void_p
|
|
paramsSize: int
|
|
status: int
|
|
NVOS21_PARAMETERS.register_fields([('hRoot', NvHandle, 0), ('hObjectParent', NvHandle, 4), ('hObjectNew', NvHandle, 8), ('hClass', NvV32, 12), ('pAllocParms', NvP64, 16), ('paramsSize', NvU32, 24), ('status', NvV32, 28)])
|
|
@c.record
|
|
class NVOS64_PARAMETERS(c.Struct):
|
|
SIZE = 48
|
|
hRoot: int
|
|
hObjectParent: int
|
|
hObjectNew: int
|
|
hClass: int
|
|
pAllocParms: ctypes.c_void_p
|
|
pRightsRequested: ctypes.c_void_p
|
|
paramsSize: int
|
|
flags: int
|
|
status: int
|
|
NVOS64_PARAMETERS.register_fields([('hRoot', NvHandle, 0), ('hObjectParent', NvHandle, 4), ('hObjectNew', NvHandle, 8), ('hClass', NvV32, 12), ('pAllocParms', NvP64, 16), ('pRightsRequested', NvP64, 24), ('paramsSize', NvU32, 32), ('flags', NvU32, 36), ('status', NvV32, 40)])
|
|
@c.record
|
|
class NVOS62_PARAMETERS(c.Struct):
|
|
SIZE = 24
|
|
hRoot: int
|
|
hObjectParent: int
|
|
hObjectNew: int
|
|
hClass: int
|
|
paramSize: int
|
|
status: int
|
|
NVOS62_PARAMETERS.register_fields([('hRoot', NvHandle, 0), ('hObjectParent', NvHandle, 4), ('hObjectNew', NvHandle, 8), ('hClass', NvV32, 12), ('paramSize', NvU32, 16), ('status', NvV32, 20)])
|
|
@c.record
|
|
class NVOS65_PARAMETERS(c.Struct):
|
|
SIZE = 32
|
|
hRoot: int
|
|
hObjectParent: int
|
|
hObjectNew: int
|
|
hClass: int
|
|
paramSize: int
|
|
versionMagic: int
|
|
maskSize: int
|
|
status: int
|
|
NVOS65_PARAMETERS.register_fields([('hRoot', NvHandle, 0), ('hObjectParent', NvHandle, 4), ('hObjectNew', NvHandle, 8), ('hClass', NvV32, 12), ('paramSize', NvU32, 16), ('versionMagic', NvU32, 20), ('maskSize', NvU32, 24), ('status', NvV32, 28)])
|
|
@c.record
|
|
class NVOS30_PARAMETERS(c.Struct):
|
|
SIZE = 56
|
|
hClient: int
|
|
hDevice: int
|
|
hChannel: int
|
|
numChannels: int
|
|
phClients: ctypes.c_void_p
|
|
phDevices: ctypes.c_void_p
|
|
phChannels: ctypes.c_void_p
|
|
flags: int
|
|
timeout: int
|
|
status: int
|
|
NVOS30_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('hChannel', NvHandle, 8), ('numChannels', NvV32, 12), ('phClients', NvP64, 16), ('phDevices', NvP64, 24), ('phChannels', NvP64, 32), ('flags', NvV32, 40), ('timeout', NvV32, 44), ('status', NvV32, 48)])
|
|
BindResultFunc: TypeAlias = c.CFUNCTYPE[None, [ctypes.c_void_p, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32]]
|
|
@c.record
|
|
class NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS(c.Struct):
|
|
SIZE = 16
|
|
sgt: ctypes.c_void_p
|
|
gem: ctypes.c_void_p
|
|
NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS.register_fields([('sgt', NvP64, 0), ('gem', NvP64, 8)])
|
|
@c.record
|
|
class NVOS32_PARAMETERS(c.Struct):
|
|
SIZE = 184
|
|
hRoot: int
|
|
hObjectParent: int
|
|
function: int
|
|
hVASpace: int
|
|
ivcHeapNumber: int
|
|
status: int
|
|
total: int
|
|
free: int
|
|
data: NVOS32_PARAMETERS_data
|
|
NvS16: TypeAlias = ctypes.c_int16
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data(c.Struct):
|
|
SIZE = 144
|
|
AllocSize: NVOS32_PARAMETERS_data_AllocSize
|
|
AllocTiledPitchHeight: NVOS32_PARAMETERS_data_AllocTiledPitchHeight
|
|
Free: NVOS32_PARAMETERS_data_Free
|
|
ReleaseCompr: NVOS32_PARAMETERS_data_ReleaseCompr
|
|
ReacquireCompr: NVOS32_PARAMETERS_data_ReacquireCompr
|
|
Info: NVOS32_PARAMETERS_data_Info
|
|
AllocSizeRange: NVOS32_PARAMETERS_data_AllocSizeRange
|
|
AllocHintAlignment: NVOS32_PARAMETERS_data_AllocHintAlignment
|
|
HwAlloc: NVOS32_PARAMETERS_data_HwAlloc
|
|
HwFree: NVOS32_PARAMETERS_data_HwFree
|
|
AllocOsDesc: NVOS32_PARAMETERS_data_AllocOsDesc
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_AllocSize(c.Struct):
|
|
SIZE = 120
|
|
owner: int
|
|
hMemory: int
|
|
type: int
|
|
flags: int
|
|
attr: int
|
|
format: int
|
|
comprCovg: int
|
|
zcullCovg: int
|
|
partitionStride: int
|
|
width: int
|
|
height: int
|
|
size: int
|
|
alignment: int
|
|
offset: int
|
|
limit: int
|
|
address: ctypes.c_void_p
|
|
rangeBegin: int
|
|
rangeEnd: int
|
|
attr2: int
|
|
ctagOffset: int
|
|
numaNode: int
|
|
NVOS32_PARAMETERS_data_AllocSize.register_fields([('owner', NvU32, 0), ('hMemory', NvHandle, 4), ('type', NvU32, 8), ('flags', NvU32, 12), ('attr', NvU32, 16), ('format', NvU32, 20), ('comprCovg', NvU32, 24), ('zcullCovg', NvU32, 28), ('partitionStride', NvU32, 32), ('width', NvU32, 36), ('height', NvU32, 40), ('size', NvU64, 48), ('alignment', NvU64, 56), ('offset', NvU64, 64), ('limit', NvU64, 72), ('address', NvP64, 80), ('rangeBegin', NvU64, 88), ('rangeEnd', NvU64, 96), ('attr2', NvU32, 104), ('ctagOffset', NvU32, 108), ('numaNode', NvS32, 112)])
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_AllocTiledPitchHeight(c.Struct):
|
|
SIZE = 120
|
|
owner: int
|
|
hMemory: int
|
|
type: int
|
|
flags: int
|
|
height: int
|
|
pitch: int
|
|
attr: int
|
|
width: int
|
|
format: int
|
|
comprCovg: int
|
|
zcullCovg: int
|
|
partitionStride: int
|
|
size: int
|
|
alignment: int
|
|
offset: int
|
|
limit: int
|
|
address: ctypes.c_void_p
|
|
rangeBegin: int
|
|
rangeEnd: int
|
|
attr2: int
|
|
ctagOffset: int
|
|
numaNode: int
|
|
NVOS32_PARAMETERS_data_AllocTiledPitchHeight.register_fields([('owner', NvU32, 0), ('hMemory', NvHandle, 4), ('type', NvU32, 8), ('flags', NvU32, 12), ('height', NvU32, 16), ('pitch', NvS32, 20), ('attr', NvU32, 24), ('width', NvU32, 28), ('format', NvU32, 32), ('comprCovg', NvU32, 36), ('zcullCovg', NvU32, 40), ('partitionStride', NvU32, 44), ('size', NvU64, 48), ('alignment', NvU64, 56), ('offset', NvU64, 64), ('limit', NvU64, 72), ('address', NvP64, 80), ('rangeBegin', NvU64, 88), ('rangeEnd', NvU64, 96), ('attr2', NvU32, 104), ('ctagOffset', NvU32, 108), ('numaNode', NvS32, 112)])
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_Free(c.Struct):
|
|
SIZE = 12
|
|
owner: int
|
|
hMemory: int
|
|
flags: int
|
|
NVOS32_PARAMETERS_data_Free.register_fields([('owner', NvU32, 0), ('hMemory', NvHandle, 4), ('flags', NvU32, 8)])
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_ReleaseCompr(c.Struct):
|
|
SIZE = 12
|
|
owner: int
|
|
flags: int
|
|
hMemory: int
|
|
NVOS32_PARAMETERS_data_ReleaseCompr.register_fields([('owner', NvU32, 0), ('flags', NvU32, 4), ('hMemory', NvHandle, 8)])
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_ReacquireCompr(c.Struct):
|
|
SIZE = 12
|
|
owner: int
|
|
flags: int
|
|
hMemory: int
|
|
NVOS32_PARAMETERS_data_ReacquireCompr.register_fields([('owner', NvU32, 0), ('flags', NvU32, 4), ('hMemory', NvHandle, 8)])
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_Info(c.Struct):
|
|
SIZE = 32
|
|
attr: int
|
|
offset: int
|
|
size: int
|
|
base: int
|
|
NVOS32_PARAMETERS_data_Info.register_fields([('attr', NvU32, 0), ('offset', NvU64, 8), ('size', NvU64, 16), ('base', NvU64, 24)])
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_AllocSizeRange(c.Struct):
|
|
SIZE = 112
|
|
owner: int
|
|
hMemory: int
|
|
type: int
|
|
flags: int
|
|
attr: int
|
|
format: int
|
|
comprCovg: int
|
|
zcullCovg: int
|
|
partitionStride: int
|
|
size: int
|
|
alignment: int
|
|
offset: int
|
|
limit: int
|
|
rangeBegin: int
|
|
rangeEnd: int
|
|
address: ctypes.c_void_p
|
|
attr2: int
|
|
ctagOffset: int
|
|
numaNode: int
|
|
NVOS32_PARAMETERS_data_AllocSizeRange.register_fields([('owner', NvU32, 0), ('hMemory', NvHandle, 4), ('type', NvU32, 8), ('flags', NvU32, 12), ('attr', NvU32, 16), ('format', NvU32, 20), ('comprCovg', NvU32, 24), ('zcullCovg', NvU32, 28), ('partitionStride', NvU32, 32), ('size', NvU64, 40), ('alignment', NvU64, 48), ('offset', NvU64, 56), ('limit', NvU64, 64), ('rangeBegin', NvU64, 72), ('rangeEnd', NvU64, 80), ('address', NvP64, 88), ('attr2', NvU32, 96), ('ctagOffset', NvU32, 100), ('numaNode', NvS32, 104)])
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_AllocHintAlignment(c.Struct):
|
|
SIZE = 56
|
|
alignType: int
|
|
alignAttr: int
|
|
alignInputFlags: int
|
|
alignSize: int
|
|
alignHeight: int
|
|
alignWidth: int
|
|
alignPitch: int
|
|
alignPad: int
|
|
alignMask: int
|
|
alignKind: int
|
|
alignAdjust: int
|
|
alignAttr2: int
|
|
NVOS32_PARAMETERS_data_AllocHintAlignment.register_fields([('alignType', NvU32, 0), ('alignAttr', NvU32, 4), ('alignInputFlags', NvU32, 8), ('alignSize', NvU64, 16), ('alignHeight', NvU32, 24), ('alignWidth', NvU32, 28), ('alignPitch', NvU32, 32), ('alignPad', NvU32, 36), ('alignMask', NvU32, 40), ('alignKind', NvU32, 44), ('alignAdjust', NvU32, 48), ('alignAttr2', NvU32, 52)])
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_HwAlloc(c.Struct):
|
|
SIZE = 144
|
|
allocOwner: int
|
|
allochMemory: int
|
|
flags: int
|
|
allocType: int
|
|
allocAttr: int
|
|
allocInputFlags: int
|
|
allocSize: int
|
|
allocHeight: int
|
|
allocWidth: int
|
|
allocPitch: int
|
|
allocMask: int
|
|
allocComprCovg: int
|
|
allocZcullCovg: int
|
|
bindResultFunc: ctypes.c_void_p
|
|
pHandle: ctypes.c_void_p
|
|
hResourceHandle: int
|
|
retAttr: int
|
|
kind: int
|
|
osDeviceHandle: int
|
|
allocAttr2: int
|
|
retAttr2: int
|
|
allocAddr: int
|
|
comprInfo: NVOS32_PARAMETERS_data_HwAlloc_comprInfo
|
|
uncompressedKind: int
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_HwAlloc_comprInfo(c.Struct):
|
|
SIZE = 24
|
|
compPageShift: int
|
|
compressedKind: int
|
|
compTagLineMin: int
|
|
compPageIndexLo: int
|
|
compPageIndexHi: int
|
|
compTagLineMultiplier: int
|
|
NVOS32_PARAMETERS_data_HwAlloc_comprInfo.register_fields([('compPageShift', NvU32, 0), ('compressedKind', NvU32, 4), ('compTagLineMin', NvU32, 8), ('compPageIndexLo', NvU32, 12), ('compPageIndexHi', NvU32, 16), ('compTagLineMultiplier', NvU32, 20)])
|
|
NVOS32_PARAMETERS_data_HwAlloc.register_fields([('allocOwner', NvU32, 0), ('allochMemory', NvHandle, 4), ('flags', NvU32, 8), ('allocType', NvU32, 12), ('allocAttr', NvU32, 16), ('allocInputFlags', NvU32, 20), ('allocSize', NvU64, 24), ('allocHeight', NvU32, 32), ('allocWidth', NvU32, 36), ('allocPitch', NvU32, 40), ('allocMask', NvU32, 44), ('allocComprCovg', NvU32, 48), ('allocZcullCovg', NvU32, 52), ('bindResultFunc', NvP64, 56), ('pHandle', NvP64, 64), ('hResourceHandle', NvHandle, 72), ('retAttr', NvU32, 76), ('kind', NvU32, 80), ('osDeviceHandle', NvU64, 88), ('allocAttr2', NvU32, 96), ('retAttr2', NvU32, 100), ('allocAddr', NvU64, 104), ('comprInfo', NVOS32_PARAMETERS_data_HwAlloc_comprInfo, 112), ('uncompressedKind', NvU32, 136)])
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_HwFree(c.Struct):
|
|
SIZE = 8
|
|
hResourceHandle: int
|
|
flags: int
|
|
NVOS32_PARAMETERS_data_HwFree.register_fields([('hResourceHandle', NvHandle, 0), ('flags', NvU32, 4)])
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_AllocOsDesc(c.Struct):
|
|
SIZE = 48
|
|
hMemory: int
|
|
type: int
|
|
flags: int
|
|
attr: int
|
|
attr2: int
|
|
descriptor: ctypes.c_void_p
|
|
limit: int
|
|
descriptorType: int
|
|
NVOS32_PARAMETERS_data_AllocOsDesc.register_fields([('hMemory', NvHandle, 0), ('type', NvU32, 4), ('flags', NvU32, 8), ('attr', NvU32, 12), ('attr2', NvU32, 16), ('descriptor', NvP64, 24), ('limit', NvU64, 32), ('descriptorType', NvU32, 40)])
|
|
NVOS32_PARAMETERS_data.register_fields([('AllocSize', NVOS32_PARAMETERS_data_AllocSize, 0), ('AllocTiledPitchHeight', NVOS32_PARAMETERS_data_AllocTiledPitchHeight, 0), ('Free', NVOS32_PARAMETERS_data_Free, 0), ('ReleaseCompr', NVOS32_PARAMETERS_data_ReleaseCompr, 0), ('ReacquireCompr', NVOS32_PARAMETERS_data_ReacquireCompr, 0), ('Info', NVOS32_PARAMETERS_data_Info, 0), ('AllocSizeRange', NVOS32_PARAMETERS_data_AllocSizeRange, 0), ('AllocHintAlignment', NVOS32_PARAMETERS_data_AllocHintAlignment, 0), ('HwAlloc', NVOS32_PARAMETERS_data_HwAlloc, 0), ('HwFree', NVOS32_PARAMETERS_data_HwFree, 0), ('AllocOsDesc', NVOS32_PARAMETERS_data_AllocOsDesc, 0)])
|
|
NVOS32_PARAMETERS.register_fields([('hRoot', NvHandle, 0), ('hObjectParent', NvHandle, 4), ('function', NvU32, 8), ('hVASpace', NvHandle, 12), ('ivcHeapNumber', NvS16, 16), ('status', NvV32, 20), ('total', NvU64, 24), ('free', NvU64, 32), ('data', NVOS32_PARAMETERS_data, 40)])
|
|
@c.record
|
|
class NV_CONTEXT_DMA_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hSubDevice: int
|
|
flags: int
|
|
hMemory: int
|
|
offset: int
|
|
limit: int
|
|
NV_CONTEXT_DMA_ALLOCATION_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('flags', NvV32, 4), ('hMemory', NvHandle, 8), ('offset', NvU64, 16), ('limit', NvU64, 24)])
|
|
@c.record
|
|
class NV_MEMORY_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 128
|
|
owner: int
|
|
type: int
|
|
flags: int
|
|
width: int
|
|
height: int
|
|
pitch: int
|
|
attr: int
|
|
attr2: int
|
|
format: int
|
|
comprCovg: int
|
|
zcullCovg: int
|
|
rangeLo: int
|
|
rangeHi: int
|
|
size: int
|
|
alignment: int
|
|
offset: int
|
|
limit: int
|
|
address: ctypes.c_void_p
|
|
ctagOffset: int
|
|
hVASpace: int
|
|
internalflags: int
|
|
tag: int
|
|
numaNode: int
|
|
NV_MEMORY_ALLOCATION_PARAMS.register_fields([('owner', NvU32, 0), ('type', NvU32, 4), ('flags', NvU32, 8), ('width', NvU32, 12), ('height', NvU32, 16), ('pitch', NvS32, 20), ('attr', NvU32, 24), ('attr2', NvU32, 28), ('format', NvU32, 32), ('comprCovg', NvU32, 36), ('zcullCovg', NvU32, 40), ('rangeLo', NvU64, 48), ('rangeHi', NvU64, 56), ('size', NvU64, 64), ('alignment', NvU64, 72), ('offset', NvU64, 80), ('limit', NvU64, 88), ('address', NvP64, 96), ('ctagOffset', NvU32, 104), ('hVASpace', NvHandle, 108), ('internalflags', NvU32, 112), ('tag', NvU32, 116), ('numaNode', NvS32, 120)])
|
|
@c.record
|
|
class NV_OS_DESC_MEMORY_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
type: int
|
|
flags: int
|
|
attr: int
|
|
attr2: int
|
|
descriptor: ctypes.c_void_p
|
|
limit: int
|
|
descriptorType: int
|
|
tag: int
|
|
NV_OS_DESC_MEMORY_ALLOCATION_PARAMS.register_fields([('type', NvU32, 0), ('flags', NvU32, 4), ('attr', NvU32, 8), ('attr2', NvU32, 12), ('descriptor', NvP64, 16), ('limit', NvU64, 24), ('descriptorType', NvU32, 32), ('tag', NvU32, 36)])
|
|
@c.record
|
|
class NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
flags: int
|
|
physAddr: int
|
|
size: int
|
|
tag: int
|
|
bGuestAllocated: int
|
|
NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS.register_fields([('flags', NvU32, 0), ('physAddr', NvU64, 8), ('size', NvU64, 16), ('tag', NvU32, 24), ('bGuestAllocated', NvBool, 28)])
|
|
@c.record
|
|
class NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 120
|
|
owner: int
|
|
flags: int
|
|
type: int
|
|
attr: int
|
|
attr2: int
|
|
height: int
|
|
width: int
|
|
pitch: int
|
|
alignment: int
|
|
comprCovg: int
|
|
zcullCovg: int
|
|
kind: int
|
|
bindResultFunc: ctypes.c_void_p
|
|
pHandle: ctypes.c_void_p
|
|
osDeviceHandle: int
|
|
size: int
|
|
allocAddr: int
|
|
compPageShift: int
|
|
compressedKind: int
|
|
compTagLineMin: int
|
|
compPageIndexLo: int
|
|
compPageIndexHi: int
|
|
compTagLineMultiplier: int
|
|
uncompressedKind: int
|
|
tag: int
|
|
NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS.register_fields([('owner', NvU32, 0), ('flags', NvU32, 4), ('type', NvU32, 8), ('attr', NvU32, 12), ('attr2', NvU32, 16), ('height', NvU32, 20), ('width', NvU32, 24), ('pitch', NvU32, 28), ('alignment', NvU32, 32), ('comprCovg', NvU32, 36), ('zcullCovg', NvU32, 40), ('kind', NvU32, 44), ('bindResultFunc', NvP64, 48), ('pHandle', NvP64, 56), ('osDeviceHandle', NvU64, 64), ('size', NvU64, 72), ('allocAddr', NvU64, 80), ('compPageShift', NvU32, 88), ('compressedKind', NvU32, 92), ('compTagLineMin', NvU32, 96), ('compPageIndexLo', NvU32, 100), ('compPageIndexHi', NvU32, 104), ('compTagLineMultiplier', NvU32, 108), ('uncompressedKind', NvU32, 112), ('tag', NvU32, 116)])
|
|
@c.record
|
|
class NVOS34_PARAMETERS(c.Struct):
|
|
SIZE = 32
|
|
hClient: int
|
|
hDevice: int
|
|
hMemory: int
|
|
pLinearAddress: ctypes.c_void_p
|
|
status: int
|
|
flags: int
|
|
NVOS34_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('hMemory', NvHandle, 8), ('pLinearAddress', NvP64, 16), ('status', NvU32, 24), ('flags', NvU32, 28)])
|
|
@c.record
|
|
class NVOS38_PARAMETERS(c.Struct):
|
|
SIZE = 72
|
|
hClient: int
|
|
hObject: int
|
|
AccessType: int
|
|
DevNodeLength: int
|
|
pDevNode: ctypes.c_void_p
|
|
ParmStrLength: int
|
|
pParmStr: ctypes.c_void_p
|
|
BinaryDataLength: int
|
|
pBinaryData: ctypes.c_void_p
|
|
Data: int
|
|
Entry: int
|
|
status: int
|
|
NVOS38_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hObject', NvHandle, 4), ('AccessType', NvV32, 8), ('DevNodeLength', NvV32, 12), ('pDevNode', NvP64, 16), ('ParmStrLength', NvV32, 24), ('pParmStr', NvP64, 32), ('BinaryDataLength', NvV32, 40), ('pBinaryData', NvP64, 48), ('Data', NvV32, 56), ('Entry', NvV32, 60), ('status', NvV32, 64)])
|
|
@c.record
|
|
class NVOS39_PARAMETERS(c.Struct):
|
|
SIZE = 56
|
|
hObjectParent: int
|
|
hSubDevice: int
|
|
hObjectNew: int
|
|
hClass: int
|
|
flags: int
|
|
selector: int
|
|
hMemory: int
|
|
offset: int
|
|
limit: int
|
|
status: int
|
|
NVOS39_PARAMETERS.register_fields([('hObjectParent', NvHandle, 0), ('hSubDevice', NvHandle, 4), ('hObjectNew', NvHandle, 8), ('hClass', NvV32, 12), ('flags', NvV32, 16), ('selector', NvU32, 20), ('hMemory', NvHandle, 24), ('offset', NvU64, 32), ('limit', NvU64, 40), ('status', NvV32, 48)])
|
|
@c.record
|
|
class NvUnixEvent(c.Struct):
|
|
SIZE = 16
|
|
hObject: int
|
|
NotifyIndex: int
|
|
info32: int
|
|
info16: int
|
|
NvUnixEvent.register_fields([('hObject', NvHandle, 0), ('NotifyIndex', NvV32, 4), ('info32', NvV32, 8), ('info16', NvU16, 12)])
|
|
@c.record
|
|
class NVOS41_PARAMETERS(c.Struct):
|
|
SIZE = 16
|
|
pEvent: ctypes.c_void_p
|
|
MoreEvents: int
|
|
status: int
|
|
NVOS41_PARAMETERS.register_fields([('pEvent', NvP64, 0), ('MoreEvents', NvV32, 8), ('status', NvV32, 12)])
|
|
@c.record
|
|
class NVOS2C_PARAMETERS(c.Struct):
|
|
SIZE = 32
|
|
hClient: int
|
|
hDevice: int
|
|
offset: int
|
|
bar: int
|
|
bytes: int
|
|
write: int
|
|
data: int
|
|
status: int
|
|
NVOS2C_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('offset', NvU32, 8), ('bar', NvU32, 12), ('bytes', NvU32, 16), ('write', NvU32, 20), ('data', NvU32, 24), ('status', NvU32, 28)])
|
|
@c.record
|
|
class NVOS46_PARAMETERS(c.Struct):
|
|
SIZE = 64
|
|
hClient: int
|
|
hDevice: int
|
|
hDma: int
|
|
hMemory: int
|
|
offset: int
|
|
length: int
|
|
flags: int
|
|
flags2: int
|
|
kindOverride: int
|
|
dmaOffset: int
|
|
status: int
|
|
NVOS46_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('hDma', NvHandle, 8), ('hMemory', NvHandle, 12), ('offset', NvU64, 16), ('length', NvU64, 24), ('flags', NvV32, 32), ('flags2', NvV32, 36), ('kindOverride', NvV32, 40), ('dmaOffset', NvU64, 48), ('status', NvV32, 56)])
|
|
NV_MAP_MEMORY_DMA_PARAMETERS: TypeAlias = NVOS46_PARAMETERS
|
|
@c.record
|
|
class NVOS47_PARAMETERS(c.Struct):
|
|
SIZE = 48
|
|
hClient: int
|
|
hDevice: int
|
|
hDma: int
|
|
hMemory: int
|
|
flags: int
|
|
dmaOffset: int
|
|
size: int
|
|
status: int
|
|
NVOS47_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('hDma', NvHandle, 8), ('hMemory', NvHandle, 12), ('flags', NvV32, 16), ('dmaOffset', NvU64, 24), ('size', NvU64, 32), ('status', NvV32, 40)])
|
|
NV_UNMAP_MEMORY_DMA_PARAMETERS: TypeAlias = NVOS47_PARAMETERS
|
|
@c.record
|
|
class NVOS49_PARAMETERS(c.Struct):
|
|
SIZE = 16
|
|
hClient: int
|
|
hChannel: int
|
|
hCtxDma: int
|
|
status: int
|
|
NVOS49_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hChannel', NvHandle, 4), ('hCtxDma', NvHandle, 8), ('status', NvV32, 12)])
|
|
@c.record
|
|
class NVOS54_PARAMETERS(c.Struct):
|
|
SIZE = 32
|
|
hClient: int
|
|
hObject: int
|
|
cmd: int
|
|
flags: int
|
|
params: ctypes.c_void_p
|
|
paramsSize: int
|
|
status: int
|
|
NVOS54_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hObject', NvHandle, 4), ('cmd', NvV32, 8), ('flags', NvU32, 12), ('params', NvP64, 16), ('paramsSize', NvU32, 24), ('status', NvV32, 28)])
|
|
@c.record
|
|
class NVOS63_PARAMETERS(c.Struct):
|
|
SIZE = 20
|
|
hClient: int
|
|
hObject: int
|
|
cmd: int
|
|
paramsSize: int
|
|
status: int
|
|
NVOS63_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hObject', NvHandle, 4), ('cmd', NvV32, 8), ('paramsSize', NvU32, 12), ('status', NvV32, 16)])
|
|
@c.record
|
|
class NVOS55_PARAMETERS(c.Struct):
|
|
SIZE = 28
|
|
hClient: int
|
|
hParent: int
|
|
hObject: int
|
|
hClientSrc: int
|
|
hObjectSrc: int
|
|
flags: int
|
|
status: int
|
|
NVOS55_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hParent', NvHandle, 4), ('hObject', NvHandle, 8), ('hClientSrc', NvHandle, 12), ('hObjectSrc', NvHandle, 16), ('flags', NvU32, 20), ('status', NvU32, 24)])
|
|
@c.record
|
|
class NVOS56_PARAMETERS(c.Struct):
|
|
SIZE = 40
|
|
hClient: int
|
|
hDevice: int
|
|
hMemory: int
|
|
pOldCpuAddress: ctypes.c_void_p
|
|
pNewCpuAddress: ctypes.c_void_p
|
|
status: int
|
|
NVOS56_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('hMemory', NvHandle, 8), ('pOldCpuAddress', NvP64, 16), ('pNewCpuAddress', NvP64, 24), ('status', NvV32, 32)])
|
|
@c.record
|
|
class NVOS57_PARAMETERS(c.Struct):
|
|
SIZE = 24
|
|
hClient: int
|
|
hObject: int
|
|
sharePolicy: struct_RS_SHARE_POLICY
|
|
status: int
|
|
@c.record
|
|
class struct_RS_SHARE_POLICY(c.Struct):
|
|
SIZE = 12
|
|
target: int
|
|
accessMask: struct_RS_ACCESS_MASK
|
|
type: int
|
|
action: int
|
|
RS_SHARE_POLICY: TypeAlias = struct_RS_SHARE_POLICY
|
|
@c.record
|
|
class struct_RS_ACCESS_MASK(c.Struct):
|
|
SIZE = 4
|
|
limbs: c.Array[ctypes.c_uint32, Literal[1]]
|
|
RS_ACCESS_MASK: TypeAlias = struct_RS_ACCESS_MASK
|
|
RsAccessLimb: TypeAlias = ctypes.c_uint32
|
|
struct_RS_ACCESS_MASK.register_fields([('limbs', c.Array[RsAccessLimb, Literal[1]], 0)])
|
|
struct_RS_SHARE_POLICY.register_fields([('target', NvU32, 0), ('accessMask', RS_ACCESS_MASK, 4), ('type', NvU16, 8), ('action', NvU8, 10)])
|
|
NVOS57_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hObject', NvHandle, 4), ('sharePolicy', RS_SHARE_POLICY, 8), ('status', NvU32, 20)])
|
|
NVPOWERSTATE_STAGE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_ENGINE_TRANSITION(c.Struct):
|
|
SIZE = 24
|
|
classId: int
|
|
cumulativeTimeus: int
|
|
engineMaxTimeus: int
|
|
engineMaxTimeClassId: int
|
|
NVPOWERSTATE_FAILURE_ENGINE_TRANSITION.register_fields([('classId', NvU32, 0), ('cumulativeTimeus', NvU64, 8), ('engineMaxTimeus', NvU32, 16), ('engineMaxTimeClassId', NvU32, 20)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_WAIT_FOR_GFW_BOOT_OK(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_WAIT_FOR_GFW_BOOT_OK.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_INIT_LIBOS_LOGGING_STRUCTURES(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_INIT_LIBOS_LOGGING_STRUCTURES.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_GSP_PREPARE_FOR_BOOTSTRAP(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_GSP_PREPARE_FOR_BOOTSTRAP.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_GSP_BOOTSTRAP(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_GSP_BOOTSTRAP.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_BOOT_GSP_RM_PROXY(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_BOOT_GSP_RM_PROXY.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_VBIOS_HANDLE_SECURE_BOOT(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_VBIOS_HANDLE_SECURE_BOOT.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_RESTORE_PCIE_CONFIG_REGISTERS(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_RESTORE_PCIE_CONFIG_REGISTERS.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_GCX_BOOT_TIMER_CB_SCHEDULE(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_GCX_BOOT_TIMER_CB_SCHEDULE.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_POWER_MANAGEMENT_RESUME_PRE_LOAD_PHYSICAL_UNATTACHED(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_POWER_MANAGEMENT_RESUME_PRE_LOAD_PHYSICAL_UNATTACHED.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_PMS_EXPECTED_CHECKPOINT_DONE(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_PMS_EXPECTED_CHECKPOINT_DONE.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_POLL_FOR_NVLINK_READY(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_POLL_FOR_NVLINK_READY.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_CE_STATE_PRE_LOAD(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_CE_STATE_PRE_LOAD.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_LOAD_PROXY_UCODE_EARLY_INIT(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_LOAD_PROXY_UCODE_EARLY_INIT.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_RESTORE_NON_WPR_REGION(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_RESTORE_NON_WPR_REGION.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_PMU_20_OS_BOOTSTRAP(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_PMU_20_OS_BOOTSTRAP.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_ENGINE(c.Struct):
|
|
SIZE = 24
|
|
engineTransition: NVPOWERSTATE_FAILURE_ENGINE_TRANSITION
|
|
NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_ENGINE.register_fields([('engineTransition', NVPOWERSTATE_FAILURE_ENGINE_TRANSITION, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_UNKNOWN(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_UNKNOWN.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_LOAD_ENGINE(c.Struct):
|
|
SIZE = 24
|
|
engineTransition: NVPOWERSTATE_FAILURE_ENGINE_TRANSITION
|
|
NVPOWERSTATE_FAILURE_STATE_LOAD_ENGINE.register_fields([('engineTransition', NVPOWERSTATE_FAILURE_ENGINE_TRANSITION, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_LOAD_UNKNOWN(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_STATE_LOAD_UNKNOWN.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_POST_LOAD_ENGINE(c.Struct):
|
|
SIZE = 24
|
|
engineTransition: NVPOWERSTATE_FAILURE_ENGINE_TRANSITION
|
|
NVPOWERSTATE_FAILURE_STATE_POST_LOAD_ENGINE.register_fields([('engineTransition', NVPOWERSTATE_FAILURE_ENGINE_TRANSITION, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_POST_LOAD_UNKNOWN(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_STATE_POST_LOAD_UNKNOWN.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_LOAD_PHYSICAL(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_STATE_LOAD_PHYSICAL.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_GSP_PREPARE_SUSPEND_RESUME_DATA(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_GSP_PREPARE_SUSPEND_RESUME_DATA.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_MC_POINTER_NULL(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_MC_POINTER_NULL.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_SAVE_PCIE_CONFIG_REGISTERS(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_SAVE_PCIE_CONFIG_REGISTERS.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_ENGINE(c.Struct):
|
|
SIZE = 24
|
|
engineTransition: NVPOWERSTATE_FAILURE_ENGINE_TRANSITION
|
|
NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_ENGINE.register_fields([('engineTransition', NVPOWERSTATE_FAILURE_ENGINE_TRANSITION, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_UNKNOWN(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_UNKNOWN.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_UNLOAD_ENGINE(c.Struct):
|
|
SIZE = 24
|
|
engineTransition: NVPOWERSTATE_FAILURE_ENGINE_TRANSITION
|
|
NVPOWERSTATE_FAILURE_STATE_UNLOAD_ENGINE.register_fields([('engineTransition', NVPOWERSTATE_FAILURE_ENGINE_TRANSITION, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_UNLOAD_UNKNOWN(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_STATE_UNLOAD_UNKNOWN.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_ENGINE(c.Struct):
|
|
SIZE = 24
|
|
engineTransition: NVPOWERSTATE_FAILURE_ENGINE_TRANSITION
|
|
NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_ENGINE.register_fields([('engineTransition', NVPOWERSTATE_FAILURE_ENGINE_TRANSITION, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_UNKNOWN(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_UNKNOWN.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_GSP_UNLOAD_RM(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_GSP_UNLOAD_RM.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_MONITOR_STATE_0(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_MONITOR_STATE_0.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_MONITOR_STATE_1(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_MONITOR_STATE_1.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_MONITOR_STATE_HIBERNATE(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
NVPOWERSTATE_FAILURE_MONITOR_STATE_HIBERNATE.register_fields([('rsvd', NvU8, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_SET_POWER_STATE_UNKNOWN(c.Struct):
|
|
SIZE = 4
|
|
state: int
|
|
NVPOWERSTATE_FAILURE_SET_POWER_STATE_UNKNOWN.register_fields([('state', NvU32, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE_DATA(c.Struct):
|
|
SIZE = 24
|
|
waitForGfwBootOk: NVPOWERSTATE_FAILURE_WAIT_FOR_GFW_BOOT_OK
|
|
initLibosLoggingStructures: NVPOWERSTATE_FAILURE_INIT_LIBOS_LOGGING_STRUCTURES
|
|
gspPrepareForBootstrap: NVPOWERSTATE_FAILURE_GSP_PREPARE_FOR_BOOTSTRAP
|
|
gspBootstrap: NVPOWERSTATE_FAILURE_GSP_BOOTSTRAP
|
|
bootGspRmProxy: NVPOWERSTATE_FAILURE_BOOT_GSP_RM_PROXY
|
|
vbiosHandleSecureBoot: NVPOWERSTATE_FAILURE_VBIOS_HANDLE_SECURE_BOOT
|
|
restorePcieConfigRegisters: NVPOWERSTATE_FAILURE_RESTORE_PCIE_CONFIG_REGISTERS
|
|
gcxBootTimerCbSchedule: NVPOWERSTATE_FAILURE_GCX_BOOT_TIMER_CB_SCHEDULE
|
|
powerManagementResumePreLoadPhysicalUnattached: NVPOWERSTATE_FAILURE_POWER_MANAGEMENT_RESUME_PRE_LOAD_PHYSICAL_UNATTACHED
|
|
pmsExpectedCheckpointDone: NVPOWERSTATE_FAILURE_PMS_EXPECTED_CHECKPOINT_DONE
|
|
pollForNvlinkReady: NVPOWERSTATE_FAILURE_POLL_FOR_NVLINK_READY
|
|
ceStatePreLoad: NVPOWERSTATE_FAILURE_CE_STATE_PRE_LOAD
|
|
loadProxyUcodeEarlyInit: NVPOWERSTATE_FAILURE_LOAD_PROXY_UCODE_EARLY_INIT
|
|
restoreNonWprRegion: NVPOWERSTATE_FAILURE_RESTORE_NON_WPR_REGION
|
|
pmu20OsBootstrap: NVPOWERSTATE_FAILURE_PMU_20_OS_BOOTSTRAP
|
|
statePreLoadEngine: NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_ENGINE
|
|
statePreLoadUnknown: NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_UNKNOWN
|
|
stateLoadEngine: NVPOWERSTATE_FAILURE_STATE_LOAD_ENGINE
|
|
stateLoadUnknown: NVPOWERSTATE_FAILURE_STATE_LOAD_UNKNOWN
|
|
statePostLoadEngine: NVPOWERSTATE_FAILURE_STATE_POST_LOAD_ENGINE
|
|
statePostLoadUnknown: NVPOWERSTATE_FAILURE_STATE_POST_LOAD_UNKNOWN
|
|
stateLoadPhysical: NVPOWERSTATE_FAILURE_STATE_LOAD_PHYSICAL
|
|
gspPrepareSuspendResumeData: NVPOWERSTATE_FAILURE_GSP_PREPARE_SUSPEND_RESUME_DATA
|
|
mcPointerNull: NVPOWERSTATE_FAILURE_MC_POINTER_NULL
|
|
savePcieConfigRegisters: NVPOWERSTATE_FAILURE_SAVE_PCIE_CONFIG_REGISTERS
|
|
statePreUnloadEngine: NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_ENGINE
|
|
statePreUnloadUnknown: NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_UNKNOWN
|
|
stateUnloadEngine: NVPOWERSTATE_FAILURE_STATE_UNLOAD_ENGINE
|
|
stateUnloadUnknown: NVPOWERSTATE_FAILURE_STATE_UNLOAD_UNKNOWN
|
|
statePostUnloadEngine: NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_ENGINE
|
|
statePostUnloadUnknown: NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_UNKNOWN
|
|
gspUnloadRm: NVPOWERSTATE_FAILURE_GSP_UNLOAD_RM
|
|
monitorState0: NVPOWERSTATE_FAILURE_MONITOR_STATE_0
|
|
monitorState1: NVPOWERSTATE_FAILURE_MONITOR_STATE_1
|
|
monitorStateHibernate: NVPOWERSTATE_FAILURE_MONITOR_STATE_HIBERNATE
|
|
setPowerStateUnknown: NVPOWERSTATE_FAILURE_SET_POWER_STATE_UNKNOWN
|
|
NVPOWERSTATE_FAILURE_DATA.register_fields([('waitForGfwBootOk', NVPOWERSTATE_FAILURE_WAIT_FOR_GFW_BOOT_OK, 0), ('initLibosLoggingStructures', NVPOWERSTATE_FAILURE_INIT_LIBOS_LOGGING_STRUCTURES, 0), ('gspPrepareForBootstrap', NVPOWERSTATE_FAILURE_GSP_PREPARE_FOR_BOOTSTRAP, 0), ('gspBootstrap', NVPOWERSTATE_FAILURE_GSP_BOOTSTRAP, 0), ('bootGspRmProxy', NVPOWERSTATE_FAILURE_BOOT_GSP_RM_PROXY, 0), ('vbiosHandleSecureBoot', NVPOWERSTATE_FAILURE_VBIOS_HANDLE_SECURE_BOOT, 0), ('restorePcieConfigRegisters', NVPOWERSTATE_FAILURE_RESTORE_PCIE_CONFIG_REGISTERS, 0), ('gcxBootTimerCbSchedule', NVPOWERSTATE_FAILURE_GCX_BOOT_TIMER_CB_SCHEDULE, 0), ('powerManagementResumePreLoadPhysicalUnattached', NVPOWERSTATE_FAILURE_POWER_MANAGEMENT_RESUME_PRE_LOAD_PHYSICAL_UNATTACHED, 0), ('pmsExpectedCheckpointDone', NVPOWERSTATE_FAILURE_PMS_EXPECTED_CHECKPOINT_DONE, 0), ('pollForNvlinkReady', NVPOWERSTATE_FAILURE_POLL_FOR_NVLINK_READY, 0), ('ceStatePreLoad', NVPOWERSTATE_FAILURE_CE_STATE_PRE_LOAD, 0), ('loadProxyUcodeEarlyInit', NVPOWERSTATE_FAILURE_LOAD_PROXY_UCODE_EARLY_INIT, 0), ('restoreNonWprRegion', NVPOWERSTATE_FAILURE_RESTORE_NON_WPR_REGION, 0), ('pmu20OsBootstrap', NVPOWERSTATE_FAILURE_PMU_20_OS_BOOTSTRAP, 0), ('statePreLoadEngine', NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_ENGINE, 0), ('statePreLoadUnknown', NVPOWERSTATE_FAILURE_STATE_PRE_LOAD_UNKNOWN, 0), ('stateLoadEngine', NVPOWERSTATE_FAILURE_STATE_LOAD_ENGINE, 0), ('stateLoadUnknown', NVPOWERSTATE_FAILURE_STATE_LOAD_UNKNOWN, 0), ('statePostLoadEngine', NVPOWERSTATE_FAILURE_STATE_POST_LOAD_ENGINE, 0), ('statePostLoadUnknown', NVPOWERSTATE_FAILURE_STATE_POST_LOAD_UNKNOWN, 0), ('stateLoadPhysical', NVPOWERSTATE_FAILURE_STATE_LOAD_PHYSICAL, 0), ('gspPrepareSuspendResumeData', NVPOWERSTATE_FAILURE_GSP_PREPARE_SUSPEND_RESUME_DATA, 0), ('mcPointerNull', NVPOWERSTATE_FAILURE_MC_POINTER_NULL, 0), ('savePcieConfigRegisters', NVPOWERSTATE_FAILURE_SAVE_PCIE_CONFIG_REGISTERS, 0), ('statePreUnloadEngine', NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_ENGINE, 0), ('statePreUnloadUnknown', NVPOWERSTATE_FAILURE_STATE_PRE_UNLOAD_UNKNOWN, 0), ('stateUnloadEngine', NVPOWERSTATE_FAILURE_STATE_UNLOAD_ENGINE, 0), ('stateUnloadUnknown', NVPOWERSTATE_FAILURE_STATE_UNLOAD_UNKNOWN, 0), ('statePostUnloadEngine', NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_ENGINE, 0), ('statePostUnloadUnknown', NVPOWERSTATE_FAILURE_STATE_POST_UNLOAD_UNKNOWN, 0), ('gspUnloadRm', NVPOWERSTATE_FAILURE_GSP_UNLOAD_RM, 0), ('monitorState0', NVPOWERSTATE_FAILURE_MONITOR_STATE_0, 0), ('monitorState1', NVPOWERSTATE_FAILURE_MONITOR_STATE_1, 0), ('monitorStateHibernate', NVPOWERSTATE_FAILURE_MONITOR_STATE_HIBERNATE, 0), ('setPowerStateUnknown', NVPOWERSTATE_FAILURE_SET_POWER_STATE_UNKNOWN, 0)])
|
|
@c.record
|
|
class NVPOWERSTATE_FAILURE(c.Struct):
|
|
SIZE = 32
|
|
stage: int
|
|
status: int
|
|
data: NVPOWERSTATE_FAILURE_DATA
|
|
NVPOWERSTATE_FAILURE.register_fields([('stage', NVPOWERSTATE_STAGE, 0), ('status', NV_STATUS, 4), ('data', NVPOWERSTATE_FAILURE_DATA, 8)])
|
|
@c.record
|
|
class NVPOWERSTATE_PARAMETERS(c.Struct):
|
|
SIZE = 64
|
|
deviceReference: int
|
|
head: int
|
|
state: int
|
|
forceMonitorState: int
|
|
bForcePerfBiosLevel: int
|
|
bIsD3HotTransition: int
|
|
bForcePowerStateFail: int
|
|
errorStatus: int
|
|
fastBootPowerState: int
|
|
bGC8Transition: int
|
|
bGC8InputRailCutOff: int
|
|
failure: NVPOWERSTATE_FAILURE
|
|
NVPOWERSTATE_PARAMETERS.register_fields([('deviceReference', NvU32, 0), ('head', NvU32, 4), ('state', NvU32, 8), ('forceMonitorState', NvU8, 12), ('bForcePerfBiosLevel', NvU8, 13), ('bIsD3HotTransition', NvU8, 14), ('bForcePowerStateFail', NvU8, 15), ('errorStatus', NvU32, 16), ('fastBootPowerState', NvU32, 20), ('bGC8Transition', NvU8, 24), ('bGC8InputRailCutOff', NvU8, 25), ('failure', NVPOWERSTATE_FAILURE, 32)])
|
|
PNVPOWERSTATE_PARAMETERS: TypeAlias = c.POINTER[NVPOWERSTATE_PARAMETERS]
|
|
@c.record
|
|
class NV_GR_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 16
|
|
version: int
|
|
flags: int
|
|
size: int
|
|
caps: int
|
|
NV_GR_ALLOCATION_PARAMETERS.register_fields([('version', NvU32, 0), ('flags', NvU32, 4), ('size', NvU32, 8), ('caps', NvU32, 12)])
|
|
ChannelPBSize: dict[int, str] = {(PB_SIZE_4KB:=0): 'PB_SIZE_4KB', (PB_SIZE_8KB:=1): 'PB_SIZE_8KB', (PB_SIZE_16KB:=2): 'PB_SIZE_16KB', (PB_SIZE_32KB:=3): 'PB_SIZE_32KB', (PB_SIZE_64KB:=4): 'PB_SIZE_64KB'}
|
|
@c.record
|
|
class NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 40
|
|
channelInstance: int
|
|
hObjectBuffer: int
|
|
hObjectNotify: int
|
|
offset: int
|
|
pControl: ctypes.c_void_p
|
|
flags: int
|
|
channelPBSize: int
|
|
subDeviceId: int
|
|
NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS.register_fields([('channelInstance', NvV32, 0), ('hObjectBuffer', NvHandle, 4), ('hObjectNotify', NvHandle, 8), ('offset', NvU32, 12), ('pControl', NvP64, 16), ('flags', NvU32, 24), ('channelPBSize', ctypes.c_uint32, 28), ('subDeviceId', NvU32, 32)])
|
|
@c.record
|
|
class NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 16
|
|
channelInstance: int
|
|
hObjectNotify: int
|
|
pControl: ctypes.c_void_p
|
|
NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS.register_fields([('channelInstance', NvV32, 0), ('hObjectNotify', NvHandle, 4), ('pControl', NvP64, 8)])
|
|
@c.record
|
|
class NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 20
|
|
hObjectError: int
|
|
hObjectEccError: int
|
|
hVASpace: int
|
|
engineType: int
|
|
bIsCallingContextVgpuPlugin: int
|
|
NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS.register_fields([('hObjectError', NvHandle, 0), ('hObjectEccError', NvHandle, 4), ('hVASpace', NvHandle, 8), ('engineType', NvU32, 12), ('bIsCallingContextVgpuPlugin', NvBool, 16)])
|
|
@c.record
|
|
class NV_SWRUNLIST_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
engineId: int
|
|
maxTSGs: int
|
|
qosIntrEnableMask: int
|
|
NV_SWRUNLIST_ALLOCATION_PARAMS.register_fields([('engineId', NvU32, 0), ('maxTSGs', NvU32, 4), ('qosIntrEnableMask', NvU32, 8)])
|
|
@c.record
|
|
class NV_ME_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 8
|
|
size: int
|
|
caps: int
|
|
NV_ME_ALLOCATION_PARAMETERS.register_fields([('size', NvU32, 0), ('caps', NvU32, 4)])
|
|
@c.record
|
|
class NV_NVDEC_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
size: int
|
|
prohibitMultipleInstances: int
|
|
engineInstance: int
|
|
NV_NVDEC_ALLOCATION_PARAMETERS.register_fields([('size', NvU32, 0), ('prohibitMultipleInstances', NvU32, 4), ('engineInstance', NvU32, 8)])
|
|
@c.record
|
|
class NV_VP_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 80
|
|
size: int
|
|
caps: int
|
|
flags: int
|
|
altUcode: int
|
|
rawUcode: ctypes.c_void_p
|
|
rawUcodeSize: int
|
|
numSubClasses: int
|
|
numSubSets: int
|
|
subClasses: ctypes.c_void_p
|
|
prohibitMultipleInstances: int
|
|
pControl: ctypes.c_void_p
|
|
hMemoryCmdBuffer: int
|
|
offset: int
|
|
NV_VP_ALLOCATION_PARAMETERS.register_fields([('size', NvU32, 0), ('caps', NvU32, 4), ('flags', NvU32, 8), ('altUcode', NvU32, 12), ('rawUcode', NvP64, 16), ('rawUcodeSize', NvU32, 24), ('numSubClasses', NvU32, 28), ('numSubSets', NvU32, 32), ('subClasses', NvP64, 40), ('prohibitMultipleInstances', NvU32, 48), ('pControl', NvP64, 56), ('hMemoryCmdBuffer', NvHandle, 64), ('offset', NvU64, 72)])
|
|
@c.record
|
|
class NV_PPP_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 8
|
|
size: int
|
|
prohibitMultipleInstances: int
|
|
NV_PPP_ALLOCATION_PARAMETERS.register_fields([('size', NvU32, 0), ('prohibitMultipleInstances', NvU32, 4)])
|
|
@c.record
|
|
class NV_NVENC_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
size: int
|
|
prohibitMultipleInstances: int
|
|
engineInstance: int
|
|
NV_NVENC_ALLOCATION_PARAMETERS.register_fields([('size', NvU32, 0), ('prohibitMultipleInstances', NvU32, 4), ('engineInstance', NvU32, 8)])
|
|
@c.record
|
|
class NV_SEC2_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 8
|
|
size: int
|
|
prohibitMultipleInstances: int
|
|
NV_SEC2_ALLOCATION_PARAMETERS.register_fields([('size', NvU32, 0), ('prohibitMultipleInstances', NvU32, 4)])
|
|
@c.record
|
|
class NV_NVJPG_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
size: int
|
|
prohibitMultipleInstances: int
|
|
engineInstance: int
|
|
NV_NVJPG_ALLOCATION_PARAMETERS.register_fields([('size', NvU32, 0), ('prohibitMultipleInstances', NvU32, 4), ('engineInstance', NvU32, 8)])
|
|
@c.record
|
|
class NV_OFA_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
size: int
|
|
prohibitMultipleInstances: int
|
|
engineInstance: int
|
|
NV_OFA_ALLOCATION_PARAMETERS.register_fields([('size', NvU32, 0), ('prohibitMultipleInstances', NvU32, 4), ('engineInstance', NvU32, 8)])
|
|
@c.record
|
|
class NVOS61_PARAMETERS(c.Struct):
|
|
SIZE = 56
|
|
hClient: int
|
|
hDevice: int
|
|
hVblank: int
|
|
pProc: c.CFUNCTYPE[None, [ctypes.c_void_p, ctypes.c_void_p]]
|
|
LogicalHead: int
|
|
pParm1: ctypes.c_void_p
|
|
pParm2: ctypes.c_void_p
|
|
bAdd: int
|
|
status: int
|
|
OSVBLANKCALLBACKPROC: TypeAlias = c.CFUNCTYPE[None, [ctypes.c_void_p, ctypes.c_void_p]]
|
|
NVOS61_PARAMETERS.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('hVblank', NvHandle, 8), ('pProc', OSVBLANKCALLBACKPROC, 16), ('LogicalHead', NvV32, 24), ('pParm1', ctypes.c_void_p, 32), ('pParm2', ctypes.c_void_p, 40), ('bAdd', NvU32, 48), ('status', NvV32, 52)])
|
|
@c.record
|
|
class NV_VASPACE_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 56
|
|
index: int
|
|
flags: int
|
|
vaSize: int
|
|
vaStartInternal: int
|
|
vaLimitInternal: int
|
|
bigPageSize: int
|
|
vaBase: int
|
|
pasid: int
|
|
NV_VASPACE_ALLOCATION_PARAMETERS.register_fields([('index', NvU32, 0), ('flags', NvV32, 4), ('vaSize', NvU64, 8), ('vaStartInternal', NvU64, 16), ('vaLimitInternal', NvU64, 24), ('bigPageSize', NvU32, 32), ('vaBase', NvU64, 40), ('pasid', NvU32, 48)])
|
|
@c.record
|
|
class NV_CTXSHARE_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
hVASpace: int
|
|
flags: int
|
|
subctxId: int
|
|
NV_CTXSHARE_ALLOCATION_PARAMETERS.register_fields([('hVASpace', NvHandle, 0), ('flags', NvU32, 4), ('subctxId', NvU32, 8)])
|
|
@c.record
|
|
class NV_TIMEOUT_CONTROL_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
cmd: int
|
|
timeoutInMs: int
|
|
deviceInstance: int
|
|
NV_TIMEOUT_CONTROL_PARAMETERS.register_fields([('cmd', NvU32, 0), ('timeoutInMs', NvU32, 4), ('deviceInstance', NvU32, 8)])
|
|
NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE: dict[int, str] = {(NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT:=0): 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT', (NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH:=1): 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH', (NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH:=2): 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH', (NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID:=3): 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID'}
|
|
@c.record
|
|
class NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 528
|
|
bDirtyTracking: int
|
|
granularity: int
|
|
accessBitMask: c.Array[ctypes.c_uint64, Literal[64]]
|
|
noOfEntries: int
|
|
addrSpace: int
|
|
NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS.register_fields([('bDirtyTracking', NvBool, 0), ('granularity', NvU32, 4), ('accessBitMask', c.Array[NvU64, Literal[64]], 8), ('noOfEntries', NvU32, 520), ('addrSpace', ctypes.c_uint32, 524)])
|
|
@c.record
|
|
class NV_HOPPER_USERMODE_A_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bBar1Mapping: int
|
|
bPriv: int
|
|
NV_HOPPER_USERMODE_A_PARAMS.register_fields([('bBar1Mapping', NvBool, 0), ('bPriv', NvBool, 1)])
|
|
@c.record
|
|
class struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
workSubmitToken: int
|
|
struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS.register_fields([('workSubmitToken', NvU32, 0)])
|
|
NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS: TypeAlias = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS
|
|
@c.record
|
|
class struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
bar2Addr: c.Array[ctypes.c_uint64, Literal[2]]
|
|
struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS.register_fields([('bar2Addr', c.Array[NvU64, Literal[2]], 0)])
|
|
NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS: TypeAlias = struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
index: int
|
|
struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS.register_fields([('index', NvU32, 0)])
|
|
NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS: TypeAlias = struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS
|
|
NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS: TypeAlias = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS(c.Struct):
|
|
SIZE = 6
|
|
cpuCapability: int
|
|
gpusCapability: int
|
|
environment: int
|
|
ccFeature: int
|
|
devToolsMode: int
|
|
multiGpuMode: int
|
|
struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS.register_fields([('cpuCapability', NvU8, 0), ('gpusCapability', NvU8, 1), ('environment', NvU8, 2), ('ccFeature', NvU8, 3), ('devToolsMode', NvU8, 4), ('multiGpuMode', NvU8, 5)])
|
|
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bAcceptClientRequest: int
|
|
struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS.register_fields([('bAcceptClientRequest', NvBool, 0)])
|
|
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bAcceptClientRequest: int
|
|
struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS.register_fields([('bAcceptClientRequest', NvBool, 0)])
|
|
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hSubDevice: int
|
|
protectedMemSizeInKb: int
|
|
unprotectedMemSizeInKb: int
|
|
struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('protectedMemSizeInKb', NvU64, 8), ('unprotectedMemSizeInKb', NvU64, 16)])
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hSubDevice: int
|
|
protectedMemSizeInKb: int
|
|
unprotectedMemSizeInKb: int
|
|
struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('protectedMemSizeInKb', NvU64, 8), ('unprotectedMemSizeInKb', NvU64, 16)])
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hSubDevice: int
|
|
numSupportedSec2CCSecureChannels: int
|
|
numSupportedCeCCSecureChannels: int
|
|
struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('numSupportedSec2CCSecureChannels', NvU32, 4), ('numSupportedCeCCSecureChannels', NvU32, 8)])
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS(c.Struct):
|
|
SIZE = 9228
|
|
hSubDevice: int
|
|
certChain: c.Array[ctypes.c_ubyte, Literal[4096]]
|
|
certChainSize: int
|
|
attestationCertChain: c.Array[ctypes.c_ubyte, Literal[5120]]
|
|
attestationCertChainSize: int
|
|
struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('certChain', c.Array[NvU8, Literal[4096]], 4), ('certChainSize', NvU32, 4100), ('attestationCertChain', c.Array[NvU8, Literal[5120]], 4104), ('attestationCertChainSize', NvU32, 9224)])
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS(c.Struct):
|
|
SIZE = 12336
|
|
hSubDevice: int
|
|
nonce: c.Array[ctypes.c_ubyte, Literal[32]]
|
|
attestationReport: c.Array[ctypes.c_ubyte, Literal[8192]]
|
|
attestationReportSize: int
|
|
isCecAttestationReportPresent: int
|
|
cecAttestationReport: c.Array[ctypes.c_ubyte, Literal[4096]]
|
|
cecAttestationReportSize: int
|
|
struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('nonce', c.Array[NvU8, Literal[32]], 4), ('attestationReport', c.Array[NvU8, Literal[8192]], 36), ('attestationReportSize', NvU32, 8228), ('isCecAttestationReportPresent', NvBool, 8232), ('cecAttestationReport', c.Array[NvU8, Literal[4096]], 8233), ('cecAttestationReportSize', NvU32, 12332)])
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hSubDevice: int
|
|
maxSec2Channels: int
|
|
maxCeChannels: int
|
|
struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('maxSec2Channels', NvU32, 4), ('maxCeChannels', NvU32, 8)])
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hSubDevice: int
|
|
keyRotationState: int
|
|
struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('keyRotationState', NvU32, 4)])
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
bEnable: int
|
|
bSkipSubmit: int
|
|
bSkipEnable: int
|
|
NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS: TypeAlias = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS
|
|
struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS.register_fields([('bEnable', NvBool, 0), ('bSkipSubmit', NvBool, 1), ('bSkipEnable', NvBool, 2)])
|
|
@c.record
|
|
class struct_NVA06F_CTRL_BIND_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
engineType: int
|
|
NVA06C_CTRL_BIND_PARAMS: TypeAlias = struct_NVA06F_CTRL_BIND_PARAMS
|
|
struct_NVA06F_CTRL_BIND_PARAMS.register_fields([('engineType', NvU32, 0)])
|
|
@c.record
|
|
class struct_NVA06C_CTRL_TIMESLICE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
timesliceUs: int
|
|
struct_NVA06C_CTRL_TIMESLICE_PARAMS.register_fields([('timesliceUs', NvU64, 0)])
|
|
NVA06C_CTRL_TIMESLICE_PARAMS: TypeAlias = struct_NVA06C_CTRL_TIMESLICE_PARAMS
|
|
NVA06C_CTRL_SET_TIMESLICE_PARAMS: TypeAlias = struct_NVA06C_CTRL_TIMESLICE_PARAMS
|
|
NVA06C_CTRL_GET_TIMESLICE_PARAMS: TypeAlias = struct_NVA06C_CTRL_TIMESLICE_PARAMS
|
|
@c.record
|
|
class struct_NVA06C_CTRL_PREEMPT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bWait: int
|
|
bManualTimeout: int
|
|
timeoutUs: int
|
|
struct_NVA06C_CTRL_PREEMPT_PARAMS.register_fields([('bWait', NvBool, 0), ('bManualTimeout', NvBool, 1), ('timeoutUs', NvU32, 4)])
|
|
NVA06C_CTRL_PREEMPT_PARAMS: TypeAlias = struct_NVA06C_CTRL_PREEMPT_PARAMS
|
|
@c.record
|
|
class struct_NVA06C_CTRL_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
tsgID: int
|
|
struct_NVA06C_CTRL_GET_INFO_PARAMS.register_fields([('tsgID', NvU32, 0)])
|
|
NVA06C_CTRL_GET_INFO_PARAMS: TypeAlias = struct_NVA06C_CTRL_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
tsgInterleaveLevel: int
|
|
struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS.register_fields([('tsgInterleaveLevel', NvU32, 0)])
|
|
NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS: TypeAlias = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS
|
|
NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS: TypeAlias = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS
|
|
NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS: TypeAlias = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS
|
|
enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE: dict[int, str] = {(NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE:=0): 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE', (NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B:=1): 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B', (NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B:=2): 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B'}
|
|
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD(c.Struct):
|
|
SIZE = 4
|
|
size: int
|
|
struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD.register_fields([('size', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE, 0)])
|
|
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD: TypeAlias = struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD
|
|
@c.record
|
|
class struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
l1: struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD
|
|
t1: struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD
|
|
struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS.register_fields([('l1', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD, 0), ('t1', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD, 4)])
|
|
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS: TypeAlias = struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS
|
|
@c.record
|
|
class struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS(c.Struct):
|
|
SIZE = 88
|
|
methodBufferMemdesc: c.Array[struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO, Literal[2]]
|
|
bar2Addr: c.Array[ctypes.c_uint64, Literal[2]]
|
|
numValidEntries: int
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO(c.Struct):
|
|
SIZE = 32
|
|
base: int
|
|
size: int
|
|
alignment: int
|
|
addressSpace: int
|
|
cpuCacheAttrib: int
|
|
NV2080_CTRL_INTERNAL_MEMDESC_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO
|
|
struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO.register_fields([('base', NvU64, 0), ('size', NvU64, 8), ('alignment', NvU64, 16), ('addressSpace', NvU32, 24), ('cpuCacheAttrib', NvU32, 28)])
|
|
struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS.register_fields([('methodBufferMemdesc', c.Array[NV2080_CTRL_INTERNAL_MEMDESC_INFO, Literal[2]], 0), ('bar2Addr', c.Array[NvU64, Literal[2]], 64), ('numValidEntries', NvU32, 80)])
|
|
NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS: TypeAlias = struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS
|
|
@c.record
|
|
class struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bRealtime: int
|
|
struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS.register_fields([('bRealtime', NvBool, 0)])
|
|
NVA06C_CTRL_MAKE_REALTIME_PARAMS: TypeAlias = struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS
|
|
NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS: TypeAlias = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS
|
|
NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS: TypeAlias = struct_NVA06C_CTRL_TIMESLICE_PARAMS
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hSubDevice: int
|
|
subDeviceId: int
|
|
pFmt: ctypes.c_void_p
|
|
struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('subDeviceId', NvU32, 4), ('pFmt', NvP64, 8)])
|
|
NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS
|
|
@c.record
|
|
class struct_NV_CTRL_VASPACE_PAGE_LEVEL(c.Struct):
|
|
SIZE = 112
|
|
pFmt: c.POINTER[struct_MMU_FMT_LEVEL]
|
|
levelFmt: struct_MMU_FMT_LEVEL
|
|
sublevelFmt: c.Array[struct_MMU_FMT_LEVEL, Literal[2]]
|
|
physAddress: int
|
|
aperture: int
|
|
size: int
|
|
entryIndex: int
|
|
@c.record
|
|
class struct_MMU_FMT_LEVEL(c.Struct):
|
|
SIZE = 24
|
|
virtAddrBitLo: int
|
|
virtAddrBitHi: int
|
|
entrySize: int
|
|
bPageTable: int
|
|
numSubLevels: int
|
|
pageLevelIdTag: int
|
|
subLevels: c.POINTER[struct_MMU_FMT_LEVEL]
|
|
struct_MMU_FMT_LEVEL.register_fields([('virtAddrBitLo', NvU8, 0), ('virtAddrBitHi', NvU8, 1), ('entrySize', NvU8, 2), ('bPageTable', NvBool, 3), ('numSubLevels', NvU8, 4), ('pageLevelIdTag', NvU32, 8), ('subLevels', c.POINTER[struct_MMU_FMT_LEVEL], 16)])
|
|
MMU_FMT_LEVEL: TypeAlias = struct_MMU_FMT_LEVEL
|
|
struct_NV_CTRL_VASPACE_PAGE_LEVEL.register_fields([('pFmt', c.POINTER[struct_MMU_FMT_LEVEL], 0), ('levelFmt', MMU_FMT_LEVEL, 8), ('sublevelFmt', c.Array[MMU_FMT_LEVEL, Literal[2]], 32), ('physAddress', NvU64, 80), ('aperture', NvU32, 88), ('size', NvU64, 96), ('entryIndex', NvU32, 104)])
|
|
NV_CTRL_VASPACE_PAGE_LEVEL: TypeAlias = struct_NV_CTRL_VASPACE_PAGE_LEVEL
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS(c.Struct):
|
|
SIZE = 712
|
|
hSubDevice: int
|
|
subDeviceId: int
|
|
virtAddress: int
|
|
pageSize: int
|
|
flags: int
|
|
numLevels: int
|
|
levels: c.Array[struct_NV_CTRL_VASPACE_PAGE_LEVEL, Literal[6]]
|
|
struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('subDeviceId', NvU32, 4), ('virtAddress', NvU64, 8), ('pageSize', NvU64, 16), ('flags', NvU64, 24), ('numLevels', NvU32, 32), ('levels', c.Array[NV_CTRL_VASPACE_PAGE_LEVEL, Literal[6]], 40)])
|
|
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hSubDevice: int
|
|
subDeviceId: int
|
|
pageSize: int
|
|
virtAddrLo: int
|
|
virtAddrHi: int
|
|
struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('subDeviceId', NvU32, 4), ('pageSize', NvU64, 8), ('virtAddrLo', NvU64, 16), ('virtAddrHi', NvU64, 24)])
|
|
NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hSubDevice: int
|
|
subDeviceId: int
|
|
pageSize: int
|
|
virtAddrLo: int
|
|
virtAddrHi: int
|
|
struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('subDeviceId', NvU32, 4), ('pageSize', NvU64, 8), ('virtAddrLo', NvU64, 16), ('virtAddrHi', NvU64, 24)])
|
|
NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS
|
|
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS(c.Struct):
|
|
SIZE = 184
|
|
hSubDevice: int
|
|
subDeviceId: int
|
|
pageSize: int
|
|
virtAddrLo: int
|
|
virtAddrHi: int
|
|
numLevelsToCopy: int
|
|
levels: c.Array[struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level, Literal[6]]
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level(c.Struct):
|
|
SIZE = 24
|
|
physAddress: int
|
|
size: int
|
|
aperture: int
|
|
pageShift: int
|
|
struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level.register_fields([('physAddress', NvU64, 0), ('size', NvU64, 8), ('aperture', NvU32, 16), ('pageShift', NvU8, 20)])
|
|
struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('subDeviceId', NvU32, 4), ('pageSize', NvU64, 8), ('virtAddrLo', NvU64, 16), ('virtAddrHi', NvU64, 24), ('numLevelsToCopy', NvU32, 32), ('levels', c.Array[struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level, Literal[6]], 40)])
|
|
NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hSubDevice: int
|
|
subDeviceId: int
|
|
requiredVaRange: int
|
|
struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('subDeviceId', NvU32, 4), ('requiredVaRange', NvU64, 8)])
|
|
NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
hSubDevice: int
|
|
subDeviceId: int
|
|
bytesFree: int
|
|
bytesTotal: int
|
|
largestFreeOffset: int
|
|
largestFreeSize: int
|
|
usableBytesFree: int
|
|
numFreeBlocks: int
|
|
struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS.register_fields([('hSubDevice', NvHandle, 0), ('subDeviceId', NvU32, 4), ('bytesFree', NvU64, 8), ('bytesTotal', NvU64, 16), ('largestFreeOffset', NvU64, 24), ('largestFreeSize', NvU64, 32), ('usableBytesFree', NvU64, 40), ('numFreeBlocks', NvU32, 48)])
|
|
NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS
|
|
NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS: TypeAlias = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS
|
|
NVA06F_CTRL_BIND_PARAMS: TypeAlias = struct_NVA06F_CTRL_BIND_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bNotifyEachChannelInTSG: int
|
|
struct_NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS.register_fields([('bNotifyEachChannelInTSG', NvBool, 0)])
|
|
NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS: TypeAlias = struct_NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
channelInterleaveLevel: int
|
|
struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS.register_fields([('channelInterleaveLevel', NvU32, 0)])
|
|
NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS: TypeAlias = struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS
|
|
NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS: TypeAlias = struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS
|
|
NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS: TypeAlias = struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_RESTART_RUNLIST_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bForceRestart: int
|
|
bBypassWait: int
|
|
struct_NVA06F_CTRL_RESTART_RUNLIST_PARAMS.register_fields([('bForceRestart', NvBool, 0), ('bBypassWait', NvBool, 1)])
|
|
NVA06F_CTRL_RESTART_RUNLIST_PARAMS: TypeAlias = struct_NVA06F_CTRL_RESTART_RUNLIST_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bImmediate: int
|
|
struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS.register_fields([('bImmediate', NvBool, 0)])
|
|
NVA06F_CTRL_STOP_CHANNEL_PARAMS: TypeAlias = struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_GET_CONTEXT_ID_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
contextId: int
|
|
struct_NVA06F_CTRL_GET_CONTEXT_ID_PARAMS.register_fields([('contextId', NvU32, 0)])
|
|
NVA06F_CTRL_GET_CONTEXT_ID_PARAMS: TypeAlias = struct_NVA06F_CTRL_GET_CONTEXT_ID_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hObject: int
|
|
mapFlags: int
|
|
addrSpaceType: int
|
|
struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS.register_fields([('hObject', NvHandle, 0), ('mapFlags', NvU32, 4), ('addrSpaceType', NvU32, 8)])
|
|
NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hObject: int
|
|
index: int
|
|
data: struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data(c.Struct):
|
|
SIZE = 8
|
|
hResult: int
|
|
iResult: int
|
|
struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data.register_fields([('hResult', NvHandle, 0), ('iResult', NvU64, 0)])
|
|
struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS.register_fields([('hObject', NvHandle, 0), ('index', NvU32, 4), ('data', struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data, 8)])
|
|
NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hObject: int
|
|
hClient: int
|
|
maskResult: struct_RS_ACCESS_MASK
|
|
struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS.register_fields([('hObject', NvHandle, 0), ('hClient', NvHandle, 4), ('maskResult', RS_ACCESS_MASK, 8)])
|
|
NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
sharePolicy: struct_RS_SHARE_POLICY
|
|
struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS.register_fields([('sharePolicy', RS_SHARE_POLICY, 0)])
|
|
NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hParent: int
|
|
classId: int
|
|
hObject: int
|
|
struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS.register_fields([('hParent', NvHandle, 0), ('classId', NvU32, 4), ('hObject', NvHandle, 8)])
|
|
NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS: TypeAlias = struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hObject: int
|
|
sharePolicy: struct_RS_SHARE_POLICY
|
|
struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS.register_fields([('hObject', NvHandle, 0), ('sharePolicy', RS_SHARE_POLICY, 4)])
|
|
NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hObject1: int
|
|
hObject2: int
|
|
bDuplicates: int
|
|
struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS.register_fields([('hObject1', NvHandle, 0), ('hObject2', NvHandle, 4), ('bDuplicates', NvBool, 8)])
|
|
NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
devDescriptor: int
|
|
channel: int
|
|
struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS.register_fields([('devDescriptor', NvU64, 0), ('channel', NvU32, 8)])
|
|
NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
state: int
|
|
count: int
|
|
missedCount: int
|
|
bCircularBuffer: int
|
|
struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS.register_fields([('state', NvU32, 0), ('count', NvU32, 4), ('missedCount', NvU32, 8), ('bCircularBuffer', NvBool, 12)])
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS: TypeAlias = struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
state: int
|
|
bCircularBuffer: int
|
|
struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS.register_fields([('state', NvU32, 0), ('bCircularBuffer', NvBool, 4)])
|
|
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS: TypeAlias = struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY(c.Struct):
|
|
SIZE = 56
|
|
counter: int
|
|
line: int
|
|
filename: c.Array[ctypes.c_ubyte, Literal[12]]
|
|
tag: int
|
|
cpuNum: int
|
|
irql: int
|
|
threadId: int
|
|
data0: int
|
|
data1: int
|
|
data2: int
|
|
struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY.register_fields([('counter', NvU64, 0), ('line', NvU32, 8), ('filename', c.Array[NvU8, Literal[12]], 12), ('tag', NvU16, 24), ('cpuNum', NvU8, 26), ('irql', NvU8, 27), ('threadId', NvU64, 32), ('data0', NvU32, 40), ('data1', NvU32, 44), ('data2', NvU32, 48)])
|
|
NV0000_CTRL_DIAG_LOCK_METER_ENTRY: TypeAlias = struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY
|
|
@c.record
|
|
class struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS(c.Struct):
|
|
SIZE = 3592
|
|
entryCount: int
|
|
entries: c.Array[struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY, Literal[64]]
|
|
struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS.register_fields([('entryCount', NvU32, 0), ('entries', c.Array[NV0000_CTRL_DIAG_LOCK_METER_ENTRY, Literal[64]], 8)])
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS: TypeAlias = struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS
|
|
@c.record
|
|
class struct_RPC_METER_ENTRY(c.Struct):
|
|
SIZE = 32
|
|
startTimeInNs: int
|
|
endTimeInNs: int
|
|
rpcDataTag: int
|
|
rpcExtraData: int
|
|
struct_RPC_METER_ENTRY.register_fields([('startTimeInNs', NvU64, 0), ('endTimeInNs', NvU64, 8), ('rpcDataTag', NvU64, 16), ('rpcExtraData', NvU64, 24)])
|
|
RPC_METER_ENTRY: TypeAlias = struct_RPC_METER_ENTRY
|
|
@c.record
|
|
class struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rpcProfileCmd: int
|
|
struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS.register_fields([('rpcProfileCmd', NvU32, 0)])
|
|
NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS: TypeAlias = struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS(c.Struct):
|
|
SIZE = 3224
|
|
firstEntryOffset: int
|
|
outputEntryCount: int
|
|
remainingEntryCount: int
|
|
elapsedTimeInNs: int
|
|
rpcProfilerBuffer: c.Array[struct_RPC_METER_ENTRY, Literal[100]]
|
|
struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS.register_fields([('firstEntryOffset', NvU32, 0), ('outputEntryCount', NvU32, 4), ('remainingEntryCount', NvU32, 8), ('elapsedTimeInNs', NvU64, 16), ('rpcProfilerBuffer', c.Array[RPC_METER_ENTRY, Literal[100]], 24)])
|
|
NV0000_CTRL_DIAG_DUMP_RPC_PARAMS: TypeAlias = struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
event: int
|
|
action: int
|
|
struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS.register_fields([('event', NvU32, 0), ('action', NvU32, 4)])
|
|
NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS: TypeAlias = struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE(c.Struct):
|
|
SIZE = 4
|
|
deviceMask: int
|
|
struct_NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE.register_fields([('deviceMask', NvU32, 0)])
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE: TypeAlias = struct_NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND(c.Struct):
|
|
SIZE = 4
|
|
gpuId: int
|
|
struct_NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND.register_fields([('gpuId', NvU32, 0)])
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND: TypeAlias = struct_NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND(c.Struct):
|
|
SIZE = 4
|
|
gpuId: int
|
|
struct_NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND.register_fields([('gpuId', NvU32, 0)])
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND: TypeAlias = struct_NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND(c.Struct):
|
|
SIZE = 8
|
|
gpuId: int
|
|
bBind: int
|
|
struct_NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND.register_fields([('gpuId', NvU32, 0), ('bBind', NvBool, 4)])
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND: TypeAlias = struct_NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND
|
|
@c.record
|
|
class struct_NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
event: int
|
|
data: struct_NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_data
|
|
@c.record
|
|
class struct_NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_data(c.Struct):
|
|
SIZE = 8
|
|
display: struct_NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE
|
|
vgpuUnbind: struct_NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND
|
|
vgpuBind: struct_NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND
|
|
gpuBindUnbind: struct_NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND
|
|
struct_NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_data.register_fields([('display', NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE, 0), ('vgpuUnbind', NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND, 0), ('vgpuBind', NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND, 0), ('gpuBindUnbind', NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND, 0)])
|
|
struct_NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS.register_fields([('event', NvU32, 0), ('data', struct_NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_data, 4)])
|
|
NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS: TypeAlias = struct_NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_LINK_MASK(c.Struct):
|
|
SIZE = 16
|
|
lenMasks: int
|
|
masks: c.Array[ctypes.c_uint64, Literal[1]]
|
|
NV0000_CTRL_NVLINK_LINK_MASK: TypeAlias = struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
struct_NV2080_CTRL_NVLINK_LINK_MASK.register_fields([('lenMasks', NvU8, 0), ('masks', c.Array[NvU64, Literal[1]], 8)])
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS(c.Struct):
|
|
SIZE = 128
|
|
gpuIds: c.Array[ctypes.c_uint32, Literal[32]]
|
|
struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS.register_fields([('gpuIds', c.Array[NvU32, Literal[32]], 0)])
|
|
NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
gpuId: int
|
|
gpuFlags: int
|
|
deviceInstance: int
|
|
subDeviceInstance: int
|
|
szName: ctypes.c_void_p
|
|
sliStatus: int
|
|
boardId: int
|
|
gpuInstance: int
|
|
numaId: int
|
|
struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS.register_fields([('gpuId', NvU32, 0), ('gpuFlags', NvU32, 4), ('deviceInstance', NvU32, 8), ('subDeviceInstance', NvU32, 12), ('szName', NvP64, 16), ('sliStatus', NvU32, 24), ('boardId', NvU32, 28), ('gpuInstance', NvU32, 32), ('numaId', NvS32, 36)])
|
|
NV0000_CTRL_GPU_GET_ID_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
gpuId: int
|
|
gpuFlags: int
|
|
deviceInstance: int
|
|
subDeviceInstance: int
|
|
sliStatus: int
|
|
boardId: int
|
|
gpuInstance: int
|
|
numaId: int
|
|
struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS.register_fields([('gpuId', NvU32, 0), ('gpuFlags', NvU32, 4), ('deviceInstance', NvU32, 8), ('subDeviceInstance', NvU32, 12), ('sliStatus', NvU32, 16), ('boardId', NvU32, 20), ('gpuInstance', NvU32, 24), ('numaId', NvS32, 28)])
|
|
NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpuId: int
|
|
status: int
|
|
struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS.register_fields([('gpuId', NvU32, 0), ('status', NvU32, 4)])
|
|
NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
deviceIds: int
|
|
struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS.register_fields([('deviceIds', NvU32, 0)])
|
|
NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS(c.Struct):
|
|
SIZE = 384
|
|
gpuIds: c.Array[ctypes.c_uint32, Literal[32]]
|
|
excludedGpuIds: c.Array[ctypes.c_uint32, Literal[32]]
|
|
gpuFlags: c.Array[ctypes.c_uint32, Literal[32]]
|
|
struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS.register_fields([('gpuIds', c.Array[NvU32, Literal[32]], 0), ('excludedGpuIds', c.Array[NvU32, Literal[32]], 128), ('gpuFlags', c.Array[NvU32, Literal[32]], 256)])
|
|
NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gpuId: int
|
|
domain: int
|
|
bus: int
|
|
slot: int
|
|
struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS.register_fields([('gpuId', NvU32, 0), ('domain', NvU32, 4), ('bus', NvU16, 8), ('slot', NvU16, 10)])
|
|
NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS(c.Struct):
|
|
SIZE = 132
|
|
gpuIds: c.Array[ctypes.c_uint32, Literal[32]]
|
|
failedId: int
|
|
struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS.register_fields([('gpuIds', c.Array[NvU32, Literal[32]], 0), ('failedId', NvU32, 128)])
|
|
NV0000_CTRL_GPU_ATTACH_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS(c.Struct):
|
|
SIZE = 128
|
|
gpuIds: c.Array[ctypes.c_uint32, Literal[32]]
|
|
struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS.register_fields([('gpuIds', c.Array[NvU32, Literal[32]], 0)])
|
|
NV0000_CTRL_GPU_DETACH_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_VIDEO_LINKS(c.Struct):
|
|
SIZE = 36
|
|
gpuId: int
|
|
connectedGpuIds: c.Array[ctypes.c_uint32, Literal[8]]
|
|
struct_NV0000_CTRL_GPU_VIDEO_LINKS.register_fields([('gpuId', NvU32, 0), ('connectedGpuIds', c.Array[NvU32, Literal[8]], 4)])
|
|
NV0000_CTRL_GPU_VIDEO_LINKS: TypeAlias = struct_NV0000_CTRL_GPU_VIDEO_LINKS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS(c.Struct):
|
|
SIZE = 1152
|
|
links: c.Array[struct_NV0000_CTRL_GPU_VIDEO_LINKS, Literal[32]]
|
|
struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS.register_fields([('links', c.Array[NV0000_CTRL_GPU_VIDEO_LINKS, Literal[32]], 0)])
|
|
NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS(c.Struct):
|
|
SIZE = 272
|
|
gpuUuid: c.Array[ctypes.c_ubyte, Literal[256]]
|
|
flags: int
|
|
gpuId: int
|
|
deviceInstance: int
|
|
subdeviceInstance: int
|
|
struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS.register_fields([('gpuUuid', c.Array[NvU8, Literal[256]], 0), ('flags', NvU32, 256), ('gpuId', NvU32, 260), ('deviceInstance', NvU32, 264), ('subdeviceInstance', NvU32, 268)])
|
|
NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS(c.Struct):
|
|
SIZE = 268
|
|
gpuId: int
|
|
flags: int
|
|
gpuUuid: c.Array[ctypes.c_ubyte, Literal[256]]
|
|
uuidStrLen: int
|
|
struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS.register_fields([('gpuId', NvU32, 0), ('flags', NvU32, 4), ('gpuUuid', c.Array[NvU8, Literal[256]], 8), ('uuidStrLen', NvU32, 264)])
|
|
NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gpuId: int
|
|
newState: int
|
|
flags: int
|
|
struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS.register_fields([('gpuId', NvU32, 0), ('newState', NvU32, 4), ('flags', NvU32, 8)])
|
|
NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gpuId: int
|
|
drainState: int
|
|
flags: int
|
|
struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS.register_fields([('gpuId', NvU32, 0), ('drainState', NvU32, 4), ('flags', NvU32, 8)])
|
|
NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_DISCOVER_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
domain: int
|
|
bus: int
|
|
slot: int
|
|
function: int
|
|
struct_NV0000_CTRL_GPU_DISCOVER_PARAMS.register_fields([('domain', NvU32, 0), ('bus', NvU8, 4), ('slot', NvU8, 5), ('function', NvU8, 6)])
|
|
NV0000_CTRL_GPU_DISCOVER_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_DISCOVER_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
enableMask: int
|
|
struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS.register_fields([('enableMask', NvU32, 0)])
|
|
NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
gpuId: int
|
|
mask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
bSkipHwNvlinkDisable: int
|
|
struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS.register_fields([('gpuId', NvU32, 0), ('mask', NvU32, 4), ('links', NV0000_CTRL_NVLINK_LINK_MASK, 8), ('bSkipHwNvlinkDisable', NvBool, 24)])
|
|
NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
hDevice: int
|
|
hChannel: int
|
|
numChannels: int
|
|
phClients: ctypes.c_void_p
|
|
phDevices: ctypes.c_void_p
|
|
phChannels: ctypes.c_void_p
|
|
flags: int
|
|
timeout: int
|
|
struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS.register_fields([('hDevice', NvHandle, 0), ('hChannel', NvHandle, 4), ('numChannels', NvV32, 8), ('phClients', NvP64, 16), ('phDevices', NvP64, 24), ('phChannels', NvP64, 32), ('flags', NvV32, 40), ('timeout', NvV32, 44)])
|
|
NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
image: int
|
|
totalSize: int
|
|
pData: ctypes.c_void_p
|
|
struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS.register_fields([('image', NvU8, 0), ('totalSize', NvU64, 8), ('pData', NvP64, 16)])
|
|
NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
mode: int
|
|
struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS.register_fields([('mode', NvU16, 0)])
|
|
NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
mode: int
|
|
bwModeScope: int
|
|
struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS.register_fields([('mode', NvU8, 0), ('bwModeScope', NvU8, 1)])
|
|
NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_ACTIVE_DEVICE(c.Struct):
|
|
SIZE = 12
|
|
gpuId: int
|
|
gpuInstanceId: int
|
|
computeInstanceId: int
|
|
struct_NV0000_CTRL_GPU_ACTIVE_DEVICE.register_fields([('gpuId', NvU32, 0), ('gpuInstanceId', NvU32, 4), ('computeInstanceId', NvU32, 8)])
|
|
NV0000_CTRL_GPU_ACTIVE_DEVICE: TypeAlias = struct_NV0000_CTRL_GPU_ACTIVE_DEVICE
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS(c.Struct):
|
|
SIZE = 3076
|
|
numDevices: int
|
|
devices: c.Array[struct_NV0000_CTRL_GPU_ACTIVE_DEVICE, Literal[256]]
|
|
struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS.register_fields([('numDevices', NvU32, 0), ('devices', c.Array[NV0000_CTRL_GPU_ACTIVE_DEVICE, Literal[256]], 4)])
|
|
NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gpuId: int
|
|
struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS.register_fields([('gpuId', NvU32, 0)])
|
|
NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gpuId: int
|
|
struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS.register_fields([('gpuId', NvU32, 0)])
|
|
NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_PCI_READ_WRITE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
bWrite: int
|
|
pciDomain: int
|
|
pciBus: int
|
|
pciDevice: int
|
|
pciFunction: int
|
|
pciOffset: int
|
|
dataSize: int
|
|
data: int
|
|
struct_NV0000_CTRL_GPU_PCI_READ_WRITE_PARAMS.register_fields([('bWrite', NvBool, 0), ('pciDomain', NvU16, 2), ('pciBus', NvU8, 4), ('pciDevice', NvU8, 5), ('pciFunction', NvU8, 6), ('pciOffset', NvU8, 7), ('dataSize', NvU32, 8), ('data', NvU32, 12)])
|
|
NV0000_CTRL_GPU_PCI_READ_WRITE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_PCI_READ_WRITE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gpuId: int
|
|
pid: int
|
|
newState: int
|
|
struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS.register_fields([('gpuId', NvU32, 0), ('pid', NvU32, 4), ('newState', NvU32, 8)])
|
|
NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gpuId: int
|
|
pid: int
|
|
state: int
|
|
struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS.register_fields([('gpuId', NvU32, 0), ('pid', NvU32, 4), ('state', NvU32, 8)])
|
|
NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
gpuId: int
|
|
pid: int
|
|
subPid: int
|
|
gpuUtil: int
|
|
fbUtil: int
|
|
maxFbUsage: int
|
|
startTime: int
|
|
endTime: int
|
|
struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS.register_fields([('gpuId', NvU32, 0), ('pid', NvU32, 4), ('subPid', NvU32, 8), ('gpuUtil', NvU32, 12), ('fbUtil', NvU32, 16), ('maxFbUsage', NvU64, 24), ('startTime', NvU64, 32), ('endTime', NvU64, 40)])
|
|
NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS(c.Struct):
|
|
SIZE = 16012
|
|
gpuId: int
|
|
pid: int
|
|
pidTbl: c.Array[ctypes.c_uint32, Literal[4000]]
|
|
pidCount: int
|
|
struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS.register_fields([('gpuId', NvU32, 0), ('pid', NvU32, 4), ('pidTbl', c.Array[NvU32, Literal[4000]], 8), ('pidCount', NvU32, 16008)])
|
|
NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpuId: int
|
|
pid: int
|
|
struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS.register_fields([('gpuId', NvU32, 0), ('pid', NvU32, 4)])
|
|
NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS: TypeAlias = struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 64
|
|
gpuId: int
|
|
pid: int
|
|
subPid: int
|
|
gpuUtil: int
|
|
fbUtil: int
|
|
sampleCount: int
|
|
maxFbUsage: int
|
|
startTime: int
|
|
endTime: int
|
|
sumGpuUtil: int
|
|
sumFbUtil: int
|
|
struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_V2_PARAMS.register_fields([('gpuId', NvU32, 0), ('pid', NvU32, 4), ('subPid', NvU32, 8), ('gpuUtil', NvU32, 12), ('fbUtil', NvU32, 16), ('sampleCount', NvU32, 20), ('maxFbUsage', NvU64, 24), ('startTime', NvU64, 32), ('endTime', NvU64, 40), ('sumGpuUtil', NvU64, 48), ('sumFbUtil', NvU64, 56)])
|
|
NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_V2_PARAMS: TypeAlias = struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
gsyncIds: c.Array[ctypes.c_uint32, Literal[4]]
|
|
struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS.register_fields([('gsyncIds', c.Array[NvU32, Literal[4]], 0)])
|
|
NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gsyncId: int
|
|
gsyncFlags: int
|
|
gsyncInstance: int
|
|
struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS.register_fields([('gsyncId', NvU32, 0), ('gsyncFlags', NvU32, 4), ('gsyncInstance', NvU32, 8)])
|
|
NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
component: int
|
|
size: int
|
|
struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS.register_fields([('component', NvU32, 0), ('size', NvU32, 4)])
|
|
NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pBuffer: ctypes.c_void_p
|
|
component: int
|
|
size: int
|
|
struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS.register_fields([('pBuffer', NvP64, 0), ('component', NvU32, 8), ('size', NvU32, 12)])
|
|
NV0000_CTRL_NVD_GET_DUMP_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
timestamp: int
|
|
cpuClkId: int
|
|
struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS.register_fields([('timestamp', NvU64, 0), ('cpuClkId', NvU8, 8)])
|
|
NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS(c.Struct):
|
|
SIZE = 15404
|
|
component: int
|
|
version: int
|
|
runtimeSizes: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
printFlags: int
|
|
signature: c.Array[ctypes.c_uint32, Literal[4]]
|
|
bufferTags: c.Array[ctypes.c_uint32, Literal[3840]]
|
|
struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS.register_fields([('component', NvU32, 0), ('version', NvU32, 4), ('runtimeSizes', c.Array[NvU8, Literal[16]], 8), ('printFlags', NvU32, 24), ('signature', c.Array[NvU32, Literal[4]], 28), ('bufferTags', c.Array[NvU32, Literal[3840]], 44)])
|
|
NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
component: int
|
|
buffer: int
|
|
tag: int
|
|
size: int
|
|
flags: int
|
|
pos: int
|
|
overflow: int
|
|
struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS.register_fields([('component', NvU32, 0), ('buffer', NvU32, 4), ('tag', NvU32, 8), ('size', NvU32, 12), ('flags', NvU32, 16), ('pos', NvU32, 20), ('overflow', NvU32, 24)])
|
|
NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS(c.Struct):
|
|
SIZE = 4016
|
|
component: int
|
|
buffer: int
|
|
blockNum: int
|
|
size: int
|
|
data: c.Array[ctypes.c_ubyte, Literal[4000]]
|
|
struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS.register_fields([('component', NvU32, 0), ('buffer', NvU32, 4), ('blockNum', NvU32, 8), ('size', NvU32, 12), ('data', c.Array[NvU8, Literal[4000]], 16)])
|
|
NV0000_CTRL_NVD_GET_NVLOG_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY(c.Struct):
|
|
SIZE = 12
|
|
tag: int
|
|
value: int
|
|
attribute: int
|
|
struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY.register_fields([('tag', NvU32, 0), ('value', NvU32, 4), ('attribute', NvU32, 8)])
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY: TypeAlias = struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS(c.Struct):
|
|
SIZE = 2436
|
|
reqIdx: int
|
|
rptIdx: int
|
|
GPUTag: int
|
|
rptTime: int
|
|
startIdx: int
|
|
endIdx: int
|
|
rptType: int
|
|
flags: int
|
|
rptCount: int
|
|
owner: int
|
|
processId: int
|
|
report: c.Array[struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY, Literal[200]]
|
|
struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS.register_fields([('reqIdx', NvU16, 0), ('rptIdx', NvU16, 2), ('GPUTag', NvU32, 4), ('rptTime', NvU32, 8), ('startIdx', NvU16, 12), ('endIdx', NvU16, 14), ('rptType', NvU16, 16), ('flags', NvU32, 20), ('rptCount', NvU16, 24), ('owner', NvU32, 28), ('processId', NvU32, 32), ('report', c.Array[NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY, Literal[200]], 36)])
|
|
NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS: TypeAlias = struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
tsBufferSize: int
|
|
pTSBuffer: ctypes.c_void_p
|
|
struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS.register_fields([('tsBufferSize', NvU32, 0), ('pTSBuffer', NvP64, 8)])
|
|
NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS(c.Struct):
|
|
SIZE = 104
|
|
subProcessID: int
|
|
subProcessName: c.Array[ctypes.c_char, Literal[100]]
|
|
struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS.register_fields([('subProcessID', NvU32, 0), ('subProcessName', c.Array[ctypes.c_char, Literal[100]], 4)])
|
|
NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS: TypeAlias = struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bIsSubProcessDisabled: int
|
|
struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS.register_fields([('bIsSubProcessDisabled', NvBool, 0)])
|
|
NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS: TypeAlias = struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS
|
|
@c.record
|
|
class struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnabled: int
|
|
struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS.register_fields([('bEnabled', NvBool, 0)])
|
|
NV0000_SYNC_GPU_BOOST_INFO_PARAMS: TypeAlias = struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG(c.Struct):
|
|
SIZE = 140
|
|
gpuCount: int
|
|
gpuIds: c.Array[ctypes.c_uint32, Literal[32]]
|
|
boostGroupId: int
|
|
bBridgeless: int
|
|
struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG.register_fields([('gpuCount', NvU32, 0), ('gpuIds', c.Array[NvU32, Literal[32]], 4), ('boostGroupId', NvU32, 132), ('bBridgeless', NvBool, 136)])
|
|
NV0000_SYNC_GPU_BOOST_GROUP_CONFIG: TypeAlias = struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG
|
|
@c.record
|
|
class struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS(c.Struct):
|
|
SIZE = 140
|
|
boostConfig: struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG
|
|
struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS.register_fields([('boostConfig', NV0000_SYNC_GPU_BOOST_GROUP_CONFIG, 0)])
|
|
NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS: TypeAlias = struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
boostGroupId: int
|
|
struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS.register_fields([('boostGroupId', NvU32, 0)])
|
|
NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS: TypeAlias = struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS
|
|
@c.record
|
|
class struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS(c.Struct):
|
|
SIZE = 2244
|
|
groupCount: int
|
|
pBoostGroups: c.Array[struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG, Literal[16]]
|
|
struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS.register_fields([('groupCount', NvU32, 0), ('pBoostGroups', c.Array[NV0000_SYNC_GPU_BOOST_GROUP_CONFIG, Literal[16]], 4)])
|
|
NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS: TypeAlias = struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
featuresMask: int
|
|
struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS.register_fields([('featuresMask', NvU32, 0)])
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
sizeOfStrings: int
|
|
pDriverVersionBuffer: ctypes.c_void_p
|
|
pVersionBuffer: ctypes.c_void_p
|
|
pTitleBuffer: ctypes.c_void_p
|
|
changelistNumber: int
|
|
officialChangelistNumber: int
|
|
struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS.register_fields([('sizeOfStrings', NvU32, 0), ('pDriverVersionBuffer', NvP64, 8), ('pVersionBuffer', NvP64, 16), ('pTitleBuffer', NvP64, 24), ('changelistNumber', NvU32, 32), ('officialChangelistNumber', NvU32, 36)])
|
|
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS
|
|
enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE: dict[int, str] = {(NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA:=0): 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA', (NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE:=1): 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE'}
|
|
NV0000_CTRL_SYSTEM_SH_SOC_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS(c.Struct):
|
|
SIZE = 108
|
|
type: int
|
|
capabilities: int
|
|
clock: int
|
|
L1DataCacheSize: int
|
|
L2DataCacheSize: int
|
|
dataCacheLineSize: int
|
|
numLogicalCpus: int
|
|
numPhysicalCpus: int
|
|
name: c.Array[ctypes.c_ubyte, Literal[52]]
|
|
family: int
|
|
model: int
|
|
stepping: int
|
|
coresOnDie: int
|
|
bCCEnabled: int
|
|
selfHostedSocType: int
|
|
struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS.register_fields([('type', NvU32, 0), ('capabilities', NvU32, 4), ('clock', NvU32, 8), ('L1DataCacheSize', NvU32, 12), ('L2DataCacheSize', NvU32, 16), ('dataCacheLineSize', NvU32, 20), ('numLogicalCpus', NvU32, 24), ('numPhysicalCpus', NvU32, 28), ('name', c.Array[NvU8, Literal[52]], 32), ('family', NvU32, 84), ('model', NvU32, 88), ('stepping', NvU8, 92), ('coresOnDie', NvU32, 96), ('bCCEnabled', NvBool, 100), ('selfHostedSocType', NV0000_CTRL_SYSTEM_SH_SOC_TYPE, 104)])
|
|
NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS(c.Struct):
|
|
SIZE = 156
|
|
vendorId: int
|
|
deviceId: int
|
|
subSysVendorId: int
|
|
subSysDeviceId: int
|
|
HBvendorId: int
|
|
HBdeviceId: int
|
|
HBsubSysVendorId: int
|
|
HBsubSysDeviceId: int
|
|
sliBondId: int
|
|
vendorNameString: c.Array[ctypes.c_ubyte, Literal[32]]
|
|
subSysVendorNameString: c.Array[ctypes.c_ubyte, Literal[32]]
|
|
chipsetNameString: c.Array[ctypes.c_ubyte, Literal[32]]
|
|
sliBondNameString: c.Array[ctypes.c_ubyte, Literal[32]]
|
|
flags: int
|
|
chipsetId: int
|
|
struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS.register_fields([('vendorId', NvU16, 0), ('deviceId', NvU16, 2), ('subSysVendorId', NvU16, 4), ('subSysDeviceId', NvU16, 6), ('HBvendorId', NvU16, 8), ('HBdeviceId', NvU16, 10), ('HBsubSysVendorId', NvU16, 12), ('HBsubSysDeviceId', NvU16, 14), ('sliBondId', NvU32, 16), ('vendorNameString', c.Array[NvU8, Literal[32]], 20), ('subSysVendorNameString', c.Array[NvU8, Literal[32]], 52), ('chipsetNameString', c.Array[NvU8, Literal[32]], 84), ('sliBondNameString', c.Array[NvU8, Literal[32]], 116), ('flags', NvU32, 148), ('chipsetId', NvU32, 152)])
|
|
NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bIsPresent: int
|
|
struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS.register_fields([('bIsPresent', NvBool, 0)])
|
|
NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
waitApiLock: int
|
|
holdRoApiLock: int
|
|
holdRwApiLock: int
|
|
waitGpuLock: int
|
|
holdGpuLock: int
|
|
struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS.register_fields([('waitApiLock', NvU64, 0), ('holdRoApiLock', NvU64, 8), ('holdRwApiLock', NvU64, 16), ('waitGpuLock', NvU64, 24), ('holdGpuLock', NvU64, 32)])
|
|
NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS(c.Struct):
|
|
SIZE = 132
|
|
numClasses: int
|
|
classes: c.Array[ctypes.c_uint32, Literal[32]]
|
|
struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS.register_fields([('numClasses', NvU32, 0), ('classes', c.Array[NvU32, Literal[32]], 4)])
|
|
NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
eventType: int
|
|
eventData: int
|
|
bEventDataForced: int
|
|
struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS.register_fields([('eventType', NvU32, 0), ('eventData', NvU32, 4), ('bEventDataForced', NvBool, 8)])
|
|
NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
systemType: int
|
|
struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS.register_fields([('systemType', NvU32, 0)])
|
|
NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS: TypeAlias = struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS(c.Struct):
|
|
SIZE = 520
|
|
cmd: int
|
|
count: int
|
|
data: c.Array[ctypes.c_ubyte, Literal[512]]
|
|
struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS.register_fields([('cmd', NvU32, 0), ('count', NvU32, 4), ('data', c.Array[NvU8, Literal[512]], 8)])
|
|
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
command: int
|
|
locale: int
|
|
data: int
|
|
struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS.register_fields([('command', NvU16, 0), ('locale', NvU16, 2), ('data', NvU32, 4)])
|
|
NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 136
|
|
cmdCount: int
|
|
succeeded: int
|
|
cmdData: c.Array[struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_cmdData, Literal[16]]
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_cmdData(c.Struct):
|
|
SIZE = 8
|
|
command: int
|
|
locale: int
|
|
data: int
|
|
struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_cmdData.register_fields([('command', NvU16, 0), ('locale', NvU16, 2), ('data', NvU32, 4)])
|
|
struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS.register_fields([('cmdCount', NvU32, 0), ('succeeded', NvU32, 4), ('cmdData', c.Array[struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_cmdData, Literal[16]], 8)])
|
|
NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS(c.Struct):
|
|
SIZE = 176
|
|
gpuIds: c.Array[ctypes.c_uint32, Literal[32]]
|
|
gpuCount: int
|
|
p2pCaps: int
|
|
p2pOptimalReadCEs: int
|
|
p2pOptimalWriteCEs: int
|
|
p2pCapsStatus: c.Array[ctypes.c_ubyte, Literal[9]]
|
|
busPeerIds: ctypes.c_void_p
|
|
busEgmPeerIds: ctypes.c_void_p
|
|
struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS.register_fields([('gpuIds', c.Array[NvU32, Literal[32]], 0), ('gpuCount', NvU32, 128), ('p2pCaps', NvU32, 132), ('p2pOptimalReadCEs', NvU32, 136), ('p2pOptimalWriteCEs', NvU32, 140), ('p2pCapsStatus', c.Array[NvU8, Literal[9]], 144), ('busPeerIds', NvP64, 160), ('busEgmPeerIds', NvP64, 168)])
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 8348
|
|
gpuIds: c.Array[ctypes.c_uint32, Literal[32]]
|
|
gpuCount: int
|
|
p2pCaps: int
|
|
p2pOptimalReadCEs: int
|
|
p2pOptimalWriteCEs: int
|
|
p2pCapsStatus: c.Array[ctypes.c_ubyte, Literal[9]]
|
|
busPeerIds: c.Array[ctypes.c_uint32, Literal[1024]]
|
|
busEgmPeerIds: c.Array[ctypes.c_uint32, Literal[1024]]
|
|
struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS.register_fields([('gpuIds', c.Array[NvU32, Literal[32]], 0), ('gpuCount', NvU32, 128), ('p2pCaps', NvU32, 132), ('p2pOptimalReadCEs', NvU32, 136), ('p2pOptimalWriteCEs', NvU32, 140), ('p2pCapsStatus', c.Array[NvU8, Literal[9]], 144), ('busPeerIds', c.Array[NvU32, Literal[1024]], 156), ('busEgmPeerIds', c.Array[NvU32, Literal[1024]], 4252)])
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS(c.Struct):
|
|
SIZE = 1352
|
|
grpACount: int
|
|
grpBCount: int
|
|
gpuIdGrpA: c.Array[ctypes.c_uint32, Literal[8]]
|
|
gpuIdGrpB: c.Array[ctypes.c_uint32, Literal[8]]
|
|
p2pCaps: c.Array[c.Array[ctypes.c_uint32, Literal[8]], Literal[8]]
|
|
a2bOptimalReadCes: c.Array[c.Array[ctypes.c_uint32, Literal[8]], Literal[8]]
|
|
a2bOptimalWriteCes: c.Array[c.Array[ctypes.c_uint32, Literal[8]], Literal[8]]
|
|
b2aOptimalReadCes: c.Array[c.Array[ctypes.c_uint32, Literal[8]], Literal[8]]
|
|
b2aOptimalWriteCes: c.Array[c.Array[ctypes.c_uint32, Literal[8]], Literal[8]]
|
|
struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS.register_fields([('grpACount', NvU32, 0), ('grpBCount', NvU32, 4), ('gpuIdGrpA', c.Array[NvU32, Literal[8]], 8), ('gpuIdGrpB', c.Array[NvU32, Literal[8]], 40), ('p2pCaps', c.Array[c.Array[NvU32, Literal[8]], Literal[8]], 72), ('a2bOptimalReadCes', c.Array[c.Array[NvU32, Literal[8]], Literal[8]], 328), ('a2bOptimalWriteCes', c.Array[c.Array[NvU32, Literal[8]], Literal[8]], 584), ('b2aOptimalReadCes', c.Array[c.Array[NvU32, Literal[8]], Literal[8]], 840), ('b2aOptimalWriteCes', c.Array[c.Array[NvU32, Literal[8]], Literal[8]], 1096)])
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
cmd: int
|
|
input: c.Array[ctypes.c_int32, Literal[2]]
|
|
result: c.Array[ctypes.c_int32, Literal[4]]
|
|
struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS.register_fields([('cmd', NvU32, 0), ('input', c.Array[NvS32, Literal[2]], 4), ('result', c.Array[NvS32, Literal[4]], 12)])
|
|
NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 148
|
|
objHndl: int
|
|
blockId: int
|
|
nextExpectedSampleTimems: int
|
|
countersReq: int
|
|
countersReturned: int
|
|
counterBlock: c.Array[ctypes.c_uint32, Literal[32]]
|
|
struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS.register_fields([('objHndl', NvU32, 0), ('blockId', NvU32, 4), ('nextExpectedSampleTimems', NvU32, 8), ('countersReq', NvU32, 12), ('countersReturned', NvU32, 16), ('counterBlock', c.Array[NvU32, Literal[32]], 20)])
|
|
NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS
|
|
NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS
|
|
NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS(c.Struct):
|
|
SIZE = 1164
|
|
cmd: int
|
|
input: int
|
|
resultSz: int
|
|
result: c.Array[ctypes.c_uint32, Literal[288]]
|
|
struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS.register_fields([('cmd', NvU32, 0), ('input', NvU32, 4), ('resultSz', NvU32, 8), ('result', c.Array[NvU32, Literal[288]], 12)])
|
|
NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
method: int
|
|
inData: ctypes.c_void_p
|
|
inDataSize: int
|
|
outStatus: int
|
|
outData: ctypes.c_void_p
|
|
outDataSize: int
|
|
struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS.register_fields([('method', NvU32, 0), ('inData', NvP64, 8), ('inDataSize', NvU16, 16), ('outStatus', NvU32, 20), ('outData', NvP64, 24), ('outDataSize', NvU16, 32)])
|
|
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
moduleMask: int
|
|
struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS.register_fields([('moduleMask', NvU32, 0)])
|
|
NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE(c.Struct):
|
|
SIZE = 8
|
|
frameTime: int
|
|
renderTime: int
|
|
targetTime: int
|
|
sleepTime: int
|
|
sampleNumber: int
|
|
struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE.register_fields([('frameTime', NvU16, 0), ('renderTime', NvU16, 2), ('targetTime', NvU16, 4), ('sleepTime', NvU8, 6), ('sampleNumber', NvU8, 7)])
|
|
NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS(c.Struct):
|
|
SIZE = 514
|
|
samples: c.Array[struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE, Literal[64]]
|
|
nextSampleNumber: int
|
|
struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS.register_fields([('samples', c.Array[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE, Literal[64]], 0), ('nextSampleNumber', NvU8, 512)])
|
|
NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
sampleData: struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE
|
|
struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS.register_fields([('sampleData', NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE, 0)])
|
|
NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS(c.Struct):
|
|
SIZE = 1288
|
|
szHostDriverVersionBuffer: c.Array[ctypes.c_char, Literal[256]]
|
|
szHostVersionBuffer: c.Array[ctypes.c_char, Literal[256]]
|
|
szHostTitleBuffer: c.Array[ctypes.c_char, Literal[256]]
|
|
szPluginTitleBuffer: c.Array[ctypes.c_char, Literal[256]]
|
|
szHostUnameBuffer: c.Array[ctypes.c_char, Literal[256]]
|
|
iHostChangelistNumber: int
|
|
iPluginChangelistNumber: int
|
|
struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS.register_fields([('szHostDriverVersionBuffer', c.Array[ctypes.c_char, Literal[256]], 0), ('szHostVersionBuffer', c.Array[ctypes.c_char, Literal[256]], 256), ('szHostTitleBuffer', c.Array[ctypes.c_char, Literal[256]], 512), ('szPluginTitleBuffer', c.Array[ctypes.c_char, Literal[256]], 768), ('szHostUnameBuffer', c.Array[ctypes.c_char, Literal[256]], 1024), ('iHostChangelistNumber', NvU32, 1280), ('iPluginChangelistNumber', NvU32, 1284)])
|
|
NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS(c.Struct):
|
|
SIZE = 65
|
|
gpuCount: int
|
|
gpuBus: c.Array[ctypes.c_ubyte, Literal[32]]
|
|
gpuExternalPowerStatus: c.Array[ctypes.c_ubyte, Literal[32]]
|
|
struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS.register_fields([('gpuCount', NvU8, 0), ('gpuBus', c.Array[NvU8, Literal[32]], 1), ('gpuExternalPowerStatus', c.Array[NvU8, Literal[32]], 33)])
|
|
NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
privStatusFlags: int
|
|
struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS.register_fields([('privStatusFlags', NvU8, 0)])
|
|
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS
|
|
enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS: dict[int, str] = {(NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP:=1): 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP', (NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED:=2): 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED', (NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS:=3): 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS', (NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED:=4): 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED'}
|
|
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
fabricStatus: int
|
|
struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS.register_fields([('fabricStatus', NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS, 0)])
|
|
NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
host_min_supported_version: int
|
|
host_max_supported_version: int
|
|
user_min_supported_version: int
|
|
user_max_supported_version: int
|
|
struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS.register_fields([('host_min_supported_version', NvU32, 0), ('host_max_supported_version', NvU32, 4), ('user_min_supported_version', NvU32, 8), ('user_max_supported_version', NvU32, 12)])
|
|
NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS: TypeAlias = struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
min_version: int
|
|
max_version: int
|
|
struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS.register_fields([('min_version', NvU32, 0), ('max_version', NvU32, 4)])
|
|
NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS: TypeAlias = struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
rm_instance_id: int
|
|
struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS.register_fields([('rm_instance_id', NvU64, 0)])
|
|
NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT(c.Struct):
|
|
SIZE = 24
|
|
batteryStateOfChargePercent: int
|
|
batteryCurrentLimitmA: int
|
|
restOfSytemReservedPowermW: int
|
|
minCpuTdpmW: int
|
|
maxCpuTdpmW: int
|
|
shortTimescaleBatteryCurrentLimitmA: int
|
|
struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT.register_fields([('batteryStateOfChargePercent', NvU8, 0), ('batteryCurrentLimitmA', NvU32, 4), ('restOfSytemReservedPowermW', NvU32, 8), ('minCpuTdpmW', NvU32, 12), ('maxCpuTdpmW', NvU32, 16), ('shortTimescaleBatteryCurrentLimitmA', NvU32, 20)])
|
|
NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT: TypeAlias = struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT
|
|
enum_QBOOST_CPU_TDP_CONTROL_TYPE: dict[int, str] = {(QBOOST_CPU_TDP_CONTROL_TYPE_DC_ONLY:=0): 'QBOOST_CPU_TDP_CONTROL_TYPE_DC_ONLY', (QBOOST_CPU_TDP_CONTROL_TYPE_DC_AC:=1): 'QBOOST_CPU_TDP_CONTROL_TYPE_DC_AC'}
|
|
QBOOST_CPU_TDP_CONTROL_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS(c.Struct):
|
|
SIZE = 884
|
|
supportedFuncs: int
|
|
gpuId: int
|
|
tpp: int
|
|
ratedTgp: int
|
|
subFunc: int
|
|
ctgpOffsetmW: int
|
|
targetTppOffsetmW: int
|
|
maxOutputOffsetmW: int
|
|
minOutputOffsetmW: int
|
|
ctgpBattOffsetmW: int
|
|
targetTppBattOffsetmW: int
|
|
maxOutputBattOffsetmW: int
|
|
minOutputBattOffsetmW: int
|
|
dcRosReserveOverridemW: int
|
|
dcTspLongTimescaleLimitmA: int
|
|
dcTspLongTimescaleLimitOverridemA: int
|
|
dcTspShortTimescaleLimitmA: int
|
|
dcTspShortTimescaleLimitOverridemA: int
|
|
bEnableForAC: int
|
|
bEnableForDC: int
|
|
version: int
|
|
samplingPeriodmS: int
|
|
samplingMulti: int
|
|
filterType: int
|
|
filterParam: struct_NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam
|
|
filterReserved: int
|
|
bIsBoostController: int
|
|
incRatio: int
|
|
decRatio: int
|
|
bSupportBatt: int
|
|
cpuType: int
|
|
gpuType: int
|
|
sysPwrIndex: int
|
|
sysPwrGetInfo: c.Array[struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT, Literal[32]]
|
|
bIsTspSupported: int
|
|
sysPwrLimitsTableVersion: int
|
|
type: int
|
|
cpuTdpmw: int
|
|
cpuTdpControlType: int
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam(c.Struct):
|
|
SIZE = 1
|
|
weight: int
|
|
windowSize: int
|
|
struct_NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam.register_fields([('weight', NvU8, 0), ('windowSize', NvU8, 0)])
|
|
struct_NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS.register_fields([('supportedFuncs', NvU32, 0), ('gpuId', NvU32, 4), ('tpp', NvU32, 8), ('ratedTgp', NvU32, 12), ('subFunc', NvU32, 16), ('ctgpOffsetmW', NvS32, 20), ('targetTppOffsetmW', NvS32, 24), ('maxOutputOffsetmW', NvS32, 28), ('minOutputOffsetmW', NvS32, 32), ('ctgpBattOffsetmW', NvS32, 36), ('targetTppBattOffsetmW', NvS32, 40), ('maxOutputBattOffsetmW', NvS32, 44), ('minOutputBattOffsetmW', NvS32, 48), ('dcRosReserveOverridemW', NvU32, 52), ('dcTspLongTimescaleLimitmA', NvU32, 56), ('dcTspLongTimescaleLimitOverridemA', NvU32, 60), ('dcTspShortTimescaleLimitmA', NvU32, 64), ('dcTspShortTimescaleLimitOverridemA', NvU32, 68), ('bEnableForAC', NvBool, 72), ('bEnableForDC', NvBool, 73), ('version', NvU8, 74), ('samplingPeriodmS', NvU16, 76), ('samplingMulti', NvU16, 78), ('filterType', NvU8, 80), ('filterParam', struct_NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam, 81), ('filterReserved', NvU16, 82), ('bIsBoostController', NvBool, 84), ('incRatio', NvU16, 86), ('decRatio', NvU16, 88), ('bSupportBatt', NvBool, 90), ('cpuType', NvU8, 91), ('gpuType', NvU8, 92), ('sysPwrIndex', NvU32, 96), ('sysPwrGetInfo', c.Array[NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT, Literal[32]], 100), ('bIsTspSupported', NvBool, 868), ('sysPwrLimitsTableVersion', NvU8, 869), ('type', NvU32, 872), ('cpuTdpmw', NvU32, 876), ('cpuTdpControlType', QBOOST_CPU_TDP_CONTROL_TYPE, 880)])
|
|
NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bExternalFabricMgmt: int
|
|
struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS.register_fields([('bExternalFabricMgmt', NvBool, 0)])
|
|
NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS: TypeAlias = struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
clientCount: int
|
|
resourceCount: int
|
|
struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS.register_fields([('clientCount', NvU32, 0), ('resourceCount', NvU64, 8)])
|
|
NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS(c.Struct):
|
|
SIZE = 1032
|
|
driverVersionBuffer: c.Array[ctypes.c_char, Literal[256]]
|
|
versionBuffer: c.Array[ctypes.c_char, Literal[256]]
|
|
driverBranch: c.Array[ctypes.c_char, Literal[256]]
|
|
titleBuffer: c.Array[ctypes.c_char, Literal[256]]
|
|
changelistNumber: int
|
|
officialChangelistNumber: int
|
|
struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS.register_fields([('driverVersionBuffer', c.Array[ctypes.c_char, Literal[256]], 0), ('versionBuffer', c.Array[ctypes.c_char, Literal[256]], 256), ('driverBranch', c.Array[ctypes.c_char, Literal[256]], 512), ('titleBuffer', c.Array[ctypes.c_char, Literal[256]], 768), ('changelistNumber', NvU32, 1024), ('officialChangelistNumber', NvU32, 1028)])
|
|
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
cmd: int
|
|
mode: int
|
|
struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS.register_fields([('cmd', NvU32, 0), ('mode', NvU32, 4)])
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
command: int
|
|
locale: int
|
|
data: int
|
|
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS.register_fields([('command', NvU16, 0), ('locale', NvU16, 2), ('data', NvU32, 4)])
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 136
|
|
cmdCount: int
|
|
succeeded: int
|
|
cmdData: c.Array[struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_cmdData, Literal[16]]
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_cmdData(c.Struct):
|
|
SIZE = 8
|
|
command: int
|
|
locale: int
|
|
data: int
|
|
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_cmdData.register_fields([('command', NvU16, 0), ('locale', NvU16, 2), ('data', NvU32, 4)])
|
|
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS.register_fields([('cmdCount', NvU32, 0), ('succeeded', NvU32, 4), ('cmdData', c.Array[struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_cmdData, Literal[16]], 8)])
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
cmd: int
|
|
input: c.Array[ctypes.c_int32, Literal[2]]
|
|
result: c.Array[ctypes.c_int32, Literal[4]]
|
|
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS.register_fields([('cmd', NvU32, 0), ('input', c.Array[NvS32, Literal[2]], 4), ('result', c.Array[NvS32, Literal[4]], 12)])
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 148
|
|
objHndl: int
|
|
blockId: int
|
|
nextExpectedSampleTimems: int
|
|
countersReq: int
|
|
countersReturned: int
|
|
counterBlock: c.Array[ctypes.c_uint32, Literal[32]]
|
|
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS.register_fields([('objHndl', NvU32, 0), ('blockId', NvU32, 4), ('nextExpectedSampleTimems', NvU32, 8), ('countersReq', NvU32, 12), ('countersReturned', NvU32, 16), ('counterBlock', c.Array[NvU32, Literal[32]], 20)])
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS(c.Struct):
|
|
SIZE = 1164
|
|
cmd: int
|
|
input: int
|
|
resultSz: int
|
|
result: c.Array[ctypes.c_uint32, Literal[288]]
|
|
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS.register_fields([('cmd', NvU32, 0), ('input', NvU32, 4), ('resultSz', NvU32, 8), ('result', c.Array[NvU32, Literal[288]], 12)])
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE(c.Struct):
|
|
SIZE = 8
|
|
frameTime: int
|
|
renderTime: int
|
|
targetTime: int
|
|
sleepTime: int
|
|
sampleNumber: int
|
|
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE.register_fields([('frameTime', NvU16, 0), ('renderTime', NvU16, 2), ('targetTime', NvU16, 4), ('sleepTime', NvU8, 6), ('sampleNumber', NvU8, 7)])
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS(c.Struct):
|
|
SIZE = 514
|
|
samples: c.Array[struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE, Literal[64]]
|
|
nextSampleNumber: int
|
|
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS.register_fields([('samples', c.Array[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE, Literal[64]], 0), ('nextSampleNumber', NvU8, 512)])
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
sampleData: struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE
|
|
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS.register_fields([('sampleData', NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE, 0)])
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_READ_CPER_PARAMS(c.Struct):
|
|
SIZE = 1056
|
|
cperTypeMask: int
|
|
uuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
cperCursor: int
|
|
buffer: c.Array[ctypes.c_ubyte, Literal[1024]]
|
|
bufferSize: int
|
|
struct_NV0000_CTRL_SYSTEM_READ_CPER_PARAMS.register_fields([('cperTypeMask', NvU64, 0), ('uuid', c.Array[NvU8, Literal[16]], 8), ('cperCursor', NvU32, 24), ('buffer', c.Array[NvU8, Literal[1024]], 28), ('bufferSize', NvU32, 1052)])
|
|
NV0000_CTRL_SYSTEM_READ_CPER_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_READ_CPER_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_SOC_PERF_LIMIT(c.Struct):
|
|
SIZE = 12
|
|
minLevelOrFreqKHz: int
|
|
maxLevelOrFreqKHz: int
|
|
clientUsageId: int
|
|
bwResource: int
|
|
struct_NV0000_CTRL_SYSTEM_SOC_PERF_LIMIT.register_fields([('minLevelOrFreqKHz', NvU32, 0), ('maxLevelOrFreqKHz', NvU32, 4), ('clientUsageId', NvU8, 8), ('bwResource', NvU8, 9)])
|
|
NV0000_CTRL_SYSTEM_SOC_PERF_LIMIT: TypeAlias = struct_NV0000_CTRL_SYSTEM_SOC_PERF_LIMIT
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMITS_PARAMS(c.Struct):
|
|
SIZE = 200
|
|
numLimits: int
|
|
limits: c.Array[struct_NV0000_CTRL_SYSTEM_SOC_PERF_LIMIT, Literal[16]]
|
|
bWaitForCompletion: int
|
|
struct_NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMITS_PARAMS.register_fields([('numLimits', NvU32, 0), ('limits', c.Array[NV0000_CTRL_SYSTEM_SOC_PERF_LIMIT, Literal[16]], 4), ('bWaitForCompletion', NvBool, 196)])
|
|
NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMITS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMITS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
offset: int
|
|
length: int
|
|
cacheOps: int
|
|
hDevice: int
|
|
hObject: int
|
|
internalOnly: int
|
|
struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS.register_fields([('offset', NvU64, 0), ('length', NvU64, 8), ('cacheOps', NvU32, 16), ('hDevice', NvHandle, 20), ('hObject', NvHandle, 24), ('internalOnly', NvU64, 32)])
|
|
NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
fd: int
|
|
struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS.register_fields([('fd', NvS32, 0)])
|
|
NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS
|
|
enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE: dict[int, str] = {(NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE:=0): 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE', (NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM:=1): 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM'}
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT(c.Struct):
|
|
SIZE = 16
|
|
type: int
|
|
data: struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data(c.Struct):
|
|
SIZE = 12
|
|
rmObject: struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data_rmObject
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data_rmObject(c.Struct):
|
|
SIZE = 12
|
|
hDevice: int
|
|
hParent: int
|
|
hObject: int
|
|
struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data_rmObject.register_fields([('hDevice', NvHandle, 0), ('hParent', NvHandle, 4), ('hObject', NvHandle, 8)])
|
|
struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data.register_fields([('rmObject', struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data_rmObject, 0)])
|
|
struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT.register_fields([('type', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE, 0), ('data', struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data, 4)])
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT: TypeAlias = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
object: struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT
|
|
fd: int
|
|
flags: int
|
|
struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS.register_fields([('object', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT, 0), ('fd', NvS32, 16), ('flags', NvU32, 20)])
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
fd: int
|
|
object: struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT
|
|
struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS.register_fields([('fd', NvS32, 0), ('object', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT, 4)])
|
|
NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpuId: int
|
|
minorNum: int
|
|
struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS.register_fields([('gpuId', NvU32, 0), ('minorNum', NvU32, 4)])
|
|
NV0000_CTRL_OS_GET_GPU_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
fd: int
|
|
deviceInstance: int
|
|
gpuInstanceId: int
|
|
maxObjects: int
|
|
metadata: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS.register_fields([('fd', NvS32, 0), ('deviceInstance', NvU32, 4), ('gpuInstanceId', NvU32, 8), ('maxObjects', NvU16, 12), ('metadata', c.Array[NvU8, Literal[64]], 14)])
|
|
NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS(c.Struct):
|
|
SIZE = 76
|
|
hDevice: int
|
|
maxObjects: int
|
|
metadata: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
fd: int
|
|
struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS.register_fields([('hDevice', NvHandle, 0), ('maxObjects', NvU16, 4), ('metadata', c.Array[NvU8, Literal[64]], 6), ('fd', NvS32, 72)])
|
|
NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS(c.Struct):
|
|
SIZE = 2128
|
|
fd: int
|
|
hDevice: int
|
|
maxObjects: int
|
|
metadata: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
objects: c.Array[ctypes.c_uint32, Literal[512]]
|
|
numObjects: int
|
|
index: int
|
|
struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS.register_fields([('fd', NvS32, 0), ('hDevice', NvHandle, 4), ('maxObjects', NvU16, 8), ('metadata', c.Array[NvU8, Literal[64]], 10), ('objects', c.Array[NvHandle, Literal[512]], 76), ('numObjects', NvU16, 2124), ('index', NvU16, 2126)])
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS(c.Struct):
|
|
SIZE = 652
|
|
fd: int
|
|
hParent: int
|
|
objects: c.Array[ctypes.c_uint32, Literal[128]]
|
|
objectTypes: c.Array[ctypes.c_ubyte, Literal[128]]
|
|
numObjects: int
|
|
index: int
|
|
struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS.register_fields([('fd', NvS32, 0), ('hParent', NvHandle, 4), ('objects', c.Array[NvHandle, Literal[128]], 8), ('objectTypes', c.Array[NvU8, Literal[128]], 520), ('numObjects', NvU16, 648), ('index', NvU16, 650)])
|
|
NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_MEMACCT_SET_LIMITS_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
cgroupFd: int
|
|
gpuId: int
|
|
softLimit: int
|
|
hardLimit: int
|
|
struct_NV0000_CTRL_OS_UNIX_MEMACCT_SET_LIMITS_PARAMS.register_fields([('cgroupFd', NvS32, 0), ('gpuId', NvU32, 4), ('softLimit', NvU64, 8), ('hardLimit', NvU64, 16)])
|
|
NV0000_CTRL_OS_UNIX_MEMACCT_SET_LIMITS_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_MEMACCT_SET_LIMITS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_MEMACCT_LIMITS(c.Struct):
|
|
SIZE = 32
|
|
gpuId: int
|
|
soft: int
|
|
hard: int
|
|
current: int
|
|
struct_NV0000_CTRL_OS_UNIX_MEMACCT_LIMITS.register_fields([('gpuId', NvU32, 0), ('soft', NvU64, 8), ('hard', NvU64, 16), ('current', NvU64, 24)])
|
|
NV0000_CTRL_OS_UNIX_MEMACCT_LIMITS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_MEMACCT_LIMITS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_MEMACCT_GET_LIMITS_PARAMS(c.Struct):
|
|
SIZE = 1032
|
|
cgroupFd: int
|
|
count: int
|
|
limits: c.Array[struct_NV0000_CTRL_OS_UNIX_MEMACCT_LIMITS, Literal[32]]
|
|
struct_NV0000_CTRL_OS_UNIX_MEMACCT_GET_LIMITS_PARAMS.register_fields([('cgroupFd', NvS32, 0), ('count', NvU32, 4), ('limits', c.Array[NV0000_CTRL_OS_UNIX_MEMACCT_LIMITS, Literal[32]], 8)])
|
|
NV0000_CTRL_OS_UNIX_MEMACCT_GET_LIMITS_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_MEMACCT_GET_LIMITS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
vgpuName: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
gpuPciId: int
|
|
gpuPciBdf: int
|
|
vgpuTypeId: int
|
|
vgpuId: int
|
|
gpuInstanceId: int
|
|
placementId: int
|
|
struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS.register_fields([('vgpuName', c.Array[NvU8, Literal[16]], 0), ('gpuPciId', NvU32, 16), ('gpuPciBdf', NvU32, 20), ('vgpuTypeId', NvU32, 24), ('vgpuId', NvU16, 28), ('gpuInstanceId', NvU32, 32), ('placementId', NvU32, 36)])
|
|
NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS: TypeAlias = struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS(c.Struct):
|
|
SIZE = 1036
|
|
gpuPciId: int
|
|
gpuPciBdf: int
|
|
numVgpuTypes: int
|
|
vgpuTypeIds: c.Array[ctypes.c_uint32, Literal[128]]
|
|
availableInstances: c.Array[ctypes.c_uint32, Literal[128]]
|
|
struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS.register_fields([('gpuPciId', NvU32, 0), ('gpuPciBdf', NvU32, 4), ('numVgpuTypes', NvU32, 8), ('vgpuTypeIds', c.Array[NvU32, Literal[128]], 12), ('availableInstances', c.Array[NvU32, Literal[128]], 524)])
|
|
NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS: TypeAlias = struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS(c.Struct):
|
|
SIZE = 18
|
|
vgpuName: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
vgpuId: int
|
|
struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS.register_fields([('vgpuName', c.Array[NvU8, Literal[16]], 0), ('vgpuId', NvU16, 16)])
|
|
NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS: TypeAlias = struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
returnStatus: int
|
|
gpuId: int
|
|
struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS.register_fields([('returnStatus', NvU32, 0), ('gpuId', NvU32, 4)])
|
|
NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS: TypeAlias = struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
vgpuName: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
mode: int
|
|
sysfs_val: int
|
|
struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS.register_fields([('vgpuName', c.Array[NvU8, Literal[16]], 0), ('mode', NvU32, 16), ('sysfs_val', NvU32, 20)])
|
|
NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_BIF_RESET_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
flags: int
|
|
struct_NV0080_CTRL_BIF_RESET_PARAMS.register_fields([('flags', NvU32, 0)])
|
|
NV0080_CTRL_BIF_RESET_PARAMS: TypeAlias = struct_NV0080_CTRL_BIF_RESET_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bL0sEnable: int
|
|
bL1Enable: int
|
|
struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS.register_fields([('bL0sEnable', NvBool, 0), ('bL1Enable', NvBool, 1)])
|
|
NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS: TypeAlias = struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
pciePowerControlMask: int
|
|
pciePowerControlIdentifiedKeyOrder: int
|
|
pciePowerControlIdentifiedKeyLocation: int
|
|
struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS.register_fields([('pciePowerControlMask', NvU32, 0), ('pciePowerControlIdentifiedKeyOrder', NvU32, 4), ('pciePowerControlIdentifiedKeyLocation', NvU32, 8)])
|
|
NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS: TypeAlias = struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK(c.Struct):
|
|
SIZE = 32
|
|
pageSize: int
|
|
pteEntrySize: int
|
|
comptagLine: int
|
|
kind: int
|
|
pteFlags: int
|
|
struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK.register_fields([('pageSize', NvU64, 0), ('pteEntrySize', NvU64, 8), ('comptagLine', NvU32, 16), ('kind', NvU32, 20), ('pteFlags', NvU32, 24)])
|
|
NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK: TypeAlias = struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS(c.Struct):
|
|
SIZE = 184
|
|
gpuAddr: int
|
|
subDeviceId: int
|
|
skipVASpaceInit: int
|
|
pteBlocks: c.Array[struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK, Literal[5]]
|
|
hVASpace: int
|
|
struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS.register_fields([('gpuAddr', NvU64, 0), ('subDeviceId', NvU32, 8), ('skipVASpaceInit', NvU8, 12), ('pteBlocks', c.Array[NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK, Literal[5]], 16), ('hVASpace', NvHandle, 176)])
|
|
NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS(c.Struct):
|
|
SIZE = 184
|
|
gpuAddr: int
|
|
subDeviceId: int
|
|
pteBlocks: c.Array[struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK, Literal[5]]
|
|
hVASpace: int
|
|
struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS.register_fields([('gpuAddr', NvU64, 0), ('subDeviceId', NvU32, 8), ('pteBlocks', c.Array[NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK, Literal[5]], 16), ('hVASpace', NvHandle, 176)])
|
|
NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS(c.Struct):
|
|
SIZE = 104
|
|
pageCount: int
|
|
hwResource: struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource
|
|
comprInfo: struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo
|
|
offset: int
|
|
gpuAddr: int
|
|
pageArray: ctypes.c_void_p
|
|
pteMem: ctypes.c_void_p
|
|
pteMemPfn: int
|
|
pageSize: int
|
|
startPageIndex: int
|
|
flags: int
|
|
hSrcVASpace: int
|
|
hTgtVASpace: int
|
|
peerId: int
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource(c.Struct):
|
|
SIZE = 16
|
|
hClient: int
|
|
hDevice: int
|
|
hMemory: int
|
|
subDeviceId: int
|
|
struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('hMemory', NvHandle, 8), ('subDeviceId', NvU32, 12)])
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo(c.Struct):
|
|
SIZE = 12
|
|
fbKind: int
|
|
sysKind: int
|
|
compTagStartOffset: int
|
|
struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo.register_fields([('fbKind', NvU32, 0), ('sysKind', NvU32, 4), ('compTagStartOffset', NvU32, 8)])
|
|
struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS.register_fields([('pageCount', NvU32, 0), ('hwResource', struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource, 4), ('comprInfo', struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo, 20), ('offset', NvU64, 32), ('gpuAddr', NvU64, 40), ('pageArray', NvP64, 48), ('pteMem', NvP64, 56), ('pteMemPfn', NvU32, 64), ('pageSize', NvU32, 68), ('startPageIndex', NvU32, 72), ('flags', NvU64, 80), ('hSrcVASpace', NvHandle, 88), ('hTgtVASpace', NvHandle, 92), ('peerId', NvU32, 96)])
|
|
NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_FLUSH_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
targetUnit: int
|
|
struct_NV0080_CTRL_DMA_FLUSH_PARAMS.register_fields([('targetUnit', NvU32, 0)])
|
|
NV0080_CTRL_DMA_FLUSH_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_FLUSH_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT(c.Struct):
|
|
SIZE = 8
|
|
pageTableSize: int
|
|
pageTableCoverage: int
|
|
struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT.register_fields([('pageTableSize', NvU32, 0), ('pageTableCoverage', NvU32, 4)])
|
|
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT: TypeAlias = struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS(c.Struct):
|
|
SIZE = 192
|
|
vaBitCount: int
|
|
pdeCoverageBitCount: int
|
|
num4KPageTableFormats: int
|
|
bigPageSize: int
|
|
compressionPageSize: int
|
|
dualPageTableSupported: int
|
|
idealVRAMPageSize: int
|
|
pageTableBigFormat: struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT
|
|
pageTable4KFormat: c.Array[struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT, Literal[16]]
|
|
hVASpace: int
|
|
vaRangeLo: int
|
|
vaSpaceId: int
|
|
supportedPageSizeMask: int
|
|
struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS.register_fields([('vaBitCount', NvU32, 0), ('pdeCoverageBitCount', NvU32, 4), ('num4KPageTableFormats', NvU32, 8), ('bigPageSize', NvU32, 12), ('compressionPageSize', NvU32, 16), ('dualPageTableSupported', NvU32, 20), ('idealVRAMPageSize', NvU32, 24), ('pageTableBigFormat', NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT, 28), ('pageTable4KFormat', c.Array[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT, Literal[16]], 36), ('hVASpace', NvHandle, 164), ('vaRangeLo', NvU64, 168), ('vaSpaceId', NvU32, 176), ('supportedPageSizeMask', NvU64, 184)])
|
|
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK(c.Struct):
|
|
SIZE = 32
|
|
ptePhysAddr: int
|
|
pteCacheAttrib: int
|
|
pteEntrySize: int
|
|
pageSize: int
|
|
pteAddrSpace: int
|
|
pdeVASpaceSize: int
|
|
pdeFlags: int
|
|
struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK.register_fields([('ptePhysAddr', NvU64, 0), ('pteCacheAttrib', NvU32, 8), ('pteEntrySize', NvU32, 12), ('pageSize', NvU32, 16), ('pteAddrSpace', NvU32, 20), ('pdeVASpaceSize', NvU32, 24), ('pdeFlags', NvU32, 28)])
|
|
NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK: TypeAlias = struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS(c.Struct):
|
|
SIZE = 208
|
|
gpuAddr: int
|
|
pdeVirtAddr: int
|
|
pdeEntrySize: int
|
|
pdeAddrSpace: int
|
|
pdeSize: int
|
|
subDeviceId: int
|
|
pteBlocks: c.Array[struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK, Literal[5]]
|
|
pdbAddr: int
|
|
hVASpace: int
|
|
struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS.register_fields([('gpuAddr', NvU64, 0), ('pdeVirtAddr', NvU64, 8), ('pdeEntrySize', NvU32, 16), ('pdeAddrSpace', NvU32, 20), ('pdeSize', NvU32, 24), ('subDeviceId', NvU32, 28), ('pteBlocks', c.Array[NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK, Literal[5]], 32), ('pdbAddr', NvU64, 192), ('hVASpace', NvHandle, 200)])
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hVASpace: int
|
|
flags: int
|
|
struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS.register_fields([('hVASpace', NvHandle, 0), ('flags', NvU32, 4)])
|
|
NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
capsTblSize: int
|
|
capsTbl: c.Array[ctypes.c_ubyte, Literal[8]]
|
|
struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS.register_fields([('capsTblSize', NvU32, 0), ('capsTbl', c.Array[NvU8, Literal[8]], 4)])
|
|
NV0080_CTRL_DMA_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
vaSpaceSize: int
|
|
hVASpace: int
|
|
struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS.register_fields([('vaSpaceSize', NvU64, 0), ('hVASpace', NvHandle, 8)])
|
|
NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
physAddr: int
|
|
numEntries: int
|
|
aperture: int
|
|
struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS.register_fields([('physAddr', NvU64, 0), ('numEntries', NvU32, 8), ('aperture', NvU32, 12)])
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(c.Struct):
|
|
SIZE = 64
|
|
pdeIndex: int
|
|
flags: int
|
|
ptParams: c.Array[struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS, Literal[2]]
|
|
hVASpace: int
|
|
pPdeBuffer: ctypes.c_void_p
|
|
subDeviceId: int
|
|
struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS.register_fields([('pdeIndex', NvU32, 0), ('flags', NvU32, 4), ('ptParams', c.Array[NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS, Literal[2]], 8), ('hVASpace', NvHandle, 40), ('pPdeBuffer', NvP64, 48), ('subDeviceId', NvU32, 56)])
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hVASpace: int
|
|
struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS.register_fields([('hVASpace', NvHandle, 0)])
|
|
NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
physAddress: int
|
|
numEntries: int
|
|
flags: int
|
|
hVASpace: int
|
|
chId: int
|
|
subDeviceId: int
|
|
pasid: int
|
|
struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS.register_fields([('physAddress', NvU64, 0), ('numEntries', NvU32, 8), ('flags', NvU32, 12), ('hVASpace', NvHandle, 16), ('chId', NvU32, 20), ('subDeviceId', NvU32, 24), ('pasid', NvU32, 28)])
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hVASpace: int
|
|
subDeviceId: int
|
|
struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS.register_fields([('hVASpace', NvHandle, 0), ('subDeviceId', NvU32, 4)])
|
|
NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FB_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
capsTblSize: int
|
|
capsTbl: ctypes.c_void_p
|
|
struct_NV0080_CTRL_FB_GET_CAPS_PARAMS.register_fields([('capsTblSize', NvU32, 0), ('capsTbl', NvP64, 8)])
|
|
NV0080_CTRL_FB_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_FB_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
Size: int
|
|
Address: int
|
|
AddressSpace: int
|
|
MaxCompbitLine: int
|
|
comptagsPerCacheLine: int
|
|
cacheLineSize: int
|
|
cacheLineSizePerSlice: int
|
|
cacheLineFetchAlignment: int
|
|
backingStoreBase: int
|
|
gobsPerComptagPerSlice: int
|
|
backingStoreCbcBase: int
|
|
comptaglineAllocationPolicy: int
|
|
privRegionStartOffset: int
|
|
cbcCoveragePerSlice: int
|
|
struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS.register_fields([('Size', NvU64, 0), ('Address', NvU64, 8), ('AddressSpace', NvU32, 16), ('MaxCompbitLine', NvU32, 20), ('comptagsPerCacheLine', NvU32, 24), ('cacheLineSize', NvU32, 28), ('cacheLineSizePerSlice', NvU32, 32), ('cacheLineFetchAlignment', NvU32, 36), ('backingStoreBase', NvU64, 40), ('gobsPerComptagPerSlice', NvU32, 48), ('backingStoreCbcBase', NvU32, 52), ('comptaglineAllocationPolicy', NvU32, 56), ('privRegionStartOffset', NvU64, 64), ('cbcCoveragePerSlice', NvU32, 72)])
|
|
NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS: TypeAlias = struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
capsTbl: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS.register_fields([('capsTbl', c.Array[NvU8, Literal[3]], 0)])
|
|
NV0080_CTRL_FB_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
value: int
|
|
struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS.register_fields([('value', NvU32, 0)])
|
|
NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS: TypeAlias = struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS
|
|
enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY: dict[int, str] = {(NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT:=0): 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT', (NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS:=1): 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS', (NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS:=2): 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS', (NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS:=3): 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS'}
|
|
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
capsTblSize: int
|
|
capsTbl: ctypes.c_void_p
|
|
struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS.register_fields([('capsTblSize', NvU32, 0), ('capsTbl', NvP64, 8)])
|
|
NV0080_CTRL_FIFO_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
engineId: int
|
|
alignment: int
|
|
size: int
|
|
struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS.register_fields([('engineId', NvU32, 0), ('alignment', NvU32, 4), ('size', NvU32, 8)])
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
numChannels: int
|
|
pChannelHandleList: ctypes.c_void_p
|
|
pChannelList: ctypes.c_void_p
|
|
struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS.register_fields([('numChannels', NvU32, 0), ('pChannelHandleList', NvP64, 8), ('pChannelList', NvP64, 16)])
|
|
NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
engineID: int
|
|
gpEntries: int
|
|
pbEntries: int
|
|
struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS.register_fields([('engineID', NvU32, 0), ('gpEntries', NvU32, 4), ('pbEntries', NvU32, 8)])
|
|
NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hChannel: int
|
|
property: int
|
|
value: int
|
|
struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS.register_fields([('hChannel', NvHandle, 0), ('property', NvU32, 4), ('value', NvU64, 8)])
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
engineID: int
|
|
struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS.register_fields([('engineID', NvU32, 0)])
|
|
NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
engineID: int
|
|
struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS.register_fields([('engineID', NvU32, 0)])
|
|
NV0080_CTRL_FIFO_START_RUNLIST_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
capsTbl: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS.register_fields([('capsTbl', c.Array[NvU8, Literal[2]], 0)])
|
|
NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 16396
|
|
numChannels: int
|
|
hChannels: c.Array[ctypes.c_uint32, Literal[4096]]
|
|
flags: int
|
|
timeout: int
|
|
struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS.register_fields([('numChannels', NvU32, 0), ('hChannels', c.Array[NvHandle, Literal[4096]], 4), ('flags', NvU32, 16388), ('timeout', NvU32, 16392)])
|
|
NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
numClasses: int
|
|
classList: ctypes.c_void_p
|
|
struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS.register_fields([('numClasses', NvU32, 0), ('classList', NvP64, 8)])
|
|
NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
numSubDevices: int
|
|
struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS.register_fields([('numSubDevices', NvU32, 0)])
|
|
NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS(c.Struct):
|
|
SIZE = 36
|
|
ConnectionCount: int
|
|
Order: c.Array[ctypes.c_uint32, Literal[8]]
|
|
struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS.register_fields([('ConnectionCount', NvU32, 0), ('Order', c.Array[NvU32, Literal[8]], 4)])
|
|
NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
subDeviceInstance: int
|
|
struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS.register_fields([('subDeviceInstance', NvU32, 0)])
|
|
NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
subDeviceInstance: int
|
|
struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS.register_fields([('subDeviceInstance', NvU32, 0)])
|
|
NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
enable: int
|
|
struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS.register_fields([('enable', NvU32, 0)])
|
|
NV0080_CTRL_GPU_SET_VIDLINK_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
newState: int
|
|
struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS.register_fields([('newState', NvU32, 0)])
|
|
NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
swStatePersistence: int
|
|
struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS.register_fields([('swStatePersistence', NvU32, 0)])
|
|
NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
virtualizationMode: int
|
|
isGridBuild: int
|
|
struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS.register_fields([('virtualizationMode', NvU32, 0), ('isGridBuild', NvBool, 4)])
|
|
NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
defaultSetting: int
|
|
currentSetting: int
|
|
pendingSetting: int
|
|
struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS.register_fields([('defaultSetting', NvU32, 0), ('currentSetting', NvU32, 4), ('pendingSetting', NvU32, 8)])
|
|
NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
setting: int
|
|
struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS.register_fields([('setting', NvU32, 0)])
|
|
NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
isVgx: int
|
|
struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS.register_fields([('isVgx', NvBool, 0)])
|
|
NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
totalVFs: int
|
|
firstVfOffset: int
|
|
vfFeatureMask: int
|
|
FirstVFBar0Address: int
|
|
FirstVFBar1Address: int
|
|
FirstVFBar2Address: int
|
|
bar0Size: int
|
|
bar1Size: int
|
|
bar2Size: int
|
|
b64bitBar0: int
|
|
b64bitBar1: int
|
|
b64bitBar2: int
|
|
bSriovEnabled: int
|
|
bSriovHeavyEnabled: int
|
|
bEmulateVFBar0TlbInvalidationRegister: int
|
|
bClientRmAllocatedCtxBuffer: int
|
|
bNonPowerOf2ChannelCountSupported: int
|
|
bVfResizableBAR1Supported: int
|
|
struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS.register_fields([('totalVFs', NvU32, 0), ('firstVfOffset', NvU32, 4), ('vfFeatureMask', NvU32, 8), ('FirstVFBar0Address', NvU64, 16), ('FirstVFBar1Address', NvU64, 24), ('FirstVFBar2Address', NvU64, 32), ('bar0Size', NvU64, 40), ('bar1Size', NvU64, 48), ('bar2Size', NvU64, 56), ('b64bitBar0', NvBool, 64), ('b64bitBar1', NvBool, 65), ('b64bitBar2', NvBool, 66), ('bSriovEnabled', NvBool, 67), ('bSriovHeavyEnabled', NvBool, 68), ('bEmulateVFBar0TlbInvalidationRegister', NvBool, 69), ('bClientRmAllocatedCtxBuffer', NvBool, 70), ('bNonPowerOf2ChannelCountSupported', NvBool, 71), ('bVfResizableBAR1Supported', NvBool, 72)])
|
|
NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS(c.Struct):
|
|
SIZE = 804
|
|
numClasses: int
|
|
classList: c.Array[ctypes.c_uint32, Literal[200]]
|
|
struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS.register_fields([('numClasses', NvU32, 0), ('classList', c.Array[NvU32, Literal[200]], 4)])
|
|
NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM(c.Struct):
|
|
SIZE = 8
|
|
subDeviceInst: int
|
|
hSubDevice: int
|
|
struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM.register_fields([('subDeviceInst', NvU32, 0), ('hSubDevice', NvHandle, 4)])
|
|
NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM: TypeAlias = struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
brands: int
|
|
struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS.register_fields([('brands', NvU32, 0)])
|
|
NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
vfBar1SizeMB: int
|
|
numVfs: int
|
|
struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS.register_fields([('vfBar1SizeMB', NvU32, 0), ('numVfs', NvU32, 4)])
|
|
NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bHeterogeneousMode: int
|
|
gpuInstanceId: int
|
|
struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS.register_fields([('bHeterogeneousMode', NvBool, 0), ('gpuInstanceId', NvU32, 4)])
|
|
NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bHeterogeneousMode: int
|
|
gpuInstanceId: int
|
|
struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS.register_fields([('bHeterogeneousMode', NvBool, 0), ('gpuInstanceId', NvU32, 4)])
|
|
NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GR_ROUTE_INFO(c.Struct):
|
|
SIZE = 16
|
|
flags: int
|
|
route: int
|
|
struct_NV0080_CTRL_GR_ROUTE_INFO.register_fields([('flags', NvU32, 0), ('route', NvU64, 8)])
|
|
NV0080_CTRL_GR_ROUTE_INFO: TypeAlias = struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
@c.record
|
|
class struct_NV0080_CTRL_GR_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
capsTblSize: int
|
|
capsTbl: ctypes.c_void_p
|
|
struct_NV0080_CTRL_GR_GET_CAPS_PARAMS.register_fields([('capsTblSize', NvU32, 0), ('capsTbl', NvP64, 8)])
|
|
NV0080_CTRL_GR_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NVXXXX_CTRL_XXX_INFO(c.Struct):
|
|
SIZE = 8
|
|
index: int
|
|
data: int
|
|
NV0080_CTRL_GR_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
struct_NVXXXX_CTRL_XXX_INFO.register_fields([('index', NvU32, 0), ('data', NvU32, 4)])
|
|
@c.record
|
|
class struct_NV0080_CTRL_GR_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
grInfoListSize: int
|
|
grInfoList: ctypes.c_void_p
|
|
struct_NV0080_CTRL_GR_GET_INFO_PARAMS.register_fields([('grInfoListSize', NvU32, 0), ('grInfoList', NvP64, 8)])
|
|
NV0080_CTRL_GR_GET_INFO_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_GET_INFO_PARAMS
|
|
enum_NV0080_CTRL_GR_TPC_PARTITION_MODE: dict[int, str] = {(NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE:=0): 'NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE', (NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC:=1): 'NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC', (NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC:=2): 'NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC'}
|
|
NV0080_CTRL_GR_TPC_PARTITION_MODE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hChannelGroup: int
|
|
mode: int
|
|
bEnableAllTpcs: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS.register_fields([('hChannelGroup', NvHandle, 0), ('mode', NV0080_CTRL_GR_TPC_PARTITION_MODE, 4), ('bEnableAllTpcs', NvBool, 8), ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO, 16)])
|
|
NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
|
|
NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
|
|
NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
capsTbl: c.Array[ctypes.c_ubyte, Literal[23]]
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
bCapsPopulated: int
|
|
struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS.register_fields([('capsTbl', c.Array[NvU8, Literal[23]], 0), ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO, 24), ('bCapsPopulated', NvBool, 40)])
|
|
NV0080_CTRL_GR_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 528
|
|
grInfoListSize: int
|
|
grInfoList: c.Array[struct_NVXXXX_CTRL_XXX_INFO, Literal[63]]
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS.register_fields([('grInfoListSize', NvU32, 0), ('grInfoList', c.Array[NV0080_CTRL_GR_INFO, Literal[63]], 4), ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO, 512)])
|
|
NV0080_CTRL_GR_GET_INFO_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
capsTblSize: int
|
|
capsTbl: ctypes.c_void_p
|
|
struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS.register_fields([('capsTblSize', NvU32, 0), ('capsTbl', NvP64, 8)])
|
|
NV0080_CTRL_HOST_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
capsTbl: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS.register_fields([('capsTbl', c.Array[NvU8, Literal[3]], 0)])
|
|
NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
params: struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
|
|
struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS.register_fields([('params', NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS, 0)])
|
|
NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS: TypeAlias = struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
params: struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
|
|
struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS.register_fields([('params', NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS, 0)])
|
|
NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS: TypeAlias = struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 804
|
|
numClients: int
|
|
clientHandles: c.Array[ctypes.c_uint32, Literal[200]]
|
|
struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS.register_fields([('numClients', NvU32, 0), ('clientHandles', c.Array[NvHandle, Literal[200]], 4)])
|
|
NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS: TypeAlias = struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bZbcSurfacesExist: int
|
|
struct_NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS.register_fields([('bZbcSurfacesExist', NvBool, 0)])
|
|
NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS: TypeAlias = struct_NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bTeardown: int
|
|
struct_NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS.register_fields([('bTeardown', NvBool, 0)])
|
|
NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS: TypeAlias = struct_NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS
|
|
NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS: TypeAlias = struct_NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_NVDEC_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
capsTblSize: int
|
|
capsTbl: ctypes.c_void_p
|
|
instanceId: int
|
|
struct_NV0080_CTRL_NVDEC_GET_CAPS_PARAMS.register_fields([('capsTblSize', NvU32, 0), ('capsTbl', NvP64, 8), ('instanceId', NvU32, 16)])
|
|
NV0080_CTRL_NVDEC_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_NVDEC_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_V2(c.Struct):
|
|
SIZE = 12
|
|
capsTbl: c.Array[ctypes.c_ubyte, Literal[8]]
|
|
instanceId: int
|
|
struct_NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_V2.register_fields([('capsTbl', c.Array[NvU8, Literal[8]], 0), ('instanceId', NvU32, 8)])
|
|
NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_V2: TypeAlias = struct_NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_V2
|
|
@c.record
|
|
class struct_NV0080_CTRL_NVENC_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
capsTblSize: int
|
|
capsTbl: ctypes.c_void_p
|
|
struct_NV0080_CTRL_NVENC_GET_CAPS_PARAMS.register_fields([('capsTblSize', NvU32, 0), ('capsTbl', NvP64, 8)])
|
|
NV0080_CTRL_NVENC_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_NVENC_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_NVENC_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
capsTbl: c.Array[ctypes.c_ubyte, Literal[6]]
|
|
instanceId: int
|
|
struct_NV0080_CTRL_NVENC_GET_CAPS_V2_PARAMS.register_fields([('capsTbl', c.Array[NvU8, Literal[6]], 0), ('instanceId', NvU32, 8)])
|
|
NV0080_CTRL_NVENC_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_NVENC_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
capsTbl: c.Array[ctypes.c_ubyte, Literal[9]]
|
|
instanceId: int
|
|
struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS.register_fields([('capsTbl', c.Array[NvU8, Literal[9]], 0), ('instanceId', NvU32, 12)])
|
|
NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bActivate: int
|
|
struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS.register_fields([('bActivate', NvBool, 0)])
|
|
NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS: TypeAlias = struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bCudaLimit: int
|
|
struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS.register_fields([('bCudaLimit', NvBool, 0)])
|
|
NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS: TypeAlias = struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
cmd: int
|
|
struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS.register_fields([('cmd', NvU32, 0)])
|
|
NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS: TypeAlias = struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
subDeviceInstance: int
|
|
width: int
|
|
height: int
|
|
depth: int
|
|
pitch: int
|
|
baseAddress: int
|
|
size: int
|
|
struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS.register_fields([('subDeviceInstance', NvU32, 0), ('width', NvU16, 4), ('height', NvU16, 6), ('depth', NvU16, 8), ('pitch', NvU16, 10), ('baseAddress', NvU64, 16), ('size', NvU64, 24)])
|
|
NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS: TypeAlias = struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS
|
|
enum_NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG: dict[int, str] = {(NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_INVALID:=0): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_INVALID', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_DEVICE_CTRL_STATUS:=1): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_DEVICE_CTRL_STATUS', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_LINK_CTRL_STATUS:=2): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_LINK_CTRL_STATUS', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_DEVICE_CTRL_STATUS_2:=3): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_DEVICE_CTRL_STATUS_2', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_LINK_CAP:=4): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_LINK_CAP', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_L1_PM_SUBSTATES_CTRL1:=5): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_L1_PM_SUBSTATES_CTRL1', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_STATUS:=6): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_STATUS', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_STATUS:=7): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_STATUS', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_STATUS:=8): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_STATUS', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_MASK:=9): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_MASK', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_MASK:=10): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_MASK', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_MASK:=11): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_MASK', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_SEVERITY:=12): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_CHECK_FAILED_SEVERITY', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_SEVERITY:=13): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_MISROUTED_TLP_SEVERITY', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_SEVERITY:=14): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_PCRC_CHECK_FAILED_SEVERITY', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TLP_ENCRYPTION_STATUS:=15): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TLP_ENCRYPTION_STATUS', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_LINK_STREAM_ENABLED:=16): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_LINK_STREAM_ENABLED', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_SELECTIVE_STREAM_ENABLED:=17): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_SELECTIVE_STREAM_ENABLED', (NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_FLOW_THROUGH_STREAM_ENABLED:=18): 'NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG_FN0_IDE_TYPE_FLOW_THROUGH_STREAM_ENABLED'}
|
|
NV2080_CTRL_BIF_PARAM_ID_CONFIG_REG: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIF_GET_DATA_PARAMS(c.Struct):
|
|
SIZE = 268
|
|
featureId: int
|
|
paramId: c.Array[ctypes.c_uint32, Literal[32]]
|
|
paramVal: c.Array[ctypes.c_uint32, Literal[32]]
|
|
flags: int
|
|
paramSize: int
|
|
struct_NV2080_CTRL_BIF_GET_DATA_PARAMS.register_fields([('featureId', NvU32, 0), ('paramId', c.Array[NvU32, Literal[32]], 4), ('paramVal', c.Array[NvU32, Literal[32]], 132), ('flags', NvU32, 260), ('paramSize', NvU32, 264)])
|
|
NV2080_CTRL_BIF_GET_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_BIF_GET_DATA_PARAMS
|
|
enum_NV2080_CTRL_BIF_FEATURE_ID: dict[int, str] = {(NV2080_CTRL_BIF_FEATURE_ID_INVALID:=0): 'NV2080_CTRL_BIF_FEATURE_ID_INVALID', (NV2080_CTRL_BIF_FEATURE_ID_CONFIG_REG:=1): 'NV2080_CTRL_BIF_FEATURE_ID_CONFIG_REG'}
|
|
NV2080_CTRL_BIF_FEATURE_ID: TypeAlias = ctypes.c_uint32
|
|
NV2080_CTRL_BIOS_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
biosInfoListSize: int
|
|
biosInfoList: ctypes.c_void_p
|
|
struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS.register_fields([('biosInfoListSize', NvU32, 0), ('biosInfoList', NvP64, 8)])
|
|
NV2080_CTRL_BIOS_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 124
|
|
biosInfoListSize: int
|
|
biosInfoList: c.Array[struct_NVXXXX_CTRL_XXX_INFO, Literal[15]]
|
|
struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS.register_fields([('biosInfoListSize', NvU32, 0), ('biosInfoList', c.Array[NV2080_CTRL_BIOS_INFO, Literal[15]], 4)])
|
|
NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_NBSI_REG_STRING(c.Struct):
|
|
SIZE = 520
|
|
size: int
|
|
type: int
|
|
value: struct_NV2080_CTRL_BIOS_NBSI_REG_STRING_value
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_NBSI_REG_STRING_value(c.Struct):
|
|
SIZE = 512
|
|
ascii: c.Array[ctypes.c_ubyte, Literal[256]]
|
|
unicode: c.Array[ctypes.c_uint16, Literal[256]]
|
|
hash: int
|
|
struct_NV2080_CTRL_BIOS_NBSI_REG_STRING_value.register_fields([('ascii', c.Array[NvU8, Literal[256]], 0), ('unicode', c.Array[NvU16, Literal[256]], 0), ('hash', NvU16, 0)])
|
|
struct_NV2080_CTRL_BIOS_NBSI_REG_STRING.register_fields([('size', NvU32, 0), ('type', NvU32, 4), ('value', struct_NV2080_CTRL_BIOS_NBSI_REG_STRING_value, 8)])
|
|
NV2080_CTRL_BIOS_NBSI_REG_STRING: TypeAlias = struct_NV2080_CTRL_BIOS_NBSI_REG_STRING
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS(c.Struct):
|
|
SIZE = 1064
|
|
module: int
|
|
path: struct_NV2080_CTRL_BIOS_NBSI_REG_STRING
|
|
valueName: struct_NV2080_CTRL_BIOS_NBSI_REG_STRING
|
|
retBuf: ctypes.c_void_p
|
|
retSize: int
|
|
errorCode: int
|
|
struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS.register_fields([('module', NvU32, 0), ('path', NV2080_CTRL_BIOS_NBSI_REG_STRING, 4), ('valueName', NV2080_CTRL_BIOS_NBSI_REG_STRING, 524), ('retBuf', NvP64, 1048), ('retSize', NvU32, 1056), ('errorCode', NvU32, 1060)])
|
|
NV2080_CTRL_BIOS_GET_NBSI_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS(c.Struct):
|
|
SIZE = 1308
|
|
module: int
|
|
path: struct_NV2080_CTRL_BIOS_NBSI_REG_STRING
|
|
valueName: struct_NV2080_CTRL_BIOS_NBSI_REG_STRING
|
|
retBuf: c.Array[ctypes.c_ubyte, Literal[256]]
|
|
retSize: int
|
|
errorCode: int
|
|
struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS.register_fields([('module', NvU32, 0), ('path', NV2080_CTRL_BIOS_NBSI_REG_STRING, 4), ('valueName', NV2080_CTRL_BIOS_NBSI_REG_STRING, 524), ('retBuf', c.Array[NvU8, Literal[256]], 1044), ('retSize', NvU32, 1300), ('errorCode', NvU32, 1304)])
|
|
NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
globType: int
|
|
globIndex: int
|
|
globSource: int
|
|
retBufOffset: int
|
|
retBuf: ctypes.c_void_p
|
|
retSize: int
|
|
totalObjSize: int
|
|
errorCode: int
|
|
struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS.register_fields([('globType', NvU16, 0), ('globIndex', NvU8, 2), ('globSource', NvU16, 4), ('retBufOffset', NvU32, 8), ('retBuf', NvP64, 16), ('retSize', NvU32, 24), ('totalObjSize', NvU32, 28), ('errorCode', NvU32, 32)])
|
|
NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
BoardID: int
|
|
chipSKU: c.Array[ctypes.c_char, Literal[9]]
|
|
chipSKUMod: c.Array[ctypes.c_char, Literal[5]]
|
|
skuConfigVersion: int
|
|
project: c.Array[ctypes.c_char, Literal[5]]
|
|
projectSKU: c.Array[ctypes.c_char, Literal[5]]
|
|
CDP: c.Array[ctypes.c_char, Literal[6]]
|
|
projectSKUMod: c.Array[ctypes.c_char, Literal[2]]
|
|
businessCycle: int
|
|
struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS.register_fields([('BoardID', NvU32, 0), ('chipSKU', c.Array[ctypes.c_char, Literal[9]], 4), ('chipSKUMod', c.Array[ctypes.c_char, Literal[5]], 13), ('skuConfigVersion', NvU32, 20), ('project', c.Array[ctypes.c_char, Literal[5]], 24), ('projectSKU', c.Array[ctypes.c_char, Literal[5]], 29), ('CDP', c.Array[ctypes.c_char, Literal[6]], 34), ('projectSKUMod', c.Array[ctypes.c_char, Literal[2]], 40), ('businessCycle', NvU32, 44)])
|
|
NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
vbiosPostTime: int
|
|
struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS.register_fields([('vbiosPostTime', NvU64, 0)])
|
|
NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
version: int
|
|
flags: int
|
|
struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS.register_fields([('version', NvU32, 0), ('flags', NvU32, 4)])
|
|
NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS
|
|
NvBoardObjIdx: TypeAlias = ctypes.c_uint16
|
|
NvBoardObjMaskIdx: TypeAlias = ctypes.c_uint16
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_PRIMITIVE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJGRP_MASK(c.Struct):
|
|
SIZE = 4
|
|
pData: c.Array[ctypes.c_uint32, Literal[1]]
|
|
struct_NV2080_CTRL_BOARDOBJGRP_MASK.register_fields([('pData', c.Array[NvU32, Literal[1]], 0)])
|
|
NV2080_CTRL_BOARDOBJGRP_MASK: TypeAlias = struct_NV2080_CTRL_BOARDOBJGRP_MASK
|
|
PNV2080_CTRL_BOARDOBJGRP_MASK: TypeAlias = c.POINTER[struct_NV2080_CTRL_BOARDOBJGRP_MASK]
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJGRP_MASK_E32(c.Struct):
|
|
SIZE = 4
|
|
super: struct_NV2080_CTRL_BOARDOBJGRP_MASK
|
|
struct_NV2080_CTRL_BOARDOBJGRP_MASK_E32.register_fields([('super', NV2080_CTRL_BOARDOBJGRP_MASK, 0)])
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_E32: TypeAlias = struct_NV2080_CTRL_BOARDOBJGRP_MASK_E32
|
|
PNV2080_CTRL_BOARDOBJGRP_MASK_E32: TypeAlias = c.POINTER[struct_NV2080_CTRL_BOARDOBJGRP_MASK_E32]
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJGRP_MASK_E255(c.Struct):
|
|
SIZE = 32
|
|
super: struct_NV2080_CTRL_BOARDOBJGRP_MASK
|
|
pDataE255: c.Array[ctypes.c_uint32, Literal[7]]
|
|
struct_NV2080_CTRL_BOARDOBJGRP_MASK_E255.register_fields([('super', NV2080_CTRL_BOARDOBJGRP_MASK, 0), ('pDataE255', c.Array[NvU32, Literal[7]], 4)])
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_E255: TypeAlias = struct_NV2080_CTRL_BOARDOBJGRP_MASK_E255
|
|
PNV2080_CTRL_BOARDOBJGRP_MASK_E255: TypeAlias = c.POINTER[struct_NV2080_CTRL_BOARDOBJGRP_MASK_E255]
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJGRP_MASK_E512(c.Struct):
|
|
SIZE = 64
|
|
super: struct_NV2080_CTRL_BOARDOBJGRP_MASK
|
|
pDataE512: c.Array[ctypes.c_uint32, Literal[15]]
|
|
struct_NV2080_CTRL_BOARDOBJGRP_MASK_E512.register_fields([('super', NV2080_CTRL_BOARDOBJGRP_MASK, 0), ('pDataE512', c.Array[NvU32, Literal[15]], 4)])
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_E512: TypeAlias = struct_NV2080_CTRL_BOARDOBJGRP_MASK_E512
|
|
PNV2080_CTRL_BOARDOBJGRP_MASK_E512: TypeAlias = c.POINTER[struct_NV2080_CTRL_BOARDOBJGRP_MASK_E512]
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJGRP_MASK_E1024(c.Struct):
|
|
SIZE = 128
|
|
super: struct_NV2080_CTRL_BOARDOBJGRP_MASK
|
|
pDataE1024: c.Array[ctypes.c_uint32, Literal[31]]
|
|
struct_NV2080_CTRL_BOARDOBJGRP_MASK_E1024.register_fields([('super', NV2080_CTRL_BOARDOBJGRP_MASK, 0), ('pDataE1024', c.Array[NvU32, Literal[31]], 4)])
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_E1024: TypeAlias = struct_NV2080_CTRL_BOARDOBJGRP_MASK_E1024
|
|
PNV2080_CTRL_BOARDOBJGRP_MASK_E1024: TypeAlias = c.POINTER[struct_NV2080_CTRL_BOARDOBJGRP_MASK_E1024]
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJGRP_MASK_E2048(c.Struct):
|
|
SIZE = 256
|
|
super: struct_NV2080_CTRL_BOARDOBJGRP_MASK
|
|
pDataE2048: c.Array[ctypes.c_uint32, Literal[63]]
|
|
struct_NV2080_CTRL_BOARDOBJGRP_MASK_E2048.register_fields([('super', NV2080_CTRL_BOARDOBJGRP_MASK, 0), ('pDataE2048', c.Array[NvU32, Literal[63]], 4)])
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_E2048: TypeAlias = struct_NV2080_CTRL_BOARDOBJGRP_MASK_E2048
|
|
PNV2080_CTRL_BOARDOBJGRP_MASK_E2048: TypeAlias = c.POINTER[struct_NV2080_CTRL_BOARDOBJGRP_MASK_E2048]
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJGRP_MASK_E8192(c.Struct):
|
|
SIZE = 1024
|
|
super: struct_NV2080_CTRL_BOARDOBJGRP_MASK
|
|
pDataE8192: c.Array[ctypes.c_uint32, Literal[255]]
|
|
struct_NV2080_CTRL_BOARDOBJGRP_MASK_E8192.register_fields([('super', NV2080_CTRL_BOARDOBJGRP_MASK, 0), ('pDataE8192', c.Array[NvU32, Literal[255]], 4)])
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_E8192: TypeAlias = struct_NV2080_CTRL_BOARDOBJGRP_MASK_E8192
|
|
PNV2080_CTRL_BOARDOBJGRP_MASK_E8192: TypeAlias = c.POINTER[struct_NV2080_CTRL_BOARDOBJGRP_MASK_E8192]
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO(c.Struct):
|
|
SIZE = 1
|
|
type: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO.register_fields([('type', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS(c.Struct):
|
|
SIZE = 1
|
|
type: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS.register_fields([('type', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL(c.Struct):
|
|
SIZE = 1
|
|
type: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL.register_fields([('type', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS(c.Struct):
|
|
SIZE = 1
|
|
type: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS.register_fields([('type', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_INTERFACE(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_INTERFACE.register_fields([('rsvd', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_INTERFACE: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_INTERFACE
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_INTERFACE(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_INTERFACE.register_fields([('rsvd', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_INTERFACE: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_INTERFACE
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_INTERFACE(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_INTERFACE.register_fields([('rsvd', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_INTERFACE: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_INTERFACE
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_INTERFACE(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_INTERFACE.register_fields([('rsvd', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_INTERFACE: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_INTERFACE
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_INTERFACE
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_INTERFACE, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_20(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_20.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_20: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_20
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_20
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_20, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_INTERFACE
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_INTERFACE, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_20(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_20.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_20: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_20
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_20
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_20, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_INTERFACE
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_INTERFACE, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_20(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_20.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_20: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_20
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_20
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_20, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_INTERFACE
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_INTERFACE, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_20(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_20.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_20: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_20
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_20
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_20, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJ_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO(c.Struct):
|
|
SIZE = 1
|
|
classType: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO.register_fields([('classType', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_SUPER_ALIAS(c.Struct):
|
|
SIZE = 8
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_SUPER_ALIAS.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_SUPER_ALIAS: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_SUPER_ALIAS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS(c.Struct):
|
|
SIZE = 1
|
|
classType: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS.register_fields([('classType', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_SUPER_ALIAS(c.Struct):
|
|
SIZE = 8
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_SUPER_ALIAS.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_SUPER_ALIAS: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_SUPER_ALIAS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL(c.Struct):
|
|
SIZE = 1
|
|
classType: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL.register_fields([('classType', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_SUPER_ALIAS(c.Struct):
|
|
SIZE = 8
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_SUPER_ALIAS.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_SUPER_ALIAS: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_SUPER_ALIAS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS(c.Struct):
|
|
SIZE = 2
|
|
classType: int
|
|
bInitialized: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS.register_fields([('classType', NvU8, 0), ('bInitialized', NvBool, 1)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_SUPER_ALIAS(c.Struct):
|
|
SIZE = 8
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_SUPER_ALIAS.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_SUPER_ALIAS: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_SUPER_ALIAS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E32(c.Struct):
|
|
SIZE = 8
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E32
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E32.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E32, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E32: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E32
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E32(c.Struct):
|
|
SIZE = 8
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E32
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E32.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E32, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E32: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E32
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E32(c.Struct):
|
|
SIZE = 8
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E32
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E32.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E32, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E32: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E32
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E32(c.Struct):
|
|
SIZE = 8
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E32
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E32.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E32, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E32: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E32
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E255(c.Struct):
|
|
SIZE = 36
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E255
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E255.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E255, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E255: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E255
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E255(c.Struct):
|
|
SIZE = 36
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E255
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E255.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E255, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E255: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E255
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E255(c.Struct):
|
|
SIZE = 36
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E255
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E255.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E255, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E255: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E255
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E255(c.Struct):
|
|
SIZE = 36
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E255
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E255.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E255, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E255: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E255
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E512(c.Struct):
|
|
SIZE = 68
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E512
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E512.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E512, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E512: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E512
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E512(c.Struct):
|
|
SIZE = 68
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E512
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E512.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E512, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E512: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E512
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E512(c.Struct):
|
|
SIZE = 68
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E512
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E512.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E512, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E512: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E512
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E512(c.Struct):
|
|
SIZE = 68
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E512
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E512.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E512, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E512: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E512
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E1024(c.Struct):
|
|
SIZE = 132
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E1024
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E1024.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E1024, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E1024: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E1024
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E1024(c.Struct):
|
|
SIZE = 132
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E1024
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E1024.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E1024, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E1024: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E1024
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E1024(c.Struct):
|
|
SIZE = 132
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E1024
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E1024.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E1024, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E1024: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E1024
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E1024(c.Struct):
|
|
SIZE = 132
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E1024
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E1024.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E1024, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E1024: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E1024
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E2048(c.Struct):
|
|
SIZE = 260
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E2048
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E2048.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E2048, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E2048: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E2048
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E2048(c.Struct):
|
|
SIZE = 260
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E2048
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E2048.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E2048, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E2048: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E2048
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E2048(c.Struct):
|
|
SIZE = 260
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E2048
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E2048.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E2048, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E2048: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E2048
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E2048(c.Struct):
|
|
SIZE = 260
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E2048
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E2048.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E2048, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E2048: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E2048
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E8192(c.Struct):
|
|
SIZE = 1028
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E8192
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E8192.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E8192, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E8192: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_E8192
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E8192(c.Struct):
|
|
SIZE = 1028
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E8192
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E8192.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E8192, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E8192: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_E8192
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E8192(c.Struct):
|
|
SIZE = 1028
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E8192
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E8192.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E8192, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E8192: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_E8192
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E8192(c.Struct):
|
|
SIZE = 1028
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS
|
|
objMask: struct_NV2080_CTRL_BOARDOBJGRP_MASK_E8192
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E8192.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS, 0), ('objMask', NV2080_CTRL_BOARDOBJGRP_MASK_E8192, 4)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E8192: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_E8192
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_INTERFACE(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_INTERFACE.register_fields([('rsvd', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_INTERFACE: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_INTERFACE
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_INTERFACE
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_INTERFACE, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_20(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_20.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_20: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_20
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_20
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_20, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_INFO_IFACE_MODEL_PMU_INIT_1X
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_INTERFACE(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_INTERFACE.register_fields([('rsvd', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_INTERFACE: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_INTERFACE
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_INTERFACE
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_INTERFACE, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_20(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_20.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_20: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_20
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_20
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_20, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_STATUS_IFACE_MODEL_PMU_INIT_1X
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_INTERFACE(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_INTERFACE.register_fields([('rsvd', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_INTERFACE: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_INTERFACE
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_INTERFACE
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_INTERFACE, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_20(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_20.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_20: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_20
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_20
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_20, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_CONTROL_IFACE_MODEL_PMU_INIT_1X
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_INTERFACE(c.Struct):
|
|
SIZE = 1
|
|
rsvd: int
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_INTERFACE.register_fields([('rsvd', NvU8, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_INTERFACE: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_INTERFACE
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_INTERFACE
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_INTERFACE, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_20(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_20.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_20: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_20
|
|
@c.record
|
|
class struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X(c.Struct):
|
|
SIZE = 1
|
|
super: struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_20
|
|
struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X.register_fields([('super', NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_20, 0)])
|
|
NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X: TypeAlias = struct_NV2080_CTRL_BOARDOBJ_BOARDOBJGRP_CLIENT_READINGS_IFACE_MODEL_PMU_INIT_1X
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pciDeviceId: int
|
|
pciSubSystemId: int
|
|
pciRevisionId: int
|
|
pciExtDeviceId: int
|
|
struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS.register_fields([('pciDeviceId', NvU32, 0), ('pciSubSystemId', NvU32, 4), ('pciRevisionId', NvU32, 8), ('pciExtDeviceId', NvU32, 12)])
|
|
NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS
|
|
NV2080_CTRL_BUS_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
busInfoListSize: int
|
|
busInfoList: ctypes.c_void_p
|
|
struct_NV2080_CTRL_BUS_GET_INFO_PARAMS.register_fields([('busInfoListSize', NvU32, 0), ('busInfoList', NvP64, 8)])
|
|
NV2080_CTRL_BUS_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 420
|
|
busInfoListSize: int
|
|
busInfoList: c.Array[struct_NVXXXX_CTRL_XXX_INFO, Literal[52]]
|
|
struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS.register_fields([('busInfoListSize', NvU32, 0), ('busInfoList', c.Array[NV2080_CTRL_BUS_INFO, Literal[52]], 4)])
|
|
NV2080_CTRL_BUS_GET_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_PCI_BAR_INFO(c.Struct):
|
|
SIZE = 24
|
|
flags: int
|
|
barSize: int
|
|
barSizeBytes: int
|
|
barOffset: int
|
|
struct_NV2080_CTRL_BUS_PCI_BAR_INFO.register_fields([('flags', NvU32, 0), ('barSize', NvU32, 4), ('barSizeBytes', NvU64, 8), ('barOffset', NvU64, 16)])
|
|
NV2080_CTRL_BUS_PCI_BAR_INFO: TypeAlias = struct_NV2080_CTRL_BUS_PCI_BAR_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS(c.Struct):
|
|
SIZE = 200
|
|
pciBarCount: int
|
|
pciBarInfo: c.Array[struct_NV2080_CTRL_BUS_PCI_BAR_INFO, Literal[8]]
|
|
struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS.register_fields([('pciBarCount', NvU32, 0), ('pciBarInfo', c.Array[NV2080_CTRL_BUS_PCI_BAR_INFO, Literal[8]], 8)])
|
|
NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pcieLinkWidth: int
|
|
failingReason: int
|
|
struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS.register_fields([('pcieLinkWidth', NvU32, 0), ('failingReason', NvU32, 4)])
|
|
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
busSpeed: int
|
|
struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS.register_fields([('busSpeed', NvU32, 0)])
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hMemory: int
|
|
struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS.register_fields([('hMemory', NvHandle, 0)])
|
|
NV2080_CTRL_BUS_MAP_BAR2_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hMemory: int
|
|
struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS.register_fields([('hMemory', NvHandle, 0)])
|
|
NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hMemory: int
|
|
offset: int
|
|
size: int
|
|
struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS.register_fields([('hMemory', NvHandle, 0), ('offset', NvU32, 4), ('size', NvU32, 8)])
|
|
NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
command: int
|
|
deviceState: int
|
|
struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS.register_fields([('command', NvU8, 0), ('deviceState', NvU32, 4)])
|
|
NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 76
|
|
pexCounterMask: int
|
|
pexTotalCorrectableErrors: int
|
|
pexCorrectableErrors: int
|
|
pexTotalNonFatalErrors: int
|
|
pexTotalFatalErrors: int
|
|
pexTotalUnsupportedReqs: int
|
|
pexCounters: c.Array[ctypes.c_uint16, Literal[31]]
|
|
struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS.register_fields([('pexCounterMask', NvU32, 0), ('pexTotalCorrectableErrors', NvU32, 4), ('pexCorrectableErrors', NvU16, 8), ('pexTotalNonFatalErrors', NvU8, 10), ('pexTotalFatalErrors', NvU8, 11), ('pexTotalUnsupportedReqs', NvU8, 12), ('pexCounters', c.Array[NvU16, Literal[31]], 14)])
|
|
NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
pexCounterMask: int
|
|
struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS.register_fields([('pexCounterMask', NvU32, 0)])
|
|
NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pexCounterMask: int
|
|
bFreezeRmCounter: int
|
|
struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS.register_fields([('pexCounterMask', NvU32, 0), ('bFreezeRmCounter', NvBool, 4)])
|
|
NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 18
|
|
pexLaneErrorStatus: int
|
|
pexLaneCounter: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS.register_fields([('pexLaneErrorStatus', NvU16, 0), ('pexLaneCounter', c.Array[NvU8, Literal[16]], 2)])
|
|
NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
bPexLtrRegkeyOverride: int
|
|
bPexRootPortLtrSupported: int
|
|
bPexGpuLtrSupported: int
|
|
pexLtrSnoopLatencyValue: int
|
|
pexLtrSnoopLatencyScale: int
|
|
pexLtrNoSnoopLatencyValue: int
|
|
pexLtrNoSnoopLatencyScale: int
|
|
struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS.register_fields([('bPexLtrRegkeyOverride', NvBool, 0), ('bPexRootPortLtrSupported', NvBool, 1), ('bPexGpuLtrSupported', NvBool, 2), ('pexLtrSnoopLatencyValue', NvU16, 4), ('pexLtrSnoopLatencyScale', NvU8, 6), ('pexLtrNoSnoopLatencyValue', NvU16, 8), ('pexLtrNoSnoopLatencyScale', NvU8, 10)])
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pexLtrSnoopLatencyValue: int
|
|
pexLtrSnoopLatencyScale: int
|
|
pexLtrNoSnoopLatencyValue: int
|
|
pexLtrNoSnoopLatencyScale: int
|
|
struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS.register_fields([('pexLtrSnoopLatencyValue', NvU16, 0), ('pexLtrSnoopLatencyScale', NvU8, 2), ('pexLtrNoSnoopLatencyValue', NvU16, 4), ('pexLtrNoSnoopLatencyScale', NvU8, 6)])
|
|
NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
pexCounterMask: int
|
|
pexCounters: c.Array[ctypes.c_uint32, Literal[7]]
|
|
struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS.register_fields([('pexCounterMask', NvU32, 0), ('pexCounters', c.Array[NvU32, Literal[7]], 4)])
|
|
NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
pexCounterMask: int
|
|
struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS.register_fields([('pexCounterMask', NvU32, 0)])
|
|
NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnable: int
|
|
struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS.register_fields([('bEnable', NvBool, 0)])
|
|
NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS(c.Struct):
|
|
SIZE = 128
|
|
nvlinkPeerIdMask: c.Array[ctypes.c_uint32, Literal[32]]
|
|
struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS.register_fields([('nvlinkPeerIdMask', c.Array[NvU32, Literal[32]], 0)])
|
|
NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
eomMode: int
|
|
eomNblks: int
|
|
eomNerrs: int
|
|
struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS.register_fields([('eomMode', NvU8, 0), ('eomNblks', NvU8, 1), ('eomNerrs', NvU8, 2)])
|
|
NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
regAddress: int
|
|
laneSelectMask: int
|
|
regValue: int
|
|
struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS.register_fields([('regAddress', NvU32, 0), ('laneSelectMask', NvU32, 4), ('regValue', NvU16, 8)])
|
|
NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS(c.Struct):
|
|
SIZE = 76
|
|
eomMode: int
|
|
eomNblks: int
|
|
eomNerrs: int
|
|
eomBerEyeSel: int
|
|
eomPamEyeSel: int
|
|
laneMask: int
|
|
eomStatus: c.Array[ctypes.c_uint16, Literal[32]]
|
|
struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS.register_fields([('eomMode', NvU8, 0), ('eomNblks', NvU8, 1), ('eomNerrs', NvU8, 2), ('eomBerEyeSel', NvU8, 3), ('eomPamEyeSel', NvU8, 4), ('laneMask', NvU32, 8), ('eomStatus', c.Array[NvU16, Literal[32]], 12)])
|
|
NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
capType: int
|
|
dbdf: int
|
|
atomicsCaps: int
|
|
struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS.register_fields([('capType', NvU32, 0), ('dbdf', NvU32, 4), ('atomicsCaps', NvU32, 8)])
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO(c.Struct):
|
|
SIZE = 8
|
|
bSupported: int
|
|
attributes: int
|
|
struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO.register_fields([('bSupported', NvBool, 0), ('attributes', NvU32, 4)])
|
|
NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO: TypeAlias = struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS(c.Struct):
|
|
SIZE = 112
|
|
capType: int
|
|
dbdf: int
|
|
atomicOp: c.Array[struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO, Literal[13]]
|
|
struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS.register_fields([('capType', NvU32, 0), ('dbdf', NvU32, 4), ('atomicOp', c.Array[NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO, Literal[13]], 8)])
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
bIsLinkUp: int
|
|
bLinkInHS: int
|
|
bEncryptionEnabled: int
|
|
nrLinks: int
|
|
maxNrLinks: int
|
|
linkMask: int
|
|
perLinkBwMBps: int
|
|
perLinkLaneWidth: int
|
|
remoteType: int
|
|
struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS.register_fields([('bIsLinkUp', NvBool, 0), ('bLinkInHS', NvBool, 1), ('bEncryptionEnabled', NvBool, 2), ('nrLinks', NvU32, 4), ('maxNrLinks', NvU32, 8), ('linkMask', NvU32, 12), ('perLinkBwMBps', NvU32, 16), ('perLinkLaneWidth', NvU32, 20), ('remoteType', NvU32, 24)])
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bDisable: int
|
|
struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS.register_fields([('bDisable', NvBool, 0)])
|
|
NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS(c.Struct):
|
|
SIZE = 168
|
|
errCnts: c.Array[struct_NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_errCnt, Literal[14]]
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_errCnt(c.Struct):
|
|
SIZE = 12
|
|
nrCrcErrIntr: int
|
|
nrReplayErrIntr: int
|
|
nrReplayB2bErrIntr: int
|
|
struct_NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_errCnt.register_fields([('nrCrcErrIntr', NvU32, 0), ('nrReplayErrIntr', NvU32, 4), ('nrReplayB2bErrIntr', NvU32, 8)])
|
|
struct_NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS.register_fields([('errCnts', c.Array[struct_NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_errCnt, Literal[14]], 0)])
|
|
NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
connectionType: int
|
|
peerId: int
|
|
bEgmPeer: int
|
|
bSpaAccessOnly: int
|
|
bUseUuid: int
|
|
remoteGpuId: int
|
|
remoteGpuUuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS.register_fields([('connectionType', NvU32, 0), ('peerId', NvU32, 4), ('bEgmPeer', NvBool, 8), ('bSpaAccessOnly', NvBool, 9), ('bUseUuid', NvBool, 10), ('remoteGpuId', NvU32, 12), ('remoteGpuUuid', c.Array[NvU8, Literal[16]], 16)])
|
|
NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
connectionType: int
|
|
peerId: int
|
|
bUseUuid: int
|
|
remoteGpuId: int
|
|
remoteGpuUuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS.register_fields([('connectionType', NvU32, 0), ('peerId', NvU32, 4), ('bUseUuid', NvBool, 8), ('remoteGpuId', NvU32, 12), ('remoteGpuUuid', c.Array[NvU8, Literal[16]], 16)])
|
|
NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
atomicsCaps: int
|
|
struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS.register_fields([('atomicsCaps', NvU32, 0)])
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS(c.Struct):
|
|
SIZE = 88
|
|
c2cStateSupportMask: int
|
|
bCl3Support: int
|
|
cl3EntryCount: int
|
|
cl3ExitCount: int
|
|
cl3ResidentTimeUs: int
|
|
cl3AvgEntryLatencyUs: int
|
|
cl3AvgExitLatencyUs: int
|
|
cl3PstateSupportMask: int
|
|
cl3DisallowReasonMask: int
|
|
bCl4Support: int
|
|
cl4EntryCount: int
|
|
cl4ExitCount: int
|
|
cl4ResidentTimeUs: int
|
|
cl4AvgEntryLatencyUs: int
|
|
cl4AvgExitLatencyUs: int
|
|
cl4PstateSupportMask: int
|
|
cl4DisallowReasonMask: int
|
|
c2cLpwrStateAllowedMask: int
|
|
localPowerState: int
|
|
remotePowerState: int
|
|
cl3IdleThresholdUs: int
|
|
cl4IdleThresholdUs: int
|
|
struct_NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS.register_fields([('c2cStateSupportMask', NvU32, 0), ('bCl3Support', NvBool, 4), ('cl3EntryCount', NvU32, 8), ('cl3ExitCount', NvU32, 12), ('cl3ResidentTimeUs', NvU32, 16), ('cl3AvgEntryLatencyUs', NvU32, 20), ('cl3AvgExitLatencyUs', NvU32, 24), ('cl3PstateSupportMask', NvU32, 28), ('cl3DisallowReasonMask', NvU32, 32), ('bCl4Support', NvBool, 36), ('cl4EntryCount', NvU32, 40), ('cl4ExitCount', NvU32, 44), ('cl4ResidentTimeUs', NvU32, 48), ('cl4AvgEntryLatencyUs', NvU32, 52), ('cl4AvgExitLatencyUs', NvU32, 56), ('cl4PstateSupportMask', NvU32, 60), ('cl4DisallowReasonMask', NvU32, 64), ('c2cLpwrStateAllowedMask', NvU32, 68), ('localPowerState', NvU32, 72), ('remotePowerState', NvU32, 76), ('cl3IdleThresholdUs', NvU32, 80), ('cl4IdleThresholdUs', NvU32, 84)])
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
c2cLpwrStateId: int
|
|
bAllowed: int
|
|
struct_NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS.register_fields([('c2cLpwrStateId', NvU32, 0), ('bAllowed', NvBool, 4)])
|
|
NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
c2cLpwrStateId: int
|
|
idleThresholdUs: int
|
|
struct_NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS.register_fields([('c2cLpwrStateId', NvU32, 0), ('idleThresholdUs', NvU32, 4)])
|
|
NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
packetCounters: c.Array[ctypes.c_uint32, Literal[14]]
|
|
struct_NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS.register_fields([('packetCounters', c.Array[NvU32, Literal[14]], 0)])
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
ceEngineType: int
|
|
capsTblSize: int
|
|
capsTbl: ctypes.c_void_p
|
|
struct_NV2080_CTRL_CE_GET_CAPS_PARAMS.register_fields([('ceEngineType', NvU32, 0), ('capsTblSize', NvU32, 4), ('capsTbl', NvP64, 8)])
|
|
NV2080_CTRL_CE_GET_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
ceEngineType: int
|
|
capsTbl: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS.register_fields([('ceEngineType', NvU32, 0), ('capsTbl', c.Array[NvU8, Literal[2]], 4)])
|
|
NV2080_CTRL_CE_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
ceEngineType: int
|
|
pceMask: int
|
|
struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS.register_fields([('ceEngineType', NvU32, 0), ('pceMask', NvU32, 4)])
|
|
NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 276
|
|
ceEngineType: int
|
|
pceLceMap: c.Array[ctypes.c_uint32, Literal[64]]
|
|
grceSharedLceMap: c.Array[ctypes.c_uint32, Literal[4]]
|
|
struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS.register_fields([('ceEngineType', NvU32, 0), ('pceLceMap', c.Array[NvU32, Literal[64]], 4), ('grceSharedLceMap', c.Array[NvU32, Literal[4]], 260)])
|
|
NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS(c.Struct):
|
|
SIZE = 280
|
|
pceLceMap: c.Array[ctypes.c_uint32, Literal[64]]
|
|
grceConfig: c.Array[ctypes.c_uint32, Literal[4]]
|
|
exposeCeMask: int
|
|
bUpdateNvlinkPceLce: int
|
|
struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS.register_fields([('pceLceMap', c.Array[NvU32, Literal[64]], 0), ('grceConfig', c.Array[NvU32, Literal[4]], 256), ('exposeCeMask', NvU32, 272), ('bUpdateNvlinkPceLce', NvBool, 276)])
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
stubbedCeMask: int
|
|
struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS.register_fields([('stubbedCeMask', NvU32, 0)])
|
|
NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS
|
|
NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
size: int
|
|
struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS.register_fields([('size', NvU32, 0)])
|
|
NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS(c.Struct):
|
|
SIZE = 132
|
|
hshubPceMasks: c.Array[ctypes.c_uint32, Literal[32]]
|
|
fbhubPceMask: int
|
|
struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS.register_fields([('hshubPceMasks', c.Array[NvU32, Literal[32]], 0), ('fbhubPceMask', NvU32, 128)])
|
|
NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS(c.Struct):
|
|
SIZE = 136
|
|
capsTbl: c.Array[c.Array[ctypes.c_ubyte, Literal[2]], Literal[64]]
|
|
present: int
|
|
struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS.register_fields([('capsTbl', c.Array[c.Array[NvU8, Literal[2]], Literal[64]], 0), ('present', NvU64, 128)])
|
|
NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
|
|
NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
ceEngineType: int
|
|
shimInstance: int
|
|
shimLocalLceIdx: int
|
|
struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS.register_fields([('ceEngineType', NvU32, 0), ('shimInstance', NvU32, 4), ('shimLocalLceIdx', NvU32, 8)])
|
|
NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS(c.Struct):
|
|
SIZE = 284
|
|
pceLceMap: c.Array[ctypes.c_uint32, Literal[64]]
|
|
grceConfig: c.Array[ctypes.c_uint32, Literal[4]]
|
|
exposeCeMask: int
|
|
bUpdateNvlinkPceLce: int
|
|
shimInstance: int
|
|
struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS.register_fields([('pceLceMap', c.Array[NvU32, Literal[64]], 0), ('grceConfig', c.Array[NvU32, Literal[4]], 256), ('exposeCeMask', NvU32, 272), ('bUpdateNvlinkPceLce', NvBool, 276), ('shimInstance', NvU32, 280)])
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS(c.Struct):
|
|
SIZE = 136
|
|
connectingHubPceMasks: c.Array[ctypes.c_uint32, Literal[32]]
|
|
fbhubPceMask: int
|
|
shimInstance: int
|
|
struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS.register_fields([('connectingHubPceMasks', c.Array[NvU32, Literal[32]], 0), ('fbhubPceMask', NvU32, 128), ('shimInstance', NvU32, 132)])
|
|
NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS
|
|
enum_NV2080_CTRL_CE_LCE_TYPE: dict[int, str] = {(NV2080_CTRL_CE_LCE_TYPE_PCIE:=1): 'NV2080_CTRL_CE_LCE_TYPE_PCIE', (NV2080_CTRL_CE_LCE_TYPE_DECOMP:=2): 'NV2080_CTRL_CE_LCE_TYPE_DECOMP', (NV2080_CTRL_CE_LCE_TYPE_SCRUB:=3): 'NV2080_CTRL_CE_LCE_TYPE_SCRUB', (NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER:=4): 'NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER', (NV2080_CTRL_CE_LCE_TYPE_C2C:=5): 'NV2080_CTRL_CE_LCE_TYPE_C2C', (NV2080_CTRL_CE_LCE_TYPE_PCIE_RD:=6): 'NV2080_CTRL_CE_LCE_TYPE_PCIE_RD', (NV2080_CTRL_CE_LCE_TYPE_PCIE_WR:=7): 'NV2080_CTRL_CE_LCE_TYPE_PCIE_WR', (NV2080_CTRL_CE_LCE_TYPE_C2C_H2D:=8): 'NV2080_CTRL_CE_LCE_TYPE_C2C_H2D', (NV2080_CTRL_CE_LCE_TYPE_C2C_D2H:=9): 'NV2080_CTRL_CE_LCE_TYPE_C2C_D2H', (NV2080_CTRL_CE_LCE_TYPE_CC_WORK_SUBMIT:=10): 'NV2080_CTRL_CE_LCE_TYPE_CC_WORK_SUBMIT'}
|
|
NV2080_CTRL_CE_LCE_TYPE: TypeAlias = ctypes.c_uint32
|
|
enum_NV2080_CTRL_CE_SHIM_PREFERENCE: dict[int, str] = {(NV2080_CTRL_CE_SHIM_PREFERENCE_SAME_SHIM:=1): 'NV2080_CTRL_CE_SHIM_PREFERENCE_SAME_SHIM', (NV2080_CTRL_CE_SHIM_PREFERENCE_DIFFERENT_SHIM:=2): 'NV2080_CTRL_CE_SHIM_PREFERENCE_DIFFERENT_SHIM'}
|
|
NV2080_CTRL_CE_SHIM_PREFERENCE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
lceType: int
|
|
metadataForLceType: int
|
|
numPces: int
|
|
numLces: int
|
|
supportedPceMask: int
|
|
supportedLceMask: int
|
|
pcePerHshub: int
|
|
multipleLceShimPreference: int
|
|
struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS.register_fields([('lceType', NV2080_CTRL_CE_LCE_TYPE, 0), ('metadataForLceType', NvU32, 4), ('numPces', NvU32, 8), ('numLces', NvU32, 12), ('supportedPceMask', NvU32, 16), ('supportedLceMask', NvU32, 20), ('pcePerHshub', NvU32, 24), ('multipleLceShimPreference', NV2080_CTRL_CE_SHIM_PREFERENCE, 28)])
|
|
NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
decompLceMask: int
|
|
shimInstance: int
|
|
struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS.register_fields([('decompLceMask', NvU64, 0), ('shimInstance', NvU32, 8)])
|
|
NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
lceIndex: int
|
|
bDecompEnabled: int
|
|
struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS.register_fields([('lceIndex', NvU32, 0), ('bDecompEnabled', NvBool, 4)])
|
|
NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
lceMask: int
|
|
numLces: int
|
|
pceAvailableMask: int
|
|
numLcesToMap: int
|
|
lceAvailableMask: int
|
|
numMinPcesPerLce: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS.register_fields([('lceMask', NvU32, 0), ('numLces', NvU32, 4), ('pceAvailableMask', NvU32, 8), ('numLcesToMap', NvU32, 12), ('lceAvailableMask', NvU32, 16), ('numMinPcesPerLce', NvU32, 20)])
|
|
NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS(c.Struct):
|
|
SIZE = 264
|
|
pceLceMap: c.Array[ctypes.c_uint32, Literal[64]]
|
|
lceAvailableMask: int
|
|
shimInstance: int
|
|
struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS.register_fields([('pceLceMap', c.Array[NvU32, Literal[64]], 0), ('lceAvailableMask', NvU32, 256), ('shimInstance', NvU32, 260)])
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE(c.Struct):
|
|
SIZE = 24
|
|
super: struct_NV2080_CTRL_PMUMON_SAMPLE
|
|
gpcClkFreqKHz: int
|
|
dramClkFreqKHz: int
|
|
nvdClkFreqKHz: int
|
|
activeGpcClkFreqKHz: int
|
|
@c.record
|
|
class struct_NV2080_CTRL_PMUMON_SAMPLE(c.Struct):
|
|
SIZE = 8
|
|
timestamp: int
|
|
NV2080_CTRL_PMUMON_SAMPLE: TypeAlias = struct_NV2080_CTRL_PMUMON_SAMPLE
|
|
struct_NV2080_CTRL_PMUMON_SAMPLE.register_fields([('timestamp', NvU64, 0)])
|
|
struct_NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE.register_fields([('super', NV2080_CTRL_PMUMON_SAMPLE, 0), ('gpcClkFreqKHz', NvU32, 8), ('dramClkFreqKHz', NvU32, 12), ('nvdClkFreqKHz', NvU32, 16), ('activeGpcClkFreqKHz', NvU32, 20)])
|
|
NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE: TypeAlias = struct_NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE
|
|
PNV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE: TypeAlias = c.POINTER[struct_NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE]
|
|
@c.record
|
|
class struct_NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS(c.Struct):
|
|
SIZE = 6024
|
|
super: struct_NV2080_CTRL_PMUMON_GET_SAMPLES_SUPER
|
|
samples: c.Array[struct_NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE, Literal[250]]
|
|
@c.record
|
|
class struct_NV2080_CTRL_PMUMON_GET_SAMPLES_SUPER(c.Struct):
|
|
SIZE = 24
|
|
tailIndex: int
|
|
sequenceId: int
|
|
headIndex: int
|
|
numSamples: int
|
|
resetCount: int
|
|
retrievalMode: int
|
|
NV2080_CTRL_PMUMON_GET_SAMPLES_SUPER: TypeAlias = struct_NV2080_CTRL_PMUMON_GET_SAMPLES_SUPER
|
|
enum_NV2080_CTRL_PMUMON_RETRIEVAL_MODE: dict[int, str] = {(NV2080_CTRL_PMUMON_RETRIEVAL_MODE_ALL_SAMPLES:=0): 'NV2080_CTRL_PMUMON_RETRIEVAL_MODE_ALL_SAMPLES', (NV2080_CTRL_PMUMON_RETRIEVAL_MODE_LATEST_SAMPLE_ONLY:=1): 'NV2080_CTRL_PMUMON_RETRIEVAL_MODE_LATEST_SAMPLE_ONLY'}
|
|
NV2080_CTRL_PMUMON_RETRIEVAL_MODE: TypeAlias = ctypes.c_uint32
|
|
struct_NV2080_CTRL_PMUMON_GET_SAMPLES_SUPER.register_fields([('tailIndex', NvU32, 0), ('sequenceId', NvU32, 4), ('headIndex', NvU32, 8), ('numSamples', NvU32, 12), ('resetCount', NvU32, 16), ('retrievalMode', NV2080_CTRL_PMUMON_RETRIEVAL_MODE, 20)])
|
|
struct_NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS.register_fields([('super', NV2080_CTRL_PMUMON_GET_SAMPLES_SUPER, 0), ('samples', c.Array[NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE, Literal[250]], 24)])
|
|
NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS: TypeAlias = struct_NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS
|
|
PNV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS: TypeAlias = c.POINTER[struct_NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS]
|
|
@c.record
|
|
class struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hClient: int
|
|
hDevice: int
|
|
engine: int
|
|
hVASpace: int
|
|
struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS.register_fields([('hClient', NvHandle, 0), ('hDevice', NvHandle, 4), ('engine', NvU32, 8), ('hVASpace', NvHandle, 12)])
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS: TypeAlias = struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS
|
|
NV2080_CTRL_DMA_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_DMA_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 2052
|
|
dmaInfoTblSize: int
|
|
dmaInfoTbl: c.Array[struct_NVXXXX_CTRL_XXX_INFO, Literal[256]]
|
|
struct_NV2080_CTRL_DMA_GET_INFO_PARAMS.register_fields([('dmaInfoTblSize', NvU32, 0), ('dmaInfoTbl', c.Array[NV2080_CTRL_DMA_INFO, Literal[256]], 4)])
|
|
NV2080_CTRL_DMA_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_DMA_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO(c.Struct):
|
|
SIZE = 12
|
|
srcAddr: int
|
|
dstAddr: int
|
|
relComptagIndex: int
|
|
struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO.register_fields([('srcAddr', NvU32, 0), ('dstAddr', NvU32, 4), ('relComptagIndex', NvU16, 8)])
|
|
NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO: TypeAlias = struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO(c.Struct):
|
|
SIZE = 24
|
|
hMemory: int
|
|
offset: int
|
|
size: int
|
|
struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO.register_fields([('hMemory', NvHandle, 0), ('offset', NvU64, 8), ('size', NvU64, 16)])
|
|
NV2080_CTRL_DMABUF_MEM_HANDLE_INFO: TypeAlias = struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS(c.Struct):
|
|
SIZE = 3104
|
|
fd: int
|
|
totalObjects: int
|
|
numObjects: int
|
|
index: int
|
|
totalSize: int
|
|
mappingType: int
|
|
bAllowMmap: int
|
|
handles: c.Array[struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO, Literal[128]]
|
|
struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS.register_fields([('fd', NvS32, 0), ('totalObjects', NvU32, 4), ('numObjects', NvU32, 8), ('index', NvU32, 12), ('totalSize', NvU64, 16), ('mappingType', NvU8, 24), ('bAllowMmap', NvBool, 25), ('handles', c.Array[NV2080_CTRL_DMABUF_MEM_HANDLE_INFO, Literal[128]], 32)])
|
|
NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS: TypeAlias = struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
sramParityUncorrectedUnique: int
|
|
sramSecDedUncorrectedUnique: int
|
|
sramCorrectedUnique: int
|
|
dramUncorrectedTotal: int
|
|
dramCorrectedTotal: int
|
|
lastClearedTimestamp: int
|
|
sramBucketL2: int
|
|
sramBucketSM: int
|
|
sramBucketPcie: int
|
|
sramBucketFirmware: int
|
|
sramBucketOther: int
|
|
sramErrorThresholdExceeded: int
|
|
struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS.register_fields([('sramParityUncorrectedUnique', NvU64, 0), ('sramSecDedUncorrectedUnique', NvU64, 8), ('sramCorrectedUnique', NvU64, 16), ('dramUncorrectedTotal', NvU64, 24), ('dramCorrectedTotal', NvU64, 32), ('lastClearedTimestamp', NvU32, 40), ('sramBucketL2', NvU64, 48), ('sramBucketSM', NvU64, 56), ('sramBucketPcie', NvU64, 64), ('sramBucketFirmware', NvU64, 72), ('sramBucketOther', NvU64, 80), ('sramErrorThresholdExceeded', NvBool, 88)])
|
|
NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
sramCorUni: int
|
|
sramUncParityUni: int
|
|
sramUncSecDedUni: int
|
|
dramCorTot: int
|
|
dramUncTot: int
|
|
struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS.register_fields([('sramCorUni', NvU64, 0), ('sramUncParityUni', NvU64, 8), ('sramUncSecDedUni', NvU64, 16), ('dramCorTot', NvU64, 24), ('dramUncTot', NvU64, 32)])
|
|
NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS: TypeAlias = struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS
|
|
@c.record
|
|
class struct_eccLocation(c.Struct):
|
|
SIZE = 12
|
|
location: int
|
|
sublocation: int
|
|
extlocation: int
|
|
struct_eccLocation.register_fields([('location', NvU32, 0), ('sublocation', NvU32, 4), ('extlocation', NvU32, 8)])
|
|
eccLocation: TypeAlias = struct_eccLocation
|
|
@c.record
|
|
class struct_NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY(c.Struct):
|
|
SIZE = 28
|
|
unit: int
|
|
location: struct_eccLocation
|
|
address: int
|
|
bIsParity: int
|
|
count: int
|
|
struct_NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY.register_fields([('unit', NvU32, 0), ('location', eccLocation, 4), ('address', NvU32, 16), ('bIsParity', NvBool, 20), ('count', NvU32, 24)])
|
|
NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY: TypeAlias = struct_NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS(c.Struct):
|
|
SIZE = 16804
|
|
entryCount: int
|
|
entries: c.Array[struct_NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY, Literal[600]]
|
|
struct_NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS.register_fields([('entryCount', NvU32, 0), ('entries', c.Array[NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_ENTRY, Literal[600]], 4)])
|
|
NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS: TypeAlias = struct_NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_ECC_INJECT_ERROR_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
unit: int
|
|
errorType: int
|
|
location: struct_eccLocation
|
|
flags: int
|
|
address: int
|
|
struct_NV2080_CTRL_ECC_INJECT_ERROR_PARAMS.register_fields([('unit', NvU32, 0), ('errorType', NvU8, 4), ('location', eccLocation, 8), ('flags', NvU32, 20), ('address', NvU64, 24)])
|
|
NV2080_CTRL_ECC_INJECT_ERROR_PARAMS: TypeAlias = struct_NV2080_CTRL_ECC_INJECT_ERROR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bTpcRepairPending: int
|
|
bChannelRepairPending: int
|
|
struct_NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS.register_fields([('bTpcRepairPending', NvBool, 0), ('bChannelRepairPending', NvBool, 1)])
|
|
NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
unit: int
|
|
location: struct_eccLocation
|
|
bCorrectableSupported: int
|
|
bUncorrectableSupported: int
|
|
struct_NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS.register_fields([('unit', NvU32, 0), ('location', eccLocation, 4), ('bCorrectableSupported', NvBool, 16), ('bUncorrectableSupported', NvBool, 17)])
|
|
NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS: TypeAlias = struct_NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bUnrepairableMemory: int
|
|
struct_NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS.register_fields([('bUnrepairableMemory', NvBool, 0)])
|
|
NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS: TypeAlias = struct_NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
event: int
|
|
action: int
|
|
bNotifyState: int
|
|
info32: int
|
|
info16: int
|
|
struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS.register_fields([('event', NvU32, 0), ('action', NvU32, 4), ('bNotifyState', NvBool, 8), ('info32', NvU32, 12), ('info16', NvU16, 16)])
|
|
NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS
|
|
enum_NV2080_EVENT_HDACODEC_DSTATE: dict[int, str] = {(NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0:=0): 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0', (NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1:=1): 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1', (NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2:=2): 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2', (NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT:=3): 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT', (NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD:=4): 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD', (NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX:=5): 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX'}
|
|
NV2080_EVENT_HDACODEC_DSTATE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hMemory: int
|
|
struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS.register_fields([('hMemory', NvHandle, 0)])
|
|
NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hSemMemory: int
|
|
semOffset: int
|
|
struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS.register_fields([('hSemMemory', NvHandle, 0), ('semOffset', NvU32, 4)])
|
|
NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
guestMSIAddr: int
|
|
guestMSIData: int
|
|
hSemMemory: int
|
|
isReset: int
|
|
vgpuUuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
domainId: int
|
|
struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS.register_fields([('guestMSIAddr', NvU64, 0), ('guestMSIData', NvU32, 8), ('hSemMemory', NvHandle, 12), ('isReset', NvBool, 16), ('vgpuUuid', c.Array[NvU8, Literal[16]], 17), ('domainId', NvU64, 40)])
|
|
NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hSemMemory: int
|
|
isSemaMemValidationEnabled: int
|
|
struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS.register_fields([('hSemMemory', NvHandle, 0), ('isSemaMemValidationEnabled', NvBool, 4)])
|
|
NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hEvent: int
|
|
struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS.register_fields([('hEvent', NvHandle, 0)])
|
|
NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS
|
|
enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD: dict[int, str] = {(NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL:=0): 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL', (NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE:=1): 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE', (NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM:=2): 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM'}
|
|
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
hEventBuffer: int
|
|
recordSize: int
|
|
levelOfDetail: int
|
|
eventFilter: int
|
|
bAllUsers: int
|
|
struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS.register_fields([('hEventBuffer', NvHandle, 0), ('recordSize', NvU32, 4), ('levelOfDetail', NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD, 8), ('eventFilter', NvU32, 12), ('bAllUsers', NvBool, 16)])
|
|
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hEventBuffer: int
|
|
tracepointMask: int
|
|
gspLoggingBufferSize: int
|
|
gspLoggingBufferWatermark: int
|
|
struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS.register_fields([('hEventBuffer', NvHandle, 0), ('tracepointMask', NvU64, 8), ('gspLoggingBufferSize', NvU32, 16), ('gspLoggingBufferWatermark', NvU32, 20)])
|
|
NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hEventBuffer: int
|
|
struct_NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS.register_fields([('hEventBuffer', NvHandle, 0)])
|
|
NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS
|
|
NV2080_CTRL_FB_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
fbInfoListSize: int
|
|
fbInfoList: ctypes.c_void_p
|
|
struct_NV2080_CTRL_FB_GET_INFO_PARAMS.register_fields([('fbInfoListSize', NvU32, 0), ('fbInfoList', NvP64, 8)])
|
|
NV2080_CTRL_FB_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 1028
|
|
fbInfoListSize: int
|
|
fbInfoList: c.Array[struct_NVXXXX_CTRL_XXX_INFO, Literal[128]]
|
|
struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS.register_fields([('fbInfoListSize', NvU32, 0), ('fbInfoList', c.Array[NV2080_CTRL_FB_INFO, Literal[128]], 4)])
|
|
NV2080_CTRL_FB_GET_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
cpuVirtAddress: ctypes.c_void_p
|
|
gpuVirtAddress: int
|
|
struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS.register_fields([('cpuVirtAddress', NvP64, 0), ('gpuVirtAddress', NvU64, 8)])
|
|
NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
flags: int
|
|
driveStrengthRiseCount: int
|
|
driveStrengthFallCount: int
|
|
driveStrengthTermCount: int
|
|
slewStrengthRiseCount: int
|
|
slewStrengthFallCount: int
|
|
struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS.register_fields([('flags', NvU32, 0), ('driveStrengthRiseCount', NvU32, 4), ('driveStrengthFallCount', NvU32, 8), ('driveStrengthTermCount', NvU32, 12), ('slewStrengthRiseCount', NvU32, 16), ('slewStrengthFallCount', NvU32, 20)])
|
|
NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
flags: int
|
|
struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS.register_fields([('flags', NvU32, 0)])
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS(c.Struct):
|
|
SIZE = 4024
|
|
addressArray: c.Array[ctypes.c_uint64, Literal[500]]
|
|
addressArraySize: int
|
|
addressAlign: int
|
|
memBlockSizeBytes: int
|
|
flags: int
|
|
struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS.register_fields([('addressArray', c.Array[NvU64, Literal[500]], 0), ('addressArraySize', NvU32, 4000), ('addressAlign', NvU32, 4004), ('memBlockSizeBytes', NvU64, 4008), ('flags', NvU32, 4016)])
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_IS_KIND_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
operation: int
|
|
kind: int
|
|
result: int
|
|
struct_NV2080_CTRL_FB_IS_KIND_PARAMS.register_fields([('operation', NvU32, 0), ('kind', NvU32, 4), ('result', NvBool, 8)])
|
|
NV2080_CTRL_FB_IS_KIND_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_IS_KIND_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
powerState: int
|
|
writeMode: int
|
|
bypassMode: int
|
|
rcmState: int
|
|
struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS.register_fields([('powerState', NvU32, 0), ('writeMode', NvU32, 4), ('bypassMode', NvU32, 8), ('rcmState', NvU32, 12)])
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS
|
|
enum_NV2080_FB_REGION_TAG: dict[int, str] = {(NV2080_FB_REGION_TAG_NONE:=0): 'NV2080_FB_REGION_TAG_NONE', (NV2080_FB_REGION_TAG_GSP_CARVEOUT:=1): 'NV2080_FB_REGION_TAG_GSP_CARVEOUT', (NV2080_FB_REGION_TAG_CPU_RM_RESERVED:=2): 'NV2080_FB_REGION_TAG_CPU_RM_RESERVED', (NV2080_FB_REGION_TAG_CPU_RM_RESERVED_HEAP:=3): 'NV2080_FB_REGION_TAG_CPU_RM_RESERVED_HEAP', (NV2080_FB_REGION_TAG_GSP_RM_RESERVED:=4): 'NV2080_FB_REGION_TAG_GSP_RM_RESERVED', (NV2080_FB_REGION_TAG_GSP_RM_RESERVED_HEAP:=5): 'NV2080_FB_REGION_TAG_GSP_RM_RESERVED_HEAP'}
|
|
NV2080_FB_REGION_TAG: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO(c.Struct):
|
|
SIZE = 56
|
|
base: int
|
|
limit: int
|
|
reserved: int
|
|
performance: int
|
|
supportCompressed: int
|
|
supportISO: int
|
|
bProtected: int
|
|
blackList: c.Array[ctypes.c_ubyte, Literal[18]]
|
|
regionTag: int
|
|
struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO.register_fields([('base', NvU64, 0), ('limit', NvU64, 8), ('reserved', NvU64, 16), ('performance', NvU32, 24), ('supportCompressed', NvBool, 28), ('supportISO', NvBool, 29), ('bProtected', NvBool, 30), ('blackList', c.Array[NvBool, Literal[18]], 31), ('regionTag', NV2080_FB_REGION_TAG, 52)])
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS(c.Struct):
|
|
SIZE = 904
|
|
numFBRegions: int
|
|
fbRegion: c.Array[struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO, Literal[16]]
|
|
struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS.register_fields([('numFBRegions', NvU32, 0), ('fbRegion', c.Array[NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO, Literal[16]], 8)])
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO(c.Struct):
|
|
SIZE = 32
|
|
pageAddressWithEccOn: int
|
|
pageAddressWithEccOff: int
|
|
rbcAddress: int
|
|
source: int
|
|
status: int
|
|
timestamp: int
|
|
struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO.register_fields([('pageAddressWithEccOn', NvU64, 0), ('pageAddressWithEccOff', NvU64, 8), ('rbcAddress', NvU32, 16), ('source', NvU32, 20), ('status', NvU32, 24), ('timestamp', NvU32, 28)])
|
|
NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO: TypeAlias = struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS(c.Struct):
|
|
SIZE = 2064
|
|
offlined: c.Array[struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO, Literal[64]]
|
|
pageSize: int
|
|
validEntries: int
|
|
numPagesAdded: int
|
|
struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS.register_fields([('offlined', c.Array[NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO, Literal[64]], 0), ('pageSize', NvU32, 2048), ('validEntries', NvU32, 2052), ('numPagesAdded', NvU32, 2056)])
|
|
NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS(c.Struct):
|
|
SIZE = 2056
|
|
offlined: c.Array[struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO, Literal[64]]
|
|
validEntries: int
|
|
bRetirementPending: int
|
|
retirementPending: int
|
|
struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS.register_fields([('offlined', c.Array[NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO, Literal[64]], 0), ('validEntries', NvU32, 2048), ('bRetirementPending', NvBool, 2052), ('retirementPending', NvU8, 2053)])
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS
|
|
enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE: dict[int, str] = {(NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS:=0): 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS', (NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY:=1): 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY', (NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS:=2): 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS'}
|
|
NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE: TypeAlias = ctypes.c_uint32
|
|
enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE: dict[int, str] = {(NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE:=0): 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE', (NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST:=1): 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST'}
|
|
NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_ACR_REQUEST_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
clientId: int
|
|
reqReadMask: int
|
|
reqWriteMask: int
|
|
regionSize: int
|
|
struct_ACR_REQUEST_PARAMS.register_fields([('clientId', NvU32, 0), ('reqReadMask', NvU32, 4), ('reqWriteMask', NvU32, 8), ('regionSize', NvU32, 12)])
|
|
ACR_REQUEST_PARAMS: TypeAlias = struct_ACR_REQUEST_PARAMS
|
|
@c.record
|
|
class struct_ACR_REGION_ID_PROP(c.Struct):
|
|
SIZE = 32
|
|
regionId: int
|
|
readMask: int
|
|
writeMask: int
|
|
regionSize: int
|
|
clientMask: int
|
|
physicalAddress: int
|
|
struct_ACR_REGION_ID_PROP.register_fields([('regionId', NvU32, 0), ('readMask', NvU32, 4), ('writeMask', NvU32, 8), ('regionSize', NvU32, 12), ('clientMask', NvU32, 16), ('physicalAddress', NvU64, 24)])
|
|
ACR_REGION_ID_PROP: TypeAlias = struct_ACR_REGION_ID_PROP
|
|
@c.record
|
|
class struct_ACR_STATUS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
allocStatus: int
|
|
regionId: int
|
|
physicalAddress: int
|
|
struct_ACR_STATUS_PARAMS.register_fields([('allocStatus', NvU32, 0), ('regionId', NvU32, 4), ('physicalAddress', NvU64, 8)])
|
|
ACR_STATUS_PARAMS: TypeAlias = struct_ACR_STATUS_PARAMS
|
|
@c.record
|
|
class struct_ACR_REGION_HANDLE(c.Struct):
|
|
SIZE = 20
|
|
hClient: int
|
|
hParent: int
|
|
hMemory: int
|
|
hClass: int
|
|
hDevice: int
|
|
struct_ACR_REGION_HANDLE.register_fields([('hClient', NvHandle, 0), ('hParent', NvHandle, 4), ('hMemory', NvHandle, 8), ('hClass', NvU32, 12), ('hDevice', NvHandle, 16)])
|
|
ACR_REGION_HANDLE: TypeAlias = struct_ACR_REGION_HANDLE
|
|
@c.record
|
|
class struct_ACR_FALCON_LS_STATUS(c.Struct):
|
|
SIZE = 4
|
|
falconId: int
|
|
bIsInLs: int
|
|
struct_ACR_FALCON_LS_STATUS.register_fields([('falconId', NvU16, 0), ('bIsInLs', NvBool, 2)])
|
|
ACR_FALCON_LS_STATUS: TypeAlias = struct_ACR_FALCON_LS_STATUS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
queryType: int
|
|
errorCode: int
|
|
acrRegionIdProp: struct_ACR_REGION_ID_PROP
|
|
clientReq: struct_ACR_REQUEST_PARAMS
|
|
clientReqStatus: struct_ACR_STATUS_PARAMS
|
|
handle: struct_ACR_REGION_HANDLE
|
|
falconStatus: struct_ACR_FALCON_LS_STATUS
|
|
struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS.register_fields([('queryType', NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE, 0), ('errorCode', NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE, 4), ('acrRegionIdProp', ACR_REGION_ID_PROP, 8), ('clientReq', ACR_REQUEST_PARAMS, 40), ('clientReqStatus', ACR_STATUS_PARAMS, 56), ('handle', ACR_REGION_HANDLE, 72), ('falconStatus', ACR_FALCON_LS_STATUS, 92)])
|
|
NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
sourceMask: int
|
|
struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS.register_fields([('sourceMask', NvU32, 0)])
|
|
NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pCompBitCopyObj: ctypes.c_void_p
|
|
pSwizzleParams: ctypes.c_void_p
|
|
struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS.register_fields([('pCompBitCopyObj', NvP64, 0), ('pSwizzleParams', NvP64, 8)])
|
|
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
fbpIndex: int
|
|
ltcMask: int
|
|
ltcCount: int
|
|
ltsMask: int
|
|
ltsCount: int
|
|
struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS.register_fields([('fbpIndex', NvU8, 0), ('ltcMask', NvU32, 4), ('ltcCount', NvU32, 8), ('ltsMask', NvU32, 12), ('ltsCount', NvU32, 16)])
|
|
NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
CBCBaseAddress: int
|
|
backingStorePA: int
|
|
backingStoreVA: c.POINTER[ctypes.c_ubyte]
|
|
backingStoreChunkPA: int
|
|
backingStoreChunkVA: c.POINTER[ctypes.c_ubyte]
|
|
backingStoreChunkSize: int
|
|
cacheWriteBitMap: c.POINTER[ctypes.c_ubyte]
|
|
backingStoreChunkOverfetch: int
|
|
PageSizeSrc: int
|
|
PageSizeDest: int
|
|
struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS.register_fields([('CBCBaseAddress', NvU32, 0), ('backingStorePA', NvU64, 8), ('backingStoreVA', c.POINTER[NvU8], 16), ('backingStoreChunkPA', NvU64, 24), ('backingStoreChunkVA', c.POINTER[NvU8], 32), ('backingStoreChunkSize', NvU32, 40), ('cacheWriteBitMap', c.POINTER[NvU8], 48), ('backingStoreChunkOverfetch', NvBool, 56), ('PageSizeSrc', NvU32, 60), ('PageSizeDest', NvU32, 64)])
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
fcbits: c.POINTER[ctypes.c_uint32]
|
|
compbits: c.POINTER[ctypes.c_uint32]
|
|
dataPhysicalStart: int
|
|
surfaceOffset: int
|
|
comptagLine: int
|
|
upper64KBCompbitSel: int
|
|
struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS.register_fields([('fcbits', c.POINTER[NvU32], 0), ('compbits', c.POINTER[NvU32], 8), ('dataPhysicalStart', NvU64, 16), ('surfaceOffset', NvU64, 24), ('comptagLine', NvU32, 32), ('upper64KBCompbitSel', NvBool, 36)])
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
fcbits: int
|
|
compbits: int
|
|
writeFc: int
|
|
dataPhysicalStart: int
|
|
surfaceOffset: int
|
|
comptagLine: int
|
|
upper64KBCompbitSel: int
|
|
struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS.register_fields([('fcbits', NvU32, 0), ('compbits', NvU32, 4), ('writeFc', NvBool, 8), ('dataPhysicalStart', NvU64, 16), ('surfaceOffset', NvU64, 24), ('comptagLine', NvU32, 32), ('upper64KBCompbitSel', NvBool, 36)])
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
SrcDataPhysicalStart: int
|
|
SrcComptagLine: int
|
|
page64KB: int
|
|
compbitBuffer: c.POINTER[ctypes.c_uint32]
|
|
upper64KBCompbitSel: int
|
|
struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS.register_fields([('SrcDataPhysicalStart', NvU64, 0), ('SrcComptagLine', NvU32, 8), ('page64KB', NvU32, 12), ('compbitBuffer', c.POINTER[NvU32], 16), ('upper64KBCompbitSel', NvBool, 24)])
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
DstDataPhysicalStart: int
|
|
DstComptagLine: int
|
|
page64KB: int
|
|
compbitBuffer: c.POINTER[ctypes.c_uint32]
|
|
upper64KBCompbitSel: int
|
|
struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS.register_fields([('DstDataPhysicalStart', NvU64, 0), ('DstComptagLine', NvU32, 8), ('page64KB', NvU32, 12), ('compbitBuffer', c.POINTER[NvU32], 16), ('upper64KBCompbitSel', NvBool, 24)])
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bForceBar1: int
|
|
struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS.register_fields([('bForceBar1', NvBool, 0)])
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pAmapConfParams: ctypes.c_void_p
|
|
pCbcSwizzleParams: ctypes.c_void_p
|
|
struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS.register_fields([('pAmapConfParams', NvP64, 0), ('pCbcSwizzleParams', NvP64, 8)])
|
|
NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS
|
|
enum_CTRL_CMD_FB_CBC_OP: dict[int, str] = {(CTRL_CMD_FB_CBC_OP_CLEAN:=0): 'CTRL_CMD_FB_CBC_OP_CLEAN', (CTRL_CMD_FB_CBC_OP_INVALIDATE:=1): 'CTRL_CMD_FB_CBC_OP_INVALIDATE'}
|
|
CTRL_CMD_FB_CBC_OP: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
fbCBCOp: int
|
|
struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS.register_fields([('fbCBCOp', CTRL_CMD_FB_CBC_OP, 0)])
|
|
NV2080_CTRL_CMD_FB_CBC_OP_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS(c.Struct):
|
|
SIZE = 512
|
|
pCompTags: c.Array[ctypes.c_uint32, Literal[127]]
|
|
numCompTags: int
|
|
struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS.register_fields([('pCompTags', c.Array[NvU32, Literal[127]], 0), ('numCompTags', NvU32, 508)])
|
|
NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
attr: int
|
|
attr2: int
|
|
size: int
|
|
ctagOffset: int
|
|
hwResId: int
|
|
retCompTagLineMin: int
|
|
retCompTagLineMax: int
|
|
struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS.register_fields([('attr', NvU32, 0), ('attr2', NvU32, 4), ('size', NvU32, 8), ('ctagOffset', NvU32, 12), ('hwResId', NvU32, 16), ('retCompTagLineMin', NvU32, 20), ('retCompTagLineMax', NvU32, 24)])
|
|
NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hwResId: int
|
|
struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS.register_fields([('hwResId', NvU32, 0)])
|
|
NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS
|
|
enum_NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE: dict[int, str] = {(NV2080_CTRL_CMD_FB_SET_VPR:=0): 'NV2080_CTRL_CMD_FB_SET_VPR'}
|
|
NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE: TypeAlias = ctypes.c_uint32
|
|
enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE: dict[int, str] = {(NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC:=0): 'NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC', (NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST:=1): 'NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST'}
|
|
NV2080_CTRL_CMD_FB_VPR_ERROR_CODE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_VPR_REQUEST_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
startAddr: int
|
|
size: int
|
|
struct_VPR_REQUEST_PARAMS.register_fields([('startAddr', NvU32, 0), ('size', NvU32, 4)])
|
|
VPR_REQUEST_PARAMS: TypeAlias = struct_VPR_REQUEST_PARAMS
|
|
@c.record
|
|
class struct_VPR_STATUS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
status: int
|
|
struct_VPR_STATUS_PARAMS.register_fields([('status', NvU32, 0)])
|
|
VPR_STATUS_PARAMS: TypeAlias = struct_VPR_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
requestType: int
|
|
requestParams: struct_VPR_REQUEST_PARAMS
|
|
statusParams: struct_VPR_STATUS_PARAMS
|
|
struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS.register_fields([('requestType', NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE, 0), ('requestParams', VPR_REQUEST_PARAMS, 4), ('statusParams', VPR_STATUS_PARAMS, 12)])
|
|
NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS
|
|
PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS: TypeAlias = c.POINTER[struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS]
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS(c.Struct):
|
|
SIZE = 264
|
|
offlinedPages: c.Array[ctypes.c_uint32, Literal[64]]
|
|
pageSize: int
|
|
validEntries: int
|
|
struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS.register_fields([('offlinedPages', c.Array[NvU32, Literal[64]], 0), ('pageSize', NvU32, 256), ('validEntries', NvU32, 260)])
|
|
NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
defaultPageSize: int
|
|
comptagsPerCacheLine: int
|
|
unpackedComptagLinesPerCacheLine: int
|
|
compCacheLineSizePerLTC: int
|
|
unpackedCompCacheLineSizePerLTC: int
|
|
slicesPerLTC: int
|
|
numActiveLTCs: int
|
|
familyName: int
|
|
chipName: int
|
|
bitsPerRAMEntry: int
|
|
ramBankWidth: int
|
|
bitsPerComptagLine: int
|
|
ramEntriesPerCompCacheLine: int
|
|
comptagLineSize: int
|
|
struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS.register_fields([('defaultPageSize', NvU32, 0), ('comptagsPerCacheLine', NvU32, 4), ('unpackedComptagLinesPerCacheLine', NvU32, 8), ('compCacheLineSizePerLTC', NvU32, 12), ('unpackedCompCacheLineSizePerLTC', NvU32, 16), ('slicesPerLTC', NvU32, 20), ('numActiveLTCs', NvU32, 24), ('familyName', NvU32, 28), ('chipName', NvU32, 32), ('bitsPerRAMEntry', NvU32, 36), ('ramBankWidth', NvU32, 40), ('bitsPerComptagLine', NvU32, 44), ('ramEntriesPerCompCacheLine', NvU32, 48), ('comptagLineSize', NvU32, 52)])
|
|
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_SET_RRD_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rrd: int
|
|
struct_NV2080_CTRL_FB_SET_RRD_PARAMS.register_fields([('rrd', NvU32, 0)])
|
|
NV2080_CTRL_FB_SET_RRD_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_SET_RRD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
limit: int
|
|
struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS.register_fields([('limit', NvU8, 0)])
|
|
NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS
|
|
NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS
|
|
NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnable: int
|
|
struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS.register_fields([('bEnable', NvBool, 0)])
|
|
NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
alignType: int
|
|
alignAttr: int
|
|
alignInputFlags: int
|
|
alignHead: int
|
|
alignSize: int
|
|
alignHeight: int
|
|
alignWidth: int
|
|
alignPitch: int
|
|
alignPad: int
|
|
alignMask: int
|
|
alignKind: int
|
|
alignAdjust: int
|
|
alignAttr2: int
|
|
struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS.register_fields([('alignType', NvU32, 0), ('alignAttr', NvU32, 4), ('alignInputFlags', NvU32, 8), ('alignHead', NvU32, 12), ('alignSize', NvU64, 16), ('alignHeight', NvU32, 24), ('alignWidth', NvU32, 28), ('alignPitch', NvU32, 32), ('alignPad', NvU32, 36), ('alignMask', NvU32, 40), ('alignKind', NvU32, 44), ('alignAdjust', NvU32, 48), ('alignAttr2', NvU32, 52)])
|
|
NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
cbcBaseAddress: int
|
|
compCacheLineSize: int
|
|
backingStoreStartPA: int
|
|
backingStoreAllocPA: int
|
|
backingStoreChunkOverfetch: int
|
|
struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS.register_fields([('cbcBaseAddress', NvU32, 0), ('compCacheLineSize', NvU32, 4), ('backingStoreStartPA', NvU64, 8), ('backingStoreAllocPA', NvU64, 16), ('backingStoreChunkOverfetch', NvU32, 24)])
|
|
NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_ROW_REMAP_ENTRY(c.Struct):
|
|
SIZE = 12
|
|
remapRegVal: int
|
|
timestamp: int
|
|
fbpa: int
|
|
sublocation: int
|
|
source: int
|
|
flags: int
|
|
struct_NV2080_CTRL_FB_ROW_REMAP_ENTRY.register_fields([('remapRegVal', NvU32, 0), ('timestamp', NvU32, 4), ('fbpa', NvU8, 8), ('sublocation', NvU8, 9), ('source', NvU8, 10), ('flags', NvU8, 11)])
|
|
NV2080_CTRL_FB_ROW_REMAP_ENTRY: TypeAlias = struct_NV2080_CTRL_FB_ROW_REMAP_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS(c.Struct):
|
|
SIZE = 6152
|
|
entryCount: int
|
|
flags: int
|
|
entries: c.Array[struct_NV2080_CTRL_FB_ROW_REMAP_ENTRY, Literal[512]]
|
|
struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS.register_fields([('entryCount', NvU32, 0), ('flags', NvU8, 4), ('entries', c.Array[NV2080_CTRL_FB_ROW_REMAP_ENTRY, Literal[512]], 8)])
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
data: c.Array[ctypes.c_ubyte, Literal[24]]
|
|
struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS.register_fields([('data', c.Array[NvU8, Literal[24]], 0)])
|
|
NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
swizzId: int
|
|
fbpEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS.register_fields([('swizzId', NvU32, 0), ('fbpEnMask', NvU64, 8)])
|
|
NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: int
|
|
ltcEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('ltcEnMask', NvU32, 4)])
|
|
NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: int
|
|
ltsEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('ltsEnMask', NvU32, 4)])
|
|
NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: int
|
|
fbpaEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('fbpaEnMask', NvU32, 4)])
|
|
NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: int
|
|
fbpaSubpEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('fbpaSubpEnMask', NvU32, 4)])
|
|
NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: int
|
|
fbpLogicalIndex: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('fbpLogicalIndex', NvU32, 4)])
|
|
NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: int
|
|
ropEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('ropEnMask', NvU32, 4)])
|
|
NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
swizzId: int
|
|
sysEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS.register_fields([('swizzId', NvU32, 0), ('sysEnMask', NvU64, 8)])
|
|
NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
fbpIndex: int
|
|
swizzId: int
|
|
ltcEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('swizzId', NvU32, 4), ('ltcEnMask', NvU32, 8)])
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
fbpIndex: int
|
|
swizzId: int
|
|
ltsEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('swizzId', NvU32, 4), ('ltsEnMask', NvU32, 8)])
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
fbpIndex: int
|
|
swizzId: int
|
|
fbpaEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('swizzId', NvU32, 4), ('fbpaEnMask', NvU32, 8)])
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
fbpIndex: int
|
|
swizzId: int
|
|
ropEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('swizzId', NvU32, 4), ('ropEnMask', NvU32, 8)])
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
fbpIndex: int
|
|
swizzId: int
|
|
fbpaSubpEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('swizzId', NvU32, 4), ('fbpaSubpEnMask', NvU64, 8)])
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
sysIdx: int
|
|
sysl2LtcEnMask: int
|
|
struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS.register_fields([('sysIdx', NvU32, 0), ('sysl2LtcEnMask', NvU32, 4)])
|
|
NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
sysIdx: int
|
|
sysl2LtsEnMask: int
|
|
struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS.register_fields([('sysIdx', NvU32, 0), ('sysl2LtsEnMask', NvU64, 8)])
|
|
NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: int
|
|
pacEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('pacEnMask', NvU32, 4)])
|
|
NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
fbpIndex: int
|
|
logicalLtcEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('logicalLtcEnMask', NvU64, 8)])
|
|
NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
fbpIndex: int
|
|
swizzId: int
|
|
logicalLtcEnMask: int
|
|
struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS.register_fields([('fbpIndex', NvU32, 0), ('swizzId', NvU32, 4), ('logicalLtcEnMask', NvU64, 8)])
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_QUERY(c.Struct):
|
|
SIZE = 32
|
|
queryType: int
|
|
reserved: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
status: int
|
|
queryParams: struct_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams(c.Struct):
|
|
SIZE = 24
|
|
inv: struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS
|
|
fbp: struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS
|
|
ltc: struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS
|
|
lts: struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS
|
|
fbpa: struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS
|
|
rop: struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS
|
|
dmLtc: struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS
|
|
dmLts: struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS
|
|
dmFbpa: struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS
|
|
dmRop: struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS
|
|
dmFbpaSubp: struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS
|
|
fbpaSubp: struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS
|
|
fbpLogicalMap: struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS
|
|
sysl2Ltc: struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS
|
|
pac: struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS
|
|
logicalLtc: struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS
|
|
dmLogicalLtc: struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS
|
|
sysl2Lts: struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS
|
|
sys: struct_NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS
|
|
struct_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams.register_fields([('inv', NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS, 0), ('fbp', NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS, 0), ('ltc', NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS, 0), ('lts', NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS, 0), ('fbpa', NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS, 0), ('rop', NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS, 0), ('dmLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS, 0), ('dmLts', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS, 0), ('dmFbpa', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS, 0), ('dmRop', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS, 0), ('dmFbpaSubp', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS, 0), ('fbpaSubp', NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS, 0), ('fbpLogicalMap', NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS, 0), ('sysl2Ltc', NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS, 0), ('pac', NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS, 0), ('logicalLtc', NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS, 0), ('dmLogicalLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS, 0), ('sysl2Lts', NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS, 0), ('sys', NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS, 0)])
|
|
struct_NV2080_CTRL_FB_FS_INFO_QUERY.register_fields([('queryType', NvU16, 0), ('reserved', c.Array[NvU8, Literal[2]], 2), ('status', NvU32, 4), ('queryParams', struct_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams, 8)])
|
|
NV2080_CTRL_FB_FS_INFO_QUERY: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_QUERY
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS(c.Struct):
|
|
SIZE = 3848
|
|
numQueries: int
|
|
reserved: c.Array[ctypes.c_ubyte, Literal[6]]
|
|
queries: c.Array[struct_NV2080_CTRL_FB_FS_INFO_QUERY, Literal[120]]
|
|
struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS.register_fields([('numQueries', NvU16, 0), ('reserved', c.Array[NvU8, Literal[6]], 2), ('queries', c.Array[NV2080_CTRL_FB_FS_INFO_QUERY, Literal[120]], 8)])
|
|
NV2080_CTRL_FB_GET_FS_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
histogram: c.Array[ctypes.c_uint32, Literal[5]]
|
|
struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS.register_fields([('histogram', c.Array[NvU32, Literal[5]], 0)])
|
|
NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO(c.Struct):
|
|
SIZE = 16
|
|
pageNumber: int
|
|
source: int
|
|
struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO.register_fields([('pageNumber', NvU64, 0), ('source', NvU8, 8)])
|
|
NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO: TypeAlias = struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS(c.Struct):
|
|
SIZE = 1040
|
|
offlined: c.Array[struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO, Literal[64]]
|
|
validEntries: int
|
|
baseIndex: int
|
|
bMore: int
|
|
struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS.register_fields([('offlined', c.Array[NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO, Literal[64]], 0), ('validEntries', NvU32, 1024), ('baseIndex', NvU32, 1028), ('bMore', NvBool, 1032)])
|
|
NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO(c.Struct):
|
|
SIZE = 24
|
|
client: int
|
|
flags: int
|
|
beginAddr: int
|
|
size: int
|
|
struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO.register_fields([('client', NvU32, 0), ('flags', NvU32, 4), ('beginAddr', NvU64, 8), ('size', NvU64, 16)])
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_INFO: TypeAlias = struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_CLIENT_INFO(c.Struct):
|
|
SIZE = 112
|
|
handle: int
|
|
pid: int
|
|
subProcessID: int
|
|
subProcessName: c.Array[ctypes.c_char, Literal[100]]
|
|
struct_NV2080_CTRL_CMD_FB_CLIENT_INFO.register_fields([('handle', NvHandle, 0), ('pid', NvU32, 4), ('subProcessID', NvU32, 8), ('subProcessName', c.Array[ctypes.c_char, Literal[100]], 12)])
|
|
NV2080_CTRL_CMD_FB_CLIENT_INFO: TypeAlias = struct_NV2080_CTRL_CMD_FB_CLIENT_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
allocCount: int
|
|
pAllocInfo: ctypes.c_void_p
|
|
clientCount: int
|
|
pClientInfo: ctypes.c_void_p
|
|
struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS.register_fields([('allocCount', NvU64, 0), ('pAllocInfo', NvP64, 8), ('clientCount', NvU64, 16), ('pClientInfo', NvP64, 24)])
|
|
NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bOnline: int
|
|
struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS.register_fields([('bOnline', NvBool, 0)])
|
|
NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS(c.Struct):
|
|
SIZE = 544
|
|
numaNodeId: int
|
|
numaMemAddr: int
|
|
numaMemSize: int
|
|
numaOfflineAddressesCount: int
|
|
numaOfflineAddresses: c.Array[ctypes.c_uint64, Literal[64]]
|
|
struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS.register_fields([('numaNodeId', NvS32, 0), ('numaMemAddr', NvU64, 8), ('numaMemSize', NvU64, 16), ('numaOfflineAddressesCount', NvU32, 24), ('numaOfflineAddresses', c.Array[NvU64, Literal[64]], 32)])
|
|
NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
maxSubmittedSemaphoreValueOffset: int
|
|
monitoredFenceThresholdOffset: int
|
|
size: int
|
|
caps: int
|
|
struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS.register_fields([('maxSubmittedSemaphoreValueOffset', NvU64, 0), ('monitoredFenceThresholdOffset', NvU64, 8), ('size', NvU64, 16), ('caps', NvU32, 24)])
|
|
NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gfid: int
|
|
invalidateAll: int
|
|
struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS.register_fields([('gfid', NvU32, 0), ('invalidateAll', NvBool, 4)])
|
|
NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS: TypeAlias = struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO(c.Struct):
|
|
SIZE = 24
|
|
allocSize: int
|
|
numBlocks: int
|
|
rsvdSize: int
|
|
struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO.register_fields([('allocSize', NvU64, 0), ('numBlocks', NvU32, 8), ('rsvdSize', NvU64, 16)])
|
|
NV2080_CTRL_CMD_FB_STATS_OWNER_INFO: TypeAlias = struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_RM_FB_STATS_ENTRY(c.Struct):
|
|
SIZE = 4848
|
|
reservedHeap: int
|
|
reservedHeapFree: int
|
|
reserved: int
|
|
fbBlockInfo: c.Array[struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO, Literal[201]]
|
|
struct_NV2080_CTRL_CMD_RM_FB_STATS_ENTRY.register_fields([('reservedHeap', NvU64, 0), ('reservedHeapFree', NvU64, 8), ('reserved', NvU64, 16), ('fbBlockInfo', c.Array[NV2080_CTRL_CMD_FB_STATS_OWNER_INFO, Literal[201]], 24)])
|
|
NV2080_CTRL_CMD_RM_FB_STATS_ENTRY: TypeAlias = struct_NV2080_CTRL_CMD_RM_FB_STATS_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS(c.Struct):
|
|
SIZE = 9728
|
|
total: int
|
|
os: int
|
|
gspCarveout: int
|
|
miscReserved: int
|
|
cpuFbInfo: struct_NV2080_CTRL_CMD_RM_FB_STATS_ENTRY
|
|
gspFbInfo: struct_NV2080_CTRL_CMD_RM_FB_STATS_ENTRY
|
|
struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS.register_fields([('total', NvU64, 0), ('os', NvU64, 8), ('gspCarveout', NvU64, 16), ('miscReserved', NvU64, 24), ('cpuFbInfo', NV2080_CTRL_CMD_RM_FB_STATS_ENTRY, 32), ('gspFbInfo', NV2080_CTRL_CMD_RM_FB_STATS_ENTRY, 4880)])
|
|
NV2080_CTRL_CMD_FB_STATS_GET_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
bStaticBar1Enabled: int
|
|
bStaticBar1WriteCombined: int
|
|
staticBar1StartOffset: int
|
|
staticBar1Size: int
|
|
struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS.register_fields([('bStaticBar1Enabled', NvBool, 0), ('bStaticBar1WriteCombined', NvBool, 1), ('staticBar1StartOffset', NvU64, 8), ('staticBar1Size', NvU64, 16)])
|
|
NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
currentConfiguration: int
|
|
struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS.register_fields([('currentConfiguration', NvU32, 0)])
|
|
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
newConfiguration: int
|
|
struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS.register_fields([('newConfiguration', NvU32, 0)])
|
|
NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
isSupported: int
|
|
struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS.register_fields([('isSupported', NvU32, 0)])
|
|
NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
currentStatus: int
|
|
struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS.register_fields([('currentStatus', NvU32, 0)])
|
|
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS(c.Struct):
|
|
SIZE = 6
|
|
flagCollectSchmooData: int
|
|
flagWrTrHybridVrefEn: int
|
|
flagWrTrHybridNonVrefEn: int
|
|
flagRdTrHybridVrefEn: int
|
|
flagRdTrHybridNonVrefEn: int
|
|
skipBootTraining: int
|
|
struct_NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS.register_fields([('flagCollectSchmooData', NvBool, 0), ('flagWrTrHybridVrefEn', NvBool, 1), ('flagWrTrHybridNonVrefEn', NvBool, 2), ('flagRdTrHybridVrefEn', NvBool, 3), ('flagRdTrHybridNonVrefEn', NvBool, 4), ('skipBootTraining', NvBool, 5)])
|
|
NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS
|
|
enum_NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE: dict[int, str] = {(NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_DISPLAY_FRM:=0): 'NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_DISPLAY_FRM', (NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_DISPLAY_FRM_RESERVED:=1): 'NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_DISPLAY_FRM_RESERVED', (NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_UEFI:=2): 'NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE_UEFI'}
|
|
NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO(c.Struct):
|
|
SIZE = 24
|
|
base: int
|
|
size: int
|
|
carveoutType: int
|
|
struct_NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO.register_fields([('base', NvU64, 0), ('size', NvU64, 8), ('carveoutType', NV2080_CTRL_FB_GET_CARVEOUT_REGION_CARVEOUT_TYPE, 16)])
|
|
NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO: TypeAlias = struct_NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS(c.Struct):
|
|
SIZE = 200
|
|
numCarveoutRegions: int
|
|
carveoutRegion: c.Array[struct_NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO, Literal[8]]
|
|
struct_NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS.register_fields([('numCarveoutRegions', NvU32, 0), ('carveoutRegion', c.Array[NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO, Literal[8]], 8)])
|
|
NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_BANK_REMAP_HISTOGRAM(c.Struct):
|
|
SIZE = 8
|
|
maxGroupCount: int
|
|
noSpareGroupCount: int
|
|
struct_NV2080_CTRL_FB_BANK_REMAP_HISTOGRAM.register_fields([('maxGroupCount', NvU32, 0), ('noSpareGroupCount', NvU32, 4)])
|
|
NV2080_CTRL_FB_BANK_REMAP_HISTOGRAM: TypeAlias = struct_NV2080_CTRL_FB_BANK_REMAP_HISTOGRAM
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_BANK_REMAP_ENTRY(c.Struct):
|
|
SIZE = 16
|
|
remapRegVal: int
|
|
timestamp: int
|
|
fbpa: int
|
|
channel: int
|
|
pseudoChannel: int
|
|
group: int
|
|
source: int
|
|
flags: int
|
|
struct_NV2080_CTRL_FB_BANK_REMAP_ENTRY.register_fields([('remapRegVal', NvU32, 0), ('timestamp', NvU32, 4), ('fbpa', NvU8, 8), ('channel', NvU8, 9), ('pseudoChannel', NvU8, 10), ('group', NvU8, 11), ('source', NvU8, 12), ('flags', NvU8, 13)])
|
|
NV2080_CTRL_FB_BANK_REMAP_ENTRY: TypeAlias = struct_NV2080_CTRL_FB_BANK_REMAP_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS(c.Struct):
|
|
SIZE = 8208
|
|
entryCount: int
|
|
flags: int
|
|
histogram: struct_NV2080_CTRL_FB_BANK_REMAP_HISTOGRAM
|
|
entries: c.Array[struct_NV2080_CTRL_FB_BANK_REMAP_ENTRY, Literal[512]]
|
|
struct_NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS.register_fields([('entryCount', NvU32, 0), ('flags', NvU8, 4), ('histogram', NV2080_CTRL_FB_BANK_REMAP_HISTOGRAM, 8), ('entries', c.Array[NV2080_CTRL_FB_BANK_REMAP_ENTRY, Literal[512]], 16)])
|
|
NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
totalMemory: int
|
|
freeMemory: int
|
|
ugpuTotalMemory: c.Array[ctypes.c_uint64, Literal[2]]
|
|
ugpuFreeMemory: c.Array[ctypes.c_uint64, Literal[2]]
|
|
struct_NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS.register_fields([('totalMemory', NvU64, 0), ('freeMemory', NvU64, 8), ('ugpuTotalMemory', c.Array[NvU64, Literal[2]], 16), ('ugpuFreeMemory', c.Array[NvU64, Literal[2]], 32)])
|
|
NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
coherentCpuFbBase: int
|
|
coherentCpuFbEnd: int
|
|
struct_NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS.register_fields([('coherentCpuFbBase', NvU64, 0), ('coherentCpuFbEnd', NvU64, 8)])
|
|
NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
wpr1Start: int
|
|
wpr1End: int
|
|
wpr2Start: int
|
|
wpr2End: int
|
|
fbRegionOfWpr2Start: int
|
|
struct_NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS.register_fields([('wpr1Start', NvU64, 0), ('wpr1End', NvU64, 8), ('wpr2Start', NvU64, 16), ('wpr2End', NvU64, 24), ('fbRegionOfWpr2Start', NvU64, 32)])
|
|
NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hChannel: int
|
|
base: int
|
|
numEntries: int
|
|
struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS.register_fields([('hChannel', NvHandle, 0), ('base', NvU64, 8), ('numEntries', NvU32, 16)])
|
|
NV2080_CTRL_CMD_SET_GPFIFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
physChannelCount: int
|
|
physChannelCountInUse: int
|
|
struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS.register_fields([('physChannelCount', NvU32, 0), ('physChannelCountInUse', NvU32, 4)])
|
|
NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS
|
|
NV2080_CTRL_FIFO_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 2056
|
|
fifoInfoTblSize: int
|
|
fifoInfoTbl: c.Array[struct_NVXXXX_CTRL_XXX_INFO, Literal[256]]
|
|
engineType: int
|
|
struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS.register_fields([('fifoInfoTblSize', NvU32, 0), ('fifoInfoTbl', c.Array[NV2080_CTRL_FIFO_INFO, Literal[256]], 4), ('engineType', NvU32, 2052)])
|
|
NV2080_CTRL_FIFO_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hChannel: int
|
|
struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS.register_fields([('hChannel', NvHandle, 0)])
|
|
NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 536
|
|
bDisable: int
|
|
numChannels: int
|
|
bOnlyDisableScheduling: int
|
|
bRewindGpPut: int
|
|
pRunlistPreemptEvent: ctypes.c_void_p
|
|
hClientList: c.Array[ctypes.c_uint32, Literal[64]]
|
|
hChannelList: c.Array[ctypes.c_uint32, Literal[64]]
|
|
struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS.register_fields([('bDisable', NvBool, 0), ('numChannels', NvU32, 4), ('bOnlyDisableScheduling', NvBool, 8), ('bRewindGpPut', NvBool, 9), ('pRunlistPreemptEvent', NvP64, 16), ('hClientList', c.Array[NvHandle, Literal[64]], 24), ('hChannelList', c.Array[NvHandle, Literal[64]], 280)])
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_MEM_INFO(c.Struct):
|
|
SIZE = 24
|
|
aperture: int
|
|
base: int
|
|
size: int
|
|
struct_NV2080_CTRL_FIFO_MEM_INFO.register_fields([('aperture', NvU32, 0), ('base', NvU64, 8), ('size', NvU64, 16)])
|
|
NV2080_CTRL_FIFO_MEM_INFO: TypeAlias = struct_NV2080_CTRL_FIFO_MEM_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO(c.Struct):
|
|
SIZE = 104
|
|
inst: struct_NV2080_CTRL_FIFO_MEM_INFO
|
|
ramfc: struct_NV2080_CTRL_FIFO_MEM_INFO
|
|
methodBuf: c.Array[struct_NV2080_CTRL_FIFO_MEM_INFO, Literal[2]]
|
|
methodBufCount: int
|
|
struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO.register_fields([('inst', NV2080_CTRL_FIFO_MEM_INFO, 0), ('ramfc', NV2080_CTRL_FIFO_MEM_INFO, 24), ('methodBuf', c.Array[NV2080_CTRL_FIFO_MEM_INFO, Literal[2]], 48), ('methodBufCount', NvU32, 96)])
|
|
NV2080_CTRL_FIFO_CHANNEL_MEM_INFO: TypeAlias = struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS(c.Struct):
|
|
SIZE = 112
|
|
hChannel: int
|
|
chMemInfo: struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO
|
|
struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS.register_fields([('hChannel', NvHandle, 0), ('chMemInfo', NV2080_CTRL_FIFO_CHANNEL_MEM_INFO, 8)])
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
aperture: int
|
|
attribute: int
|
|
struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS.register_fields([('aperture', NvU32, 0), ('attribute', NvU32, 4)])
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY(c.Struct):
|
|
SIZE = 120
|
|
timestampNs: int
|
|
timeRunTotalNs: int
|
|
timeRunNs: int
|
|
swrlId: int
|
|
targetTimeSlice: int
|
|
cumulativePreemptionTime: int
|
|
cumulativeIdleTime: int
|
|
weight: int
|
|
counters: c.Array[ctypes.c_uint64, Literal[8]]
|
|
NvS64: TypeAlias = ctypes.c_int64
|
|
struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY.register_fields([('timestampNs', NvU64, 0), ('timeRunTotalNs', NvS64, 8), ('timeRunNs', NvU32, 16), ('swrlId', NvU32, 20), ('targetTimeSlice', NvU32, 24), ('cumulativePreemptionTime', NvU64, 32), ('cumulativeIdleTime', NvU64, 40), ('weight', NvU32, 48), ('counters', c.Array[NvU64, Literal[8]], 56)])
|
|
NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY: TypeAlias = struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS(c.Struct):
|
|
SIZE = 24024
|
|
engineId: int
|
|
count: int
|
|
entry: c.Array[struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY, Literal[200]]
|
|
schedPolicy: int
|
|
arrEnabled: int
|
|
arrAvgFactor: int
|
|
targetTimesliceNs: int
|
|
struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS.register_fields([('engineId', NvU32, 0), ('count', NvU32, 4), ('entry', c.Array[NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRY, Literal[200]], 8), ('schedPolicy', NvU32, 24008), ('arrEnabled', NvU32, 24012), ('arrAvgFactor', NvU32, 24016), ('targetTimesliceNs', NvU32, 24020)])
|
|
NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
timeout: int
|
|
bEnable: int
|
|
struct_NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS.register_fields([('timeout', NvU32, 0), ('bEnable', NvBool, 4)])
|
|
NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_DEVICE_ENTRY(c.Struct):
|
|
SIZE = 100
|
|
engineData: c.Array[ctypes.c_uint32, Literal[16]]
|
|
pbdmaIds: c.Array[ctypes.c_uint32, Literal[2]]
|
|
pbdmaFaultIds: c.Array[ctypes.c_uint32, Literal[2]]
|
|
numPbdmas: int
|
|
engineName: c.Array[ctypes.c_char, Literal[16]]
|
|
struct_NV2080_CTRL_FIFO_DEVICE_ENTRY.register_fields([('engineData', c.Array[NvU32, Literal[16]], 0), ('pbdmaIds', c.Array[NvU32, Literal[2]], 64), ('pbdmaFaultIds', c.Array[NvU32, Literal[2]], 72), ('numPbdmas', NvU32, 80), ('engineName', c.Array[ctypes.c_char, Literal[16]], 84)])
|
|
NV2080_CTRL_FIFO_DEVICE_ENTRY: TypeAlias = struct_NV2080_CTRL_FIFO_DEVICE_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS(c.Struct):
|
|
SIZE = 3212
|
|
baseIndex: int
|
|
numEntries: int
|
|
bMore: int
|
|
entries: c.Array[struct_NV2080_CTRL_FIFO_DEVICE_ENTRY, Literal[32]]
|
|
struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS.register_fields([('baseIndex', NvU32, 0), ('numEntries', NvU32, 4), ('bMore', NvBool, 8), ('entries', c.Array[NV2080_CTRL_FIFO_DEVICE_ENTRY, Literal[32]], 12)])
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
engineType: int
|
|
vChid: int
|
|
faultType: int
|
|
struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS.register_fields([('engineType', NvU32, 0), ('vChid', NvU32, 4), ('faultType', NvU32, 8)])
|
|
NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
flags: int
|
|
schedPolicy: int
|
|
struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS.register_fields([('flags', NvU32, 0), ('schedPolicy', NvU32, 4)])
|
|
NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hClient: int
|
|
hChannel: int
|
|
hUserdMemory: int
|
|
gpFifoEntries: int
|
|
gpFifoOffset: int
|
|
userdOffset: int
|
|
struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS.register_fields([('hClient', NvHandle, 0), ('hChannel', NvHandle, 4), ('hUserdMemory', NvHandle, 8), ('gpFifoEntries', NvU32, 12), ('gpFifoOffset', NvU64, 16), ('userdOffset', NvU64, 24)])
|
|
NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bDisable: int
|
|
struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS.register_fields([('bDisable', NvBool, 0)])
|
|
NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: int
|
|
size: int
|
|
addressSpace: int
|
|
cacheAttrib: int
|
|
struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS.register_fields([('base', NvU64, 0), ('size', NvU64, 8), ('addressSpace', NvU32, 16), ('cacheAttrib', NvU32, 20)])
|
|
NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 516
|
|
runlistId: int
|
|
bitMask: c.Array[ctypes.c_uint32, Literal[128]]
|
|
struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS.register_fields([('runlistId', NvU32, 0), ('bitMask', c.Array[NvU32, Literal[128]], 4)])
|
|
NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS(c.Struct):
|
|
SIZE = 520
|
|
numChannels: int
|
|
hClientList: c.Array[ctypes.c_uint32, Literal[64]]
|
|
hChannelList: c.Array[ctypes.c_uint32, Literal[64]]
|
|
bEnableAfterKeyRotation: int
|
|
struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS.register_fields([('numChannels', NvU32, 0), ('hClientList', c.Array[NvHandle, Literal[64]], 4), ('hChannelList', c.Array[NvHandle, Literal[64]], 260), ('bEnableAfterKeyRotation', NvBool, 516)])
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS(c.Struct):
|
|
SIZE = 264
|
|
numChannels: int
|
|
hChannelList: c.Array[ctypes.c_uint32, Literal[64]]
|
|
bEnableAfterKeyRotation: int
|
|
struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS.register_fields([('numChannels', NvU32, 0), ('hChannelList', c.Array[NvHandle, Literal[64]], 4), ('bEnableAfterKeyRotation', NvBool, 260)])
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS(c.Struct):
|
|
SIZE = 520
|
|
numChannels: int
|
|
hClientList: c.Array[ctypes.c_uint32, Literal[64]]
|
|
hChannelList: c.Array[ctypes.c_uint32, Literal[64]]
|
|
bEnableAfterKeyRotation: int
|
|
struct_NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS.register_fields([('numChannels', NvU32, 0), ('hClientList', c.Array[NvHandle, Literal[64]], 4), ('hChannelList', c.Array[NvHandle, Literal[64]], 260), ('bEnableAfterKeyRotation', NvBool, 516)])
|
|
NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
engineId: int
|
|
schedPolicy: int
|
|
arrEnabled: int
|
|
targetTimesliceNs: int
|
|
arrAvgFactor: int
|
|
struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS.register_fields([('engineId', NvU32, 0), ('schedPolicy', NvU32, 4), ('arrEnabled', NvU32, 8), ('targetTimesliceNs', NvU32, 12), ('arrAvgFactor', NvU32, 16)])
|
|
NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
engineId: int
|
|
schedPolicy: int
|
|
enableArr: int
|
|
timesliceTargetNs: int
|
|
frequencyForARR: int
|
|
avgFactorForARR: int
|
|
struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS.register_fields([('engineId', NvU32, 0), ('schedPolicy', NvU32, 4), ('enableArr', NvU32, 8), ('timesliceTargetNs', NvU32, 12), ('frequencyForARR', NvU32, 16), ('avgFactorForARR', NvU32, 20)])
|
|
NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 44
|
|
engineId: int
|
|
supportedSchedulers: c.Array[ctypes.c_uint32, Literal[3]]
|
|
bIsArrModeSupported: int
|
|
maxTimesliceNs: int
|
|
minTimesliceNs: int
|
|
maxFrequencyForARR: int
|
|
minFrequencyForARR: int
|
|
maxAvgFactorForARR: int
|
|
minAvgFactorForARR: int
|
|
struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS.register_fields([('engineId', NvU32, 0), ('supportedSchedulers', c.Array[NvU32, Literal[3]], 4), ('bIsArrModeSupported', NvBool, 16), ('maxTimesliceNs', NvU32, 20), ('minTimesliceNs', NvU32, 24), ('maxFrequencyForARR', NvU32, 28), ('minFrequencyForARR', NvU32, 32), ('maxAvgFactorForARR', NvU32, 36), ('minAvgFactorForARR', NvU32, 40)])
|
|
NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS(c.Struct):
|
|
SIZE = 1552
|
|
hClient: int
|
|
hChannelOrTsg: int
|
|
tsgId: int
|
|
numChannels: int
|
|
channelUniqueID: c.Array[ctypes.c_uint32, Literal[128]]
|
|
vasUniqueID: c.Array[ctypes.c_uint32, Literal[128]]
|
|
veid: c.Array[ctypes.c_uint32, Literal[128]]
|
|
struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS.register_fields([('hClient', NvHandle, 0), ('hChannelOrTsg', NvHandle, 4), ('tsgId', NvU32, 8), ('numChannels', NvU32, 12), ('channelUniqueID', c.Array[NvU32, Literal[128]], 16), ('vasUniqueID', c.Array[NvU32, Literal[128]], 528), ('veid', c.Array[NvU32, Literal[128]], 1040)])
|
|
NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS(c.Struct):
|
|
SIZE = 1540
|
|
hClients: c.Array[ctypes.c_uint32, Literal[128]]
|
|
hChannels: c.Array[ctypes.c_uint32, Literal[128]]
|
|
numChannels: int
|
|
channelUniqueIDs: c.Array[ctypes.c_uint32, Literal[128]]
|
|
struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS.register_fields([('hClients', c.Array[NvHandle, Literal[128]], 0), ('hChannels', c.Array[NvHandle, Literal[128]], 512), ('numChannels', NvU32, 1024), ('channelUniqueIDs', c.Array[NvU32, Literal[128]], 1028)])
|
|
NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLA_RANGE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: int
|
|
size: int
|
|
mode: int
|
|
hVASpace: int
|
|
struct_NV2080_CTRL_FLA_RANGE_PARAMS.register_fields([('base', NvU64, 0), ('size', NvU64, 8), ('mode', NvU32, 16), ('hVASpace', NvHandle, 20)])
|
|
NV2080_CTRL_FLA_RANGE_PARAMS: TypeAlias = struct_NV2080_CTRL_FLA_RANGE_PARAMS
|
|
enum_NV2080_CTRL_FLA_ADDRSPACE: dict[int, str] = {(NV2080_CTRL_FLA_ADDRSPACE_SYSMEM:=0): 'NV2080_CTRL_FLA_ADDRSPACE_SYSMEM', (NV2080_CTRL_FLA_ADDRSPACE_FBMEM:=1): 'NV2080_CTRL_FLA_ADDRSPACE_FBMEM'}
|
|
NV2080_CTRL_FLA_ADDRSPACE: TypeAlias = ctypes.c_uint32
|
|
enum_NV2080_CTRL_FLA_ACTION: dict[int, str] = {(NV2080_CTRL_FLA_ACTION_BIND:=0): 'NV2080_CTRL_FLA_ACTION_BIND', (NV2080_CTRL_FLA_ACTION_UNBIND:=1): 'NV2080_CTRL_FLA_ACTION_UNBIND'}
|
|
NV2080_CTRL_FLA_ACTION: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
imbPhysAddr: int
|
|
addrSpace: int
|
|
flaAction: int
|
|
struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS.register_fields([('imbPhysAddr', NvU64, 0), ('addrSpace', NV2080_CTRL_FLA_ADDRSPACE, 8), ('flaAction', NV2080_CTRL_FLA_ACTION, 12)])
|
|
NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS: TypeAlias = struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
base: int
|
|
size: int
|
|
struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS.register_fields([('base', NvU64, 0), ('size', NvU64, 8)])
|
|
NV2080_CTRL_FLA_GET_RANGE_PARAMS: TypeAlias = struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
totalSize: int
|
|
freeSize: int
|
|
struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS.register_fields([('totalSize', NvU64, 0), ('freeSize', NvU64, 8)])
|
|
NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
flcnID: int
|
|
heapSize: int
|
|
heapFree: int
|
|
struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS.register_fields([('flcnID', NvU32, 0), ('heapSize', NvU32, 4), ('heapFree', NvU32, 8)])
|
|
NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
engine: int
|
|
engineArch: int
|
|
struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS.register_fields([('engine', NvU32, 0), ('engineArch', NvU32, 4)])
|
|
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER(c.Struct):
|
|
SIZE = 36
|
|
mask: c.Array[ctypes.c_ubyte, Literal[36]]
|
|
struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER.register_fields([('mask', c.Array[NvU8, Literal[36]], 0)])
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER: TypeAlias = struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
engine: int
|
|
pageSize: int
|
|
offset: int
|
|
size: int
|
|
queueFeatureId: int
|
|
NvUPtr: TypeAlias = ctypes.c_uint64
|
|
struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS.register_fields([('engine', NvU32, 0), ('pageSize', NvU32, 4), ('offset', NvUPtr, 8), ('size', NvU32, 16), ('queueFeatureId', NvU8, 20)])
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 44
|
|
engine: int
|
|
eventFilter: struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER
|
|
queueId: int
|
|
struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS.register_fields([('engine', NvU32, 0), ('eventFilter', NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER, 4), ('queueId', NvU8, 40)])
|
|
NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS
|
|
NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS
|
|
NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
hUserClient: int
|
|
hChannel: int
|
|
alignment: int
|
|
size: int
|
|
bufferHandle: ctypes.c_void_p
|
|
pageCount: int
|
|
physAddr: int
|
|
aperture: int
|
|
kind: int
|
|
pageSize: int
|
|
bIsContigous: int
|
|
bDeviceDescendant: int
|
|
uuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS.register_fields([('hUserClient', NvHandle, 0), ('hChannel', NvHandle, 4), ('alignment', NvU64, 8), ('size', NvU64, 16), ('bufferHandle', NvP64, 24), ('pageCount', NvU64, 32), ('physAddr', NvU64, 40), ('aperture', NvU32, 48), ('kind', NvU32, 52), ('pageSize', NvU32, 56), ('bIsContigous', NvBool, 60), ('bDeviceDescendant', NvBool, 61), ('uuid', c.Array[NvU8, Literal[16]], 62)])
|
|
NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hChannel: int
|
|
totalBufferSize: int
|
|
struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS.register_fields([('hChannel', NvHandle, 0), ('totalBufferSize', NvU64, 8)])
|
|
NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpioPin: int
|
|
bInput: int
|
|
struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS.register_fields([('gpioPin', NvU32, 0), ('bInput', NvBool, 4)])
|
|
NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpioPin: int
|
|
value: int
|
|
struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS.register_fields([('gpioPin', NvU32, 0), ('value', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpioPin: int
|
|
value: int
|
|
struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS.register_fields([('gpioPin', NvU32, 0), ('value', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
function: int
|
|
pin: int
|
|
struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS.register_fields([('function', NvU32, 0), ('pin', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS
|
|
NV2080_CTRL_GPU_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
gpuInfoListSize: int
|
|
gpuInfoList: ctypes.c_void_p
|
|
struct_NV2080_CTRL_GPU_GET_INFO_PARAMS.register_fields([('gpuInfoListSize', NvU32, 0), ('gpuInfoList', NvP64, 8)])
|
|
NV2080_CTRL_GPU_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 580
|
|
gpuInfoListSize: int
|
|
gpuInfoList: c.Array[struct_NVXXXX_CTRL_XXX_INFO, Literal[72]]
|
|
struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS.register_fields([('gpuInfoListSize', NvU32, 0), ('gpuInfoList', c.Array[NV2080_CTRL_GPU_INFO, Literal[72]], 4)])
|
|
NV2080_CTRL_GPU_GET_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS(c.Struct):
|
|
SIZE = 68
|
|
gpuNameStringFlags: int
|
|
gpuNameString: struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString(c.Struct):
|
|
SIZE = 64
|
|
ascii: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString.register_fields([('ascii', c.Array[NvU8, Literal[64]], 0)])
|
|
struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS.register_fields([('gpuNameStringFlags', NvU32, 0), ('gpuNameString', struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString, 4)])
|
|
NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS(c.Struct):
|
|
SIZE = 64
|
|
gpuShortNameString: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS.register_fields([('gpuShortNameString', c.Array[NvU8, Literal[64]], 0)])
|
|
NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_POWER_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
target: int
|
|
newLevel: int
|
|
oldLevel: int
|
|
struct_NV2080_CTRL_GPU_SET_POWER_PARAMS.register_fields([('target', NvU32, 0), ('newLevel', NvU32, 4), ('oldLevel', NvU32, 8)])
|
|
NV2080_CTRL_GPU_SET_POWER_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_POWER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_SDM_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
subdeviceMask: int
|
|
struct_NV2080_CTRL_GPU_GET_SDM_PARAMS.register_fields([('subdeviceMask', NvU32, 0)])
|
|
NV2080_CTRL_GPU_GET_SDM_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_SDM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_SDM_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
subdeviceMask: int
|
|
struct_NV2080_CTRL_GPU_SET_SDM_PARAMS.register_fields([('subdeviceMask', NvU32, 0)])
|
|
NV2080_CTRL_GPU_SET_SDM_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_SDM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
type: int
|
|
struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS.register_fields([('type', NvU32, 0)])
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_REG_OP(c.Struct):
|
|
SIZE = 32
|
|
regOp: int
|
|
regType: int
|
|
regStatus: int
|
|
regQuad: int
|
|
regGroupMask: int
|
|
regSubGroupMask: int
|
|
regOffset: int
|
|
regValueHi: int
|
|
regValueLo: int
|
|
regAndNMaskHi: int
|
|
regAndNMaskLo: int
|
|
struct_NV2080_CTRL_GPU_REG_OP.register_fields([('regOp', NvU8, 0), ('regType', NvU8, 1), ('regStatus', NvU8, 2), ('regQuad', NvU8, 3), ('regGroupMask', NvU32, 4), ('regSubGroupMask', NvU32, 8), ('regOffset', NvU32, 12), ('regValueHi', NvU32, 16), ('regValueLo', NvU32, 20), ('regAndNMaskHi', NvU32, 24), ('regAndNMaskLo', NvU32, 28)])
|
|
NV2080_CTRL_GPU_REG_OP: TypeAlias = struct_NV2080_CTRL_GPU_REG_OP
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
hClientTarget: int
|
|
hChannelTarget: int
|
|
bNonTransactional: int
|
|
reserved00: c.Array[ctypes.c_uint32, Literal[2]]
|
|
regOpCount: int
|
|
regOps: ctypes.c_void_p
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
NV2080_CTRL_GR_ROUTE_INFO: TypeAlias = struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS.register_fields([('hClientTarget', NvHandle, 0), ('hChannelTarget', NvHandle, 4), ('bNonTransactional', NvU32, 8), ('reserved00', c.Array[NvU32, Literal[2]], 12), ('regOpCount', NvU32, 20), ('regOps', NvP64, 24), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 32)])
|
|
NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
engineCount: int
|
|
engineList: ctypes.c_void_p
|
|
struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS.register_fields([('engineCount', NvU32, 0), ('engineList', NvP64, 8)])
|
|
NV2080_CTRL_GPU_GET_ENGINES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS(c.Struct):
|
|
SIZE = 340
|
|
engineCount: int
|
|
engineList: c.Array[ctypes.c_uint32, Literal[84]]
|
|
struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS.register_fields([('engineCount', NvU32, 0), ('engineList', c.Array[NvU32, Literal[84]], 4)])
|
|
NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
engineType: int
|
|
numClasses: int
|
|
classList: ctypes.c_void_p
|
|
struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS.register_fields([('engineType', NvU32, 0), ('numClasses', NvU32, 4), ('classList', NvP64, 8)])
|
|
NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
engineType: int
|
|
mmuFaultId: int
|
|
bSubcontextSupported: int
|
|
struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS.register_fields([('engineType', NvU32, 0), ('mmuFaultId', NvU32, 4), ('bSubcontextSupported', NvBool, 8)])
|
|
NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY(c.Struct):
|
|
SIZE = 32
|
|
gpuPhysAddr: int
|
|
gpuVirtAddr: int
|
|
size: int
|
|
physAttr: int
|
|
bufferId: int
|
|
bInitialize: int
|
|
bNonmapped: int
|
|
struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY.register_fields([('gpuPhysAddr', NvU64, 0), ('gpuVirtAddr', NvU64, 8), ('size', NvU64, 16), ('physAttr', NvU32, 24), ('bufferId', NvU16, 28), ('bInitialize', NvU8, 30), ('bNonmapped', NvU8, 31)])
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY: TypeAlias = struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS(c.Struct):
|
|
SIZE = 560
|
|
engineType: int
|
|
hClient: int
|
|
ChID: int
|
|
hChanClient: int
|
|
hObject: int
|
|
hVirtMemory: int
|
|
virtAddress: int
|
|
size: int
|
|
entryCount: int
|
|
promoteEntry: c.Array[struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY, Literal[16]]
|
|
struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS.register_fields([('engineType', NvU32, 0), ('hClient', NvHandle, 4), ('ChID', NvU32, 8), ('hChanClient', NvHandle, 12), ('hObject', NvHandle, 16), ('hVirtMemory', NvHandle, 20), ('virtAddress', NvU64, 24), ('size', NvU64, 32), ('entryCount', NvU32, 40), ('promoteEntry', c.Array[NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY, Literal[16]], 48)])
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS
|
|
PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS: TypeAlias = c.POINTER[struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
engineType: int
|
|
hClient: int
|
|
ChID: int
|
|
hChanClient: int
|
|
hObject: int
|
|
struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS.register_fields([('engineType', NvU32, 0), ('hClient', NvHandle, 4), ('ChID', NvU32, 8), ('hChanClient', NvHandle, 12), ('hObject', NvHandle, 16)])
|
|
NV2080_CTRL_GPU_EVICT_CTX_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS
|
|
PNV2080_CTRL_GPU_EVICT_CTX_PARAMS: TypeAlias = c.POINTER[struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
engineType: int
|
|
hClient: int
|
|
ChID: int
|
|
hChanClient: int
|
|
hObject: int
|
|
hVirtMemory: int
|
|
physAddress: int
|
|
physAttr: int
|
|
hDmaHandle: int
|
|
index: int
|
|
size: int
|
|
struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS.register_fields([('engineType', NvU32, 0), ('hClient', NvHandle, 4), ('ChID', NvU32, 8), ('hChanClient', NvHandle, 12), ('hObject', NvHandle, 16), ('hVirtMemory', NvHandle, 20), ('physAddress', NvU64, 24), ('physAttr', NvU32, 32), ('hDmaHandle', NvHandle, 36), ('index', NvU32, 40), ('size', NvU64, 48)])
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS
|
|
PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS: TypeAlias = c.POINTER[struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
eccIntrStatus: int
|
|
struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS.register_fields([('eccIntrStatus', NvU32, 0)])
|
|
NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS(c.Struct):
|
|
SIZE = 8
|
|
count: int
|
|
struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS.register_fields([('count', NvU64, 0)])
|
|
NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS(c.Struct):
|
|
SIZE = 40
|
|
enabled: int
|
|
scrubComplete: int
|
|
supported: int
|
|
dbe: struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS
|
|
dbeNonResettable: struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS
|
|
sbe: struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS
|
|
sbeNonResettable: struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS
|
|
struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS.register_fields([('enabled', NvBool, 0), ('scrubComplete', NvBool, 1), ('supported', NvBool, 2), ('dbe', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS, 8), ('dbeNonResettable', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS, 16), ('sbe', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS, 24), ('sbeNonResettable', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS, 32)])
|
|
NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1664
|
|
units: c.Array[struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS, Literal[41]]
|
|
bFatalPoisonError: int
|
|
uncorrectableError: int
|
|
flags: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS.register_fields([('units', c.Array[NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS, Literal[41]], 0), ('bFatalPoisonError', NvBool, 1640), ('uncorrectableError', NvU8, 1641), ('flags', NvU32, 1644), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 1648)])
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
rules: int
|
|
flags: int
|
|
struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS.register_fields([('rules', NvU32, 0), ('flags', NvU32, 4)])
|
|
NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rules: int
|
|
struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS.register_fields([('rules', NvU32, 0)])
|
|
NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
currentConfiguration: int
|
|
defaultConfiguration: int
|
|
struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS.register_fields([('currentConfiguration', NvU32, 0), ('defaultConfiguration', NvU32, 4)])
|
|
NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
newConfiguration: int
|
|
struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS.register_fields([('newConfiguration', NvU32, 0)])
|
|
NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
statuses: int
|
|
flags: int
|
|
struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS.register_fields([('statuses', NvU32, 0), ('flags', NvU8, 4)])
|
|
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gpcMask: int
|
|
struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS.register_fields([('gpcMask', NvU32, 0)])
|
|
NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: int
|
|
tpcMask: int
|
|
struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS.register_fields([('gpcId', NvU32, 0), ('tpcMask', NvU32, 4)])
|
|
NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: int
|
|
zcullMask: int
|
|
struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS.register_fields([('gpcId', NvU32, 0), ('zcullMask', NvU32, 4)])
|
|
NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS(c.Struct):
|
|
SIZE = 136
|
|
buildDate: int
|
|
marketingName: c.Array[ctypes.c_ubyte, Literal[24]]
|
|
serialNumber: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
memoryManufacturer: int
|
|
memoryPartID: c.Array[ctypes.c_ubyte, Literal[20]]
|
|
memoryDateCode: c.Array[ctypes.c_ubyte, Literal[6]]
|
|
productPartNumber: c.Array[ctypes.c_ubyte, Literal[20]]
|
|
boardRevision: c.Array[ctypes.c_ubyte, Literal[3]]
|
|
boardType: int
|
|
board699PartNumber: c.Array[ctypes.c_ubyte, Literal[20]]
|
|
board965PartNumber: c.Array[ctypes.c_ubyte, Literal[20]]
|
|
struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS.register_fields([('buildDate', NvU32, 0), ('marketingName', c.Array[NvU8, Literal[24]], 4), ('serialNumber', c.Array[NvU8, Literal[16]], 28), ('memoryManufacturer', NvU8, 44), ('memoryPartID', c.Array[NvU8, Literal[20]], 45), ('memoryDateCode', c.Array[NvU8, Literal[6]], 65), ('productPartNumber', c.Array[NvU8, Literal[20]], 71), ('boardRevision', c.Array[NvU8, Literal[3]], 91), ('boardType', NvU8, 94), ('board699PartNumber', c.Array[NvU8, Literal[20]], 95), ('board965PartNumber', c.Array[NvU8, Literal[20]], 115)])
|
|
NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ID_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gpuId: int
|
|
struct_NV2080_CTRL_GPU_GET_ID_PARAMS.register_fields([('gpuId', NvU32, 0)])
|
|
NV2080_CTRL_GPU_GET_ID_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
mode: int
|
|
struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS.register_fields([('mode', NvU32, 0)])
|
|
NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
currentMode: int
|
|
struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS.register_fields([('currentMode', NvU32, 0)])
|
|
NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS(c.Struct):
|
|
SIZE = 144
|
|
engineType: int
|
|
partnershipClassId: int
|
|
runqueue: int
|
|
numPartners: int
|
|
partnerList: c.Array[ctypes.c_uint32, Literal[32]]
|
|
struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS.register_fields([('engineType', NvU32, 0), ('partnershipClassId', NvU32, 4), ('runqueue', NvU32, 8), ('numPartners', NvU32, 12), ('partnerList', c.Array[NvU32, Literal[32]], 16)])
|
|
NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS(c.Struct):
|
|
SIZE = 268
|
|
index: int
|
|
flags: int
|
|
length: int
|
|
data: c.Array[ctypes.c_ubyte, Literal[256]]
|
|
struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS.register_fields([('index', NvU32, 0), ('flags', NvU32, 4), ('length', NvU32, 8), ('data', c.Array[NvU8, Literal[256]], 12)])
|
|
NV2080_CTRL_GPU_GET_GID_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS(c.Struct):
|
|
SIZE = 5
|
|
objectType: c.Array[ctypes.c_char, Literal[3]]
|
|
version: int
|
|
subversion: int
|
|
struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS.register_fields([('objectType', c.Array[ctypes.c_char, Literal[3]], 0), ('version', NvU8, 3), ('subversion', NvU8, 4)])
|
|
NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
isOptimusEnabled: int
|
|
struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS.register_fields([('isOptimusEnabled', NvBool, 0)])
|
|
NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
targetEngine: int
|
|
ipVersion: int
|
|
struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS.register_fields([('targetEngine', NvU32, 0), ('ipVersion', NvU32, 4)])
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
attribute: int
|
|
bSupported: int
|
|
struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS.register_fields([('attribute', NvU32, 0), ('bSupported', NvBool, 4)])
|
|
NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
attribute: int
|
|
value: int
|
|
struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS.register_fields([('attribute', NvU32, 0), ('value', NvU32, 4)])
|
|
NV2080_CTRL_CMD_GPU_ILLUM_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS
|
|
NV2080_CTRL_GPU_GET_ILLUM_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS
|
|
NV2080_CTRL_GPU_SET_ILLUM_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
version: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS.register_fields([('version', c.Array[NvU8, Literal[16]], 0)])
|
|
NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fwVersion: int
|
|
oemVersion: int
|
|
siliconRevision: int
|
|
hwbcResourceType: int
|
|
struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS.register_fields([('fwVersion', NvU32, 0), ('oemVersion', NvU8, 4), ('siliconRevision', NvU8, 5), ('hwbcResourceType', NvU8, 6)])
|
|
NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS(c.Struct):
|
|
SIZE = 1204
|
|
bridgeCount: int
|
|
hPhysicalBridges: c.Array[ctypes.c_uint32, Literal[100]]
|
|
bridgeList: c.Array[struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS, Literal[100]]
|
|
struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS.register_fields([('bridgeCount', NvU8, 0), ('hPhysicalBridges', c.Array[NvHandle, Literal[100]], 4), ('bridgeList', c.Array[NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS, Literal[100]], 404)])
|
|
NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
bus: int
|
|
device: int
|
|
func: int
|
|
oemVersion: int
|
|
siliconRevision: int
|
|
hwbcResourceType: int
|
|
domain: int
|
|
fwVersion: int
|
|
struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS.register_fields([('bus', NvU8, 0), ('device', NvU8, 1), ('func', NvU8, 2), ('oemVersion', NvU8, 3), ('siliconRevision', NvU8, 4), ('hwbcResourceType', NvU8, 5), ('domain', NvU32, 8), ('fwVersion', NvU32, 12)])
|
|
NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS(c.Struct):
|
|
SIZE = 2004
|
|
bridgeCount: int
|
|
physicalBridgeIds: c.Array[ctypes.c_uint32, Literal[100]]
|
|
bridgeList: c.Array[struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS, Literal[100]]
|
|
struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS.register_fields([('bridgeCount', NvU8, 0), ('physicalBridgeIds', c.Array[NvU32, Literal[100]], 4), ('bridgeList', c.Array[NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS, Literal[100]], 404)])
|
|
NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
scrubberStatus: int
|
|
remainingTimeMs: int
|
|
scrubStartAddr: int
|
|
scrubEndAddr: int
|
|
struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS.register_fields([('scrubberStatus', NvU32, 0), ('remainingTimeMs', NvU32, 4), ('scrubStartAddr', NvU64, 8), ('scrubEndAddr', NvU64, 16)])
|
|
NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
minStartAddr: int
|
|
maxEndAddr: int
|
|
struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS.register_fields([('minStartAddr', NvU64, 0), ('maxEndAddr', NvU64, 8)])
|
|
NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
gpcId: int
|
|
numPesInGpc: int
|
|
activePesMask: int
|
|
maxTpcPerGpcCount: int
|
|
tpcToPesMap: c.Array[ctypes.c_uint32, Literal[10]]
|
|
struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS.register_fields([('gpcId', NvU32, 0), ('numPesInGpc', NvU32, 4), ('activePesMask', NvU32, 8), ('maxTpcPerGpcCount', NvU32, 12), ('tpcToPesMap', c.Array[NvU32, Literal[10]], 16)])
|
|
NV2080_CTRL_GPU_GET_PES_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS(c.Struct):
|
|
SIZE = 504
|
|
oemInfo: c.Array[ctypes.c_ubyte, Literal[504]]
|
|
struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS.register_fields([('oemInfo', c.Array[NvU8, Literal[504]], 0)])
|
|
NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS
|
|
enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE: dict[int, str] = {(NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS:=0): 'NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS', (NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE:=1): 'NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE'}
|
|
NV2080_CTRL_VPR_INFO_QUERY_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
queryType: int
|
|
bIsVprEnabled: int
|
|
vprStartAddressInBytes: int
|
|
vprEndAddressInBytes: int
|
|
struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS.register_fields([('queryType', NV2080_CTRL_VPR_INFO_QUERY_TYPE, 0), ('bIsVprEnabled', NvBool, 4), ('vprStartAddressInBytes', NvU64, 8), ('vprEndAddressInBytes', NvU64, 16)])
|
|
NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS
|
|
enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE: dict[int, str] = {(NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264:=0): 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264', (NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC:=1): 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC', (NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1:=2): 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1'}
|
|
NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
queryType: int
|
|
encoderCapacity: int
|
|
struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS.register_fields([('queryType', NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE, 0), ('encoderCapacity', NvU32, 4)])
|
|
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
encoderSessionCount: int
|
|
averageEncodeFps: int
|
|
averageEncodeLatency: int
|
|
struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS.register_fields([('encoderSessionCount', NvU32, 0), ('averageEncodeFps', NvU32, 4), ('averageEncodeLatency', NvU32, 8)])
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVENC_SW_SESSION_INFO(c.Struct):
|
|
SIZE = 32
|
|
processId: int
|
|
subProcessId: int
|
|
sessionId: int
|
|
codecType: int
|
|
hResolution: int
|
|
vResolution: int
|
|
averageEncodeFps: int
|
|
averageEncodeLatency: int
|
|
struct_NV2080_CTRL_NVENC_SW_SESSION_INFO.register_fields([('processId', NvU32, 0), ('subProcessId', NvU32, 4), ('sessionId', NvU32, 8), ('codecType', NvU32, 12), ('hResolution', NvU32, 16), ('vResolution', NvU32, 20), ('averageEncodeFps', NvU32, 24), ('averageEncodeLatency', NvU32, 28)])
|
|
NV2080_CTRL_NVENC_SW_SESSION_INFO: TypeAlias = struct_NV2080_CTRL_NVENC_SW_SESSION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
sessionInfoTblEntry: int
|
|
sessionInfoTbl: ctypes.c_void_p
|
|
struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS.register_fields([('sessionInfoTblEntry', NvU32, 0), ('sessionInfoTbl', NvP64, 8)])
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fabricBaseAddr: int
|
|
struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS.register_fields([('fabricBaseAddr', NvU64, 0)])
|
|
NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
handle: int
|
|
struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS.register_fields([('handle', NvU32, 0)])
|
|
NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
statusMask: int
|
|
xusbData: int
|
|
ppcData: int
|
|
struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS.register_fields([('statusMask', NvU32, 0), ('xusbData', NvU32, 4), ('ppcData', NvU32, 8)])
|
|
NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_PARTITION_SPAN(c.Struct):
|
|
SIZE = 16
|
|
lo: int
|
|
hi: int
|
|
struct_NV2080_CTRL_GPU_PARTITION_SPAN.register_fields([('lo', NvU64, 0), ('hi', NvU64, 8)])
|
|
NV2080_CTRL_GPU_PARTITION_SPAN: TypeAlias = struct_NV2080_CTRL_GPU_PARTITION_SPAN
|
|
@c.record
|
|
class struct_NV2080_CTRL_EXEC_PARTITION_SPAN(c.Struct):
|
|
SIZE = 16
|
|
lo: int
|
|
hi: int
|
|
struct_NV2080_CTRL_EXEC_PARTITION_SPAN.register_fields([('lo', NvU64, 0), ('hi', NvU64, 8)])
|
|
NV2080_CTRL_EXEC_PARTITION_SPAN: TypeAlias = struct_NV2080_CTRL_EXEC_PARTITION_SPAN
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_PARTITION_INFO(c.Struct):
|
|
SIZE = 48
|
|
swizzId: int
|
|
uuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
partitionFlag: int
|
|
bValid: int
|
|
placement: struct_NV2080_CTRL_GPU_PARTITION_SPAN
|
|
struct_NV2080_CTRL_GPU_SET_PARTITION_INFO.register_fields([('swizzId', NvU32, 0), ('uuid', c.Array[NvU8, Literal[16]], 4), ('partitionFlag', NvU32, 20), ('bValid', NvBool, 24), ('placement', NV2080_CTRL_GPU_PARTITION_SPAN, 32)])
|
|
NV2080_CTRL_GPU_SET_PARTITION_INFO: TypeAlias = struct_NV2080_CTRL_GPU_SET_PARTITION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS(c.Struct):
|
|
SIZE = 392
|
|
partitionCount: int
|
|
partitionInfo: c.Array[struct_NV2080_CTRL_GPU_SET_PARTITION_INFO, Literal[8]]
|
|
struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS.register_fields([('partitionCount', NvU32, 0), ('partitionInfo', c.Array[NV2080_CTRL_GPU_SET_PARTITION_INFO, Literal[8]], 8)])
|
|
NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PARTITION_INFO(c.Struct):
|
|
SIZE = 232
|
|
swizzId: int
|
|
partitionFlag: int
|
|
grEngCount: int
|
|
veidCount: int
|
|
smCount: int
|
|
ceCount: int
|
|
nvEncCount: int
|
|
nvDecCount: int
|
|
nvJpgCount: int
|
|
nvOfaCount: int
|
|
gpcCount: int
|
|
virtualGpcCount: int
|
|
gfxGpcCount: int
|
|
gpcsPerGr: c.Array[ctypes.c_uint32, Literal[8]]
|
|
virtualGpcsPerGr: c.Array[ctypes.c_uint32, Literal[8]]
|
|
gfxGpcPerGr: c.Array[ctypes.c_uint32, Literal[8]]
|
|
veidsPerGr: c.Array[ctypes.c_uint32, Literal[8]]
|
|
memSize: int
|
|
span: struct_NV2080_CTRL_GPU_PARTITION_SPAN
|
|
bValid: int
|
|
bPartitionError: int
|
|
validCTSIdMask: int
|
|
validGfxCTSIdMask: int
|
|
struct_NV2080_CTRL_GPU_GET_PARTITION_INFO.register_fields([('swizzId', NvU32, 0), ('partitionFlag', NvU32, 4), ('grEngCount', NvU32, 8), ('veidCount', NvU32, 12), ('smCount', NvU32, 16), ('ceCount', NvU32, 20), ('nvEncCount', NvU32, 24), ('nvDecCount', NvU32, 28), ('nvJpgCount', NvU32, 32), ('nvOfaCount', NvU32, 36), ('gpcCount', NvU32, 40), ('virtualGpcCount', NvU32, 44), ('gfxGpcCount', NvU32, 48), ('gpcsPerGr', c.Array[NvU32, Literal[8]], 52), ('virtualGpcsPerGr', c.Array[NvU32, Literal[8]], 84), ('gfxGpcPerGr', c.Array[NvU32, Literal[8]], 116), ('veidsPerGr', c.Array[NvU32, Literal[8]], 148), ('memSize', NvU64, 184), ('span', NV2080_CTRL_GPU_PARTITION_SPAN, 192), ('bValid', NvBool, 208), ('bPartitionError', NvBool, 209), ('validCTSIdMask', NvU64, 216), ('validGfxCTSIdMask', NvU64, 224)])
|
|
NV2080_CTRL_GPU_GET_PARTITION_INFO: TypeAlias = struct_NV2080_CTRL_GPU_GET_PARTITION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS(c.Struct):
|
|
SIZE = 1864
|
|
queryPartitionInfo: c.Array[struct_NV2080_CTRL_GPU_GET_PARTITION_INFO, Literal[8]]
|
|
validPartitionCount: int
|
|
bGetAllPartitionInfo: int
|
|
struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS.register_fields([('queryPartitionInfo', c.Array[NV2080_CTRL_GPU_GET_PARTITION_INFO, Literal[8]], 0), ('validPartitionCount', NvU32, 1856), ('bGetAllPartitionInfo', NvBool, 1860)])
|
|
NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS(c.Struct):
|
|
SIZE = 44
|
|
swizzId: int
|
|
gpcCountPerSmcEng: c.Array[ctypes.c_uint32, Literal[8]]
|
|
updateSmcEngMask: int
|
|
bUseAllGPCs: int
|
|
struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS.register_fields([('swizzId', NvU32, 0), ('gpcCountPerSmcEng', c.Array[NvU32, Literal[8]], 4), ('updateSmcEngMask', NvU32, 36), ('bUseAllGPCs', NvBool, 40)])
|
|
NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_FAULT_PACKET(c.Struct):
|
|
SIZE = 32
|
|
data: c.Array[ctypes.c_ubyte, Literal[32]]
|
|
struct_NV2080_CTRL_GPU_FAULT_PACKET.register_fields([('data', c.Array[NvU8, Literal[32]], 0)])
|
|
NV2080_CTRL_GPU_FAULT_PACKET: TypeAlias = struct_NV2080_CTRL_GPU_FAULT_PACKET
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
faultPacket: struct_NV2080_CTRL_GPU_FAULT_PACKET
|
|
struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS.register_fields([('faultPacket', NV2080_CTRL_GPU_FAULT_PACKET, 0)])
|
|
NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS
|
|
NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS(c.Struct):
|
|
SIZE = 1008
|
|
engineList: c.Array[ctypes.c_uint32, Literal[84]]
|
|
runlistPriBase: c.Array[ctypes.c_uint32, Literal[84]]
|
|
runlistId: c.Array[ctypes.c_uint32, Literal[84]]
|
|
struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS.register_fields([('engineList', c.Array[NvU32, Literal[84]], 0), ('runlistPriBase', c.Array[NvU32, Literal[84]], 336), ('runlistId', c.Array[NvU32, Literal[84]], 672)])
|
|
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS(c.Struct):
|
|
SIZE = 672
|
|
engineList: c.Array[ctypes.c_uint32, Literal[84]]
|
|
hwEngineID: c.Array[ctypes.c_uint32, Literal[84]]
|
|
struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS.register_fields([('engineList', c.Array[NvU32, Literal[84]], 0), ('hwEngineID', c.Array[NvU32, Literal[84]], 336)])
|
|
NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
sessionCount: int
|
|
averageFPS: int
|
|
averageLatency: int
|
|
struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS.register_fields([('sessionCount', NvU32, 0), ('averageFPS', NvU32, 4), ('averageLatency', NvU32, 8)])
|
|
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO(c.Struct):
|
|
SIZE = 52
|
|
processId: int
|
|
subProcessId: int
|
|
vgpuInstanceId: int
|
|
sessionId: int
|
|
sessionType: int
|
|
displayOrdinal: int
|
|
sessionFlags: int
|
|
hMaxResolution: int
|
|
vMaxResolution: int
|
|
hResolution: int
|
|
vResolution: int
|
|
averageFPS: int
|
|
averageLatency: int
|
|
struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO.register_fields([('processId', NvU32, 0), ('subProcessId', NvU32, 4), ('vgpuInstanceId', NvU32, 8), ('sessionId', NvU32, 12), ('sessionType', NvU32, 16), ('displayOrdinal', NvU32, 20), ('sessionFlags', NvU32, 24), ('hMaxResolution', NvU32, 28), ('vMaxResolution', NvU32, 32), ('hResolution', NvU32, 36), ('vResolution', NvU32, 40), ('averageFPS', NvU32, 44), ('averageLatency', NvU32, 48)])
|
|
NV2080_CTRL_NVFBC_SW_SESSION_INFO: TypeAlias = struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS(c.Struct):
|
|
SIZE = 13316
|
|
sessionInfoCount: int
|
|
sessionInfoTbl: c.Array[struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO, Literal[256]]
|
|
struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS.register_fields([('sessionInfoCount', NvU32, 0), ('sessionInfoTbl', c.Array[NV2080_CTRL_NVFBC_SW_SESSION_INFO, Literal[256]], 4)])
|
|
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
firstAsyncCEIdx: int
|
|
struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS.register_fields([('firstAsyncCEIdx', NvU32, 0)])
|
|
NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
vmmuSegmentSize: int
|
|
struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS.register_fields([('vmmuSegmentSize', NvU64, 0)])
|
|
NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS(c.Struct):
|
|
SIZE = 280
|
|
partitionFlag: int
|
|
partitionCount: int
|
|
availableSpans: c.Array[struct_NV2080_CTRL_GPU_PARTITION_SPAN, Literal[8]]
|
|
availableSpansCount: int
|
|
totalPartitionCount: int
|
|
totalSpans: c.Array[struct_NV2080_CTRL_GPU_PARTITION_SPAN, Literal[8]]
|
|
totalSpansCount: int
|
|
bStaticInfo: int
|
|
struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS.register_fields([('partitionFlag', NvU32, 0), ('partitionCount', NvU32, 4), ('availableSpans', c.Array[NV2080_CTRL_GPU_PARTITION_SPAN, Literal[8]], 8), ('availableSpansCount', NvU32, 136), ('totalPartitionCount', NvU32, 140), ('totalSpans', c.Array[NV2080_CTRL_GPU_PARTITION_SPAN, Literal[8]], 144), ('totalSpansCount', NvU32, 272), ('bStaticInfo', NvBool, 276)])
|
|
NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS
|
|
NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
partitioningMode: int
|
|
struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS.register_fields([('partitioningMode', NvU32, 0)])
|
|
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO(c.Struct):
|
|
SIZE = 64
|
|
partitionFlag: int
|
|
grCount: int
|
|
gfxGrCount: int
|
|
gpcCount: int
|
|
virtualGpcCount: int
|
|
gfxGpcCount: int
|
|
veidCount: int
|
|
smCount: int
|
|
ceCount: int
|
|
nvEncCount: int
|
|
nvDecCount: int
|
|
nvJpgCount: int
|
|
nvOfaCount: int
|
|
memorySize: int
|
|
struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO.register_fields([('partitionFlag', NvU32, 0), ('grCount', NvU32, 4), ('gfxGrCount', NvU32, 8), ('gpcCount', NvU32, 12), ('virtualGpcCount', NvU32, 16), ('gfxGpcCount', NvU32, 20), ('veidCount', NvU32, 24), ('smCount', NvU32, 28), ('ceCount', NvU32, 32), ('nvEncCount', NvU32, 36), ('nvDecCount', NvU32, 40), ('nvJpgCount', NvU32, 44), ('nvOfaCount', NvU32, 48), ('memorySize', NvU64, 56)])
|
|
NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO: TypeAlias = struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS(c.Struct):
|
|
SIZE = 5768
|
|
descCount: int
|
|
partitionDescs: c.Array[struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO, Literal[90]]
|
|
struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS.register_fields([('descCount', NvU32, 0), ('partitionDescs', c.Array[NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO, Literal[90]], 8)])
|
|
NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
maxSupportedPageSize: int
|
|
struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS.register_fields([('maxSupportedPageSize', NvU64, 0)])
|
|
NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
gpcId: int
|
|
count: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS.register_fields([('gpcId', NvU32, 0), ('count', NvU32, 4), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 8)])
|
|
NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
swizzId: c.Array[ctypes.c_uint32, Literal[9]]
|
|
partitionCount: int
|
|
struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS.register_fields([('swizzId', c.Array[NvU32, Literal[9]], 0), ('partitionCount', NvU32, 36)])
|
|
NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS(c.Struct):
|
|
SIZE = 3812
|
|
idType: int
|
|
id: int
|
|
pidTblCount: int
|
|
pidTbl: c.Array[ctypes.c_uint32, Literal[950]]
|
|
struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS.register_fields([('idType', NvU32, 0), ('id', NvU32, 4), ('pidTblCount', NvU32, 8), ('pidTbl', c.Array[NvU32, Literal[950]], 12)])
|
|
NV2080_CTRL_GPU_GET_PIDS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO(c.Struct):
|
|
SIZE = 8
|
|
computeInstanceId: int
|
|
gpuInstanceId: int
|
|
struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO.register_fields([('computeInstanceId', NvU32, 0), ('gpuInstanceId', NvU32, 4)])
|
|
NV2080_CTRL_SMC_SUBSCRIPTION_INFO: TypeAlias = struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA(c.Struct):
|
|
SIZE = 48
|
|
memPrivate: int
|
|
memSharedOwned: int
|
|
memSharedDuped: int
|
|
protectedMemPrivate: int
|
|
protectedMemSharedOwned: int
|
|
protectedMemSharedDuped: int
|
|
struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA.register_fields([('memPrivate', NvU64, 0), ('memSharedOwned', NvU64, 8), ('memSharedDuped', NvU64, 16), ('protectedMemPrivate', NvU64, 24), ('protectedMemSharedOwned', NvU64, 32), ('protectedMemSharedDuped', NvU64, 40)])
|
|
NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA: TypeAlias = struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA
|
|
@c.record
|
|
class union_NV2080_CTRL_GPU_PID_INFO_DATA(c.Struct):
|
|
SIZE = 48
|
|
vidMemUsage: struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA
|
|
union_NV2080_CTRL_GPU_PID_INFO_DATA.register_fields([('vidMemUsage', NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA, 0)])
|
|
NV2080_CTRL_GPU_PID_INFO_DATA: TypeAlias = union_NV2080_CTRL_GPU_PID_INFO_DATA
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_PID_INFO(c.Struct):
|
|
SIZE = 72
|
|
pid: int
|
|
index: int
|
|
result: int
|
|
data: union_NV2080_CTRL_GPU_PID_INFO_DATA
|
|
smcSubscription: struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO
|
|
struct_NV2080_CTRL_GPU_PID_INFO.register_fields([('pid', NvU32, 0), ('index', NvU32, 4), ('result', NvU32, 8), ('data', NV2080_CTRL_GPU_PID_INFO_DATA, 16), ('smcSubscription', NV2080_CTRL_SMC_SUBSCRIPTION_INFO, 64)])
|
|
NV2080_CTRL_GPU_PID_INFO: TypeAlias = struct_NV2080_CTRL_GPU_PID_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS(c.Struct):
|
|
SIZE = 14408
|
|
pidInfoListCount: int
|
|
pidInfoList: c.Array[struct_NV2080_CTRL_GPU_PID_INFO, Literal[200]]
|
|
struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS.register_fields([('pidInfoListCount', NvU32, 0), ('pidInfoList', c.Array[NV2080_CTRL_GPU_PID_INFO, Literal[200]], 8)])
|
|
NV2080_CTRL_GPU_GET_PID_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
faultType: int
|
|
struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS.register_fields([('faultType', NvU32, 0)])
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS
|
|
enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE: dict[int, str] = {(NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT:=0): 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT', (NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT:=1): 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT', (NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM:=2): 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM', (NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG:=3): 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG', (NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX:=4): 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX'}
|
|
NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG(c.Struct):
|
|
SIZE = 8
|
|
type: int
|
|
data: struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data(c.Struct):
|
|
SIZE = 4
|
|
timeslice: int
|
|
struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data.register_fields([('timeslice', NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE, 0)])
|
|
struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG.register_fields([('type', NvU32, 0), ('data', struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data, 4)])
|
|
NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG: TypeAlias = struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
config: struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG
|
|
struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS.register_fields([('config', NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG, 0)])
|
|
NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 260
|
|
numConfigs: int
|
|
configList: c.Array[struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG, Literal[32]]
|
|
struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS.register_fields([('numConfigs', NvU32, 0), ('configList', c.Array[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG, Literal[32]], 4)])
|
|
NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_GFID_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
domain: int
|
|
bus: int
|
|
device: int
|
|
func: int
|
|
gfid: int
|
|
gfidMask: int
|
|
struct_NV2080_CTRL_GPU_GET_GFID_PARAMS.register_fields([('domain', NvU32, 0), ('bus', NvU8, 4), ('device', NvU8, 5), ('func', NvU8, 6), ('gfid', NvU32, 8), ('gfidMask', NvU32, 12)])
|
|
NV2080_CTRL_GPU_GET_GFID_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_GFID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gfid: int
|
|
bEnable: int
|
|
fabricPartitionId: int
|
|
struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS.register_fields([('gfid', NvU32, 0), ('bEnable', NvBool, 4), ('fabricPartitionId', NvU32, 8)])
|
|
NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
addressStart: int
|
|
addressLength: int
|
|
protection: int
|
|
struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS.register_fields([('addressStart', NvU64, 0), ('addressLength', NvU64, 8), ('protection', NvU32, 16)])
|
|
NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS(c.Struct):
|
|
SIZE = 2608
|
|
engineCount: int
|
|
engineList: c.Array[ctypes.c_uint32, Literal[200]]
|
|
engineStateLoadTime: c.Array[ctypes.c_uint64, Literal[200]]
|
|
engineIsInit: c.Array[ctypes.c_ubyte, Literal[200]]
|
|
struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS.register_fields([('engineCount', NvU32, 0), ('engineList', c.Array[NvU32, Literal[200]], 4), ('engineStateLoadTime', c.Array[NvU64, Literal[200]], 808), ('engineIsInit', c.Array[NvBool, Literal[200]], 2408)])
|
|
NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 20804
|
|
engineCount: int
|
|
engineID: c.Array[ctypes.c_uint32, Literal[200]]
|
|
engineName: c.Array[c.Array[ctypes.c_char, Literal[100]], Literal[200]]
|
|
struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS.register_fields([('engineCount', NvU32, 0), ('engineID', c.Array[NvU32, Literal[200]], 4), ('engineName', c.Array[c.Array[ctypes.c_char, Literal[100]], Literal[200]], 804)])
|
|
NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS(c.Struct):
|
|
SIZE = 3240
|
|
hClientTarget: int
|
|
hChannelTarget: int
|
|
bNonTransactional: int
|
|
reserved00: c.Array[ctypes.c_uint32, Literal[2]]
|
|
regOpCount: int
|
|
regOps: c.Array[struct_NV2080_CTRL_GPU_REG_OP, Literal[100]]
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS.register_fields([('hClientTarget', NvHandle, 0), ('hChannelTarget', NvHandle, 4), ('bNonTransactional', NvU32, 8), ('reserved00', c.Array[NvU32, Literal[2]], 12), ('regOpCount', NvU32, 20), ('regOps', c.Array[NV2080_CTRL_GPU_REG_OP, Literal[100]], 24), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 3224)])
|
|
NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SKYLINE_INFO(c.Struct):
|
|
SIZE = 76
|
|
skylineVgpcSize: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
singletonVgpcMask: int
|
|
maxInstances: int
|
|
computeSizeFlag: int
|
|
struct_NV2080_CTRL_GPU_SKYLINE_INFO.register_fields([('skylineVgpcSize', c.Array[NvU8, Literal[64]], 0), ('singletonVgpcMask', NvU32, 64), ('maxInstances', NvU32, 68), ('computeSizeFlag', NvU32, 72)])
|
|
NV2080_CTRL_GPU_SKYLINE_INFO: TypeAlias = struct_NV2080_CTRL_GPU_SKYLINE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS(c.Struct):
|
|
SIZE = 688
|
|
skylineTable: c.Array[struct_NV2080_CTRL_GPU_SKYLINE_INFO, Literal[9]]
|
|
validEntries: int
|
|
struct_NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS.register_fields([('skylineTable', c.Array[NV2080_CTRL_GPU_SKYLINE_INFO, Literal[9]], 0), ('validEntries', NvU32, 684)])
|
|
NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO(c.Struct):
|
|
SIZE = 52
|
|
gpuId: int
|
|
gpuUuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
p2pCaps: int
|
|
p2pOptimalReadCEs: int
|
|
p2pOptimalWriteCEs: int
|
|
p2pCapsStatus: c.Array[ctypes.c_ubyte, Literal[9]]
|
|
busPeerId: int
|
|
busEgmPeerId: int
|
|
struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO.register_fields([('gpuId', NvU32, 0), ('gpuUuid', c.Array[NvU8, Literal[16]], 4), ('p2pCaps', NvU32, 20), ('p2pOptimalReadCEs', NvU32, 24), ('p2pOptimalWriteCEs', NvU32, 28), ('p2pCapsStatus', c.Array[NvU8, Literal[9]], 32), ('busPeerId', NvU32, 44), ('busEgmPeerId', NvU32, 48)])
|
|
NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO: TypeAlias = struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS(c.Struct):
|
|
SIZE = 1672
|
|
bAllCaps: int
|
|
bUseUuid: int
|
|
peerGpuCount: int
|
|
peerGpuCaps: c.Array[struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO, Literal[32]]
|
|
struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS.register_fields([('bAllCaps', NvBool, 0), ('bUseUuid', NvBool, 1), ('peerGpuCount', NvU32, 4), ('peerGpuCaps', c.Array[NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO, Literal[32]], 8)])
|
|
NV2080_CTRL_GET_P2P_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_COMPUTE_PROFILE(c.Struct):
|
|
SIZE = 20
|
|
computeSize: int
|
|
flags: int
|
|
gfxGpcCount: int
|
|
gpcCount: int
|
|
veidCount: int
|
|
smCount: int
|
|
struct_NV2080_CTRL_GPU_COMPUTE_PROFILE.register_fields([('computeSize', NvU8, 0), ('flags', NvU16, 2), ('gfxGpcCount', NvU32, 4), ('gpcCount', NvU32, 8), ('veidCount', NvU32, 12), ('smCount', NvU32, 16)])
|
|
NV2080_CTRL_GPU_COMPUTE_PROFILE: TypeAlias = struct_NV2080_CTRL_GPU_COMPUTE_PROFILE
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS(c.Struct):
|
|
SIZE = 168
|
|
partitionFlag: int
|
|
profileCount: int
|
|
profiles: c.Array[struct_NV2080_CTRL_GPU_COMPUTE_PROFILE, Literal[8]]
|
|
struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS.register_fields([('partitionFlag', NvU32, 0), ('profileCount', NvU32, 4), ('profiles', c.Array[NV2080_CTRL_GPU_COMPUTE_PROFILE, Literal[8]], 8)])
|
|
NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
state: int
|
|
status: int
|
|
clusterUuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
fabricPartitionId: int
|
|
fabricCaps: int
|
|
fabricCliqueId: int
|
|
fabricHealthMask: int
|
|
fabricHealthSummary: int
|
|
struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS.register_fields([('state', NvU8, 0), ('status', NV_STATUS, 4), ('clusterUuid', c.Array[NvU8, Literal[16]], 8), ('fabricPartitionId', NvU16, 24), ('fabricCaps', NvU64, 32), ('fabricCliqueId', NvU32, 40), ('fabricHealthMask', NvU32, 44), ('fabricHealthSummary', NvU8, 48)])
|
|
NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pciDevId: int
|
|
chipSku: c.Array[ctypes.c_ubyte, Literal[4]]
|
|
chipMajor: int
|
|
chipMinor: int
|
|
struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS.register_fields([('pciDevId', NvU32, 0), ('chipSku', c.Array[NvU8, Literal[4]], 4), ('chipMajor', NvU32, 8), ('chipMinor', NvU32, 12)])
|
|
NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
swizzId: int
|
|
struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS.register_fields([('swizzId', NvU32, 0)])
|
|
NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS(c.Struct):
|
|
SIZE = 1832
|
|
hClientTarget: int
|
|
hChannelTarget: int
|
|
bNonTransactional: int
|
|
regOpCount: int
|
|
smIds: c.Array[ctypes.c_uint32, Literal[50]]
|
|
regOps: c.Array[struct_NV2080_CTRL_GPU_REG_OP, Literal[50]]
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS.register_fields([('hClientTarget', NvHandle, 0), ('hChannelTarget', NvHandle, 4), ('bNonTransactional', NvU32, 8), ('regOpCount', NvU32, 12), ('smIds', c.Array[NvU32, Literal[50]], 16), ('regOps', c.Array[NV2080_CTRL_GPU_REG_OP, Literal[50]], 216), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 1816)])
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bResetRequired: int
|
|
struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS.register_fields([('bResetRequired', NvBool, 0)])
|
|
NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bDrainRecommended: int
|
|
struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS.register_fields([('bDrainRecommended', NvBool, 0)])
|
|
NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 16388
|
|
sessionInfoTblEntry: int
|
|
sessionInfoTbl: c.Array[struct_NV2080_CTRL_NVENC_SW_SESSION_INFO, Literal[512]]
|
|
struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS.register_fields([('sessionInfoTblEntry', NvU32, 0), ('sessionInfoTbl', c.Array[NV2080_CTRL_NVENC_SW_SESSION_INFO, Literal[512]], 4)])
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO(c.Struct):
|
|
SIZE = 20
|
|
engDesc: int
|
|
ctxAttr: int
|
|
ctxBufferSize: int
|
|
addrSpaceList: int
|
|
registerBase: int
|
|
struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO.register_fields([('engDesc', NvU32, 0), ('ctxAttr', NvU32, 4), ('ctxBufferSize', NvU32, 8), ('addrSpaceList', NvU32, 12), ('registerBase', NvU32, 16)])
|
|
NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO: TypeAlias = struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS(c.Struct):
|
|
SIZE = 1284
|
|
numConstructedFalcons: int
|
|
constructedFalconsTable: c.Array[struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO, Literal[64]]
|
|
struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS.register_fields([('numConstructedFalcons', NvU32, 0), ('constructedFalconsTable', c.Array[NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO, Literal[64]], 4)])
|
|
NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_VF_MSIX_CAPS(c.Struct):
|
|
SIZE = 12
|
|
msix_header: int
|
|
msix_table: int
|
|
msix_pba: int
|
|
struct_NV2080_VF_MSIX_CAPS.register_fields([('msix_header', NvU32, 0), ('msix_table', NvU32, 4), ('msix_pba', NvU32, 8)])
|
|
NV2080_VF_MSIX_CAPS: TypeAlias = struct_NV2080_VF_MSIX_CAPS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
gfid: int
|
|
vfMsixCap: struct_NV2080_VF_MSIX_CAPS
|
|
struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS.register_fields([('gfid', NvU32, 0), ('vfMsixCap', NV2080_VF_MSIX_CAPS, 4)])
|
|
NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS
|
|
enum_NV2080_CTRL_GPU_RECOVERY_ACTION: dict[int, str] = {(NV2080_CTRL_GPU_RECOVERY_ACTION_NONE:=0): 'NV2080_CTRL_GPU_RECOVERY_ACTION_NONE', (NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_PF_FLR:=1): 'NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_PF_FLR', (NV2080_CTRL_GPU_RECOVERY_ACTION_OS_REBOOT:=2): 'NV2080_CTRL_GPU_RECOVERY_ACTION_OS_REBOOT', (NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P:=3): 'NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P', (NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET:=4): 'NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET', (NV2080_CTRL_GPU_RECOVERY_ACTION_RECOVER_IMEX_DOMAIN:=5): 'NV2080_CTRL_GPU_RECOVERY_ACTION_RECOVER_IMEX_DOMAIN', (NV2080_CTRL_GPU_RECOVERY_ACTION_BUS_RESET:=6): 'NV2080_CTRL_GPU_RECOVERY_ACTION_BUS_RESET', (NV2080_CTRL_GPU_RECOVERY_ACTION_SYSTEM_REBOOT:=7): 'NV2080_CTRL_GPU_RECOVERY_ACTION_SYSTEM_REBOOT'}
|
|
NV2080_CTRL_GPU_RECOVERY_ACTION: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
action: int
|
|
struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS.register_fields([('action', NV2080_CTRL_GPU_RECOVERY_ACTION, 0)])
|
|
NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bFipsEnabled: int
|
|
struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS.register_fields([('bFipsEnabled', NvBool, 0)])
|
|
NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS
|
|
enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE: dict[int, str] = {(NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID:=0): 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID', (NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC:=1): 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC', (NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC:=2): 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC'}
|
|
NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_RAFTS_FLOORSWEEP_INFO(c.Struct):
|
|
SIZE = 12
|
|
unitType: int
|
|
parentId: int
|
|
mask: int
|
|
struct_NV2080_RAFTS_FLOORSWEEP_INFO.register_fields([('unitType', NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE, 0), ('parentId', NvU32, 4), ('mask', NvU32, 8)])
|
|
NV2080_RAFTS_FLOORSWEEP_INFO: TypeAlias = struct_NV2080_RAFTS_FLOORSWEEP_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS(c.Struct):
|
|
SIZE = 344
|
|
tpcCountMatrix: c.Array[c.Array[ctypes.c_ubyte, Literal[12]], Literal[2]]
|
|
bValid: int
|
|
floorSweepConfig: c.Array[struct_NV2080_RAFTS_FLOORSWEEP_INFO, Literal[26]]
|
|
gfxGpcCount: int
|
|
gfxTpcPerGpcCount: int
|
|
maxUgpuTpcDiff: int
|
|
struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS.register_fields([('tpcCountMatrix', c.Array[c.Array[NvU8, Literal[12]], Literal[2]], 0), ('bValid', NvBool, 24), ('floorSweepConfig', c.Array[NV2080_RAFTS_FLOORSWEEP_INFO, Literal[26]], 28), ('gfxGpcCount', NvU8, 340), ('gfxTpcPerGpcCount', NvU8, 341), ('maxUgpuTpcDiff', NvU8, 342)])
|
|
NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS(c.Struct):
|
|
SIZE = 152
|
|
partitionFlag: int
|
|
computeSize: int
|
|
totalProfileCount: int
|
|
totalSpans: c.Array[struct_NV2080_CTRL_EXEC_PARTITION_SPAN, Literal[8]]
|
|
totalSpansCount: int
|
|
struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS.register_fields([('partitionFlag', NvU32, 0), ('computeSize', NvU32, 4), ('totalProfileCount', NvU32, 8), ('totalSpans', c.Array[NV2080_CTRL_EXEC_PARTITION_SPAN, Literal[8]], 16), ('totalSpansCount', NvU32, 144)])
|
|
NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpc: int
|
|
tpcReconfigMask: int
|
|
struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS.register_fields([('gpc', NvU32, 0), ('tpcReconfigMask', NvU32, 4)])
|
|
NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
test: int
|
|
dataSize: int
|
|
startTimestamp: int
|
|
stopTimestamp: int
|
|
data: ctypes.c_void_p
|
|
struct_NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS.register_fields([('test', NvU8, 0), ('dataSize', NvU32, 4), ('startTimestamp', NvU64, 8), ('stopTimestamp', NvU64, 16), ('data', NvP64, 24)])
|
|
NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
maxRpcSize: int
|
|
finnRmapiSize: int
|
|
rpcGspControlSize: int
|
|
rpcMessageHeaderSize: int
|
|
timestampFreq: int
|
|
struct_NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS.register_fields([('maxRpcSize', NvU32, 0), ('finnRmapiSize', NvU32, 4), ('rpcGspControlSize', NvU32, 8), ('rpcMessageHeaderSize', NvU32, 12), ('timestampFreq', NvU64, 16)])
|
|
NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
supportedFeatures: int
|
|
struct_NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS.register_fields([('supportedFeatures', NvU32, 0)])
|
|
NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS: TypeAlias = struct_NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
permanentPolledDataMask: int
|
|
struct_NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS.register_fields([('permanentPolledDataMask', NvU64, 0)])
|
|
NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
flags: int
|
|
struct_NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS.register_fields([('flags', NvU32, 0)])
|
|
NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
bWrite: int
|
|
head: int
|
|
index: int
|
|
data: int
|
|
struct_NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS.register_fields([('bWrite', NvBool, 0), ('head', NvU32, 4), ('index', NvU8, 8), ('data', NvU8, 9)])
|
|
NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS
|
|
enum_NV2080_CTRL_GPU_INJECT_ERROR_TYPE: dict[int, str] = {(NV2080_CTRL_GPU_INJECT_ERROR_MESSAGE_QUEUE:=0): 'NV2080_CTRL_GPU_INJECT_ERROR_MESSAGE_QUEUE', (NV2080_CTRL_GPU_INJECT_ERROR__COUNT:=1): 'NV2080_CTRL_GPU_INJECT_ERROR__COUNT'}
|
|
NV2080_CTRL_GPU_INJECT_ERROR_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
errorType: int
|
|
struct_NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS.register_fields([('errorType', NvU32, 0)])
|
|
NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
flags: int
|
|
struct_NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS.register_fields([('flags', NvU32, 0)])
|
|
NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
defaultTimeout: int
|
|
struct_NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS.register_fields([('defaultTimeout', NvU32, 0)])
|
|
NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS
|
|
enum_NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_TYPE: dict[int, str] = {(NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RSA_DECRYPTION:=0): 'NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RSA_DECRYPTION', (NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_ECDSA:=1): 'NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_ECDSA', (NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RNG:=2): 'NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RNG', (NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_SHA:=3): 'NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_SHA'}
|
|
NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 120
|
|
opcode: int
|
|
inputMessageSize: int
|
|
inputMessage: ctypes.c_void_p
|
|
outputMessageSize: int
|
|
outputMessage: ctypes.c_void_p
|
|
modulusSize: int
|
|
modulus: ctypes.c_void_p
|
|
exponent: c.Array[ctypes.c_ubyte, Literal[4]]
|
|
usePresetKey: int
|
|
keySize: int
|
|
key: ctypes.c_void_p
|
|
nonce: c.Array[ctypes.c_ubyte, Literal[48]]
|
|
struct_NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS.register_fields([('opcode', NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_TYPE, 0), ('inputMessageSize', NvU32, 4), ('inputMessage', NvP64, 8), ('outputMessageSize', NvU32, 16), ('outputMessage', NvP64, 24), ('modulusSize', NvU32, 32), ('modulus', NvP64, 40), ('exponent', c.Array[NvU8, Literal[4]], 48), ('usePresetKey', NvBool, 52), ('keySize', NvU32, 56), ('key', NvP64, 64), ('nonce', c.Array[NvU8, Literal[48]], 72)])
|
|
NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
isResetCoupled: int
|
|
struct_NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS.register_fields([('isResetCoupled', NvBool, 0)])
|
|
NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS
|
|
enum_NV2080_CTRL_GPU_DIELET_TYPE: dict[int, str] = {(NV2080_CTRL_GPU_DIELET_TYPE_UGD:=0): 'NV2080_CTRL_GPU_DIELET_TYPE_UGD', (NV2080_CTRL_GPU_DIELET_TYPE_IODN:=1): 'NV2080_CTRL_GPU_DIELET_TYPE_IODN', (NV2080_CTRL_GPU_DIELET_TYPE_IODS:=2): 'NV2080_CTRL_GPU_DIELET_TYPE_IODS', (NV2080_CTRL_GPU_DIELET_TYPE_LAST:=3): 'NV2080_CTRL_GPU_DIELET_TYPE_LAST'}
|
|
NV2080_CTRL_GPU_DIELET_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_DIELET_INFO(c.Struct):
|
|
SIZE = 8
|
|
dieletType: int
|
|
typeSpecificId: int
|
|
struct_NV2080_CTRL_GPU_GET_DIELET_INFO.register_fields([('dieletType', NV2080_CTRL_GPU_DIELET_TYPE, 0), ('typeSpecificId', NvU32, 4)])
|
|
NV2080_CTRL_GPU_GET_DIELET_INFO: TypeAlias = struct_NV2080_CTRL_GPU_GET_DIELET_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS(c.Struct):
|
|
SIZE = 2052
|
|
dieletListSize: int
|
|
dielets: c.Array[struct_NV2080_CTRL_GPU_GET_DIELET_INFO, Literal[256]]
|
|
struct_NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS.register_fields([('dieletListSize', NvU32, 0), ('dielets', c.Array[NV2080_CTRL_GPU_GET_DIELET_INFO, Literal[256]], 4)])
|
|
NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS
|
|
enum_NV2080_CTRL_GPU_UNIT_TYPE: dict[int, str] = {(NV2080_CTRL_GPU_UNIT_TYPE_SYSLTC:=0): 'NV2080_CTRL_GPU_UNIT_TYPE_SYSLTC', (NV2080_CTRL_GPU_UNIT_TYPE_SYSLTS:=1): 'NV2080_CTRL_GPU_UNIT_TYPE_SYSLTS', (NV2080_CTRL_GPU_UNIT_TYPE_HSHUBCHI:=2): 'NV2080_CTRL_GPU_UNIT_TYPE_HSHUBCHI', (NV2080_CTRL_GPU_UNIT_TYPE_HSHUBNVL:=3): 'NV2080_CTRL_GPU_UNIT_TYPE_HSHUBNVL', (NV2080_CTRL_GPU_UNIT_TYPE_LAST:=4): 'NV2080_CTRL_GPU_UNIT_TYPE_LAST'}
|
|
NV2080_CTRL_GPU_UNIT_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
dieletType: int
|
|
dieletTypeSpecificId: int
|
|
unitType: int
|
|
unitMask: int
|
|
struct_NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS.register_fields([('dieletType', NV2080_CTRL_GPU_DIELET_TYPE, 0), ('dieletTypeSpecificId', NvU32, 4), ('unitType', NV2080_CTRL_GPU_UNIT_TYPE, 8), ('unitMask', NvU32, 12)])
|
|
NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bIsDevtoolInUse: int
|
|
struct_NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS.register_fields([('bIsDevtoolInUse', NvBool, 0)])
|
|
NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPUMON_SAMPLE(c.Struct):
|
|
SIZE = 8
|
|
timeStamp: int
|
|
struct_NV2080_CTRL_GPUMON_SAMPLE.register_fields([('timeStamp', NvU64, 0)])
|
|
NV2080_CTRL_GPUMON_SAMPLE: TypeAlias = struct_NV2080_CTRL_GPUMON_SAMPLE
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPUMON_SAMPLES(c.Struct):
|
|
SIZE = 24
|
|
type: int
|
|
bufSize: int
|
|
count: int
|
|
tracker: int
|
|
pSamples: ctypes.c_void_p
|
|
struct_NV2080_CTRL_GPUMON_SAMPLES.register_fields([('type', NvU8, 0), ('bufSize', NvU32, 4), ('count', NvU32, 8), ('tracker', NvU32, 12), ('pSamples', NvP64, 16)])
|
|
NV2080_CTRL_GPUMON_SAMPLES: TypeAlias = struct_NV2080_CTRL_GPUMON_SAMPLES
|
|
NV2080_CTRL_GR_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
grInfoListSize: int
|
|
grInfoList: ctypes.c_void_p
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GR_GET_INFO_PARAMS.register_fields([('grInfoListSize', NvU32, 0), ('grInfoList', NvP64, 8), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 16)])
|
|
NV2080_CTRL_GR_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hChannel: int
|
|
hShareClient: int
|
|
hShareChannel: int
|
|
zcullMode: int
|
|
struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS.register_fields([('hChannel', NvHandle, 0), ('hShareClient', NvHandle, 4), ('hShareChannel', NvHandle, 8), ('zcullMode', NvU32, 12)])
|
|
NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
widthAlignPixels: int
|
|
heightAlignPixels: int
|
|
pixelSquaresByAliquots: int
|
|
aliquotTotal: int
|
|
zcullRegionByteMultiplier: int
|
|
zcullRegionHeaderSize: int
|
|
zcullSubregionHeaderSize: int
|
|
subregionCount: int
|
|
subregionWidthAlignPixels: int
|
|
subregionHeightAlignPixels: int
|
|
struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS.register_fields([('widthAlignPixels', NvU32, 0), ('heightAlignPixels', NvU32, 4), ('pixelSquaresByAliquots', NvU32, 8), ('aliquotTotal', NvU32, 12), ('zcullRegionByteMultiplier', NvU32, 16), ('zcullRegionHeaderSize', NvU32, 20), ('zcullSubregionHeaderSize', NvU32, 24), ('subregionCount', NvU32, 28), ('subregionWidthAlignPixels', NvU32, 32), ('subregionHeightAlignPixels', NvU32, 36)])
|
|
NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hChannel: int
|
|
pmMode: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS.register_fields([('hChannel', NvHandle, 0), ('pmMode', NvU32, 4), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 8)])
|
|
NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hClient: int
|
|
hChannel: int
|
|
vMemPtr: int
|
|
zcullMode: int
|
|
struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS.register_fields([('hClient', NvHandle, 0), ('hChannel', NvHandle, 4), ('vMemPtr', NvU64, 8), ('zcullMode', NvU32, 16)])
|
|
NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
hClient: int
|
|
hChannel: int
|
|
vMemPtr: int
|
|
pmMode: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS.register_fields([('hClient', NvHandle, 0), ('hChannel', NvHandle, 4), ('vMemPtr', NvU64, 8), ('pmMode', NvU32, 16), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 24)])
|
|
NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hClient: int
|
|
hChannel: int
|
|
vMemPtr: int
|
|
struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS.register_fields([('hClient', NvHandle, 0), ('hChannel', NvHandle, 4), ('vMemPtr', NvU64, 8)])
|
|
NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS(c.Struct):
|
|
SIZE = 152
|
|
mapValueCount: int
|
|
mapValues: c.Array[ctypes.c_ubyte, Literal[128]]
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS.register_fields([('mapValueCount', NvU32, 0), ('mapValues', c.Array[NvU8, Literal[128]], 4), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 136)])
|
|
NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hChannel: int
|
|
smpcMode: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS.register_fields([('hChannel', NvHandle, 0), ('smpcMode', NvU32, 4), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 8)])
|
|
NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS(c.Struct):
|
|
SIZE = 4120
|
|
smId: c.Array[struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_smId, Literal[512]]
|
|
smCount: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_smId(c.Struct):
|
|
SIZE = 8
|
|
gpcId: int
|
|
tpcId: int
|
|
struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_smId.register_fields([('gpcId', NvU32, 0), ('tpcId', NvU32, 4)])
|
|
struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS.register_fields([('smId', c.Array[struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_smId, Literal[512]], 0), ('smCount', NvU32, 4096), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 4104)])
|
|
NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
flags: int
|
|
hChannel: int
|
|
gfxpPreemptMode: int
|
|
cilpPreemptMode: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS.register_fields([('flags', NvU32, 0), ('hChannel', NvHandle, 4), ('gfxpPreemptMode', NvU32, 8), ('cilpPreemptMode', NvU32, 12), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 16)])
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS
|
|
enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS: dict[int, str] = {(NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN:=0): 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN', (NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL:=1): 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL', (NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL:=2): 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL', (NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB:=3): 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB', (NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV:=4): 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV', (NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL:=5): 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL', (NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL:=6): 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL', (NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU:=7): 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU', (NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP:=8): 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP', (NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END:=9): 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END'}
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS(c.Struct):
|
|
SIZE = 112
|
|
flags: int
|
|
hClient: int
|
|
hChannel: int
|
|
vMemPtrs: c.Array[ctypes.c_uint64, Literal[9]]
|
|
gfxpPreemptMode: int
|
|
cilpPreemptMode: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS.register_fields([('flags', NvU32, 0), ('hClient', NvHandle, 4), ('hChannel', NvHandle, 8), ('vMemPtrs', c.Array[NvU64, Literal[9]], 16), ('gfxpPreemptMode', NvU32, 88), ('cilpPreemptMode', NvU32, 92), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 96)])
|
|
NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hChannel: int
|
|
samplingMode: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS.register_fields([('hChannel', NvHandle, 0), ('samplingMode', NvU32, 4), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 8)])
|
|
NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
ropUnitCount: int
|
|
ropOperationsFactor: int
|
|
ropOperationsCount: int
|
|
struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS.register_fields([('ropUnitCount', NvU32, 0), ('ropOperationsFactor', NvU32, 4), ('ropOperationsCount', NvU32, 8)])
|
|
NV2080_CTRL_GR_GET_ROP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hChannel: int
|
|
flags: int
|
|
saveCnt: int
|
|
restoreCnt: int
|
|
wfiSaveCnt: int
|
|
ctaSaveCnt: int
|
|
cilpSaveCnt: int
|
|
gfxpSaveCnt: int
|
|
struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS.register_fields([('hChannel', NvHandle, 0), ('flags', NvU32, 4), ('saveCnt', NvU32, 8), ('restoreCnt', NvU32, 12), ('wfiSaveCnt', NvU32, 16), ('ctaSaveCnt', NvU32, 20), ('cilpSaveCnt', NvU32, 24), ('gfxpSaveCnt', NvU32, 28)])
|
|
NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hChannel: int
|
|
totalBufferSize: int
|
|
struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS.register_fields([('hChannel', NvHandle, 0), ('totalBufferSize', NvU64, 8)])
|
|
NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTX_BUFFER_INFO(c.Struct):
|
|
SIZE = 80
|
|
alignment: int
|
|
size: int
|
|
bufferHandle: ctypes.c_void_p
|
|
pageCount: int
|
|
physAddr: int
|
|
bufferType: int
|
|
aperture: int
|
|
kind: int
|
|
pageSize: int
|
|
bIsContigous: int
|
|
bGlobalBuffer: int
|
|
bLocalBuffer: int
|
|
bDeviceDescendant: int
|
|
uuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
struct_NV2080_CTRL_GR_CTX_BUFFER_INFO.register_fields([('alignment', NvU64, 0), ('size', NvU64, 8), ('bufferHandle', NvP64, 16), ('pageCount', NvU64, 24), ('physAddr', NvU64, 32), ('bufferType', NvU32, 40), ('aperture', NvU32, 44), ('kind', NvU32, 48), ('pageSize', NvU32, 52), ('bIsContigous', NvBool, 56), ('bGlobalBuffer', NvBool, 57), ('bLocalBuffer', NvBool, 58), ('bDeviceDescendant', NvBool, 59), ('uuid', c.Array[NvU8, Literal[16]], 60)])
|
|
NV2080_CTRL_GR_CTX_BUFFER_INFO: TypeAlias = struct_NV2080_CTRL_GR_CTX_BUFFER_INFO
|
|
PNV2080_CTRL_GR_CTX_BUFFER_INFO: TypeAlias = c.POINTER[struct_NV2080_CTRL_GR_CTX_BUFFER_INFO]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS(c.Struct):
|
|
SIZE = 5136
|
|
hUserClient: int
|
|
hChannel: int
|
|
bufferCount: int
|
|
ctxBufferInfo: c.Array[struct_NV2080_CTRL_GR_CTX_BUFFER_INFO, Literal[64]]
|
|
struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS.register_fields([('hUserClient', NvHandle, 0), ('hChannel', NvHandle, 4), ('bufferCount', NvU32, 8), ('ctxBufferInfo', c.Array[NV2080_CTRL_GR_CTX_BUFFER_INFO, Literal[64]], 16)])
|
|
NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS(c.Struct):
|
|
SIZE = 9240
|
|
globalSmId: c.Array[struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_globalSmId, Literal[512]]
|
|
numSm: int
|
|
numTpc: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_globalSmId(c.Struct):
|
|
SIZE = 18
|
|
gpcId: int
|
|
localTpcId: int
|
|
localSmId: int
|
|
globalTpcId: int
|
|
virtualGpcId: int
|
|
migratableTpcId: int
|
|
ugpuId: int
|
|
physicalCpcId: int
|
|
virtualTpcId: int
|
|
struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_globalSmId.register_fields([('gpcId', NvU16, 0), ('localTpcId', NvU16, 2), ('localSmId', NvU16, 4), ('globalTpcId', NvU16, 6), ('virtualGpcId', NvU16, 8), ('migratableTpcId', NvU16, 10), ('ugpuId', NvU16, 12), ('physicalCpcId', NvU16, 14), ('virtualTpcId', NvU16, 16)])
|
|
struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS.register_fields([('globalSmId', c.Array[struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_globalSmId, Literal[512]], 0), ('numSm', NvU16, 9216), ('numTpc', NvU16, 9218), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 9224)])
|
|
NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
chID: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS.register_fields([('chID', NvU32, 0), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 8)])
|
|
NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
attribBufferSize: int
|
|
struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS.register_fields([('attribBufferSize', NvU32, 0)])
|
|
NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
maxSlots: int
|
|
slotStride: int
|
|
ctrlStructSize: int
|
|
ctrlStructAlign: int
|
|
poolSize: int
|
|
poolAlign: int
|
|
struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS.register_fields([('maxSlots', NvU32, 0), ('slotStride', NvU32, 4), ('ctrlStructSize', NvU64, 8), ('ctrlStructAlign', NvU64, 16), ('poolSize', NvU64, 24), ('poolAlign', NvU64, 32)])
|
|
NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
maxSlots: int
|
|
hMemory: int
|
|
offset: int
|
|
size: int
|
|
struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS.register_fields([('maxSlots', NvU32, 0), ('hMemory', NvHandle, 4), ('offset', NvU32, 8), ('size', NvU32, 12)])
|
|
NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS(c.Struct):
|
|
SIZE = 272
|
|
numSlots: int
|
|
slots: c.Array[ctypes.c_uint32, Literal[64]]
|
|
hMemory: int
|
|
offset: int
|
|
size: int
|
|
struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS.register_fields([('numSlots', NvU32, 0), ('slots', c.Array[NvU32, Literal[64]], 4), ('hMemory', NvHandle, 260), ('offset', NvU32, 264), ('size', NvU32, 268)])
|
|
NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS(c.Struct):
|
|
SIZE = 276
|
|
numSlots: int
|
|
slots: c.Array[ctypes.c_uint32, Literal[64]]
|
|
bRemoveSpecificSlots: int
|
|
hMemory: int
|
|
offset: int
|
|
size: int
|
|
struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS.register_fields([('numSlots', NvU32, 0), ('slots', c.Array[NvU32, Literal[64]], 4), ('bRemoveSpecificSlots', NvBool, 260), ('hMemory', NvHandle, 264), ('offset', NvU32, 268), ('size', NvU32, 272)])
|
|
NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS
|
|
NV2080_CTRL_GR_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS
|
|
NV2080_CTRL_GR_GET_INFO_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
gpcMask: int
|
|
struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS.register_fields([('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 0), ('gpcMask', NvU32, 16)])
|
|
NV2080_CTRL_GR_GET_GPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
gpcId: int
|
|
tpcMask: int
|
|
struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS.register_fields([('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 0), ('gpcId', NvU32, 16), ('tpcMask', NvU32, 20)])
|
|
NV2080_CTRL_GR_GET_TPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS
|
|
NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
engineId: int
|
|
alignment: int
|
|
size: int
|
|
bInfoPopulated: int
|
|
struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS.register_fields([('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 0), ('engineId', NvU32, 16), ('alignment', NvU32, 20), ('size', NvU32, 24), ('bInfoPopulated', NvBool, 28)])
|
|
NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
imla0: int
|
|
fmla16: int
|
|
dp: int
|
|
fmla32: int
|
|
ffma: int
|
|
imla1: int
|
|
imla2: int
|
|
imla3: int
|
|
imla4: int
|
|
struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS.register_fields([('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 0), ('imla0', NvU8, 16), ('fmla16', NvU8, 17), ('dp', NvU8, 18), ('fmla32', NvU8, 19), ('ffma', NvU8, 20), ('imla1', NvU8, 21), ('imla2', NvU8, 22), ('imla3', NvU8, 23), ('imla4', NvU8, 24)])
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS(c.Struct):
|
|
SIZE = 2044
|
|
smIssueRateModifierListSize: int
|
|
smIssueRateModifierList: c.Array[struct_NVXXXX_CTRL_XXX_INFO, Literal[255]]
|
|
struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS.register_fields([('smIssueRateModifierListSize', NvU32, 0), ('smIssueRateModifierList', c.Array[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2, Literal[255]], 4)])
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS
|
|
NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS(c.Struct):
|
|
SIZE = 2044
|
|
smIssueThrottleCtrlListSize: int
|
|
smIssueThrottleCtrlList: c.Array[struct_NVXXXX_CTRL_XXX_INFO, Literal[255]]
|
|
struct_NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS.register_fields([('smIssueThrottleCtrlListSize', NvU32, 0), ('smIssueThrottleCtrlList', c.Array[NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL, Literal[255]], 4)])
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS
|
|
enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD: dict[int, str] = {(NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL:=0): 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL', (NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE:=1): 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE', (NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT:=2): 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT', (NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM:=3): 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM'}
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
hEventBuffer: int
|
|
recordSize: int
|
|
levelOfDetail: int
|
|
eventFilter: int
|
|
bAllUsers: int
|
|
struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS.register_fields([('hEventBuffer', NvHandle, 0), ('recordSize', NvU32, 4), ('levelOfDetail', NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD, 8), ('eventFilter', NvU32, 12), ('bAllUsers', NvBool, 16)])
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
physSyspipeId: int
|
|
gpcMask: int
|
|
struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS.register_fields([('physSyspipeId', NvU32, 0), ('gpcMask', NvU32, 4)])
|
|
NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
gpcId: int
|
|
ppcMask: int
|
|
struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS.register_fields([('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 0), ('gpcId', NvU32, 16), ('ppcMask', NvU32, 20)])
|
|
NV2080_CTRL_GR_GET_PPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: int
|
|
numTpcs: int
|
|
struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS.register_fields([('gpcId', NvU32, 0), ('numTpcs', NvU32, 4)])
|
|
NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hChannel: int
|
|
zcullMode: int
|
|
pmMode: int
|
|
smpcMode: int
|
|
cilpPreemptMode: int
|
|
gfxpPreemptMode: int
|
|
struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS.register_fields([('hChannel', NvHandle, 0), ('zcullMode', NvU32, 4), ('pmMode', NvU32, 8), ('smpcMode', NvU32, 12), ('cilpPreemptMode', NvU32, 16), ('gfxpPreemptMode', NvU32, 20)])
|
|
NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS
|
|
NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: int
|
|
zcullMask: int
|
|
struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS.register_fields([('gpcId', NvU32, 0), ('zcullMask', NvU32, 4)])
|
|
NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS
|
|
enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE: dict[int, str] = {(NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE:=0): 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE', (NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD:=1): 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD', (NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU:=2): 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU', (NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED:=3): 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED', (NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN:=4): 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN', (NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY:=5): 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY'}
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hEventBuffer: int
|
|
recordSize: int
|
|
levelOfDetail: int
|
|
eventFilter: int
|
|
bAllUsers: int
|
|
reasonCode: int
|
|
struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS.register_fields([('hEventBuffer', NvHandle, 0), ('recordSize', NvU32, 4), ('levelOfDetail', NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD, 8), ('eventFilter', NvU32, 12), ('bAllUsers', NvBool, 16), ('reasonCode', NvU32, 20)])
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
physGfxGpcMask: int
|
|
numGfxTpc: int
|
|
struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS.register_fields([('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 0), ('physGfxGpcMask', NvU32, 16), ('numGfxTpc', NvU32, 20)])
|
|
NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
gpc: int
|
|
tpcReconfigMask: int
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS.register_fields([('gpc', NvU32, 0), ('tpcReconfigMask', NvU32, 4), ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 8)])
|
|
NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
expectedCharCount: int
|
|
bUseInterrupt: int
|
|
struct_NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS.register_fields([('expectedCharCount', NvU32, 0), ('bUseInterrupt', NvBool, 4)])
|
|
NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gpcCount: int
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS.register_fields([('gpcCount', NvU32, 0)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: int
|
|
chipletGpcMap: int
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS.register_fields([('gpcId', NvU32, 0), ('chipletGpcMap', NvU32, 4)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: int
|
|
tpcMask: int
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS.register_fields([('gpcId', NvU32, 0), ('tpcMask', NvU32, 4)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: int
|
|
ppcMask: int
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS.register_fields([('gpcId', NvU32, 0), ('ppcMask', NvU32, 4)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
swizzId: int
|
|
gpcId: int
|
|
chipletGpcMap: int
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS.register_fields([('swizzId', NvU32, 0), ('gpcId', NvU32, 4), ('chipletGpcMap', NvU32, 8)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: int
|
|
ropMask: int
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS.register_fields([('gpcId', NvU32, 0), ('ropMask', NvU32, 4)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
chipletSyspipeMask: int
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS.register_fields([('chipletSyspipeMask', NvU32, 0)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
swizzId: int
|
|
physSyspipeIdCount: int
|
|
physSyspipeId: c.Array[ctypes.c_ubyte, Literal[8]]
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS.register_fields([('swizzId', NvU16, 0), ('physSyspipeIdCount', NvU16, 2), ('physSyspipeId', c.Array[NvU8, Literal[8]], 4)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
swizzId: int
|
|
grIdx: int
|
|
gpcEnMask: int
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS.register_fields([('swizzId', NvU32, 0), ('grIdx', NvU32, 4), ('gpcEnMask', NvU32, 8)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
syspipeId: int
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS.register_fields([('syspipeId', NvU32, 0)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
chipletSyspipeMask: int
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS.register_fields([('chipletSyspipeMask', NvU32, 0)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
swizzId: int
|
|
grIdx: int
|
|
gpcEnMask: int
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS.register_fields([('swizzId', NvU32, 0), ('grIdx', NvU32, 4), ('gpcEnMask', NvU32, 8)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
queryType: int
|
|
reserved: c.Array[ctypes.c_ubyte, Literal[2]]
|
|
status: int
|
|
queryData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData(c.Struct):
|
|
SIZE = 12
|
|
gpcCountData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS
|
|
chipletGpcMapData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS
|
|
tpcMaskData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS
|
|
ppcMaskData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS
|
|
partitionGpcMapData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS
|
|
syspipeMaskData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS
|
|
partitionChipletSyspipeData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS
|
|
dmGpcMaskData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS
|
|
partitionSyspipeIdData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS
|
|
ropMaskData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS
|
|
gfxSyspipeMaskData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS
|
|
gfxGpcMaskData: struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData.register_fields([('gpcCountData', NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS, 0), ('chipletGpcMapData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS, 0), ('tpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS, 0), ('ppcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS, 0), ('partitionGpcMapData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS, 0), ('syspipeMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS, 0), ('partitionChipletSyspipeData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS, 0), ('dmGpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS, 0), ('partitionSyspipeIdData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS, 0), ('ropMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS, 0), ('gfxSyspipeMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GRAPHICS_SYSPIPE_MASK_PARAMS, 0), ('gfxGpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_GFX_CAPABLE_GPC_MASK_PARAMS, 0)])
|
|
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS.register_fields([('queryType', NvU16, 0), ('reserved', c.Array[NvU8, Literal[2]], 2), ('status', NvU32, 4), ('queryData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData, 8)])
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS(c.Struct):
|
|
SIZE = 1928
|
|
numQueries: int
|
|
reserved: c.Array[ctypes.c_ubyte, Literal[6]]
|
|
queries: c.Array[struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS, Literal[96]]
|
|
struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS.register_fields([('numQueries', NvU16, 0), ('reserved', c.Array[NvU8, Literal[6]], 2), ('queries', c.Array[NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS, Literal[96]], 8)])
|
|
NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
gspFeatures: int
|
|
bValid: int
|
|
bDefaultGspRmGpu: int
|
|
firmwareVersion: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS.register_fields([('gspFeatures', NvU32, 0), ('bValid', NvBool, 4), ('bDefaultGspRmGpu', NvBool, 5), ('firmwareVersion', c.Array[NvU8, Literal[64]], 6)])
|
|
NV2080_CTRL_GSP_GET_FEATURES_PARAMS: TypeAlias = struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT(c.Struct):
|
|
SIZE = 32
|
|
allocatedSize: int
|
|
usableSize: int
|
|
memTrackOverhead: int
|
|
allocationCount: int
|
|
struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT.register_fields([('allocatedSize', NvU64, 0), ('usableSize', NvU64, 8), ('memTrackOverhead', NvU64, 16), ('allocationCount', NvU32, 24)])
|
|
NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT: TypeAlias = struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT
|
|
@c.record
|
|
class struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS(c.Struct):
|
|
SIZE = 88
|
|
gfid: int
|
|
managedSize: int
|
|
largestFreeChunkSize: int
|
|
current: struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT
|
|
peak: struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT
|
|
struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS.register_fields([('gfid', NvU32, 0), ('managedSize', NvU64, 8), ('largestFreeChunkSize', NvU64, 16), ('current', NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT, 24), ('peak', NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT, 56)])
|
|
NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
allocatedSize: int
|
|
peakAllocatedSize: int
|
|
managedSize: int
|
|
allocationCount: int
|
|
peakAllocationCount: int
|
|
largestFreeChunkSize: int
|
|
struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS.register_fields([('allocatedSize', NvU64, 0), ('peakAllocatedSize', NvU64, 8), ('managedSize', NvU64, 16), ('allocationCount', NvU32, 24), ('peakAllocationCount', NvU32, 28), ('largestFreeChunkSize', NvU64, 32)])
|
|
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS(c.Struct):
|
|
SIZE = 16
|
|
allocations: int
|
|
peakAllocations: int
|
|
objectSize: int
|
|
struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS.register_fields([('allocations', NvU32, 0), ('peakAllocations', NvU32, 4), ('objectSize', NvU64, 8)])
|
|
NV2080_CTRL_GSP_LIBOS_POOL_STATS: TypeAlias = struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS(c.Struct):
|
|
SIZE = 1040
|
|
poolStats: c.Array[struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS, Literal[64]]
|
|
totalHeapSize: int
|
|
poolCount: int
|
|
struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS.register_fields([('poolStats', c.Array[NV2080_CTRL_GSP_LIBOS_POOL_STATS, Literal[64]], 0), ('totalHeapSize', NvU64, 1024), ('poolCount', NvU8, 1032)])
|
|
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
iters: int
|
|
pSysmemPA: int
|
|
struct_NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS.register_fields([('iters', NvU64, 0), ('pSysmemPA', NvU64, 8)])
|
|
NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS
|
|
enum_NV2080_CTRL_GSP_CORE_TEST_OP: dict[int, str] = {(NV2080_CTRL_GSP_CORE_TEST_OP_WRITE_LATENCY:=0): 'NV2080_CTRL_GSP_CORE_TEST_OP_WRITE_LATENCY', (NV2080_CTRL_GSP_CORE_TEST_OP_READ_LATENCY:=1): 'NV2080_CTRL_GSP_CORE_TEST_OP_READ_LATENCY', (NV2080_CTRL_GSP_CORE_TEST_OP_WRITE_BLOCK:=2): 'NV2080_CTRL_GSP_CORE_TEST_OP_WRITE_BLOCK', (NV2080_CTRL_GSP_CORE_TEST_OP_READ_BLOCK:=3): 'NV2080_CTRL_GSP_CORE_TEST_OP_READ_BLOCK', (NV2080_CTRL_GSP_CORE_TEST_SYSMEM_TO_FB_OP_COPY_NAIVE:=4): 'NV2080_CTRL_GSP_CORE_TEST_SYSMEM_TO_FB_OP_COPY_NAIVE', (NV2080_CTRL_GSP_CORE_TEST_FB_TO_FB_OP_COPY_NAIVE:=5): 'NV2080_CTRL_GSP_CORE_TEST_FB_TO_FB_OP_COPY_NAIVE', (NV2080_CTRL_GSP_CORE_TEST_DMEM_TO_FB_OP_PORT_MEM_COPY:=6): 'NV2080_CTRL_GSP_CORE_TEST_DMEM_TO_FB_OP_PORT_MEM_COPY', (NV2080_CTRL_GSP_CORE_TEST_FB_TO_DMEM_OP_PORT_MEM_COPY:=7): 'NV2080_CTRL_GSP_CORE_TEST_FB_TO_DMEM_OP_PORT_MEM_COPY', (NV2080_CTRL_GSP_CORE_TEST_FB_TO_FB_OP_PORT_MEM_COPY:=8): 'NV2080_CTRL_GSP_CORE_TEST_FB_TO_FB_OP_PORT_MEM_COPY', (NV2080_CTRL_GSP_CORE_TEST_DMEM_TO_FB_OP_DMA:=9): 'NV2080_CTRL_GSP_CORE_TEST_DMEM_TO_FB_OP_DMA', (NV2080_CTRL_GSP_CORE_TEST_FB_TO_DMEM_OP_DMA:=10): 'NV2080_CTRL_GSP_CORE_TEST_FB_TO_DMEM_OP_DMA', (NV2080_CTRL_GSP_CORE_TEST_FB_TO_FB_OP_DMA:=11): 'NV2080_CTRL_GSP_CORE_TEST_FB_TO_FB_OP_DMA', (NV2080_CTRL_GSP_CORE_TEST_L1D_INVAL_TIME:=12): 'NV2080_CTRL_GSP_CORE_TEST_L1D_INVAL_TIME'}
|
|
NV2080_CTRL_GSP_CORE_TEST_OP: TypeAlias = ctypes.c_uint32
|
|
enum_NV2080_CTRL_GSP_CORE_TEST_MEM: dict[int, str] = {(NV2080_CTRL_GSP_CORE_TEST_MEM_DMEM:=0): 'NV2080_CTRL_GSP_CORE_TEST_MEM_DMEM', (NV2080_CTRL_GSP_CORE_TEST_MEM_FB:=1): 'NV2080_CTRL_GSP_CORE_TEST_MEM_FB', (NV2080_CTRL_GSP_CORE_TEST_MEM_SYSMEM:=2): 'NV2080_CTRL_GSP_CORE_TEST_MEM_SYSMEM'}
|
|
NV2080_CTRL_GSP_CORE_TEST_MEM: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
op: int
|
|
mem: int
|
|
flags: int
|
|
size: int
|
|
iters: int
|
|
timeNs: int
|
|
cycles: int
|
|
struct_NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS.register_fields([('op', NV2080_CTRL_GSP_CORE_TEST_OP, 0), ('mem', NV2080_CTRL_GSP_CORE_TEST_MEM, 4), ('flags', NvU64, 8), ('size', NvU64, 16), ('iters', NvU64, 24), ('timeNs', NvU64, 32), ('cycles', NvU64, 40)])
|
|
NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hshubNcisocMask: int
|
|
hshubNvlMask: int
|
|
struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS.register_fields([('hshubNcisocMask', NvU32, 0), ('hshubNvlMask', NvU32, 4)])
|
|
NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
ecMode: int
|
|
status: int
|
|
struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS.register_fields([('ecMode', NvU32, 0), ('status', NvU32, 4)])
|
|
NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 532
|
|
version: int
|
|
port: int
|
|
flags: int
|
|
inputCount: int
|
|
inputBuffer: c.Array[ctypes.c_ubyte, Literal[256]]
|
|
outputCount: int
|
|
outputBuffer: c.Array[ctypes.c_ubyte, Literal[256]]
|
|
struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS.register_fields([('version', NvU32, 0), ('port', NvU32, 4), ('flags', NvU32, 8), ('inputCount', NvU32, 12), ('inputBuffer', c.Array[NvU8, Literal[256]], 16), ('outputCount', NvU32, 272), ('outputBuffer', c.Array[NvU8, Literal[256]], 276)])
|
|
NV2080_CTRL_I2C_READ_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 276
|
|
version: int
|
|
port: int
|
|
flags: int
|
|
inputCount: int
|
|
inputBuffer: c.Array[ctypes.c_ubyte, Literal[256]]
|
|
encrClientID: int
|
|
struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS.register_fields([('version', NvU32, 0), ('port', NvU32, 4), ('flags', NvU32, 8), ('inputCount', NvU32, 12), ('inputBuffer', c.Array[NvU8, Literal[256]], 16), ('encrClientID', NvU32, 272)])
|
|
NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_I2C_RW_REG_PARAMS(c.Struct):
|
|
SIZE = 276
|
|
version: int
|
|
port: int
|
|
flags: int
|
|
addr: int
|
|
reg: int
|
|
bufsize: int
|
|
buffer: c.Array[ctypes.c_ubyte, Literal[255]]
|
|
struct_NV2080_CTRL_I2C_RW_REG_PARAMS.register_fields([('version', NvU32, 0), ('port', NvU32, 4), ('flags', NvU32, 8), ('addr', NvU32, 12), ('reg', NvU8, 16), ('bufsize', NvU8, 17), ('buffer', c.Array[NvU8, Literal[255]], 18)])
|
|
NV2080_CTRL_I2C_RW_REG_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_RW_REG_PARAMS
|
|
NV2080_CTRL_I2C_READ_REG_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_RW_REG_PARAMS
|
|
NV2080_CTRL_I2C_WRITE_REG_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_RW_REG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_I2C_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
token: int
|
|
cmd: int
|
|
port: int
|
|
flags: int
|
|
data: ctypes.c_void_p
|
|
status: int
|
|
dataBuffSize: int
|
|
speed: int
|
|
encrClientID: int
|
|
struct_NV2080_CTRL_I2C_ACCESS_PARAMS.register_fields([('token', NvU32, 0), ('cmd', NvU32, 4), ('port', NvU32, 8), ('flags', NvU32, 12), ('data', NvP64, 16), ('status', NvU32, 24), ('dataBuffSize', NvU32, 28), ('speed', NvU32, 32), ('encrClientID', NvU32, 36)])
|
|
NV2080_CTRL_I2C_ACCESS_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_ACCESS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
head: int
|
|
authType: int
|
|
status: int
|
|
struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS.register_fields([('head', NvU32, 0), ('authType', NvU32, 4), ('status', NvU32, 8)])
|
|
NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
feHwSysCap: int
|
|
windowPresentMask: int
|
|
numHeads: int
|
|
i2cPort: int
|
|
internalDispActiveMask: int
|
|
embeddedDisplayPortMask: int
|
|
bExternalMuxSupported: int
|
|
bInternalMuxSupported: int
|
|
numDispChannels: int
|
|
struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS.register_fields([('feHwSysCap', NvU32, 0), ('windowPresentMask', NvU32, 4), ('numHeads', NvU32, 8), ('i2cPort', NvU32, 12), ('internalDispActiveMask', NvU32, 16), ('embeddedDisplayPortMask', NvU32, 20), ('bExternalMuxSupported', NvBool, 24), ('bInternalMuxSupported', NvBool, 25), ('numDispChannels', NvU32, 28)])
|
|
NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
bOneToOneComptagLineAllocation: int
|
|
bUseOneToFourComptagLineAllocation: int
|
|
bUseRawModeComptaglineAllocation: int
|
|
bDisableCompbitBacking: int
|
|
bDisablePostL2Compression: int
|
|
bEnabledEccFBPA: int
|
|
bL2PreFill: int
|
|
l2CacheSize: int
|
|
bFbpaPresent: int
|
|
comprPageSize: int
|
|
comprPageShift: int
|
|
ramType: int
|
|
ltcCount: int
|
|
ltsPerLtcCount: int
|
|
struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS.register_fields([('bOneToOneComptagLineAllocation', NvBool, 0), ('bUseOneToFourComptagLineAllocation', NvBool, 1), ('bUseRawModeComptaglineAllocation', NvBool, 2), ('bDisableCompbitBacking', NvBool, 3), ('bDisablePostL2Compression', NvBool, 4), ('bEnabledEccFBPA', NvBool, 5), ('bL2PreFill', NvBool, 6), ('l2CacheSize', NvU64, 8), ('bFbpaPresent', NvBool, 16), ('comprPageSize', NvU32, 20), ('comprPageShift', NvU32, 24), ('ramType', NvU32, 28), ('ltcCount', NvU32, 32), ('ltsPerLtcCount', NvU32, 36)])
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 520
|
|
accessCounterIndex: int
|
|
bufferSize: int
|
|
bufferPteArray: c.Array[ctypes.c_uint64, Literal[64]]
|
|
struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS.register_fields([('accessCounterIndex', NvU32, 0), ('bufferSize', NvU32, 4), ('bufferPteArray', c.Array[NvU64, Literal[64]], 8)])
|
|
NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
accessCounterIndex: int
|
|
struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS.register_fields([('accessCounterIndex', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS(c.Struct):
|
|
SIZE = 23
|
|
capsTbl: c.Array[ctypes.c_ubyte, Literal[23]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS.register_fields([('capsTbl', c.Array[NvU8, Literal[23]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_CAPS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 184
|
|
engineCaps: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS.register_fields([('engineCaps', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_CAPS, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER(c.Struct):
|
|
SIZE = 9220
|
|
globalSmId: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_globalSmId, Literal[512]]
|
|
numSm: int
|
|
numTpc: int
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_globalSmId(c.Struct):
|
|
SIZE = 18
|
|
gpcId: int
|
|
localTpcId: int
|
|
localSmId: int
|
|
globalTpcId: int
|
|
virtualGpcId: int
|
|
migratableTpcId: int
|
|
ugpuId: int
|
|
physicalCpcId: int
|
|
virtualTpcId: int
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_globalSmId.register_fields([('gpcId', NvU16, 0), ('localTpcId', NvU16, 2), ('localSmId', NvU16, 4), ('globalTpcId', NvU16, 6), ('virtualGpcId', NvU16, 8), ('migratableTpcId', NvU16, 10), ('ugpuId', NvU16, 12), ('physicalCpcId', NvU16, 14), ('virtualTpcId', NvU16, 16)])
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER.register_fields([('globalSmId', c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_globalSmId, Literal[512]], 0), ('numSm', NvU16, 9216), ('numTpc', NvU16, 9218)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS(c.Struct):
|
|
SIZE = 73760
|
|
globalSmOrder: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS.register_fields([('globalSmOrder', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVDEC_CAPS(c.Struct):
|
|
SIZE = 8
|
|
capsTbl: c.Array[ctypes.c_ubyte, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_NVDEC_CAPS.register_fields([('capsTbl', c.Array[NvU8, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_NVDEC_CAPS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVDEC_CAPS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVDEC_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
caps: c.Array[struct_NV2080_CTRL_INTERNAL_NVDEC_CAPS, Literal[8]]
|
|
valid: c.Array[ctypes.c_ubyte, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_NVDEC_GET_CAPS_PARAMS.register_fields([('caps', c.Array[NV2080_CTRL_INTERNAL_NVDEC_CAPS, Literal[8]], 0), ('valid', c.Array[NvBool, Literal[8]], 64)])
|
|
NV2080_CTRL_INTERNAL_NVDEC_GET_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVDEC_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVENC_CAPS(c.Struct):
|
|
SIZE = 6
|
|
capsTbl: c.Array[ctypes.c_ubyte, Literal[6]]
|
|
struct_NV2080_CTRL_INTERNAL_NVENC_CAPS.register_fields([('capsTbl', c.Array[NvU8, Literal[6]], 0)])
|
|
NV2080_CTRL_INTERNAL_NVENC_CAPS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVENC_CAPS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVENC_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
caps: c.Array[struct_NV2080_CTRL_INTERNAL_NVENC_CAPS, Literal[8]]
|
|
valid: c.Array[ctypes.c_ubyte, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_NVENC_GET_CAPS_PARAMS.register_fields([('caps', c.Array[NV2080_CTRL_INTERNAL_NVENC_CAPS, Literal[8]], 0), ('valid', c.Array[NvBool, Literal[8]], 48)])
|
|
NV2080_CTRL_INTERNAL_NVENC_GET_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVENC_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS(c.Struct):
|
|
SIZE = 1336
|
|
gpcMask: int
|
|
tpcMask: c.Array[ctypes.c_uint32, Literal[64]]
|
|
tpcCount: c.Array[ctypes.c_uint32, Literal[64]]
|
|
physGpcMask: int
|
|
mmuPerGpc: c.Array[ctypes.c_uint32, Literal[64]]
|
|
tpcToPesMap: c.Array[ctypes.c_uint32, Literal[10]]
|
|
numPesPerGpc: c.Array[ctypes.c_uint32, Literal[64]]
|
|
zcullMask: c.Array[ctypes.c_uint32, Literal[64]]
|
|
physGfxGpcMask: int
|
|
numGfxTpc: int
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS.register_fields([('gpcMask', NvU32, 0), ('tpcMask', c.Array[NvU32, Literal[64]], 4), ('tpcCount', c.Array[NvU32, Literal[64]], 260), ('physGpcMask', NvU32, 516), ('mmuPerGpc', c.Array[NvU32, Literal[64]], 520), ('tpcToPesMap', c.Array[NvU32, Literal[10]], 776), ('numPesPerGpc', c.Array[NvU32, Literal[64]], 816), ('zcullMask', c.Array[NvU32, Literal[64]], 1072), ('physGfxGpcMask', NvU32, 1328), ('numGfxTpc', NvU32, 1332)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS(c.Struct):
|
|
SIZE = 10688
|
|
floorsweepingMasks: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS.register_fields([('floorsweepingMasks', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS(c.Struct):
|
|
SIZE = 1056
|
|
hUserClient: int
|
|
hChannel: int
|
|
bufferType: int
|
|
firstPage: int
|
|
numPages: int
|
|
physAddrs: c.Array[ctypes.c_uint64, Literal[128]]
|
|
bNoMorePages: int
|
|
struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS.register_fields([('hUserClient', NvHandle, 0), ('hChannel', NvHandle, 4), ('bufferType', NvU32, 8), ('firstPage', NvU32, 12), ('numPages', NvU32, 16), ('physAddrs', c.Array[NvU64, Literal[128]], 24), ('bNoMorePages', NvBool, 1048)])
|
|
NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS: TypeAlias = struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GR_INFO(c.Struct):
|
|
SIZE = 8
|
|
index: int
|
|
data: int
|
|
struct_NV2080_CTRL_INTERNAL_GR_INFO.register_fields([('index', NvU32, 0), ('data', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_GR_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO(c.Struct):
|
|
SIZE = 504
|
|
infoList: c.Array[struct_NV2080_CTRL_INTERNAL_GR_INFO, Literal[63]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO.register_fields([('infoList', c.Array[NV2080_CTRL_INTERNAL_GR_INFO, Literal[63]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 4032
|
|
engineInfo: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS.register_fields([('engineInfo', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_INFO, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO(c.Struct):
|
|
SIZE = 40
|
|
widthAlignPixels: int
|
|
heightAlignPixels: int
|
|
pixelSquaresByAliquots: int
|
|
aliquotTotal: int
|
|
zcullRegionByteMultiplier: int
|
|
zcullRegionHeaderSize: int
|
|
zcullSubregionHeaderSize: int
|
|
subregionCount: int
|
|
subregionWidthAlignPixels: int
|
|
subregionHeightAlignPixels: int
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO.register_fields([('widthAlignPixels', NvU32, 0), ('heightAlignPixels', NvU32, 4), ('pixelSquaresByAliquots', NvU32, 8), ('aliquotTotal', NvU32, 12), ('zcullRegionByteMultiplier', NvU32, 16), ('zcullRegionHeaderSize', NvU32, 20), ('zcullSubregionHeaderSize', NvU32, 24), ('subregionCount', NvU32, 28), ('subregionWidthAlignPixels', NvU32, 32), ('subregionHeightAlignPixels', NvU32, 36)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS(c.Struct):
|
|
SIZE = 320
|
|
engineZcullInfo: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS.register_fields([('engineZcullInfo', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO(c.Struct):
|
|
SIZE = 12
|
|
ropUnitCount: int
|
|
ropOperationsFactor: int
|
|
ropOperationsCount: int
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO.register_fields([('ropUnitCount', NvU32, 0), ('ropOperationsFactor', NvU32, 4), ('ropOperationsCount', NvU32, 8)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
engineRopInfo: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS.register_fields([('engineRopInfo', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS(c.Struct):
|
|
SIZE = 256
|
|
mask: c.Array[ctypes.c_uint32, Literal[64]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS.register_fields([('mask', c.Array[NvU32, Literal[64]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS(c.Struct):
|
|
SIZE = 2048
|
|
enginePpcMasks: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS.register_fields([('enginePpcMasks', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO(c.Struct):
|
|
SIZE = 8
|
|
size: int
|
|
alignment: int
|
|
struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO.register_fields([('size', NvU32, 0), ('alignment', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO(c.Struct):
|
|
SIZE = 208
|
|
engine: c.Array[struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO, Literal[26]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO.register_fields([('engine', c.Array[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO, Literal[26]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS(c.Struct):
|
|
SIZE = 1664
|
|
engineContextBuffersInfo: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS.register_fields([('engineContextBuffersInfo', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER(c.Struct):
|
|
SIZE = 9
|
|
imla0: int
|
|
fmla16: int
|
|
dp: int
|
|
fmla32: int
|
|
ffma: int
|
|
imla1: int
|
|
imla2: int
|
|
imla3: int
|
|
imla4: int
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER.register_fields([('imla0', NvU8, 0), ('fmla16', NvU8, 1), ('dp', NvU8, 2), ('fmla32', NvU8, 3), ('ffma', NvU8, 4), ('imla1', NvU8, 5), ('imla2', NvU8, 6), ('imla3', NvU8, 7), ('imla4', NvU8, 8)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
smIssueRateModifier: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS.register_fields([('smIssueRateModifier', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS(c.Struct):
|
|
SIZE = 88
|
|
chipSubRev: int
|
|
emulationRev1: int
|
|
isCmpSku: int
|
|
pciDeviceId: int
|
|
pciSubDeviceId: int
|
|
pciRevisionId: int
|
|
regBases: c.Array[ctypes.c_uint32, Literal[16]]
|
|
struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS.register_fields([('chipSubRev', NvU8, 0), ('emulationRev1', NvU32, 4), ('isCmpSku', NvBool, 8), ('pciDeviceId', NvU32, 12), ('pciSubDeviceId', NvU32, 16), ('pciRevisionId', NvU32, 20), ('regBases', c.Array[NvU32, Literal[16]], 24)])
|
|
NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
bEnable: int
|
|
struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS.register_fields([('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 0), ('bEnable', NvBool, 16)])
|
|
NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
grRouteInfo: struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
offset: int
|
|
struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS.register_fields([('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO, 0), ('offset', NvU32, 16)])
|
|
NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE(c.Struct):
|
|
SIZE = 4
|
|
fecsRecordSize: int
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE.register_fields([('fecsRecordSize', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
fecsRecordSize: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS.register_fields([('fecsRecordSize', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES(c.Struct):
|
|
SIZE = 32
|
|
fecsRecordSize: int
|
|
timestampHiTagMask: int
|
|
timestampHiTagShift: int
|
|
timestampVMask: int
|
|
numLowerBitsZeroShift: int
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES.register_fields([('fecsRecordSize', NvU32, 0), ('timestampHiTagMask', NvU32, 4), ('timestampHiTagShift', NvU8, 8), ('timestampVMask', NvU64, 16), ('numLowerBitsZeroShift', NvU8, 24)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS(c.Struct):
|
|
SIZE = 256
|
|
fecsTraceDefines: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS.register_fields([('fecsTraceDefines', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DEVICE_INFO(c.Struct):
|
|
SIZE = 48
|
|
faultId: int
|
|
instanceId: int
|
|
typeEnum: int
|
|
resetId: int
|
|
devicePriBase: int
|
|
isEngine: int
|
|
rlEngId: int
|
|
runlistPriBase: int
|
|
groupId: int
|
|
ginTargetId: int
|
|
deviceBroadcastPriBase: int
|
|
groupLocalInstanceId: int
|
|
struct_NV2080_CTRL_INTERNAL_DEVICE_INFO.register_fields([('faultId', NvU32, 0), ('instanceId', NvU32, 4), ('typeEnum', NvU32, 8), ('resetId', NvU32, 12), ('devicePriBase', NvU32, 16), ('isEngine', NvU32, 20), ('rlEngId', NvU32, 24), ('runlistPriBase', NvU32, 28), ('groupId', NvU32, 32), ('ginTargetId', NvU32, 36), ('deviceBroadcastPriBase', NvU32, 40), ('groupLocalInstanceId', NvU32, 44)])
|
|
NV2080_CTRL_INTERNAL_DEVICE_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_DEVICE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS(c.Struct):
|
|
SIZE = 24580
|
|
numEntries: int
|
|
deviceInfoTable: c.Array[struct_NV2080_CTRL_INTERNAL_DEVICE_INFO, Literal[512]]
|
|
struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS.register_fields([('numEntries', NvU32, 0), ('deviceInfoTable', c.Array[NV2080_CTRL_INTERNAL_DEVICE_INFO, Literal[512]], 4)])
|
|
NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS(c.Struct):
|
|
SIZE = 20492
|
|
userRegisterAccessMapSize: int
|
|
compressedSize: int
|
|
compressedData: c.Array[ctypes.c_ubyte, Literal[16384]]
|
|
profilingRangesSize: int
|
|
profilingRanges: c.Array[ctypes.c_ubyte, Literal[4096]]
|
|
struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS.register_fields([('userRegisterAccessMapSize', NvU32, 0), ('compressedSize', NvU32, 4), ('compressedData', c.Array[NvU8, Literal[16384]], 8), ('profilingRangesSize', NvU32, 16392), ('profilingRanges', c.Array[NvU8, Literal[4096]], 16396)])
|
|
NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NV_RANGE(c.Struct):
|
|
SIZE = 16
|
|
lo: int
|
|
hi: int
|
|
struct_NV2080_CTRL_INTERNAL_NV_RANGE.register_fields([('lo', NvU64, 0), ('hi', NvU64, 8)])
|
|
NV2080_CTRL_INTERNAL_NV_RANGE: TypeAlias = struct_NV2080_CTRL_INTERNAL_NV_RANGE
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
swizzId: int
|
|
memAddrRange: struct_NV2080_CTRL_INTERNAL_NV_RANGE
|
|
struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS.register_fields([('swizzId', NvU32, 0), ('memAddrRange', NV2080_CTRL_INTERNAL_NV_RANGE, 8)])
|
|
NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES(c.Struct):
|
|
SIZE = 1
|
|
bPerSubCtxheaderSupported: int
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES.register_fields([('bPerSubCtxheaderSupported', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
ctsId: int
|
|
bCheckClientGI: int
|
|
giComputeSize: int
|
|
bCtsIdValid: int
|
|
struct_NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS.register_fields([('ctsId', NvU32, 0), ('bCheckClientGI', NvBool, 4), ('giComputeSize', NvU32, 8), ('bCtsIdValid', NvBool, 12)])
|
|
NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pdbTable: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS.register_fields([('pdbTable', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
instMemPhysAddr: int
|
|
instMemSize: int
|
|
instMemAddrSpace: int
|
|
instMemCpuCacheAttr: int
|
|
struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS.register_fields([('instMemPhysAddr', NvU64, 0), ('instMemSize', NvU64, 8), ('instMemAddrSpace', NvU32, 16), ('instMemCpuCacheAttr', NvU32, 20)])
|
|
NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
ipVersion: int
|
|
struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS.register_fields([('ipVersion', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
smcMode: int
|
|
struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS.register_fields([('smcMode', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
head: int
|
|
rgLineNum: int
|
|
intrLine: int
|
|
bEnable: int
|
|
struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS.register_fields([('head', NvU32, 0), ('rgLineNum', NvU32, 4), ('intrLine', NvU32, 8), ('bEnable', NvBool, 12)])
|
|
NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO(c.Struct):
|
|
SIZE = 72
|
|
partitionFlag: int
|
|
grCount: int
|
|
gfxGrCount: int
|
|
gpcCount: int
|
|
virtualGpcCount: int
|
|
gfxGpcCount: int
|
|
veidCount: int
|
|
smCount: int
|
|
ceCount: int
|
|
nvEncCount: int
|
|
nvDecCount: int
|
|
nvJpgCount: int
|
|
nvOfaCount: int
|
|
validCTSIdMask: int
|
|
validGfxCTSIdMask: int
|
|
struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO.register_fields([('partitionFlag', NvU32, 0), ('grCount', NvU32, 4), ('gfxGrCount', NvU32, 8), ('gpcCount', NvU32, 12), ('virtualGpcCount', NvU32, 16), ('gfxGpcCount', NvU32, 20), ('veidCount', NvU32, 24), ('smCount', NvU32, 28), ('ceCount', NvU32, 32), ('nvEncCount', NvU32, 36), ('nvDecCount', NvU32, 40), ('nvJpgCount', NvU32, 44), ('nvOfaCount', NvU32, 48), ('validCTSIdMask', NvU64, 56), ('validGfxCTSIdMask', NvU64, 64)])
|
|
NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS(c.Struct):
|
|
SIZE = 6488
|
|
count: int
|
|
table: c.Array[struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO, Literal[90]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS.register_fields([('count', NvU32, 0), ('table', c.Array[NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO, Literal[90]], 8)])
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
partitionableMemSize: int
|
|
bottomRsvdSize: int
|
|
topRsvdSize: int
|
|
partitionableStartAddr: int
|
|
partitionableEndAddr: int
|
|
struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS.register_fields([('partitionableMemSize', NvU64, 0), ('bottomRsvdSize', NvU64, 8), ('topRsvdSize', NvU64, 16), ('partitionableStartAddr', NvU64, 24), ('partitionableEndAddr', NvU64, 32)])
|
|
NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
engineMask: c.Array[ctypes.c_uint64, Literal[4]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS.register_fields([('engineMask', c.Array[NvU64, Literal[4]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS(c.Struct):
|
|
SIZE = 4112
|
|
rlBuffers: c.Array[c.Array[struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO, Literal[2]], Literal[64]]
|
|
runlistIdMask: int
|
|
swizzId: int
|
|
struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS.register_fields([('rlBuffers', c.Array[c.Array[NV2080_CTRL_INTERNAL_MEMDESC_INFO, Literal[2]], Literal[64]], 0), ('runlistIdMask', NvU64, 4096), ('swizzId', NvU32, 4104)])
|
|
NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS(c.Struct):
|
|
SIZE = 492
|
|
tegraImpImportData: struct_TEGRA_IMP_IMPORT_DATA
|
|
@c.record
|
|
class struct_TEGRA_IMP_IMPORT_DATA(c.Struct):
|
|
SIZE = 492
|
|
max_iso_bw_kbps: int
|
|
num_dram_channels: int
|
|
num_dram_clk_entries: int
|
|
dram_clk_instance: c.Array[struct_DRAM_CLK_INSTANCE, Literal[24]]
|
|
TEGRA_IMP_IMPORT_DATA: TypeAlias = struct_TEGRA_IMP_IMPORT_DATA
|
|
@c.record
|
|
class struct_DRAM_CLK_INSTANCE(c.Struct):
|
|
SIZE = 20
|
|
dram_clk_freq_khz: int
|
|
mchub_clk_khz: int
|
|
mc_clk_khz: int
|
|
max_iso_bw_kbps: int
|
|
switch_latency_ns: int
|
|
DRAM_CLK_INSTANCE: TypeAlias = struct_DRAM_CLK_INSTANCE
|
|
struct_DRAM_CLK_INSTANCE.register_fields([('dram_clk_freq_khz', NvU32, 0), ('mchub_clk_khz', NvU32, 4), ('mc_clk_khz', NvU32, 8), ('max_iso_bw_kbps', NvU32, 12), ('switch_latency_ns', NvU32, 16)])
|
|
struct_TEGRA_IMP_IMPORT_DATA.register_fields([('max_iso_bw_kbps', NvU32, 0), ('num_dram_channels', NvU32, 4), ('num_dram_clk_entries', NvU32, 8), ('dram_clk_instance', c.Array[DRAM_CLK_INSTANCE, Literal[24]], 12)])
|
|
struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS.register_fields([('tegraImpImportData', TEGRA_IMP_IMPORT_DATA, 0)])
|
|
NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS(c.Struct):
|
|
SIZE = 6
|
|
pciDeviceId: int
|
|
pciSubDeviceId: int
|
|
iseGPUBridge: int
|
|
approvedBusType: int
|
|
struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS.register_fields([('pciDeviceId', NvU16, 0), ('pciSubDeviceId', NvU16, 2), ('iseGPUBridge', NvBool, 4), ('approvedBusType', NvU8, 5)])
|
|
NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
local2Remote: int
|
|
remote2Local: int
|
|
localP2PDomainRemoteAddr: int
|
|
remoteP2PDomainLocalAddr: int
|
|
remoteWMBoxLocalAddr: int
|
|
p2pWmbTag: int
|
|
bNeedWarBug999673: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS.register_fields([('local2Remote', NvU32, 0), ('remote2Local', NvU32, 4), ('localP2PDomainRemoteAddr', NvU64, 8), ('remoteP2PDomainLocalAddr', NvU64, 16), ('remoteWMBoxLocalAddr', NvU64, 24), ('p2pWmbTag', NvU64, 32), ('bNeedWarBug999673', NvBool, 40)])
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
local2Remote: int
|
|
remote2Local: int
|
|
localP2PDomainRemoteAddr: int
|
|
remoteP2PDomainLocalAddr: int
|
|
remoteWMBoxAddrU64: int
|
|
p2pWmbTag: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS.register_fields([('local2Remote', NvU32, 0), ('remote2Local', NvU32, 4), ('localP2PDomainRemoteAddr', NvU64, 8), ('remoteP2PDomainLocalAddr', NvU64, 16), ('remoteWMBoxAddrU64', NvU64, 24), ('p2pWmbTag', NvU64, 32)])
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
peerIdx: int
|
|
bNeedWarBug999673: int
|
|
struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS.register_fields([('peerIdx', NvU32, 0), ('bNeedWarBug999673', NvBool, 4)])
|
|
NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
peerId: int
|
|
struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS.register_fields([('peerId', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
peerId: int
|
|
struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS.register_fields([('peerId', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS(c.Struct):
|
|
SIZE = 2056
|
|
gfid: int
|
|
numEntries: int
|
|
gpaEntries: c.Array[ctypes.c_uint64, Literal[128]]
|
|
spaEntries: c.Array[ctypes.c_uint64, Literal[128]]
|
|
struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS.register_fields([('gfid', NvU32, 0), ('numEntries', NvU32, 4), ('gpaEntries', c.Array[NvU64, Literal[128]], 8), ('spaEntries', c.Array[NvU64, Literal[128]], 1032)])
|
|
NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
addressSpace: int
|
|
physicalAddr: int
|
|
limit: int
|
|
cacheSnoop: int
|
|
hclass: int
|
|
channelInstance: int
|
|
valid: int
|
|
pbTargetAperture: int
|
|
channelPBSize: int
|
|
subDeviceId: int
|
|
struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS.register_fields([('addressSpace', NvU32, 0), ('physicalAddr', NvU64, 8), ('limit', NvU64, 16), ('cacheSnoop', NvU32, 24), ('hclass', NvU32, 28), ('channelInstance', NvU32, 32), ('valid', NvBool, 36), ('pbTargetAperture', NvU32, 40), ('channelPBSize', NvU32, 44), ('subDeviceId', NvU32, 48)])
|
|
NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
replayableFaultBufferSize: int
|
|
replayableShadowFaultBufferMetadataSize: int
|
|
nonReplayableFaultBufferSize: int
|
|
nonReplayableShadowFaultBufferMetadataSize: int
|
|
struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS.register_fields([('replayableFaultBufferSize', NvU32, 0), ('replayableShadowFaultBufferMetadataSize', NvU32, 4), ('nonReplayableFaultBufferSize', NvU32, 8), ('nonReplayableShadowFaultBufferMetadataSize', NvU32, 12)])
|
|
NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
moduleIndex: int
|
|
size: int
|
|
struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS.register_fields([('moduleIndex', NvU32, 0), ('size', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY(c.Struct):
|
|
SIZE = 16
|
|
engineIdx: int
|
|
pmcIntrMask: int
|
|
vectorStall: int
|
|
vectorNonStall: int
|
|
struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY.register_fields([('engineIdx', NvU16, 0), ('pmcIntrMask', NvU32, 4), ('vectorStall', NvU32, 8), ('vectorNonStall', NvU32, 12)])
|
|
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY: TypeAlias = struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS(c.Struct):
|
|
SIZE = 2112
|
|
tableLen: int
|
|
table: c.Array[struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY, Literal[128]]
|
|
subtreeMap: c.Array[struct_NV2080_INTR_CATEGORY_SUBTREE_MAP, Literal[7]]
|
|
@c.record
|
|
class struct_NV2080_INTR_CATEGORY_SUBTREE_MAP(c.Struct):
|
|
SIZE = 8
|
|
subtreeMask: int
|
|
NV2080_INTR_CATEGORY_SUBTREE_MAP: TypeAlias = struct_NV2080_INTR_CATEGORY_SUBTREE_MAP
|
|
struct_NV2080_INTR_CATEGORY_SUBTREE_MAP.register_fields([('subtreeMask', NvU64, 0)])
|
|
struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS.register_fields([('tableLen', NvU32, 0), ('table', c.Array[NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY, Literal[128]], 4), ('subtreeMap', c.Array[NV2080_INTR_CATEGORY_SUBTREE_MAP, Literal[7]], 2056)])
|
|
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bReservation: int
|
|
struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS.register_fields([('bReservation', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
bReservation: int
|
|
bClientHandlesGrGating: int
|
|
bRmHandlesIdleSlow: int
|
|
struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS.register_fields([('bReservation', NvBool, 0), ('bClientHandlesGrGating', NvBool, 1), ('bRmHandlesIdleSlow', NvBool, 2)])
|
|
NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
displayMask: int
|
|
numHeads: int
|
|
struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS.register_fields([('displayMask', NvU32, 0), ('numHeads', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS(c.Struct):
|
|
SIZE = 240
|
|
fbMemPageRanges: c.Array[struct_NV2080_CTRL_INTERNAL_NV_RANGE, Literal[15]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS.register_fields([('fbMemPageRanges', c.Array[NV2080_CTRL_INTERNAL_NV_RANGE, Literal[15]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
runlistId: int
|
|
numChannels: int
|
|
struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS.register_fields([('runlistId', NvU32, 0), ('numChannels', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
memBoundaryCfgA: int
|
|
memBoundaryCfgB: int
|
|
memBoundaryCfgC: int
|
|
memBoundaryCfg: int
|
|
memBoundaryCfgValInit: int
|
|
struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS.register_fields([('memBoundaryCfgA', NvU64, 0), ('memBoundaryCfgB', NvU64, 8), ('memBoundaryCfgC', NvU32, 16), ('memBoundaryCfg', NvU32, 20), ('memBoundaryCfgValInit', NvU32, 24)])
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS
|
|
NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
data: c.Array[ctypes.c_uint32, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS.register_fields([('data', c.Array[NvU32, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
powerState: int
|
|
struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS.register_fields([('powerState', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X(c.Struct):
|
|
SIZE = 8
|
|
flags: int
|
|
duration: int
|
|
struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X.register_fields([('flags', NvBool, 0), ('duration', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bActivate: int
|
|
struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS.register_fields([('bActivate', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
flags: int
|
|
bBridgeless: int
|
|
currLimits: c.Array[ctypes.c_uint32, Literal[2]]
|
|
struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS.register_fields([('flags', NvU32, 0), ('bBridgeless', NvBool, 4), ('currLimits', c.Array[NvU32, Literal[2]], 8)])
|
|
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hysteresisus: int
|
|
bHystersisEnable: int
|
|
bSliGpuBoostSyncEnable: int
|
|
struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS.register_fields([('hysteresisus', NvU64, 0), ('bHystersisEnable', NvBool, 8), ('bSliGpuBoostSyncEnable', NvBool, 9)])
|
|
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 2064
|
|
hClient: int
|
|
hObject: int
|
|
faultBufferSize: int
|
|
faultBufferPteArray: c.Array[ctypes.c_uint64, Literal[256]]
|
|
struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS.register_fields([('hClient', NvHandle, 0), ('hObject', NvHandle, 4), ('faultBufferSize', NvU32, 8), ('faultBufferPteArray', c.Array[NvU64, Literal[256]], 16)])
|
|
NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 24032
|
|
shadowFaultBufferQueuePhysAddr: int
|
|
shadowFaultBufferSize: int
|
|
shadowFaultBufferMetadataSize: int
|
|
shadowFaultBufferPteArray: c.Array[ctypes.c_uint64, Literal[3000]]
|
|
shadowFaultBufferType: int
|
|
faultBufferSharedMemoryPhysAddr: int
|
|
struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS.register_fields([('shadowFaultBufferQueuePhysAddr', NvU64, 0), ('shadowFaultBufferSize', NvU32, 8), ('shadowFaultBufferMetadataSize', NvU32, 12), ('shadowFaultBufferPteArray', c.Array[NvU64, Literal[3000]], 16), ('shadowFaultBufferType', NvU32, 24016), ('faultBufferSharedMemoryPhysAddr', NvU64, 24024)])
|
|
NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
shadowFaultBufferType: int
|
|
struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS.register_fields([('shadowFaultBufferType', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS(c.Struct):
|
|
SIZE = 184
|
|
PdeCopyParams: struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS
|
|
struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS.register_fields([('PdeCopyParams', NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS, 0)])
|
|
NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X(c.Struct):
|
|
SIZE = 16
|
|
flags: int
|
|
boostDuration: int
|
|
gfId: int
|
|
bOverrideInfinite: int
|
|
struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X.register_fields([('flags', NvU32, 0), ('boostDuration', NvU32, 4), ('gfId', NvU32, 8), ('bOverrideInfinite', NvBool, 12)])
|
|
NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X(c.Struct):
|
|
SIZE = 8
|
|
bIsCudaClient: int
|
|
gfId: int
|
|
struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X.register_fields([('bIsCudaClient', NvBool, 0), ('gfId', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO(c.Struct):
|
|
SIZE = 80
|
|
skylineVgpcSize: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
singletonVgpcMask: int
|
|
maxInstances: int
|
|
computeSizeFlag: int
|
|
numNonSingletonVgpcs: int
|
|
struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO.register_fields([('skylineVgpcSize', c.Array[NvU8, Literal[64]], 0), ('singletonVgpcMask', NvU32, 64), ('maxInstances', NvU32, 68), ('computeSizeFlag', NvU32, 72), ('numNonSingletonVgpcs', NvU32, 76)])
|
|
NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS(c.Struct):
|
|
SIZE = 724
|
|
skylineTable: c.Array[struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO, Literal[9]]
|
|
validEntries: int
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS.register_fields([('skylineTable', c.Array[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO, Literal[9]], 0), ('validEntries', NvU32, 720)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS
|
|
NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS
|
|
NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS
|
|
NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS
|
|
NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bZbcSurfacesExist: int
|
|
struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS.register_fields([('bZbcSurfacesExist', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO(c.Struct):
|
|
SIZE = 56
|
|
enginesMask: c.Array[ctypes.c_uint64, Literal[4]]
|
|
partitionFlags: int
|
|
gpcMask: int
|
|
virtualGpcCount: int
|
|
veidOffset: int
|
|
veidCount: int
|
|
struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO.register_fields([('enginesMask', c.Array[NvU64, Literal[4]], 0), ('partitionFlags', NvU32, 32), ('gpcMask', NvU32, 36), ('virtualGpcCount', NvU32, 40), ('veidOffset', NvU32, 44), ('veidCount', NvU32, 48)])
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
swizzId: int
|
|
uuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
info: struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO
|
|
struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS.register_fields([('swizzId', NvU32, 0), ('uuid', c.Array[NvU8, Literal[16]], 4), ('info', NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO, 24)])
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
|
|
NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
|
|
NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
flags: int
|
|
struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS.register_fields([('flags', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
bPcieGen4Capable: int
|
|
bIsC2CLinkUp: int
|
|
bIsDeviceMultiFunction: int
|
|
bGcxPmuCfgSpaceRestore: int
|
|
struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS.register_fields([('bPcieGen4Capable', NvBool, 0), ('bIsC2CLinkUp', NvBool, 1), ('bIsDeviceMultiFunction', NvBool, 2), ('bGcxPmuCfgSpaceRestore', NvBool, 3)])
|
|
NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
programPeerMask: int
|
|
invalidatePeerMask: int
|
|
programPciePeerMask: int
|
|
struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS.register_fields([('programPeerMask', NvU32, 0), ('invalidatePeerMask', NvU32, 4), ('programPciePeerMask', NvU32, 8)])
|
|
NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS(c.Struct):
|
|
SIZE = 36
|
|
linkMask: int
|
|
hshubIds: c.Array[ctypes.c_ubyte, Literal[32]]
|
|
struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS.register_fields([('linkMask', NvU32, 0), ('hshubIds', c.Array[NvU8, Literal[32]], 4)])
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
numHshubs: int
|
|
struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS.register_fields([('numHshubs', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
hshubId: int
|
|
struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS.register_fields([('hshubId', NvU8, 0)])
|
|
NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
egmPeerId: int
|
|
struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS.register_fields([('egmPeerId', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
bGet: int
|
|
addr: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS.register_fields([('bGet', NvBool, 0), ('addr', NvU64, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
maxActiveVGpuVMCount: int
|
|
struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS.register_fields([('maxActiveVGpuVMCount', NvU8, 0)])
|
|
NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bRawMode: int
|
|
struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS.register_fields([('bRawMode', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
ccuSampleSize: int
|
|
struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS.register_fields([('ccuSampleSize', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO(c.Struct):
|
|
SIZE = 16
|
|
phyAddr: int
|
|
shrBufSize: int
|
|
cntBlkSize: int
|
|
struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO.register_fields([('phyAddr', NvU64, 0), ('shrBufSize', NvU32, 8), ('cntBlkSize', NvU32, 12)])
|
|
NV2080_CTRL_INTERNAL_CCU_MAP_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS(c.Struct):
|
|
SIZE = 144
|
|
mapInfo: c.Array[struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO, Literal[9]]
|
|
struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS.register_fields([('mapInfo', c.Array[NV2080_CTRL_INTERNAL_CCU_MAP_INFO, Literal[9]], 0)])
|
|
NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bDevShrBuf: int
|
|
bMigShrBuf: int
|
|
struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS.register_fields([('bDevShrBuf', NvBool, 0), ('bMigShrBuf', NvBool, 1)])
|
|
NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO(c.Struct):
|
|
SIZE = 40
|
|
gpuId: int
|
|
gpuInstance: int
|
|
p2pCaps: int
|
|
p2pOptimalReadCEs: int
|
|
p2pOptimalWriteCEs: int
|
|
p2pCapsStatus: c.Array[ctypes.c_ubyte, Literal[9]]
|
|
busPeerId: int
|
|
busEgmPeerId: int
|
|
struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO.register_fields([('gpuId', NvU32, 0), ('gpuInstance', NvU32, 4), ('p2pCaps', NvU32, 8), ('p2pOptimalReadCEs', NvU32, 12), ('p2pOptimalWriteCEs', NvU32, 16), ('p2pCapsStatus', c.Array[NvU8, Literal[9]], 20), ('busPeerId', NvU32, 32), ('busEgmPeerId', NvU32, 36)])
|
|
NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS(c.Struct):
|
|
SIZE = 1284
|
|
peerGpuCount: int
|
|
peerGpuInfos: c.Array[struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO, Literal[32]]
|
|
struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS.register_fields([('peerGpuCount', NvU32, 0), ('peerGpuInfos', c.Array[NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO, Literal[32]], 4)])
|
|
NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS(c.Struct):
|
|
SIZE = 132
|
|
peerGpuIdCount: int
|
|
peerGpuIds: c.Array[ctypes.c_uint32, Literal[32]]
|
|
struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS.register_fields([('peerGpuIdCount', NvU32, 0), ('peerGpuIds', c.Array[NvU32, Literal[32]], 4)])
|
|
NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
bCommonPciSwitchFound: int
|
|
p2pReadCapsStatus: int
|
|
p2pWriteCapsStatus: int
|
|
struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS.register_fields([('bCommonPciSwitchFound', NvBool, 0), ('p2pReadCapsStatus', NvU8, 1), ('p2pWriteCapsStatus', NvU8, 2)])
|
|
NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
enableRo: int
|
|
struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS.register_fields([('enableRo', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
bSave: int
|
|
bUseVbios: int
|
|
bReturnEarly: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS.register_fields([('bSave', NvBool, 0), ('bUseVbios', NvBool, 1), ('bReturnEarly', NvBool, 2)])
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
bSave: int
|
|
bUseVbios: int
|
|
bVbiosCallSuccessful: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS.register_fields([('bSave', NvBool, 0), ('bUseVbios', NvBool, 1), ('bVbiosCallSuccessful', NvBool, 2)])
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE(c.Struct):
|
|
SIZE = 24
|
|
computeSize: int
|
|
flags: int
|
|
gfxGpcCount: int
|
|
gpcCount: int
|
|
veidCount: int
|
|
smCount: int
|
|
physicalSlots: int
|
|
struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE.register_fields([('computeSize', NvU8, 0), ('flags', NvU16, 2), ('gfxGpcCount', NvU32, 4), ('gpcCount', NvU32, 8), ('veidCount', NvU32, 12), ('smCount', NvU32, 16), ('physicalSlots', NvU32, 20)])
|
|
NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE: TypeAlias = struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS(c.Struct):
|
|
SIZE = 196
|
|
profileCount: int
|
|
profiles: c.Array[struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS.register_fields([('profileCount', NvU32, 0), ('profiles', c.Array[NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE, Literal[8]], 4)])
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bStreamState: int
|
|
struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS.register_fields([('bStreamState', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bExtDevFound: int
|
|
struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS.register_fields([('bExtDevFound', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
timingParameters: struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS
|
|
@c.record
|
|
class struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
gpuId: int
|
|
output: int
|
|
protocol: int
|
|
structure: int
|
|
adjust: int
|
|
hDeltaStep: int
|
|
hDeltaMax: int
|
|
vDeltaStep: int
|
|
vDeltaMax: int
|
|
hSyncEnd: int
|
|
hBlankEnd: int
|
|
hBlankStart: int
|
|
hTotal: int
|
|
vSyncEnd: int
|
|
vBlankEnd: int
|
|
vBlankStart: int
|
|
vInterlacedBlankEnd: int
|
|
vInterlacedBlankStart: int
|
|
vTotal: int
|
|
refreshX10K: int
|
|
pixelClockHz: int
|
|
bOptimized: int
|
|
NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS: TypeAlias = struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS
|
|
struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS.register_fields([('gpuId', NvU32, 0), ('output', NvU32, 4), ('protocol', NvU32, 8), ('structure', NvU32, 12), ('adjust', NvU32, 16), ('hDeltaStep', NvU32, 20), ('hDeltaMax', NvU32, 24), ('vDeltaStep', NvU32, 28), ('vDeltaMax', NvU32, 32), ('hSyncEnd', NvU32, 36), ('hBlankEnd', NvU32, 40), ('hBlankStart', NvU32, 44), ('hTotal', NvU32, 48), ('vSyncEnd', NvU32, 52), ('vBlankEnd', NvU32, 56), ('vBlankStart', NvU32, 60), ('vInterlacedBlankEnd', NvU32, 64), ('vInterlacedBlankStart', NvU32, 68), ('vTotal', NvU32, 72), ('refreshX10K', NvU32, 76), ('pixelClockHz', NvU64, 80), ('bOptimized', NvBool, 88)])
|
|
struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS.register_fields([('timingParameters', NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS, 0)])
|
|
NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
displayIds: c.Array[ctypes.c_uint32, Literal[4]]
|
|
struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS.register_fields([('displayIds', c.Array[NvU32, Literal[4]], 0)])
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS(c.Struct):
|
|
SIZE = 52
|
|
slave: c.Array[ctypes.c_uint32, Literal[4]]
|
|
localSlave: c.Array[ctypes.c_uint32, Literal[4]]
|
|
master: c.Array[ctypes.c_uint32, Literal[4]]
|
|
regStatus: int
|
|
struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS.register_fields([('slave', c.Array[NvU32, Literal[4]], 0), ('localSlave', c.Array[NvU32, Literal[4]], 16), ('master', c.Array[NvU32, Literal[4]], 32), ('regStatus', NvU32, 48)])
|
|
NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
headIdx: int
|
|
vActiveLines: int
|
|
struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS.register_fields([('headIdx', NvU32, 0), ('vActiveLines', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
displays: int
|
|
displayId: int
|
|
struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS.register_fields([('displays', NvU32, 0), ('displayId', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bEnableMaster: int
|
|
bRasterSyncGpioSaved: int
|
|
bRasterSyncGpioDirection: int
|
|
struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS.register_fields([('bEnableMaster', NvBool, 0), ('bRasterSyncGpioSaved', NvBool, 1), ('bRasterSyncGpioDirection', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hClient: int
|
|
hSysMem: int
|
|
bEnteringGcoffState: int
|
|
sysmemAddrOfSuspendResumeData: int
|
|
struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS.register_fields([('hClient', NvHandle, 0), ('hSysMem', NvHandle, 4), ('bEnteringGcoffState', NvBool, 8), ('sysmemAddrOfSuspendResumeData', NvU64, 16)])
|
|
NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bDisableActiveChannels: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS.register_fields([('bDisableActiveChannels', NvBool, 0)])
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hostReservedFb: int
|
|
vgpuTypeId: int
|
|
struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS.register_fields([('hostReservedFb', NvU64, 0), ('vgpuTypeId', NvU32, 8)])
|
|
NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS(c.Struct):
|
|
SIZE = 4104
|
|
status: int
|
|
backLightDataSize: int
|
|
backLightData: c.Array[ctypes.c_ubyte, Literal[4096]]
|
|
struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS.register_fields([('status', NvU32, 0), ('backLightDataSize', NvU16, 4), ('backLightData', c.Array[NvU8, Literal[4096]], 6)])
|
|
NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
numActiveLinksPerIoctrl: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS.register_fields([('numActiveLinksPerIoctrl', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
numLinksPerIoctrl: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS.register_fields([('numLinksPerIoctrl', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bIsSysCtrlSupported: int
|
|
bIsPlatformLegacy: int
|
|
struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS.register_fields([('bIsSysCtrlSupported', NvBool, 0), ('bIsPlatformLegacy', NvBool, 1)])
|
|
NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI(c.Struct):
|
|
SIZE = 8
|
|
sensorId: int
|
|
limit: int
|
|
struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI.register_fields([('sensorId', NvU32, 0), ('limit', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI: TypeAlias = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA(c.Struct):
|
|
SIZE = 12
|
|
type: int
|
|
data: struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data(c.Struct):
|
|
SIZE = 8
|
|
smbpbi: struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI
|
|
struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data.register_fields([('smbpbi', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI, 0)])
|
|
struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA.register_fields([('type', NvU8, 0), ('data', struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data, 4)])
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA: TypeAlias = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
flags: int
|
|
syncData: struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA
|
|
struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS.register_fields([('flags', NvU8, 0), ('syncData', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA, 4)])
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS
|
|
NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS
|
|
NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
flag: int
|
|
bStatus: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS.register_fields([('flag', NvU8, 0), ('bStatus', NvBool, 1)])
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnable: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS.register_fields([('bEnable', NvBool, 0)])
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bEnable: int
|
|
clientLimit: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS.register_fields([('bEnable', NvBool, 0), ('clientLimit', NvU32, 4)])
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
targetTemp: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS.register_fields([('targetTemp', NvS32, 0)])
|
|
NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnable: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS.register_fields([('bEnable', NvBool, 0)])
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
ctgpOffsetmW: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS.register_fields([('ctgpOffsetmW', NvU32, 0)])
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bVpsPs20Supported: int
|
|
vPstateIdxHighest: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS.register_fields([('bVpsPs20Supported', NvBool, 0), ('vPstateIdxHighest', NvU32, 4)])
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pStateIdx: int
|
|
vPstateIdxMapping: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS.register_fields([('pStateIdx', NvU32, 0), ('vPstateIdxMapping', NvU32, 4)])
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
vPstateIdx: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS.register_fields([('vPstateIdx', NvU32, 0)])
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bIsGC6Satisfied: int
|
|
bIsGCOFFSatisfied: int
|
|
struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS.register_fields([('bIsGC6Satisfied', NvBool, 0), ('bIsGCOFFSatisfied', NvBool, 1)])
|
|
NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
maxSec2SecureChannels: int
|
|
maxCeSecureChannels: int
|
|
struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS.register_fields([('maxSec2SecureChannels', NvU32, 0), ('maxCeSecureChannels', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bDisable: int
|
|
struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS.register_fields([('bDisable', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
pinSetIn: int
|
|
pinSetOut: int
|
|
bMasterScanLock: int
|
|
masterScanLockPin: int
|
|
bSlaveScanLock: int
|
|
slaveScanLockPin: int
|
|
struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS.register_fields([('pinSetIn', NvU32, 0), ('pinSetOut', NvU32, 4), ('bMasterScanLock', NvBool, 8), ('masterScanLockPin', NvU32, 12), ('bSlaveScanLock', NvBool, 16), ('slaveScanLockPin', NvU32, 20)])
|
|
NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pinSet: int
|
|
gpioFunction: int
|
|
gpioPin: int
|
|
gpioDirection: int
|
|
struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS.register_fields([('pinSet', NvU32, 0), ('gpioFunction', NvU32, 4), ('gpioPin', NvU32, 8), ('gpioDirection', NvBool, 12)])
|
|
NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_EDID_DATA(c.Struct):
|
|
SIZE = 524
|
|
status: int
|
|
acpiId: int
|
|
bufferSize: int
|
|
edidBuffer: c.Array[ctypes.c_ubyte, Literal[512]]
|
|
struct_NV2080_CTRL_INTERNAL_EDID_DATA.register_fields([('status', NvU32, 0), ('acpiId', NvU32, 4), ('bufferSize', NvU32, 8), ('edidBuffer', c.Array[NvU8, Literal[512]], 12)])
|
|
NV2080_CTRL_INTERNAL_EDID_DATA: TypeAlias = struct_NV2080_CTRL_INTERNAL_EDID_DATA
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS(c.Struct):
|
|
SIZE = 8388
|
|
tableLen: int
|
|
edidTable: c.Array[struct_NV2080_CTRL_INTERNAL_EDID_DATA, Literal[16]]
|
|
struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS.register_fields([('tableLen', NvU32, 0), ('edidTable', c.Array[NV2080_CTRL_INTERNAL_EDID_DATA, Literal[16]], 4)])
|
|
NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
numProbes: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS.register_fields([('numProbes', NvU64, 0)])
|
|
NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
bwMode: int
|
|
bLocalEgmEnabled: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS.register_fields([('bwMode', NvU16, 0), ('bLocalEgmEnabled', NvBool, 2)])
|
|
NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bwMode: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS.register_fields([('bwMode', NvU16, 0)])
|
|
NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bIsBar1Trusted: int
|
|
bIsPcieTrusted: int
|
|
struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS.register_fields([('bIsBar1Trusted', NvBool, 0), ('bIsPcieTrusted', NvBool, 1)])
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK(c.Struct):
|
|
SIZE = 12
|
|
ivMask: c.Array[ctypes.c_uint32, Literal[3]]
|
|
struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK.register_fields([('ivMask', c.Array[NvU32, Literal[3]], 0)])
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK: TypeAlias = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
engineId: int
|
|
ivMaskSet: c.Array[struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK, Literal[3]]
|
|
struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS.register_fields([('engineId', NvU32, 0), ('ivMaskSet', c.Array[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK, Literal[3]], 4)])
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS(c.Struct):
|
|
SIZE = 76
|
|
engineId: int
|
|
ivMaskSet: c.Array[struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK, Literal[6]]
|
|
struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS.register_fields([('engineId', NvU32, 0), ('ivMaskSet', c.Array[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK, Literal[6]], 4)])
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
globalH2DKey: int
|
|
updatedEncryptIVMask: c.Array[ctypes.c_uint32, Literal[3]]
|
|
updatedDecryptIVMask: c.Array[ctypes.c_uint32, Literal[3]]
|
|
struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS.register_fields([('globalH2DKey', NvU32, 0), ('updatedEncryptIVMask', c.Array[NvU32, Literal[3]], 4), ('updatedDecryptIVMask', c.Array[NvU32, Literal[3]], 16)])
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
exceptionType: int
|
|
globalH2DKey: int
|
|
struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS.register_fields([('exceptionType', NvU32, 0), ('globalH2DKey', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bAcceptClientRequest: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS.register_fields([('bAcceptClientRequest', NvBool, 0)])
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
attackerAdvantage: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS.register_fields([('attackerAdvantage', NvU64, 0)])
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
logicalUprocId: int
|
|
struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS.register_fields([('logicalUprocId', NvU8, 0)])
|
|
NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS
|
|
enum_NV2080_CTRL_MEMMGR_MEMORY_OP: dict[int, str] = {(NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY:=0): 'NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY', (NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET:=1): 'NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET'}
|
|
NV2080_CTRL_MEMMGR_MEMORY_OP: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO(c.Struct):
|
|
SIZE = 32
|
|
baseAddr: int
|
|
size: int
|
|
offset: int
|
|
aperture: int
|
|
cpuCacheAttrib: int
|
|
struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO.register_fields([('baseAddr', NvU64, 0), ('size', NvU64, 8), ('offset', NvU64, 16), ('aperture', NvU32, 24), ('cpuCacheAttrib', NvU32, 28)])
|
|
NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
src: struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO
|
|
authTag: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
dst: struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO
|
|
transferSize: int
|
|
value: int
|
|
memop: int
|
|
struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS.register_fields([('src', NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO, 0), ('authTag', c.Array[NvU8, Literal[16]], 32), ('dst', NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO, 48), ('transferSize', NvU64, 80), ('value', NvU32, 88), ('memop', NV2080_CTRL_MEMMGR_MEMORY_OP, 92)])
|
|
NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
addrSysPhys: int
|
|
addrWidth: int
|
|
mask: int
|
|
maskWidth: int
|
|
struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS.register_fields([('addrSysPhys', NvU64, 0), ('addrWidth', NvU32, 8), ('mask', NvU32, 12), ('maskWidth', NvU32, 16)])
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
peerId: int
|
|
addrSysPhys: int
|
|
addrWidth: int
|
|
mask: int
|
|
maskWidth: int
|
|
struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS.register_fields([('peerId', NvU32, 0), ('addrSysPhys', NvU64, 8), ('addrWidth', NvU32, 16), ('mask', NvU32, 20), ('maskWidth', NvU32, 24)])
|
|
NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
limitMin: int
|
|
limitRated: int
|
|
limitMax: int
|
|
limitCurr: int
|
|
limitBattRated: int
|
|
limitBattMax: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS.register_fields([('limitMin', NvU32, 0), ('limitRated', NvU32, 4), ('limitMax', NvU32, 8), ('limitCurr', NvU32, 12), ('limitBattRated', NvU32, 16), ('limitBattMax', NvU32, 20)])
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
bInit: int
|
|
physAddr: int
|
|
struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS.register_fields([('bInit', NvBool, 0), ('physAddr', NvU64, 8)])
|
|
NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
polledDataMask: int
|
|
pollIntervalMs: int
|
|
struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS.register_fields([('polledDataMask', NvU64, 0), ('pollIntervalMs', NvU32, 8)])
|
|
NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
tracepointMask: int
|
|
bufferAddr: int
|
|
bufferSize: int
|
|
bufferWatermark: int
|
|
flag: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS.register_fields([('tracepointMask', NvU64, 0), ('bufferAddr', NvU64, 8), ('bufferSize', NvU32, 16), ('bufferWatermark', NvU32, 20), ('flag', NvU8, 24)])
|
|
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
bMaxwellSec2Enabled: int
|
|
bNv95A1TsecEnabled: int
|
|
bHopperSec2WorkLaunchAEnabled: int
|
|
struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS.register_fields([('bMaxwellSec2Enabled', NvBool, 0), ('bNv95A1TsecEnabled', NvBool, 1), ('bHopperSec2WorkLaunchAEnabled', NvBool, 2)])
|
|
NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bInPMTransition: int
|
|
newPMLevel: int
|
|
struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS.register_fields([('bInPMTransition', NvBool, 0), ('newPMLevel', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bSuccessful: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS.register_fields([('bSuccessful', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
freeHeapSize: int
|
|
struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS.register_fields([('freeHeapSize', NvU64, 0)])
|
|
NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
attribute: int
|
|
value: int
|
|
struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS.register_fields([('attribute', NvU32, 0), ('value', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bApplyStereoPinAlwaysHiWar: int
|
|
struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS.register_fields([('bApplyStereoPinAlwaysHiWar', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
maxHshubs: int
|
|
struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS.register_fields([('maxHshubs', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rasterSyncDecodeMode: int
|
|
struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS.register_fields([('rasterSyncDecodeMode', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
spaValue: int
|
|
struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS.register_fields([('spaValue', NvU64, 0)])
|
|
NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
peerMask: int
|
|
bEnable: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS.register_fields([('peerMask', NvU32, 0), ('bEnable', NvBool, 4)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
mode: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS.register_fields([('mode', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
seedData: c.Array[ctypes.c_uint32, Literal[7]]
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS.register_fields([('seedData', c.Array[NvU32, Literal[7]], 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
remoteDeviceType: int
|
|
ipVerDlPl: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS.register_fields([('remoteDeviceType', NvU32, 0), ('ipVerDlPl', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
seedData: c.Array[ctypes.c_uint32, Literal[7]]
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS.register_fields([('seedData', c.Array[NvU32, Literal[7]], 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO(c.Struct):
|
|
SIZE = 24
|
|
remoteSid: int
|
|
remoteDeviceType: int
|
|
remoteLinkId: int
|
|
localSid: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO.register_fields([('remoteSid', NvU64, 0), ('remoteDeviceType', NvU32, 8), ('remoteLinkId', NvU32, 12), ('localSid', NvU64, 16)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
bInitnegotiateConfigGood: int
|
|
remoteLocalSidInfo: struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS.register_fields([('bInitnegotiateConfigGood', NvBool, 0), ('remoteLocalSidInfo', NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bPollDone: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS.register_fields([('bPollDone', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
mode: int
|
|
bSync: int
|
|
linkMode: int
|
|
linkModeParams: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams(c.Struct):
|
|
SIZE = 32
|
|
linkModeOffParams: struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS
|
|
linkModePreHsParams: struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS
|
|
linkModeInitPhase1Params: struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS
|
|
linkModePostInitNegotiateParams: struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS
|
|
linkModePostInitOptimizeParams: struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams.register_fields([('linkModeOffParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS, 0), ('linkModePreHsParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS, 0), ('linkModeInitPhase1Params', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS, 0), ('linkModePostInitNegotiateParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS, 0), ('linkModePostInitOptimizeParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS, 0)])
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS.register_fields([('mode', NvU64, 0), ('bSync', NvBool, 8), ('linkMode', NvU32, 12), ('linkModeParams', struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams, 16)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
mode: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS.register_fields([('mode', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
mode: int
|
|
bSync: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS.register_fields([('mode', NvU64, 0), ('bSync', NvBool, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
sublinkMode: int
|
|
sublinkSubMode: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS.register_fields([('sublinkMode', NvU32, 0), ('sublinkSubMode', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
mode: int
|
|
bSync: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS.register_fields([('mode', NvU64, 0), ('bSync', NvBool, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
mode: int
|
|
bSync: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS.register_fields([('mode', NvU64, 0), ('bSync', NvBool, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
laneRxdetStatusMask: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS.register_fields([('laneRxdetStatusMask', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bSync: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS.register_fields([('bSync', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
ipVerDlPl: int
|
|
token: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS.register_fields([('ipVerDlPl', NvU32, 0), ('token', NvU64, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bUnlocked: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS.register_fields([('bUnlocked', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE(c.Struct):
|
|
SIZE = 56
|
|
type: int
|
|
callbackParams: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams(c.Struct):
|
|
SIZE = 48
|
|
getDlLinkMode: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS
|
|
setDlLinkMode: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS
|
|
getTlLinkMode: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS
|
|
setTlLinkMode: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS
|
|
getTxSublinkMode: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS
|
|
setTxSublinkMode: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS
|
|
getRxSublinkMode: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS
|
|
setRxSublinkMode: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS
|
|
getRxSublinkDetect: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS
|
|
setRxSublinkDetect: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS
|
|
writeDiscoveryToken: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS
|
|
readDiscoveryToken: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS
|
|
getUphyLoad: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams.register_fields([('getDlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS, 0), ('setDlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS, 0), ('getTlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS, 0), ('setTlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS, 0), ('getTxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS, 0), ('setTxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS, 0), ('getRxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS, 0), ('setRxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS, 0), ('getRxSublinkDetect', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS, 0), ('setRxSublinkDetect', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS, 0), ('writeDiscoveryToken', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS, 0), ('readDiscoveryToken', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS, 0), ('getUphyLoad', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS, 0)])
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE.register_fields([('type', NvU8, 0), ('callbackParams', struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS(c.Struct):
|
|
SIZE = 64
|
|
linkId: int
|
|
callbackType: struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS.register_fields([('linkId', NvU32, 0), ('callbackType', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
linkId: int
|
|
remoteLocalSidInfo: struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS.register_fields([('linkId', NvU32, 0), ('remoteLocalSidInfo', NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnableAli: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS.register_fields([('bEnableAli', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
updateType: int
|
|
bSysMem: int
|
|
peerMask: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS.register_fields([('updateType', NvBool, 0), ('bSysMem', NvBool, 1), ('peerMask', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
peerId: int
|
|
peerLinkMask: int
|
|
bEgmPeer: int
|
|
bNvswitchConn: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS.register_fields([('peerId', NvU32, 0), ('peerLinkMask', NvU64, 8), ('bEgmPeer', NvBool, 16), ('bNvswitchConn', NvBool, 17)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
peerMask: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS.register_fields([('peerMask', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS(c.Struct):
|
|
SIZE = 92
|
|
xid: int
|
|
message: c.Array[ctypes.c_ubyte, Literal[81]]
|
|
len: int
|
|
struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS.register_fields([('xid', NvU32, 0), ('message', c.Array[NvU8, Literal[81]], 4), ('len', NvU32, 88)])
|
|
NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
mapTypeMask: int
|
|
peerMask: int
|
|
bL2Entry: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS.register_fields([('mapTypeMask', NvU32, 0), ('peerMask', NvU32, 4), ('bL2Entry', NvBool, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
bSave: int
|
|
linkMask: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
NV2080_CTRL_NVLINK_LINK_MASK: TypeAlias = struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS.register_fields([('bSave', NvBool, 0), ('linkMask', NV2080_CTRL_NVLINK_LINK_MASK, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
flags: int
|
|
bSysmem: int
|
|
peerLinkMask: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS.register_fields([('flags', NvU32, 0), ('bSysmem', NvBool, 4), ('peerLinkMask', NvU64, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bNvlinkSysmemEnabled: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS.register_fields([('bNvlinkSysmemEnabled', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
gpuInst: int
|
|
peerLinkMask: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS.register_fields([('gpuInst', NvU32, 0), ('peerLinkMask', NvU64, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
remoteDeviceType: int
|
|
remoteChipSid: int
|
|
linkId: int
|
|
laneRxdetStatusMask: int
|
|
remoteLinkNumber: int
|
|
remotePciDeviceId: int
|
|
remoteDomain: int
|
|
remoteBus: int
|
|
remoteDevice: int
|
|
remoteFunction: int
|
|
bConnected: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS.register_fields([('remoteDeviceType', NvU64, 0), ('remoteChipSid', NvU64, 8), ('linkId', NvU32, 16), ('laneRxdetStatusMask', NvU32, 20), ('remoteLinkNumber', NvU32, 24), ('remotePciDeviceId', NvU32, 28), ('remoteDomain', NvU32, 32), ('remoteBus', NvU8, 36), ('remoteDevice', NvU8, 37), ('remoteFunction', NvU8, 38), ('bConnected', NvBool, 39)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkMask: int
|
|
initializedLinks: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS.register_fields([('linkMask', NvU32, 0), ('initializedLinks', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkMask: int
|
|
bSync: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS.register_fields([('linkMask', NvU32, 0), ('bSync', NvBool, 4)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS(c.Struct):
|
|
SIZE = 264
|
|
postRxDetLinkMask: int
|
|
laneRxdetStatusMask: c.Array[ctypes.c_uint32, Literal[64]]
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS.register_fields([('postRxDetLinkMask', NvU64, 0), ('laneRxdetStatusMask', c.Array[NvU32, Literal[64]], 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
bSync: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS.register_fields([('linkMask', NvU32, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('bSync', NvBool, 24)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES(c.Struct):
|
|
SIZE = 16
|
|
bValid: int
|
|
linkId: int
|
|
ioctrlId: int
|
|
pllMasterLinkId: int
|
|
pllSlaveLinkId: int
|
|
ipVerDlPl: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES.register_fields([('bValid', NvBool, 0), ('linkId', NvU8, 1), ('ioctrlId', NvU32, 4), ('pllMasterLinkId', NvU8, 8), ('pllSlaveLinkId', NvU8, 9), ('ipVerDlPl', NvU32, 12)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS(c.Struct):
|
|
SIZE = 1088
|
|
ioctrlMask: int
|
|
ioctrlNumEntries: int
|
|
ioctrlSize: int
|
|
discoveredLinks: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
ipVerNvlink: int
|
|
maxSupportedLinks: int
|
|
probeRequestTimeMs: int
|
|
linkStateChangeTimeMs: int
|
|
linkInfo: c.Array[struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES, Literal[64]]
|
|
supportedCounterMask: struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
counterMask: c.Array[ctypes.c_uint64, Literal[2]]
|
|
NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS
|
|
struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS.register_fields([('counterMask', c.Array[NvU64, Literal[2]], 0)])
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS.register_fields([('ioctrlMask', NvU32, 0), ('ioctrlNumEntries', NvU8, 4), ('ioctrlSize', NvU32, 8), ('discoveredLinks', NV2080_CTRL_NVLINK_LINK_MASK, 16), ('ipVerNvlink', NvU32, 32), ('maxSupportedLinks', NvU32, 36), ('probeRequestTimeMs', NvU32, 40), ('linkStateChangeTimeMs', NvU32, 44), ('linkInfo', c.Array[NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES, Literal[64]], 48), ('supportedCounterMask', NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS, 1072)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES(c.Struct):
|
|
SIZE = 8
|
|
ipVerIoctrl: int
|
|
ipVerMinion: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES.register_fields([('ipVerIoctrl', NvU32, 0), ('ipVerMinion', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
ioctrlIdx: int
|
|
PublicId: int
|
|
localDiscoveredLinks: int
|
|
localGlobalLinkOffset: int
|
|
ioctrlDiscoverySize: int
|
|
numDevices: int
|
|
ipRevisions: struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS.register_fields([('ioctrlIdx', NvU32, 0), ('PublicId', NvU32, 4), ('localDiscoveredLinks', NvU32, 8), ('localGlobalLinkOffset', NvU32, 12), ('ioctrlDiscoverySize', NvU32, 16), ('numDevices', NvU8, 20), ('ipRevisions', NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES, 24)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
bPlatformLinerateDefined: int
|
|
platformLineRate: int
|
|
nvlinkLinkSpeed: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS.register_fields([('bPlatformLinerateDefined', NvBool, 0), ('platformLineRate', NvU32, 4), ('nvlinkLinkSpeed', NvU32, 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS(c.Struct):
|
|
SIZE = 88
|
|
linkMask: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
bActiveOnly: int
|
|
bIsLinkActive: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS.register_fields([('linkMask', NV2080_CTRL_NVLINK_LINK_MASK, 0), ('bActiveOnly', NvBool, 16), ('bIsLinkActive', c.Array[NvBool, Literal[64]], 17)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkMask: int
|
|
flags: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS.register_fields([('linkMask', NvU32, 0), ('flags', NvU32, 4)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
linkMask: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS.register_fields([('linkMask', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES(c.Struct):
|
|
SIZE = 60
|
|
bLinkConnectedToSystem: int
|
|
bLinkConnectedToPeer: int
|
|
bLinkReset: int
|
|
subLinkWidth: int
|
|
linkState: int
|
|
txSublinkState: int
|
|
rxSublinkState: int
|
|
bLaneReversal: int
|
|
nvlinkLinkClockKHz: int
|
|
nvlinkLineRateMbps: int
|
|
nvlinkLinkClockMhz: int
|
|
nvlinkLinkDataRateKiBps: int
|
|
nvlinkRefClkType: int
|
|
nvlinkReqLinkClockMhz: int
|
|
nvlinkMinL1Threshold: int
|
|
nvlinkMaxL1Threshold: int
|
|
nvlinkL1ThresholdUnits: int
|
|
nvlpwIdx: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES.register_fields([('bLinkConnectedToSystem', NvBool, 0), ('bLinkConnectedToPeer', NvBool, 1), ('bLinkReset', NvBool, 2), ('subLinkWidth', NvU8, 3), ('linkState', NvU32, 4), ('txSublinkState', NvU32, 8), ('rxSublinkState', NvU32, 12), ('bLaneReversal', NvBool, 16), ('nvlinkLinkClockKHz', NvU32, 20), ('nvlinkLineRateMbps', NvU32, 24), ('nvlinkLinkClockMhz', NvU32, 28), ('nvlinkLinkDataRateKiBps', NvU32, 32), ('nvlinkRefClkType', NvU8, 36), ('nvlinkReqLinkClockMhz', NvU32, 40), ('nvlinkMinL1Threshold', NvU32, 44), ('nvlinkMaxL1Threshold', NvU32, 48), ('nvlinkL1ThresholdUnits', NvU32, 52), ('nvlpwIdx', NvU32, 56)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS(c.Struct):
|
|
SIZE = 3880
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
enabledNvlpwMask: int
|
|
nvlinkRefClkSpeedKHz: int
|
|
bSublinkStateInst: int
|
|
linkInfo: c.Array[struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES, Literal[64]]
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS.register_fields([('linkMask', NvU64, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('enabledNvlpwMask', NvU64, 24), ('nvlinkRefClkSpeedKHz', NvU32, 32), ('bSublinkStateInst', NvBool, 36), ('linkInfo', c.Array[NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES, Literal[64]], 40)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
sysmemLinkMask: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS.register_fields([('sysmemLinkMask', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS(c.Struct):
|
|
SIZE = 264
|
|
bLegacyForcedConfig: int
|
|
bOverrideComputePeerMode: int
|
|
phase: int
|
|
linkConnection: c.Array[ctypes.c_uint32, Literal[64]]
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS.register_fields([('bLegacyForcedConfig', NvBool, 0), ('bOverrideComputePeerMode', NvBool, 1), ('phase', NvU32, 4), ('linkConnection', c.Array[NvU32, Literal[64]], 8)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bLaneShutdownOnUnload: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS.register_fields([('bLaneShutdownOnUnload', NvBool, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
notUsed: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS.register_fields([('notUsed', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
sysmemLinkMask: int
|
|
struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS.register_fields([('sysmemLinkMask', NvU32, 0)])
|
|
NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
PublicId: int
|
|
logBufferSize: int
|
|
logBufferAddr: int
|
|
struct_NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS.register_fields([('PublicId', NvU32, 0), ('logBufferSize', NvU64, 8), ('logBufferAddr', NvU64, 16)])
|
|
NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
hfrpPrivBase: c.Array[ctypes.c_uint32, Literal[5]]
|
|
hfrpIntrCtrlReg: c.Array[ctypes.c_uint32, Literal[5]]
|
|
struct_NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS.register_fields([('hfrpPrivBase', c.Array[NvU32, Literal[5]], 0), ('hfrpIntrCtrlReg', c.Array[NvU32, Literal[5]], 20)])
|
|
NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
opType: int
|
|
flags: int
|
|
ringBufferSize: int
|
|
ringBufferOffset: int
|
|
userdPa: int
|
|
userdVa: int
|
|
usermodeGpuVa: int
|
|
instBlkAddr: int
|
|
instBlkAperture: int
|
|
userdAperture: int
|
|
inputWorkSubmitToken: int
|
|
cmcWorkSubmitToken: int
|
|
cmcHandle: int
|
|
struct_NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS.register_fields([('opType', NvU32, 0), ('flags', NvU32, 4), ('ringBufferSize', NvU32, 8), ('ringBufferOffset', NvU64, 16), ('userdPa', NvU64, 24), ('userdVa', NvU64, 32), ('usermodeGpuVa', NvU64, 40), ('instBlkAddr', NvU64, 48), ('instBlkAperture', NvU8, 56), ('userdAperture', NvU8, 57), ('inputWorkSubmitToken', NvU32, 60), ('cmcWorkSubmitToken', NvU32, 64), ('cmcHandle', NvU32, 68)])
|
|
NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2(c.Struct):
|
|
SIZE = 2044
|
|
smIssueRateModifierListSize: int
|
|
smIssueRateModifierList: c.Array[struct_NVXXXX_CTRL_XXX_INFO, Literal[255]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2.register_fields([('smIssueRateModifierListSize', NvU32, 0), ('smIssueRateModifierList', c.Array[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2, Literal[255]], 4)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS(c.Struct):
|
|
SIZE = 16352
|
|
smIssueRateModifierV2: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS.register_fields([('smIssueRateModifierV2', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL(c.Struct):
|
|
SIZE = 2044
|
|
smIssueThrottleCtrlListSize: int
|
|
smIssueThrottleCtrlList: c.Array[struct_NVXXXX_CTRL_XXX_INFO, Literal[255]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL.register_fields([('smIssueThrottleCtrlListSize', NvU32, 0), ('smIssueThrottleCtrlList', c.Array[NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL, Literal[255]], 4)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS(c.Struct):
|
|
SIZE = 16352
|
|
smIssueThrottleCtrl: c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL, Literal[8]]
|
|
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS.register_fields([('smIssueThrottleCtrl', c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_THROTTLE_CTRL, Literal[8]], 0)])
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
memDescInfo: struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO
|
|
engDesc: int
|
|
bEngineFound: int
|
|
struct_NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS.register_fields([('memDescInfo', NV2080_CTRL_INTERNAL_MEMDESC_INFO, 0), ('engDesc', NvU32, 32), ('bEngineFound', NvBool, 36)])
|
|
NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEYS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS(c.Struct):
|
|
SIZE = 80024
|
|
params: struct_NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS
|
|
@c.record
|
|
class struct_NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS(c.Struct):
|
|
SIZE = 80024
|
|
gpuId: int
|
|
hTotal: int
|
|
vTotal: int
|
|
minRefreshRatex10000: int
|
|
maxRefreshRatex10000: int
|
|
numFractions: int
|
|
fractions: c.Array[struct_NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS_fraction, Literal[5000]]
|
|
NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS: TypeAlias = struct_NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS
|
|
@c.record
|
|
class struct_NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS_fraction(c.Struct):
|
|
SIZE = 16
|
|
numerator: int
|
|
denominator: int
|
|
struct_NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS_fraction.register_fields([('numerator', NvU64, 0), ('denominator', NvU64, 8)])
|
|
struct_NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS.register_fields([('gpuId', NvU32, 0), ('hTotal', NvU32, 4), ('vTotal', NvU32, 8), ('minRefreshRatex10000', NvU32, 12), ('maxRefreshRatex10000', NvU32, 16), ('numFractions', NvU32, 20), ('fractions', c.Array[struct_NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS_fraction, Literal[5000]], 24)])
|
|
struct_NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS.register_fields([('params', NV30F1_CTRL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS, 0)])
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
ucode: int
|
|
gfid: int
|
|
bEnabled: int
|
|
bClear: int
|
|
instrumentationType: int
|
|
struct_NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS.register_fields([('ucode', NvU32, 0), ('gfid', NvU32, 4), ('bEnabled', NvBool, 8), ('bClear', NvBool, 9), ('instrumentationType', NvU32, 12)])
|
|
NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
ucode: int
|
|
gfid: int
|
|
bEnabled: int
|
|
bClear: int
|
|
instrumentationType: int
|
|
struct_NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS.register_fields([('ucode', NvU32, 0), ('gfid', NvU32, 4), ('bEnabled', NvBool, 8), ('bClear', NvBool, 9), ('instrumentationType', NvU32, 12)])
|
|
NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS(c.Struct):
|
|
SIZE = 65560
|
|
ucode: int
|
|
gfid: int
|
|
offset: int
|
|
instrumentationType: int
|
|
data: c.Array[ctypes.c_ubyte, Literal[65536]]
|
|
dataSize: int
|
|
bComplete: int
|
|
struct_NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS.register_fields([('ucode', NvU32, 0), ('gfid', NvU32, 4), ('offset', NvU32, 8), ('instrumentationType', NvU32, 12), ('data', c.Array[NvU8, Literal[65536]], 16), ('dataSize', NvU32, 65552), ('bComplete', NvBool, 65556)])
|
|
NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
ctrlParamVal: int
|
|
struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS.register_fields([('ctrlParamVal', NvU32, 0)])
|
|
NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
responseVal: int
|
|
struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS.register_fields([('responseVal', NvU32, 0)])
|
|
NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
architecture: int
|
|
implementation: int
|
|
revision: int
|
|
subRevision: int
|
|
struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS.register_fields([('architecture', NvU32, 0), ('implementation', NvU32, 4), ('revision', NvU32, 8), ('subRevision', NvU8, 12)])
|
|
NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
engines: int
|
|
struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS.register_fields([('engines', NvU32, 0)])
|
|
NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
manufacturer: int
|
|
struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS.register_fields([('manufacturer', NvU32, 0)])
|
|
NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bOwnedByRm: int
|
|
struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS.register_fields([('bOwnedByRm', NvBool, 0)])
|
|
NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY(c.Struct):
|
|
SIZE = 8
|
|
nv2080EngineType: int
|
|
notificationIntrVector: int
|
|
struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY.register_fields([('nv2080EngineType', NvU32, 0), ('notificationIntrVector', NvU32, 4)])
|
|
NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY: TypeAlias = struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS(c.Struct):
|
|
SIZE = 2052
|
|
numEntries: int
|
|
entries: c.Array[struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY, Literal[256]]
|
|
struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS.register_fields([('numEntries', NvU32, 0), ('entries', c.Array[NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY, Literal[256]], 4)])
|
|
NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY(c.Struct):
|
|
SIZE = 16
|
|
nv2080IntrType: int
|
|
pmcIntrMask: int
|
|
intrVectorStall: int
|
|
intrVectorNonStall: int
|
|
struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY.register_fields([('nv2080IntrType', NvU32, 0), ('pmcIntrMask', NvU32, 4), ('intrVectorStall', NvU32, 8), ('intrVectorNonStall', NvU32, 12)])
|
|
NV2080_CTRL_MC_STATIC_INTR_ENTRY: TypeAlias = struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS(c.Struct):
|
|
SIZE = 516
|
|
numEntries: int
|
|
entries: c.Array[struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY, Literal[32]]
|
|
struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS.register_fields([('numEntries', NvU32, 0), ('entries', c.Array[NV2080_CTRL_MC_STATIC_INTR_ENTRY, Literal[32]], 4)])
|
|
NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS
|
|
enum_NV2080_INTR_CATEGORY: dict[int, str] = {(NV2080_INTR_CATEGORY_DEFAULT:=0): 'NV2080_INTR_CATEGORY_DEFAULT', (NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE:=1): 'NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE', (NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION:=2): 'NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION', (NV2080_INTR_CATEGORY_RUNLIST:=3): 'NV2080_INTR_CATEGORY_RUNLIST', (NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION:=4): 'NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION', (NV2080_INTR_CATEGORY_UVM_OWNED:=5): 'NV2080_INTR_CATEGORY_UVM_OWNED', (NV2080_INTR_CATEGORY_UVM_SHARED:=6): 'NV2080_INTR_CATEGORY_UVM_SHARED', (NV2080_INTR_CATEGORY_ENUM_COUNT:=7): 'NV2080_INTR_CATEGORY_ENUM_COUNT'}
|
|
NV2080_INTR_CATEGORY: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
subtreeMap: c.Array[struct_NV2080_INTR_CATEGORY_SUBTREE_MAP, Literal[7]]
|
|
struct_NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS.register_fields([('subtreeMap', c.Array[NV2080_INTR_CATEGORY_SUBTREE_MAP, Literal[7]], 0)])
|
|
NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
component: int
|
|
size: int
|
|
struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS.register_fields([('component', NvU32, 0), ('size', NvU32, 4)])
|
|
NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pBuffer: ctypes.c_void_p
|
|
component: int
|
|
size: int
|
|
struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS.register_fields([('pBuffer', NvP64, 0), ('component', NvU32, 8), ('size', NvU32, 12)])
|
|
NV2080_CTRL_NVD_GET_DUMP_PARAMS: TypeAlias = struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS(c.Struct):
|
|
SIZE = 32
|
|
userMinOffset: int
|
|
userMaxOffset: int
|
|
factoryMinOffset: int
|
|
factoryMaxOffset: int
|
|
lastActiveClock: int
|
|
lastActiveVolt: int
|
|
lastActivePoint: int
|
|
kappa: int
|
|
struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS.register_fields([('userMinOffset', NvS32, 0), ('userMaxOffset', NvS32, 4), ('factoryMinOffset', NvU32, 8), ('factoryMaxOffset', NvU32, 12), ('lastActiveClock', NvU32, 16), ('lastActiveVolt', NvU32, 20), ('lastActivePoint', NvU32, 24), ('kappa', NvU32, 28)])
|
|
NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS: TypeAlias = struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS
|
|
@c.record
|
|
class struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG(c.Struct):
|
|
SIZE = 72
|
|
pstateVer: int
|
|
gpcOverclock: struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS
|
|
mclkOverclock: struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS
|
|
bUserOverclocked: int
|
|
bFactoryOverclocked: int
|
|
struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG.register_fields([('pstateVer', NvU32, 0), ('gpcOverclock', NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS, 4), ('mclkOverclock', NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS, 36), ('bUserOverclocked', NvBool, 68), ('bFactoryOverclocked', NvBool, 69)])
|
|
NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG: TypeAlias = struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG
|
|
@c.record
|
|
class struct_NV2080_NOCAT_JOURNAL_GPU_STATE(c.Struct):
|
|
SIZE = 240
|
|
bValid: int
|
|
strap: int
|
|
deviceId: int
|
|
vendorId: int
|
|
subsystemVendor: int
|
|
subsystemId: int
|
|
revision: int
|
|
type: int
|
|
vbiosVersion: int
|
|
bOptimus: int
|
|
bMsHybrid: int
|
|
bFullPower: int
|
|
vbiosOemVersion: int
|
|
memoryType: int
|
|
tag: c.Array[ctypes.c_ubyte, Literal[65]]
|
|
vbiosProject: c.Array[ctypes.c_ubyte, Literal[65]]
|
|
bInFullchipReset: int
|
|
bInSecBusReset: int
|
|
bInGc6Reset: int
|
|
overclockCfg: struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG
|
|
struct_NV2080_NOCAT_JOURNAL_GPU_STATE.register_fields([('bValid', NvBool, 0), ('strap', NvU32, 4), ('deviceId', NvU16, 8), ('vendorId', NvU16, 10), ('subsystemVendor', NvU16, 12), ('subsystemId', NvU16, 14), ('revision', NvU16, 16), ('type', NvU16, 18), ('vbiosVersion', NvU32, 20), ('bOptimus', NvBool, 24), ('bMsHybrid', NvBool, 25), ('bFullPower', NvBool, 26), ('vbiosOemVersion', NvU32, 28), ('memoryType', NvU16, 32), ('tag', c.Array[NvU8, Literal[65]], 34), ('vbiosProject', c.Array[NvU8, Literal[65]], 99), ('bInFullchipReset', NvBool, 164), ('bInSecBusReset', NvBool, 165), ('bInGc6Reset', NvBool, 166), ('overclockCfg', NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG, 168)])
|
|
NV2080_NOCAT_JOURNAL_GPU_STATE: TypeAlias = struct_NV2080_NOCAT_JOURNAL_GPU_STATE
|
|
@c.record
|
|
class struct_NV2080_NOCAT_JOURNAL_ENTRY(c.Struct):
|
|
SIZE = 1272
|
|
recType: int
|
|
bugcheck: int
|
|
tdrBucketId: int
|
|
source: c.Array[ctypes.c_ubyte, Literal[65]]
|
|
subsystem: int
|
|
errorCode: int
|
|
diagBufferLen: int
|
|
diagBuffer: c.Array[ctypes.c_ubyte, Literal[1024]]
|
|
faultingEngine: c.Array[ctypes.c_ubyte, Literal[65]]
|
|
mmuFaultType: int
|
|
mmuErrorSrc: int
|
|
tdrReason: c.Array[ctypes.c_ubyte, Literal[65]]
|
|
struct_NV2080_NOCAT_JOURNAL_ENTRY.register_fields([('recType', NvU8, 0), ('bugcheck', NvU32, 4), ('tdrBucketId', NvU32, 8), ('source', c.Array[NvU8, Literal[65]], 12), ('subsystem', NvU32, 80), ('errorCode', NvU64, 88), ('diagBufferLen', NvU32, 96), ('diagBuffer', c.Array[NvU8, Literal[1024]], 100), ('faultingEngine', c.Array[NvU8, Literal[65]], 1124), ('mmuFaultType', NvU32, 1192), ('mmuErrorSrc', NvU32, 1196), ('tdrReason', c.Array[NvU8, Literal[65]], 1200)])
|
|
NV2080_NOCAT_JOURNAL_ENTRY: TypeAlias = struct_NV2080_NOCAT_JOURNAL_ENTRY
|
|
@c.record
|
|
class struct_NV2080_NOCAT_JOURNAL_RECORD(c.Struct):
|
|
SIZE = 1544
|
|
GPUTag: int
|
|
loadAddress: int
|
|
timeStamp: int
|
|
stateMask: int
|
|
nocatGpuState: struct_NV2080_NOCAT_JOURNAL_GPU_STATE
|
|
nocatJournalEntry: struct_NV2080_NOCAT_JOURNAL_ENTRY
|
|
struct_NV2080_NOCAT_JOURNAL_RECORD.register_fields([('GPUTag', NvU32, 0), ('loadAddress', NvU64, 8), ('timeStamp', NvU64, 16), ('stateMask', NvU64, 24), ('nocatGpuState', NV2080_NOCAT_JOURNAL_GPU_STATE, 32), ('nocatJournalEntry', NV2080_NOCAT_JOURNAL_ENTRY, 272)])
|
|
NV2080_NOCAT_JOURNAL_RECORD: TypeAlias = struct_NV2080_NOCAT_JOURNAL_RECORD
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS(c.Struct):
|
|
SIZE = 15656
|
|
flags: int
|
|
nocatRecordCount: int
|
|
nocatOutstandingRecordCount: int
|
|
journalRecords: c.Array[struct_NV2080_NOCAT_JOURNAL_RECORD, Literal[10]]
|
|
activityCounters: c.Array[ctypes.c_uint32, Literal[32]]
|
|
reserved: c.Array[ctypes.c_ubyte, Literal[65]]
|
|
struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS.register_fields([('flags', NvU32, 0), ('nocatRecordCount', NvU32, 4), ('nocatOutstandingRecordCount', NvU32, 8), ('journalRecords', c.Array[NV2080_NOCAT_JOURNAL_RECORD, Literal[10]], 16), ('activityCounters', c.Array[NvU32, Literal[32]], 15456), ('reserved', c.Array[NvU8, Literal[65]], 15584)])
|
|
NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS: TypeAlias = struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS
|
|
@c.record
|
|
class struct_NV2080CtrlNocatJournalDataTdrReason(c.Struct):
|
|
SIZE = 96
|
|
flags: int
|
|
source: c.Array[ctypes.c_ubyte, Literal[65]]
|
|
subsystem: int
|
|
errorCode: int
|
|
reasonCode: int
|
|
struct_NV2080CtrlNocatJournalDataTdrReason.register_fields([('flags', NvU32, 0), ('source', c.Array[NvU8, Literal[65]], 4), ('subsystem', NvU32, 72), ('errorCode', NvU64, 80), ('reasonCode', NvU32, 88)])
|
|
NV2080CtrlNocatJournalDataTdrReason: TypeAlias = struct_NV2080CtrlNocatJournalDataTdrReason
|
|
@c.record
|
|
class struct_NV2080CtrlNocatJournalSetTag(c.Struct):
|
|
SIZE = 72
|
|
flags: int
|
|
tag: c.Array[ctypes.c_ubyte, Literal[65]]
|
|
struct_NV2080CtrlNocatJournalSetTag.register_fields([('flags', NvU32, 0), ('tag', c.Array[NvU8, Literal[65]], 4)])
|
|
NV2080CtrlNocatJournalSetTag: TypeAlias = struct_NV2080CtrlNocatJournalSetTag
|
|
@c.record
|
|
class struct_NV2080CtrlNocatJournalRclog(c.Struct):
|
|
SIZE = 92
|
|
flags: int
|
|
rclogSize: int
|
|
rmGpuId: int
|
|
APIType: int
|
|
contextType: int
|
|
exceptType: int
|
|
processImageName: c.Array[ctypes.c_ubyte, Literal[65]]
|
|
struct_NV2080CtrlNocatJournalRclog.register_fields([('flags', NvU32, 0), ('rclogSize', NvU32, 4), ('rmGpuId', NvU32, 8), ('APIType', NvU32, 12), ('contextType', NvU32, 16), ('exceptType', NvU32, 20), ('processImageName', c.Array[NvU8, Literal[65]], 24)])
|
|
NV2080CtrlNocatJournalRclog: TypeAlias = struct_NV2080CtrlNocatJournalRclog
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS(c.Struct):
|
|
SIZE = 104
|
|
dataType: int
|
|
targetRecordType: int
|
|
nocatJournalData: struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData(c.Struct):
|
|
SIZE = 96
|
|
tdrReason: struct_NV2080CtrlNocatJournalDataTdrReason
|
|
tagData: struct_NV2080CtrlNocatJournalSetTag
|
|
rclog: struct_NV2080CtrlNocatJournalRclog
|
|
struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData.register_fields([('tdrReason', NV2080CtrlNocatJournalDataTdrReason, 0), ('tagData', NV2080CtrlNocatJournalSetTag, 0), ('rclog', NV2080CtrlNocatJournalRclog, 0)])
|
|
struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS.register_fields([('dataType', NvU32, 0), ('targetRecordType', NvU32, 4), ('nocatJournalData', struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData, 8)])
|
|
NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080CtrlNocatJournalInsertRecord(c.Struct):
|
|
SIZE = 1208
|
|
flags: int
|
|
timestamp: int
|
|
recType: int
|
|
bugcheck: int
|
|
source: c.Array[ctypes.c_char, Literal[65]]
|
|
subsystem: int
|
|
errorCode: int
|
|
faultingEngine: c.Array[ctypes.c_char, Literal[65]]
|
|
tdrReason: int
|
|
diagBufferLen: int
|
|
diagBuffer: c.Array[ctypes.c_ubyte, Literal[1024]]
|
|
struct_NV2080CtrlNocatJournalInsertRecord.register_fields([('flags', NvU32, 0), ('timestamp', NvU64, 8), ('recType', NvU8, 16), ('bugcheck', NvU32, 20), ('source', c.Array[ctypes.c_char, Literal[65]], 24), ('subsystem', NvU32, 92), ('errorCode', NvU64, 96), ('faultingEngine', c.Array[ctypes.c_char, Literal[65]], 104), ('tdrReason', NvU32, 172), ('diagBufferLen', NvU32, 176), ('diagBuffer', c.Array[NvU8, Literal[1024]], 180)])
|
|
NV2080CtrlNocatJournalInsertRecord: TypeAlias = struct_NV2080CtrlNocatJournalInsertRecord
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS(c.Struct):
|
|
SIZE = 1208
|
|
nocatJournalRecord: struct_NV2080CtrlNocatJournalInsertRecord
|
|
struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS.register_fields([('nocatJournalRecord', NV2080CtrlNocatJournalInsertRecord, 0)])
|
|
NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
capsTbl: int
|
|
lowestNvlinkVersion: int
|
|
highestNvlinkVersion: int
|
|
lowestNciVersion: int
|
|
highestNciVersion: int
|
|
discoveredLinkMask: int
|
|
enabledLinkMask: int
|
|
discoveredLinks: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
enabledLinks: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS.register_fields([('capsTbl', NvU32, 0), ('lowestNvlinkVersion', NvU8, 4), ('highestNvlinkVersion', NvU8, 5), ('lowestNciVersion', NvU8, 6), ('highestNciVersion', NvU8, 7), ('discoveredLinkMask', NvU32, 8), ('enabledLinkMask', NvU32, 12), ('discoveredLinks', NV2080_CTRL_NVLINK_LINK_MASK, 16), ('enabledLinks', NV2080_CTRL_NVLINK_LINK_MASK, 32)])
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_DEVICE_INFO(c.Struct):
|
|
SIZE = 56
|
|
deviceIdFlags: int
|
|
domain: int
|
|
bus: int
|
|
device: int
|
|
function: int
|
|
pciDeviceId: int
|
|
deviceType: int
|
|
deviceUUID: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
fabricRecoveryStatusMask: int
|
|
struct_NV2080_CTRL_NVLINK_DEVICE_INFO.register_fields([('deviceIdFlags', NvU32, 0), ('domain', NvU32, 4), ('bus', NvU16, 8), ('device', NvU16, 10), ('function', NvU16, 12), ('pciDeviceId', NvU32, 16), ('deviceType', NvU64, 24), ('deviceUUID', c.Array[NvU8, Literal[16]], 32), ('fabricRecoveryStatusMask', NvU32, 48)])
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO: TypeAlias = struct_NV2080_CTRL_NVLINK_DEVICE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO(c.Struct):
|
|
SIZE = 216
|
|
capsTbl: int
|
|
phyType: int
|
|
subLinkWidth: int
|
|
linkState: int
|
|
rxSublinkStatus: int
|
|
txSublinkStatus: int
|
|
bLaneReversal: int
|
|
nvlinkVersion: int
|
|
nciVersion: int
|
|
phyVersion: int
|
|
nvlinkLinkClockKHz: int
|
|
nvlinkCommonClockSpeedKHz: int
|
|
nvlinkRefClkSpeedKHz: int
|
|
nvlinkCommonClockSpeedMhz: int
|
|
nvlinkLineRateMbps: int
|
|
nvlinkLinkClockMhz: int
|
|
nvlinkRefClkType: int
|
|
nvlinkLinkDataRateKiBps: int
|
|
nvlinkRefClkSpeedMhz: int
|
|
connected: int
|
|
loopProperty: int
|
|
remoteDeviceLinkNumber: int
|
|
localDeviceLinkNumber: int
|
|
remoteLinkSid: int
|
|
localLinkSid: int
|
|
laneRxdetStatusMask: int
|
|
nvlinkMinL1Threshold: int
|
|
nvlinkMaxL1Threshold: int
|
|
nvlinkL1ThresholdUnits: int
|
|
remoteDeviceInfo: struct_NV2080_CTRL_NVLINK_DEVICE_INFO
|
|
localDeviceInfo: struct_NV2080_CTRL_NVLINK_DEVICE_INFO
|
|
nvlpwIdx: int
|
|
struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO.register_fields([('capsTbl', NvU32, 0), ('phyType', NvU8, 4), ('subLinkWidth', NvU8, 5), ('linkState', NvU32, 8), ('rxSublinkStatus', NvU8, 12), ('txSublinkStatus', NvU8, 13), ('bLaneReversal', NvBool, 14), ('nvlinkVersion', NvU8, 15), ('nciVersion', NvU8, 16), ('phyVersion', NvU8, 17), ('nvlinkLinkClockKHz', NvU32, 20), ('nvlinkCommonClockSpeedKHz', NvU32, 24), ('nvlinkRefClkSpeedKHz', NvU32, 28), ('nvlinkCommonClockSpeedMhz', NvU32, 32), ('nvlinkLineRateMbps', NvU32, 36), ('nvlinkLinkClockMhz', NvU32, 40), ('nvlinkRefClkType', NvU8, 44), ('nvlinkLinkDataRateKiBps', NvU32, 48), ('nvlinkRefClkSpeedMhz', NvU32, 52), ('connected', NvBool, 56), ('loopProperty', NvU8, 57), ('remoteDeviceLinkNumber', NvU8, 58), ('localDeviceLinkNumber', NvU8, 59), ('remoteLinkSid', NvU64, 64), ('localLinkSid', NvU64, 72), ('laneRxdetStatusMask', NvU32, 80), ('nvlinkMinL1Threshold', NvU32, 84), ('nvlinkMaxL1Threshold', NvU32, 88), ('nvlinkL1ThresholdUnits', NvU32, 92), ('remoteDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO, 96), ('localDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO, 152), ('nvlpwIdx', NvU32, 208)])
|
|
NV2080_CTRL_NVLINK_LINK_STATUS_INFO: TypeAlias = struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO
|
|
enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT: dict[int, str] = {(NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US:=0): 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US', (NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US:=1): 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US'}
|
|
NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS(c.Struct):
|
|
SIZE = 13864
|
|
enabledLinkMask: int
|
|
enabledLinks: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
bSublinkStateInst: int
|
|
bNvleModeEnabled: int
|
|
linkInfo: c.Array[struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO, Literal[64]]
|
|
enabledNvlpwMask: int
|
|
struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS.register_fields([('enabledLinkMask', NvU32, 0), ('enabledLinks', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('bSublinkStateInst', NvBool, 24), ('bNvleModeEnabled', NvBool, 25), ('linkInfo', c.Array[NV2080_CTRL_NVLINK_LINK_STATUS_INFO, Literal[64]], 32), ('enabledNvlpwMask', NvU64, 13856)])
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_ERR_INFO(c.Struct):
|
|
SIZE = 112
|
|
TLErrlog: int
|
|
TLIntrEn: int
|
|
TLCTxErrStatus0: int
|
|
TLCTxErrStatus1: int
|
|
TLCTxSysErrStatus0: int
|
|
TLCRxErrStatus0: int
|
|
TLCRxErrStatus1: int
|
|
TLCRxSysErrStatus0: int
|
|
TLCTxErrLogEn0: int
|
|
TLCTxErrLogEn1: int
|
|
TLCTxSysErrLogEn0: int
|
|
TLCRxErrLogEn0: int
|
|
TLCRxErrLogEn1: int
|
|
TLCRxSysErrLogEn0: int
|
|
MIFTxErrStatus0: int
|
|
MIFRxErrStatus0: int
|
|
NVLIPTLnkErrStatus0: int
|
|
NVLIPTLnkErrLogEn0: int
|
|
NVLIPTLnkCtrlLinkStateRequest: int
|
|
DLSpeedStatusTx: int
|
|
DLSpeedStatusRx: int
|
|
NVLDLRxSlsmErrCntl: int
|
|
NVLDLTopLinkState: int
|
|
NVLDLTopIntr: int
|
|
DLStatMN00: int
|
|
DLStatUC01: int
|
|
MinionNvlinkLinkIntr: int
|
|
bExcessErrorDL: int
|
|
struct_NV2080_CTRL_NVLINK_ERR_INFO.register_fields([('TLErrlog', NvU32, 0), ('TLIntrEn', NvU32, 4), ('TLCTxErrStatus0', NvU32, 8), ('TLCTxErrStatus1', NvU32, 12), ('TLCTxSysErrStatus0', NvU32, 16), ('TLCRxErrStatus0', NvU32, 20), ('TLCRxErrStatus1', NvU32, 24), ('TLCRxSysErrStatus0', NvU32, 28), ('TLCTxErrLogEn0', NvU32, 32), ('TLCTxErrLogEn1', NvU32, 36), ('TLCTxSysErrLogEn0', NvU32, 40), ('TLCRxErrLogEn0', NvU32, 44), ('TLCRxErrLogEn1', NvU32, 48), ('TLCRxSysErrLogEn0', NvU32, 52), ('MIFTxErrStatus0', NvU32, 56), ('MIFRxErrStatus0', NvU32, 60), ('NVLIPTLnkErrStatus0', NvU32, 64), ('NVLIPTLnkErrLogEn0', NvU32, 68), ('NVLIPTLnkCtrlLinkStateRequest', NvU32, 72), ('DLSpeedStatusTx', NvU32, 76), ('DLSpeedStatusRx', NvU32, 80), ('NVLDLRxSlsmErrCntl', NvU32, 84), ('NVLDLTopLinkState', NvU32, 88), ('NVLDLTopIntr', NvU32, 92), ('DLStatMN00', NvU32, 96), ('DLStatUC01', NvU32, 100), ('MinionNvlinkLinkIntr', NvU32, 104), ('bExcessErrorDL', NvBool, 108)])
|
|
NV2080_CTRL_NVLINK_ERR_INFO: TypeAlias = struct_NV2080_CTRL_NVLINK_ERR_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO(c.Struct):
|
|
SIZE = 8
|
|
NVLIPTErrStatus0: int
|
|
NVLIPTErrLogEn0: int
|
|
struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO.register_fields([('NVLIPTErrStatus0', NvU32, 0), ('NVLIPTErrLogEn0', NvU32, 4)])
|
|
NV2080_CTRL_NVLINK_COMMON_ERR_INFO: TypeAlias = struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS(c.Struct):
|
|
SIZE = 7224
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
linkErrInfo: c.Array[struct_NV2080_CTRL_NVLINK_ERR_INFO, Literal[64]]
|
|
ioctrlMask: int
|
|
commonErrInfo: c.Array[struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO, Literal[3]]
|
|
ErrInfoFlags: int
|
|
struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS.register_fields([('linkMask', NvU32, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('linkErrInfo', c.Array[NV2080_CTRL_NVLINK_ERR_INFO, Literal[64]], 24), ('ioctrlMask', NvU32, 7192), ('commonErrInfo', c.Array[NV2080_CTRL_NVLINK_COMMON_ERR_INFO, Literal[3]], 7196), ('ErrInfoFlags', NvU8, 7220)])
|
|
NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES(c.Struct):
|
|
SIZE = 264
|
|
bTx0TlCounterOverflow: int
|
|
bTx1TlCounterOverflow: int
|
|
bRx0TlCounterOverflow: int
|
|
bRx1TlCounterOverflow: int
|
|
value: c.Array[ctypes.c_uint64, Literal[32]]
|
|
struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES.register_fields([('bTx0TlCounterOverflow', NvBool, 0), ('bTx1TlCounterOverflow', NvBool, 1), ('bRx0TlCounterOverflow', NvBool, 2), ('bRx1TlCounterOverflow', NvBool, 3), ('value', c.Array[NvU64, Literal[32]], 8)])
|
|
NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 16928
|
|
counterMask: int
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
counters: c.Array[struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES, Literal[64]]
|
|
struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS.register_fields([('counterMask', NvU32, 0), ('linkMask', NvU64, 8), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 16), ('counters', c.Array[NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES, Literal[64]], 32)])
|
|
NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
counterMask: int
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS.register_fields([('counterMask', NvU32, 0), ('linkMask', NvU64, 8), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 16)])
|
|
NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES(c.Struct):
|
|
SIZE = 16
|
|
overFlow: int
|
|
value: int
|
|
struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES.register_fields([('overFlow', NvBool, 0), ('value', NvU64, 8)])
|
|
NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES: TypeAlias = struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS(c.Struct):
|
|
SIZE = 28712
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
counterMask: c.Array[ctypes.c_uint64, Literal[2]]
|
|
counter: c.Array[c.Array[struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES, Literal[28]], Literal[64]]
|
|
struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS.register_fields([('linkMask', NvU64, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('counterMask', c.Array[NvU64, Literal[2]], 24), ('counter', c.Array[c.Array[NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES, Literal[28]], Literal[64]], 40)])
|
|
NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
counterMask: c.Array[ctypes.c_uint64, Literal[2]]
|
|
struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS.register_fields([('linkMask', NvU64, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('counterMask', c.Array[NvU64, Literal[2]], 24)])
|
|
NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
bFatalError: int
|
|
struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS.register_fields([('linkMask', NvU32, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('bFatalError', NvBool, 24)])
|
|
NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS
|
|
enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE: dict[int, str] = {(NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR:=1): 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR', (NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR:=2): 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR', (NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR:=3): 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR', (NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR:=4): 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR', (NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX:=5): 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX'}
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG(c.Struct):
|
|
SIZE = 16
|
|
errType: int
|
|
errSettings: int
|
|
struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG.register_fields([('errType', NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE, 0), ('errSettings', NvU64, 8)])
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG: TypeAlias = struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS(c.Struct):
|
|
SIZE = 1048
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
errCfg: c.Array[struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG, Literal[64]]
|
|
struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS.register_fields([('linkMask', NvU64, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('errCfg', c.Array[NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG, Literal[64]], 24)])
|
|
NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO(c.Struct):
|
|
SIZE = 20
|
|
txErrInfo: int
|
|
packetErrInfo: int
|
|
authErrInfo: int
|
|
linkStatus: int
|
|
errInjectStatus: int
|
|
struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO.register_fields([('txErrInfo', NvU32, 0), ('packetErrInfo', NvU32, 4), ('authErrInfo', NvU32, 8), ('linkStatus', NvU32, 12), ('errInjectStatus', NvU32, 16)])
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO: TypeAlias = struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS(c.Struct):
|
|
SIZE = 1304
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
errInfo: c.Array[struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO, Literal[64]]
|
|
struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS.register_fields([('linkMask', NvU64, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('errInfo', c.Array[NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO, Literal[64]], 24)])
|
|
NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS(c.Struct):
|
|
SIZE = 280
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
numRecoveries: c.Array[ctypes.c_uint32, Literal[64]]
|
|
struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS.register_fields([('linkMask', NvU32, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('numRecoveries', c.Array[NvU32, Literal[64]], 24)])
|
|
NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkId: int
|
|
remoteType: int
|
|
struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS.register_fields([('linkId', NvU32, 0), ('remoteType', NvU32, 4)])
|
|
NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
linkId: int
|
|
supportedCounts: int
|
|
fatalErrorCounts: c.Array[ctypes.c_ubyte, Literal[63]]
|
|
struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS.register_fields([('linkId', NvU32, 0), ('supportedCounts', NvU64, 8), ('fatalErrorCounts', c.Array[NvU8, Literal[63]], 16)])
|
|
NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE(c.Struct):
|
|
SIZE = 8
|
|
errorsPerMinute: int
|
|
timestamp: int
|
|
struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE.register_fields([('errorsPerMinute', NvU32, 0), ('timestamp', NvU32, 4)])
|
|
NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE: TypeAlias = struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS(c.Struct):
|
|
SIZE = 92
|
|
linkId: int
|
|
numDailyMaxNonfatalErrorRates: int
|
|
dailyMaxNonfatalErrorRates: c.Array[struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE, Literal[5]]
|
|
numMonthlyMaxNonfatalErrorRates: int
|
|
monthlyMaxNonfatalErrorRates: c.Array[struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE, Literal[5]]
|
|
struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS.register_fields([('linkId', NvU32, 0), ('numDailyMaxNonfatalErrorRates', NvU32, 4), ('dailyMaxNonfatalErrorRates', c.Array[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE, Literal[5]], 8), ('numMonthlyMaxNonfatalErrorRates', NvU32, 48), ('monthlyMaxNonfatalErrorRates', c.Array[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE, Literal[5]], 52)])
|
|
NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnabled: int
|
|
struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS.register_fields([('bEnabled', NvBool, 0)])
|
|
NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkId: int
|
|
params: int
|
|
struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS.register_fields([('linkId', NvU8, 0), ('params', NvU32, 4)])
|
|
NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
powerState: int
|
|
struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS.register_fields([('linkMask', NvU32, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('powerState', NvU32, 24)])
|
|
NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkId: int
|
|
powerState: int
|
|
struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS.register_fields([('linkId', NvU32, 0), ('powerState', NvU32, 4)])
|
|
NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS
|
|
enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE: dict[int, str] = {(TLC_RX_LNK:=0): 'TLC_RX_LNK', (TLC_TX_SYS:=1): 'TLC_TX_SYS'}
|
|
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE: TypeAlias = ctypes.c_uint32
|
|
enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE: dict[int, str] = {(TX_SYS_TX_RSP_STATUS_HW_ERR:=0): 'TX_SYS_TX_RSP_STATUS_HW_ERR', (TX_SYS_TX_RSP_STATUS_UR_ERR:=1): 'TX_SYS_TX_RSP_STATUS_UR_ERR', (TX_SYS_TX_RSP_STATUS_PRIV_ERR:=2): 'TX_SYS_TX_RSP_STATUS_PRIV_ERR'}
|
|
NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE: TypeAlias = ctypes.c_uint32
|
|
enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE: dict[int, str] = {(RX_LNK_RX_RSP_STATUS_HW_ERR:=0): 'RX_LNK_RX_RSP_STATUS_HW_ERR', (RX_LNK_RX_RSP_STATUS_UR_ERR:=1): 'RX_LNK_RX_RSP_STATUS_UR_ERR', (RX_LNK_RX_RSP_STATUS_PRIV_ERR:=2): 'RX_LNK_RX_RSP_STATUS_PRIV_ERR'}
|
|
NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE(c.Struct):
|
|
SIZE = 4
|
|
txSysErrorType: int
|
|
rxLnkErrorType: int
|
|
union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE.register_fields([('txSysErrorType', NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE, 0), ('rxLnkErrorType', NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE, 0)])
|
|
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE: TypeAlias = union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
linkId: int
|
|
device: int
|
|
bBroadcast: int
|
|
errorType: union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE
|
|
struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS.register_fields([('linkId', NvU32, 0), ('device', NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE, 4), ('bBroadcast', NvBool, 8), ('errorType', NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE, 12)])
|
|
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
linkId: int
|
|
numLanes: int
|
|
figureOfMeritValues: c.Array[ctypes.c_uint16, Literal[4]]
|
|
struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS.register_fields([('linkId', NvU32, 0), ('numLanes', NvU8, 4), ('figureOfMeritValues', c.Array[NvU16, Literal[4]], 6)])
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
peerMask: int
|
|
bEnable: int
|
|
struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS.register_fields([('peerMask', NvU32, 0), ('bEnable', NvBool, 4)])
|
|
NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkId: int
|
|
lane: int
|
|
addr: int
|
|
phyConfigData: int
|
|
struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS.register_fields([('linkId', NvU8, 0), ('lane', NvU8, 1), ('addr', NvU16, 2), ('phyConfigData', NvU32, 4)])
|
|
NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_LANE_ERROR(c.Struct):
|
|
SIZE = 12
|
|
bValid: int
|
|
eccErrorValue: int
|
|
overflowed: int
|
|
struct_NV2080_CTRL_NVLINK_LANE_ERROR.register_fields([('bValid', NvBool, 0), ('eccErrorValue', NvU32, 4), ('overflowed', NvBool, 8)])
|
|
NV2080_CTRL_NVLINK_LANE_ERROR: TypeAlias = struct_NV2080_CTRL_NVLINK_LANE_ERROR
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR(c.Struct):
|
|
SIZE = 56
|
|
errorLane: c.Array[struct_NV2080_CTRL_NVLINK_LANE_ERROR, Literal[4]]
|
|
eccDecFailed: int
|
|
eccDecFailedOverflowed: int
|
|
struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR.register_fields([('errorLane', c.Array[NV2080_CTRL_NVLINK_LANE_ERROR, Literal[4]], 0), ('eccDecFailed', NvU32, 48), ('eccDecFailedOverflowed', NvBool, 52)])
|
|
NV2080_CTRL_NVLINK_LINK_ECC_ERROR: TypeAlias = struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS(c.Struct):
|
|
SIZE = 3608
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
errorLink: c.Array[struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR, Literal[64]]
|
|
struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS.register_fields([('linkMask', NvU32, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('errorLink', c.Array[NV2080_CTRL_NVLINK_LINK_ECC_ERROR, Literal[64]], 24)])
|
|
NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES(c.Struct):
|
|
SIZE = 32
|
|
value: c.Array[ctypes.c_uint64, Literal[4]]
|
|
struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES.register_fields([('value', c.Array[NvU64, Literal[4]], 0)])
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES: TypeAlias = struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 2080
|
|
counterMask: int
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
counters: c.Array[struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES, Literal[64]]
|
|
struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS.register_fields([('counterMask', NvU16, 0), ('linkMask', NvU64, 8), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 16), ('counters', c.Array[NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES, Literal[64]], 32)])
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bLockPowerMode: int
|
|
struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS.register_fields([('bLockPowerMode', NvBool, 0)])
|
|
NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
linkId: int
|
|
counterValidMask: int
|
|
counterValues: c.Array[ctypes.c_uint32, Literal[16]]
|
|
struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS.register_fields([('linkId', NvU32, 0), ('counterValidMask', NvU32, 4), ('counterValues', c.Array[NvU32, Literal[16]], 8)])
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkId: int
|
|
loopbackMode: int
|
|
struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS.register_fields([('linkId', NvU32, 0), ('loopbackMode', NvU8, 4)])
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO(c.Struct):
|
|
SIZE = 6
|
|
bValid: int
|
|
passCount: int
|
|
failCount: int
|
|
struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO.register_fields([('bValid', NvBool, 0), ('passCount', NvU16, 2), ('failCount', NvU16, 4)])
|
|
NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO: TypeAlias = struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 216
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
refreshCount: c.Array[struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO, Literal[32]]
|
|
struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS.register_fields([('linkMask', NvU32, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('refreshCount', c.Array[NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO, Literal[32]], 24)])
|
|
NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS.register_fields([('linkMask', NvU32, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8)])
|
|
NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
bGet: int
|
|
addr: int
|
|
struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS.register_fields([('bGet', NvBool, 0), ('addr', NvU64, 8)])
|
|
NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS(c.Struct):
|
|
SIZE = 176
|
|
discoveredLinks: int
|
|
discoveredLinkMasks: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
connectedLinksMask: int
|
|
connectedLinks: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
bridgeSensableLinks: int
|
|
bridgeSensableLinkMasks: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
bridgedLinks: int
|
|
bridgedLinkMasks: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
initDisabledLinksMask: int
|
|
initDisabledLinks: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
vbiosDisabledLinkMask: int
|
|
vbiosDisabledLinks: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
initializedLinks: int
|
|
initializedLinkMasks: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
bEnableTrainingAtLoad: int
|
|
bEnableSafeModeAtLoad: int
|
|
struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS.register_fields([('discoveredLinks', NvU64, 0), ('discoveredLinkMasks', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('connectedLinksMask', NvU32, 24), ('connectedLinks', NV2080_CTRL_NVLINK_LINK_MASK, 32), ('bridgeSensableLinks', NvU64, 48), ('bridgeSensableLinkMasks', NV2080_CTRL_NVLINK_LINK_MASK, 56), ('bridgedLinks', NvU32, 72), ('bridgedLinkMasks', NV2080_CTRL_NVLINK_LINK_MASK, 80), ('initDisabledLinksMask', NvU32, 96), ('initDisabledLinks', NV2080_CTRL_NVLINK_LINK_MASK, 104), ('vbiosDisabledLinkMask', NvU64, 120), ('vbiosDisabledLinks', NV2080_CTRL_NVLINK_LINK_MASK, 128), ('initializedLinks', NvU32, 144), ('initializedLinkMasks', NV2080_CTRL_NVLINK_LINK_MASK, 152), ('bEnableTrainingAtLoad', NvBool, 168), ('bEnableSafeModeAtLoad', NvBool, 169)])
|
|
NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
initDisabledLinksMask: int
|
|
initDisabledLinks: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
bSkipHwNvlinkDisable: int
|
|
struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS.register_fields([('initDisabledLinksMask', NvU32, 0), ('initDisabledLinks', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('bSkipHwNvlinkDisable', NvBool, 24)])
|
|
NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS
|
|
enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND: dict[int, str] = {(NVLINK_EOM_CONTROL_START_EOM:=0): 'NVLINK_EOM_CONTROL_START_EOM', (NVLINK_EOM_CONTROL_END_EOM:=1): 'NVLINK_EOM_CONTROL_END_EOM', (NVLINK_EOM_CONTROL_CONFIG_EOM:=2): 'NVLINK_EOM_CONTROL_CONFIG_EOM', (NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE:=3): 'NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE'}
|
|
NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT(c.Struct):
|
|
SIZE = 4
|
|
upper: int
|
|
middle: int
|
|
lower: int
|
|
composite: int
|
|
struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT.register_fields([('upper', NvU8, 0), ('middle', NvU8, 1), ('lower', NvU8, 2), ('composite', NvU8, 3)])
|
|
NV2080_CTRL_NVLINK_EOM_MEASUREMENT: TypeAlias = struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
cmd: int
|
|
linkId: int
|
|
params: int
|
|
measurements: c.Array[struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT, Literal[4]]
|
|
struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS.register_fields([('cmd', NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND, 0), ('linkId', NvU32, 4), ('params', NvU32, 8), ('measurements', c.Array[NV2080_CTRL_NVLINK_EOM_MEASUREMENT, Literal[4]], 12)])
|
|
NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS(c.Struct):
|
|
SIZE = 5124
|
|
data: c.Array[ctypes.c_ubyte, Literal[5120]]
|
|
dataSize: int
|
|
struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS.register_fields([('data', c.Array[NvU8, Literal[5120]], 0), ('dataSize', NvU32, 5120)])
|
|
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
l1Threshold: int
|
|
l1ExitThreshold: int
|
|
struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS.register_fields([('l1Threshold', NvU32, 0), ('l1ExitThreshold', NvU32, 4)])
|
|
NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
l1Threshold: int
|
|
l1ExitThreshold: int
|
|
bL1Enabled: int
|
|
bL1ThermThrottlingEnabled: int
|
|
struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS.register_fields([('l1Threshold', NvU32, 0), ('l1ExitThreshold', NvU32, 4), ('bL1Enabled', NvBool, 8), ('bL1ThermThrottlingEnabled', NvBool, 9)])
|
|
NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS(c.Struct):
|
|
SIZE = 5124
|
|
buffer: c.Array[ctypes.c_ubyte, Literal[5120]]
|
|
dataSize: int
|
|
struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS.register_fields([('buffer', c.Array[NvU8, Literal[5120]], 0), ('dataSize', NvU32, 5120)])
|
|
NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkId: int
|
|
bIsGpuDegraded: int
|
|
struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS.register_fields([('linkId', NvU32, 0), ('bIsGpuDegraded', NvBool, 4)])
|
|
NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
bIsEnoughNvLink: int
|
|
numBridge: int
|
|
bridgePresenceMask: int
|
|
struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS.register_fields([('bIsEnoughNvLink', NvBool, 0), ('numBridge', NvU32, 4), ('bridgePresenceMask', NvU32, 8)])
|
|
NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
linkId: int
|
|
struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS.register_fields([('linkId', NvU32, 0)])
|
|
NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PORT_EVENT(c.Struct):
|
|
SIZE = 24
|
|
portEventType: int
|
|
gpuId: int
|
|
linkId: int
|
|
time: int
|
|
struct_NV2080_CTRL_NVLINK_PORT_EVENT.register_fields([('portEventType', NvU32, 0), ('gpuId', NvU32, 4), ('linkId', NvU32, 8), ('time', NvU64, 16)])
|
|
NV2080_CTRL_NVLINK_PORT_EVENT: TypeAlias = struct_NV2080_CTRL_NVLINK_PORT_EVENT
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS(c.Struct):
|
|
SIZE = 1560
|
|
portEventIndex: int
|
|
nextPortEventIndex: int
|
|
portEventCount: int
|
|
bOverflow: int
|
|
portEvent: c.Array[struct_NV2080_CTRL_NVLINK_PORT_EVENT, Literal[64]]
|
|
struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS.register_fields([('portEventIndex', NvU64, 0), ('nextPortEventIndex', NvU64, 8), ('portEventCount', NvU32, 16), ('bOverflow', NvBool, 20), ('portEvent', c.Array[NV2080_CTRL_NVLINK_PORT_EVENT, Literal[64]], 24)])
|
|
NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
linkId: int
|
|
struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS.register_fields([('linkId', NvU32, 0)])
|
|
NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bReducedNvlinkConfig: int
|
|
struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS.register_fields([('bReducedNvlinkConfig', NvBool, 0)])
|
|
NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_DATA(c.Struct):
|
|
SIZE = 496
|
|
data: c.Array[ctypes.c_ubyte, Literal[496]]
|
|
struct_NV2080_CTRL_NVLINK_PRM_DATA.register_fields([('data', c.Array[NvU8, Literal[496]], 0)])
|
|
NV2080_CTRL_NVLINK_PRM_DATA: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_DATA
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS(c.Struct):
|
|
SIZE = 39
|
|
ibGuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
rackGuid: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
chassisPhysicalSlotNumber: int
|
|
computeSlotIndex: int
|
|
nodeIndex: int
|
|
peerType: int
|
|
moduleId: int
|
|
nvlinkSignalingProtocol: int
|
|
linksPerSpigot: int
|
|
struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS.register_fields([('ibGuid', c.Array[NvU8, Literal[16]], 0), ('rackGuid', c.Array[NvU8, Literal[16]], 16), ('chassisPhysicalSlotNumber', NvU8, 32), ('computeSlotIndex', NvU8, 33), ('nodeIndex', NvU8, 34), ('peerType', NvU8, 35), ('moduleId', NvU8, 36), ('nvlinkSignalingProtocol', NvU8, 37), ('linksPerSpigot', NvU8, 38)])
|
|
NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD(c.Struct):
|
|
SIZE = 4
|
|
pllIndex: int
|
|
address: int
|
|
struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD.register_fields([('pllIndex', NvU8, 0), ('address', NvU16, 2)])
|
|
NV2080_CTRL_NVLINK_UPHY_CLN_CMD: TypeAlias = struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS(c.Struct):
|
|
SIZE = 536
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
uphyCmd: c.Array[struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD, Literal[64]]
|
|
data: c.Array[ctypes.c_uint32, Literal[64]]
|
|
struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS.register_fields([('linkMask', NvU32, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('uphyCmd', c.Array[NV2080_CTRL_NVLINK_UPHY_CLN_CMD, Literal[64]], 24), ('data', c.Array[NvU32, Literal[64]], 280)])
|
|
NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
rbmModesList: c.Array[ctypes.c_uint16, Literal[23]]
|
|
rbmTotalModes: int
|
|
struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS.register_fields([('rbmModesList', c.Array[NvU16, Literal[23]], 0), ('rbmTotalModes', NvU8, 46)])
|
|
NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
rbmMode: int
|
|
bForceSync: int
|
|
rbmSetPollTimeoutMs: int
|
|
struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS.register_fields([('rbmMode', NvU16, 0), ('bForceSync', NvBool, 2), ('rbmSetPollTimeoutMs', NvU32, 4)])
|
|
NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
rbmMode: int
|
|
struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS.register_fields([('rbmMode', NvU16, 0)])
|
|
NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
localDeviceInfo: struct_NV2080_CTRL_NVLINK_DEVICE_INFO
|
|
struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS.register_fields([('localDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO, 0)])
|
|
NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS
|
|
enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY: dict[int, str] = {(NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL:=0): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL:=1): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL:=2): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION:=3): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT:=4): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL:=5): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE:=6): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL:=7): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL:=8): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR:=9): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL:=10): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL:=11): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL:=12): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL:=13): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL:=14): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL:=15): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL:=16): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL:=17): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL:=18): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL:=19): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL:=20): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_FATAL:=21): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX:=22): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_MVB_NON_FATAL:=23): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_MVB_NON_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_MVB_FATAL:=24): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_MVB_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_MVB_NON_FATAL:=25): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_MVB_NON_FATAL', (NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_MVB_FATAL:=26): 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_MVB_FATAL'}
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
severity: int
|
|
struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS.register_fields([('linkMask', NvU32, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('severity', NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY, 24)])
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
localGpuAlid: int
|
|
localGpuClid: int
|
|
remoteGpuAlid: int
|
|
remoteGpuClid: int
|
|
bNvleQualMode: int
|
|
localGpuPlatformInfo: struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS
|
|
remoteGpuPlatformInfo: struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS
|
|
struct_NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS.register_fields([('localGpuAlid', NvU32, 0), ('localGpuClid', NvU32, 4), ('remoteGpuAlid', NvU32, 8), ('remoteGpuClid', NvU32, 12), ('bNvleQualMode', NvBool, 16), ('localGpuPlatformInfo', NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS, 17), ('remoteGpuPlatformInfo', NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS, 56)])
|
|
NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP(c.Struct):
|
|
SIZE = 8
|
|
alid: int
|
|
clid: int
|
|
struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP.register_fields([('alid', NvU32, 0), ('clid', NvU32, 4)])
|
|
NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP: TypeAlias = struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE(c.Struct):
|
|
SIZE = 260
|
|
alidClidMap: c.Array[struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP, Literal[32]]
|
|
numEntries: int
|
|
struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE.register_fields([('alidClidMap', c.Array[NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP, Literal[32]], 0), ('numEntries', NvU32, 256)])
|
|
NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE: TypeAlias = struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE_V2(c.Struct):
|
|
SIZE = 1028
|
|
alidClidMap: c.Array[struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP, Literal[128]]
|
|
numEntries: int
|
|
struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE_V2.register_fields([('alidClidMap', c.Array[NV2080_CTRL_NVLINK_NVLE_ALID_CLID_MAP, Literal[128]], 0), ('numEntries', NvU32, 1024)])
|
|
NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE_V2: TypeAlias = struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE_V2
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS(c.Struct):
|
|
SIZE = 276
|
|
bGet: int
|
|
alid: int
|
|
clid: int
|
|
alidClidTable: struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE
|
|
bClidUpdated: int
|
|
struct_NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS.register_fields([('bGet', NvBool, 0), ('alid', NvU32, 4), ('clid', NvU32, 8), ('alidClidTable', NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE, 12), ('bClidUpdated', NvBool, 272)])
|
|
NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS
|
|
enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE: dict[int, str] = {(NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED:=0): 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED', (NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE:=1): 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE', (NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED:=2): 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED', (NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED:=3): 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED', (NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE:=4): 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE'}
|
|
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG(c.Struct):
|
|
SIZE = 8
|
|
mode: int
|
|
toggleActiveTime: int
|
|
toggleInactiveTime: int
|
|
bTrigger: int
|
|
struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG.register_fields([('mode', NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE, 0), ('toggleActiveTime', NvU8, 4), ('toggleInactiveTime', NvU8, 5), ('bTrigger', NvBool, 6)])
|
|
NV2080_CTRL_NVLINK_L1_FORCE_CONFIG: TypeAlias = struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
config: struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG
|
|
struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS.register_fields([('linkMask', NvU32, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('config', NV2080_CTRL_NVLINK_L1_FORCE_CONFIG, 24)])
|
|
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS(c.Struct):
|
|
SIZE = 536
|
|
linkMask: int
|
|
links: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
config: c.Array[struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG, Literal[64]]
|
|
struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS.register_fields([('linkMask', NvU32, 0), ('links', NV2080_CTRL_NVLINK_LINK_MASK, 8), ('config', c.Array[NV2080_CTRL_NVLINK_L1_FORCE_CONFIG, Literal[64]], 24)])
|
|
NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bMmuNvlinkEncryptEn: int
|
|
bNvlinkTlwEncryptEn: int
|
|
struct_NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS.register_fields([('bMmuNvlinkEncryptEn', NvBool, 0), ('bNvlinkTlwEncryptEn', NvBool, 1)])
|
|
NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SEMANTIC_VERSION(c.Struct):
|
|
SIZE = 16
|
|
ucodeType: int
|
|
major: int
|
|
minor: int
|
|
subMinor: int
|
|
struct_NV2080_CTRL_NVLINK_SEMANTIC_VERSION.register_fields([('ucodeType', NvU8, 0), ('major', NvU32, 4), ('minor', NvU32, 8), ('subMinor', NvU32, 12)])
|
|
NV2080_CTRL_NVLINK_SEMANTIC_VERSION: TypeAlias = struct_NV2080_CTRL_NVLINK_SEMANTIC_VERSION
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS(c.Struct):
|
|
SIZE = 264
|
|
firmwareVersion: c.Array[struct_NV2080_CTRL_NVLINK_SEMANTIC_VERSION, Literal[16]]
|
|
chipTypeArch: int
|
|
numValidEntries: int
|
|
struct_NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS.register_fields([('firmwareVersion', c.Array[NV2080_CTRL_NVLINK_SEMANTIC_VERSION, Literal[16]], 0), ('chipTypeArch', NvU8, 256), ('numValidEntries', NvU32, 260)])
|
|
NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bIsNvleEnabled: int
|
|
struct_NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS.register_fields([('bIsNvleEnabled', NvBool, 0)])
|
|
NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 496
|
|
prm: struct_NV2080_CTRL_NVLINK_PRM_DATA
|
|
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS.register_fields([('prm', NV2080_CTRL_NVLINK_PRM_DATA, 0)])
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM(c.Struct):
|
|
SIZE = 36
|
|
data: c.Array[ctypes.c_ubyte, Literal[32]]
|
|
size: int
|
|
NvUFXP0_8: TypeAlias = ctypes.c_ubyte
|
|
struct_NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM.register_fields([('data', c.Array[NvUFXP0_8, Literal[32]], 0), ('size', NvU32, 32)])
|
|
NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM: TypeAlias = struct_NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PLR_TX_BW_LOSS_LOW_FREQUENCY(c.Struct):
|
|
SIZE = 12
|
|
lastPlrTxBwLossLf: int
|
|
meanPlrTxBwLossLf: int
|
|
maxPlrTxBwLossLf: int
|
|
consBelowPlrTxBwLossLfThreshold: int
|
|
numOfPlrTxBwLossLfWarnings: int
|
|
numOfPlrTxBwLossLfAlarms: int
|
|
struct_NV2080_CTRL_NVLINK_PLR_TX_BW_LOSS_LOW_FREQUENCY.register_fields([('lastPlrTxBwLossLf', NvU16, 0), ('meanPlrTxBwLossLf', NvU16, 2), ('maxPlrTxBwLossLf', NvU16, 4), ('consBelowPlrTxBwLossLfThreshold', NvU16, 6), ('numOfPlrTxBwLossLfWarnings', NvU16, 8), ('numOfPlrTxBwLossLfAlarms', NvU16, 10)])
|
|
NV2080_CTRL_NVLINK_PLR_TX_BW_LOSS_LOW_FREQUENCY: TypeAlias = struct_NV2080_CTRL_NVLINK_PLR_TX_BW_LOSS_LOW_FREQUENCY
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_RECOVERY_BW_LOSS_LOW_FREQUENCY(c.Struct):
|
|
SIZE = 12
|
|
lastRecoveryBwLossLf: int
|
|
meanRecoveryBwLossLf: int
|
|
maxRecoveryBwLossLf: int
|
|
consBelowRecoveryBwLossLfThreshold: int
|
|
numOfRecoveryBwLossLfWarnings: int
|
|
numOfRecoveryBwLossLfAlarms: int
|
|
struct_NV2080_CTRL_NVLINK_RECOVERY_BW_LOSS_LOW_FREQUENCY.register_fields([('lastRecoveryBwLossLf', NvU16, 0), ('meanRecoveryBwLossLf', NvU16, 2), ('maxRecoveryBwLossLf', NvU16, 4), ('consBelowRecoveryBwLossLfThreshold', NvU16, 6), ('numOfRecoveryBwLossLfWarnings', NvU16, 8), ('numOfRecoveryBwLossLfAlarms', NvU16, 10)])
|
|
NV2080_CTRL_NVLINK_RECOVERY_BW_LOSS_LOW_FREQUENCY: TypeAlias = struct_NV2080_CTRL_NVLINK_RECOVERY_BW_LOSS_LOW_FREQUENCY
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_EFFECTIVE_BER_LOW_FREQUENCY(c.Struct):
|
|
SIZE = 10
|
|
consBelowEffBerLfThreshold: int
|
|
numOfEffBerLfWarnings: int
|
|
numOfEffBerLfAlarms: int
|
|
meanEffBerLfMagnitude: int
|
|
lastEffBerLfMagnitude: int
|
|
maxEffBerLfMagnitude: int
|
|
maxEffBerLfCoef: int
|
|
struct_NV2080_CTRL_NVLINK_EFFECTIVE_BER_LOW_FREQUENCY.register_fields([('consBelowEffBerLfThreshold', NvU16, 0), ('numOfEffBerLfWarnings', NvU16, 2), ('numOfEffBerLfAlarms', NvU16, 4), ('meanEffBerLfMagnitude', NvU8, 6), ('lastEffBerLfMagnitude', NvU8, 7), ('maxEffBerLfMagnitude', NvU8, 8), ('maxEffBerLfCoef', NvU8, 9)])
|
|
NV2080_CTRL_NVLINK_EFFECTIVE_BER_LOW_FREQUENCY: TypeAlias = struct_NV2080_CTRL_NVLINK_EFFECTIVE_BER_LOW_FREQUENCY
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS(c.Struct):
|
|
SIZE = 84
|
|
linkId: int
|
|
globalMaxRawBERExp: int
|
|
globalMaxEffBERExp: int
|
|
linkDownCount: int
|
|
downReasonHistogram: struct_NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM
|
|
linkXidHistogram: struct_NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM
|
|
struct_NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS.register_fields([('linkId', NvU32, 0), ('globalMaxRawBERExp', NvU8, 4), ('globalMaxEffBERExp', NvU8, 5), ('linkDownCount', NvU32, 8), ('downReasonHistogram', NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM, 12), ('linkXidHistogram', NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM, 48)])
|
|
NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS(c.Struct):
|
|
SIZE = 60
|
|
linkId: int
|
|
initialRawBERExp: int
|
|
initialEffBERExp: int
|
|
lastDownReason: int
|
|
uptime: int
|
|
localMaxRawBERExp: int
|
|
localMaxEffBERExp: int
|
|
currEffBERMonitor: int
|
|
plrXmitRetryWithinTSecMaxLo: int
|
|
totalSuccessfulRecoveryEvents: int
|
|
plrTxBwLossLf: struct_NV2080_CTRL_NVLINK_PLR_TX_BW_LOSS_LOW_FREQUENCY
|
|
recoveryBwLossLf: struct_NV2080_CTRL_NVLINK_RECOVERY_BW_LOSS_LOW_FREQUENCY
|
|
effBerLf: struct_NV2080_CTRL_NVLINK_EFFECTIVE_BER_LOW_FREQUENCY
|
|
lastDownAdvancedReason: int
|
|
struct_NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS.register_fields([('linkId', NvU32, 0), ('initialRawBERExp', NvU8, 4), ('initialEffBERExp', NvU8, 5), ('lastDownReason', NvU8, 6), ('uptime', NvU32, 8), ('localMaxRawBERExp', NvU8, 12), ('localMaxEffBERExp', NvU8, 13), ('currEffBERMonitor', NvU16, 14), ('plrXmitRetryWithinTSecMaxLo', NvU32, 16), ('totalSuccessfulRecoveryEvents', NvU32, 20), ('plrTxBwLossLf', NV2080_CTRL_NVLINK_PLR_TX_BW_LOSS_LOW_FREQUENCY, 24), ('recoveryBwLossLf', NV2080_CTRL_NVLINK_RECOVERY_BW_LOSS_LOW_FREQUENCY, 36), ('effBerLf', NV2080_CTRL_NVLINK_EFFECTIVE_BER_LOW_FREQUENCY, 48), ('lastDownAdvancedReason', NvU16, 58)])
|
|
NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS(c.Struct):
|
|
SIZE = 496
|
|
MFDE: struct_NV2080_CTRL_NVLINK_PRM_DATA
|
|
struct_NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS.register_fields([('MFDE', NV2080_CTRL_NVLINK_PRM_DATA, 0)])
|
|
NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_NODE_HOSTNAME(c.Struct):
|
|
SIZE = 64
|
|
name: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
struct_NV2080_CTRL_NVLINK_NODE_HOSTNAME.register_fields([('name', c.Array[NvU8, Literal[64]], 0)])
|
|
NV2080_CTRL_NVLINK_NODE_HOSTNAME: TypeAlias = struct_NV2080_CTRL_NVLINK_NODE_HOSTNAME
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS(c.Struct):
|
|
SIZE = 64
|
|
hostname: struct_NV2080_CTRL_NVLINK_NODE_HOSTNAME
|
|
struct_NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS.register_fields([('hostname', NV2080_CTRL_NVLINK_NODE_HOSTNAME, 0)])
|
|
NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS(c.Struct):
|
|
SIZE = 64
|
|
hostname: struct_NV2080_CTRL_NVLINK_NODE_HOSTNAME
|
|
struct_NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS.register_fields([('hostname', NV2080_CTRL_NVLINK_NODE_HOSTNAME, 0)])
|
|
NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
clid: int
|
|
struct_NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS.register_fields([('clid', NvU32, 0)])
|
|
NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
linkMask: int
|
|
bRemapTableMseLocked: int
|
|
bRemapTableLockDisabled: int
|
|
struct_NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS.register_fields([('linkMask', NvU64, 0), ('bRemapTableMseLocked', NvBool, 8), ('bRemapTableLockDisabled', NvBool, 9)])
|
|
NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS(c.Struct):
|
|
SIZE = 260
|
|
flaRemapTabAddr: c.Array[ctypes.c_uint32, Literal[32]]
|
|
gpaRemapTabAddr: c.Array[ctypes.c_uint32, Literal[32]]
|
|
remapTabSize: int
|
|
struct_NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS.register_fields([('flaRemapTabAddr', c.Array[NvU32, Literal[32]], 0), ('gpaRemapTabAddr', c.Array[NvU32, Literal[32]], 128), ('remapTabSize', NvU32, 256)])
|
|
NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS(c.Struct):
|
|
SIZE = 32
|
|
txPipe0Cntr: int
|
|
txPipe1Cntr: int
|
|
rxPipe0Cntr: int
|
|
rxPipe1Cntr: int
|
|
struct_NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS.register_fields([('txPipe0Cntr', NvU64, 0), ('txPipe1Cntr', NvU64, 8), ('rxPipe0Cntr', NvU64, 16), ('rxPipe1Cntr', NvU64, 24)])
|
|
NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS: TypeAlias = struct_NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 2064
|
|
linkMask: struct_NV2080_CTRL_NVLINK_LINK_MASK
|
|
nvleCounters: c.Array[struct_NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS, Literal[64]]
|
|
struct_NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS.register_fields([('linkMask', NV2080_CTRL_NVLINK_LINK_MASK, 0), ('nvleCounters', c.Array[NV2080_CTRL_NVLINK_NVLE_PKT_CNTRS, Literal[64]], 16)])
|
|
NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS(c.Struct):
|
|
SIZE = 120
|
|
nvleKey: c.Array[ctypes.c_ubyte, Literal[32]]
|
|
localGpuAlid: int
|
|
remoteGpuAlid: int
|
|
localGpuPlatformInfo: struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS
|
|
remoteGpuPlatformInfo: struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS
|
|
struct_NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS.register_fields([('nvleKey', c.Array[NvU8, Literal[32]], 0), ('localGpuAlid', NvU32, 32), ('remoteGpuAlid', NvU32, 36), ('localGpuPlatformInfo', NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS, 40), ('remoteGpuPlatformInfo', NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS, 79)])
|
|
NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 1036
|
|
flaRemapTabAddr: c.Array[ctypes.c_uint32, Literal[128]]
|
|
gpaRemapTabAddr: c.Array[ctypes.c_uint32, Literal[128]]
|
|
remapTabSize: int
|
|
remapEntryStart: int
|
|
remapEntryEnd: int
|
|
struct_NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS.register_fields([('flaRemapTabAddr', c.Array[NvU32, Literal[128]], 0), ('gpaRemapTabAddr', c.Array[NvU32, Literal[128]], 512), ('remapTabSize', NvU32, 1024), ('remapEntryStart', NvU32, 1028), ('remapEntryEnd', NvU32, 1032)])
|
|
NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS(c.Struct):
|
|
SIZE = 1044
|
|
bGet: int
|
|
alid: int
|
|
clid: int
|
|
alidClidTable: struct_NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE_V2
|
|
bClidUpdated: int
|
|
struct_NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS.register_fields([('bGet', NvBool, 0), ('alid', NvU32, 4), ('clid', NvU32, 8), ('alidClidTable', NV2080_CTRL_NVLINK_NVLE_ALID_CLID_TABLE_V2, 12), ('bClidUpdated', NvBool, 1040)])
|
|
NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_BOOST_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
flags: int
|
|
duration: int
|
|
struct_NV2080_CTRL_PERF_BOOST_PARAMS.register_fields([('flags', NvU32, 0), ('duration', NvU32, 4)])
|
|
NV2080_CTRL_PERF_BOOST_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_BOOST_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bAcquire: int
|
|
struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS.register_fields([('bAcquire', NvBool, 0)])
|
|
NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
powerState: int
|
|
struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS.register_fields([('powerState', NvU32, 0)])
|
|
NV2080_CTRL_PERF_POWERSTATE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
powerStateInfo: struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS
|
|
struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS.register_fields([('powerStateInfo', NV2080_CTRL_PERF_POWERSTATE_PARAMS, 0)])
|
|
NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
powerState: int
|
|
struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS.register_fields([('powerState', NvU32, 0)])
|
|
NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS
|
|
enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT: dict[int, str] = {(NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM:=0): 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM', (NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342:=1): 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342', (NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL:=2): 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL', (NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS:=3): 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS', (NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE:=4): 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE', (NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS:=5): 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS'}
|
|
NV2080_CTRL_PERF_RATED_TDP_CLIENT: TypeAlias = ctypes.c_uint32
|
|
enum_NV2080_CTRL_PERF_RATED_TDP_ACTION: dict[int, str] = {(NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT:=0): 'NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT', (NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED:=1): 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED', (NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT:=2): 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT', (NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK:=3): 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK', (NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR:=4): 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR'}
|
|
NV2080_CTRL_PERF_RATED_TDP_ACTION: TypeAlias = ctypes.c_uint32
|
|
enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE: dict[int, str] = {(NV2080_CTRL_PERF_VPSTATE_RATED_TDP:=0): 'NV2080_CTRL_PERF_VPSTATE_RATED_TDP', (NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST:=1): 'NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST', (NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES:=2): 'NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES'}
|
|
NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST(c.Struct):
|
|
SIZE = 8
|
|
action: int
|
|
vPstateType: int
|
|
struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST.register_fields([('action', NV2080_CTRL_PERF_RATED_TDP_ACTION, 0), ('vPstateType', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE, 4)])
|
|
NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST: TypeAlias = struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
rm: struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm
|
|
output: int
|
|
outputVPstate: int
|
|
inputs: c.Array[ctypes.c_uint32, Literal[5]]
|
|
vPstateTypes: c.Array[ctypes.c_uint32, Literal[5]]
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm(c.Struct):
|
|
SIZE = 8
|
|
clientActiveMask: int
|
|
bRegkeyLimitRatedTdp: int
|
|
struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm.register_fields([('clientActiveMask', NvU32, 0), ('bRegkeyLimitRatedTdp', NvU8, 4)])
|
|
struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS.register_fields([('rm', struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm, 0), ('output', NV2080_CTRL_PERF_RATED_TDP_ACTION, 8), ('outputVPstate', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE, 12), ('inputs', c.Array[NV2080_CTRL_PERF_RATED_TDP_ACTION, Literal[5]], 16), ('vPstateTypes', c.Array[NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE, Literal[5]], 36)])
|
|
NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
client: int
|
|
input: int
|
|
vPstateType: int
|
|
struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS.register_fields([('client', NV2080_CTRL_PERF_RATED_TDP_CLIENT, 0), ('input', NV2080_CTRL_PERF_RATED_TDP_ACTION, 4), ('vPstateType', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE, 8)])
|
|
NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS
|
|
NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS
|
|
NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE(c.Struct):
|
|
SIZE = 128
|
|
util: int
|
|
vgpuScale: int
|
|
procId: int
|
|
subProcessID: int
|
|
subProcessName: c.Array[ctypes.c_char, Literal[100]]
|
|
pOsPidInfo: int
|
|
struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE.register_fields([('util', NvU32, 0), ('vgpuScale', NvU32, 4), ('procId', NvU32, 8), ('subProcessID', NvU32, 12), ('subProcessName', c.Array[ctypes.c_char, Literal[100]], 16), ('pOsPidInfo', NvU64, 120)])
|
|
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE: TypeAlias = struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE(c.Struct):
|
|
SIZE = 776
|
|
base: struct_NV2080_CTRL_GPUMON_SAMPLE
|
|
fb: struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE
|
|
gr: struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE
|
|
nvenc: struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE
|
|
nvdec: struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE
|
|
nvjpg: struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE
|
|
nvofa: struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE
|
|
struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE.register_fields([('base', NV2080_CTRL_GPUMON_SAMPLE, 0), ('fb', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE, 8), ('gr', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE, 136), ('nvenc', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE, 264), ('nvdec', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE, 392), ('nvjpg', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE, 520), ('nvofa', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE, 648)])
|
|
NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE: TypeAlias = struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE
|
|
NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM: TypeAlias = struct_NV2080_CTRL_GPUMON_SAMPLES
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS(c.Struct):
|
|
SIZE = 55888
|
|
type: int
|
|
bufSize: int
|
|
count: int
|
|
tracker: int
|
|
samples: c.Array[struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE, Literal[72]]
|
|
struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS.register_fields([('type', NvU8, 0), ('bufSize', NvU32, 4), ('count', NvU32, 8), ('tracker', NvU32, 12), ('samples', c.Array[NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE, Literal[72]], 16)])
|
|
NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
prevPstate: int
|
|
action: int
|
|
struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS.register_fields([('prevPstate', NvU32, 0), ('action', NvU32, 4)])
|
|
NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
bGpuIsIdle: int
|
|
bRestoreToMax: int
|
|
idleTimeUs: int
|
|
busyTimeUs: int
|
|
struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS.register_fields([('bGpuIsIdle', NvBool, 0), ('bRestoreToMax', NvBool, 1), ('idleTimeUs', NvU64, 8), ('busyTimeUs', NvU64, 16)])
|
|
NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_CLK_INFO(c.Struct):
|
|
SIZE = 24
|
|
flags: int
|
|
domain: int
|
|
currentFreq: int
|
|
defaultFreq: int
|
|
minFreq: int
|
|
maxFreq: int
|
|
struct_NV2080_CTRL_PERF_GET_CLK_INFO.register_fields([('flags', NvU32, 0), ('domain', NvU32, 4), ('currentFreq', NvU32, 8), ('defaultFreq', NvU32, 12), ('minFreq', NvU32, 16), ('maxFreq', NvU32, 20)])
|
|
NV2080_CTRL_PERF_GET_CLK_INFO: TypeAlias = struct_NV2080_CTRL_PERF_GET_CLK_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
level: int
|
|
flags: int
|
|
perfGetClkInfoList: ctypes.c_void_p
|
|
perfGetClkInfoListSize: int
|
|
struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS.register_fields([('level', NvU32, 0), ('flags', NvU32, 4), ('perfGetClkInfoList', NvP64, 8), ('perfGetClkInfoListSize', NvU32, 16)])
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 780
|
|
level: int
|
|
flags: int
|
|
perfGetClkInfoList: c.Array[struct_NV2080_CTRL_PERF_GET_CLK_INFO, Literal[32]]
|
|
perfGetClkInfoListSize: int
|
|
struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS.register_fields([('level', NvU32, 0), ('flags', NvU32, 4), ('perfGetClkInfoList', c.Array[NV2080_CTRL_PERF_GET_CLK_INFO, Literal[32]], 8), ('perfGetClkInfoListSize', NvU32, 776)])
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS
|
|
enum_NV2080_CTRL_CMD_PERF_VID_ENG: dict[int, str] = {(NV2080_CTRL_CMD_PERF_VID_ENG_NVENC:=1): 'NV2080_CTRL_CMD_PERF_VID_ENG_NVENC', (NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC:=2): 'NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC', (NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG:=3): 'NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG', (NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA:=4): 'NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA'}
|
|
NV2080_CTRL_CMD_PERF_VID_ENG: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
engineType: int
|
|
clkPercentBusy: int
|
|
samplingPeriodUs: int
|
|
struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS.register_fields([('engineType', NV2080_CTRL_CMD_PERF_VID_ENG, 0), ('clkPercentBusy', NvU32, 4), ('samplingPeriodUs', NvU32, 8)])
|
|
NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
powerStateInfo: struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS
|
|
struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS.register_fields([('powerStateInfo', NV2080_CTRL_PERF_POWERSTATE_PARAMS, 0)])
|
|
NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
videoEvent: int
|
|
struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS.register_fields([('videoEvent', NvU32, 0)])
|
|
NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS
|
|
NV2080_CTRL_PERF_PSTATES_ID: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
currPstate: int
|
|
struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS.register_fields([('currPstate', NvU32, 0)])
|
|
NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS
|
|
NV2080_CTRL_CLK_DOMAIN_TEGRA: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
clkDomain: int
|
|
clkPercentBusy: int
|
|
struct_NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS.register_fields([('clkDomain', NV2080_CTRL_CLK_DOMAIN_TEGRA, 0), ('clkPercentBusy', NvU32, 4)])
|
|
NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
moduleId: int
|
|
nvswitchSupport: int
|
|
struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS.register_fields([('moduleId', NvU32, 0), ('nvswitchSupport', NvU8, 4)])
|
|
NV2080_CTRL_PMGR_MODULE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS
|
|
enum_NV2080_CTRL_GC6_FLAVOR_ID: dict[int, str] = {(NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID:=0): 'NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID', (NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS:=1): 'NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS', (NV2080_CTRL_GC6_FLAVOR_ID_MAX:=4): 'NV2080_CTRL_GC6_FLAVOR_ID_MAX'}
|
|
NV2080_CTRL_GC6_FLAVOR_ID: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GC6_ENTRY_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
flavorId: int
|
|
stepMask: int
|
|
params: struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params
|
|
@c.record
|
|
class struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params(c.Struct):
|
|
SIZE = 3
|
|
bIsRTD3Transition: int
|
|
bIsRTD3CoreRailPowerCut: int
|
|
bSkipPstateSanity: int
|
|
struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params.register_fields([('bIsRTD3Transition', NvBool, 0), ('bIsRTD3CoreRailPowerCut', NvBool, 1), ('bSkipPstateSanity', NvBool, 2)])
|
|
struct_NV2080_CTRL_GC6_ENTRY_PARAMS.register_fields([('flavorId', NV2080_CTRL_GC6_FLAVOR_ID, 0), ('stepMask', NvU32, 4), ('params', struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params, 8)])
|
|
NV2080_CTRL_GC6_ENTRY_PARAMS: TypeAlias = struct_NV2080_CTRL_GC6_ENTRY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GC6_EXIT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
flavorId: int
|
|
params: struct_NV2080_CTRL_GC6_EXIT_PARAMS_params
|
|
@c.record
|
|
class struct_NV2080_CTRL_GC6_EXIT_PARAMS_params(c.Struct):
|
|
SIZE = 3
|
|
bIsGpuSelfWake: int
|
|
bIsRTD3Transition: int
|
|
bIsRTD3HotTransition: int
|
|
struct_NV2080_CTRL_GC6_EXIT_PARAMS_params.register_fields([('bIsGpuSelfWake', NvBool, 0), ('bIsRTD3Transition', NvBool, 1), ('bIsRTD3HotTransition', NvBool, 2)])
|
|
struct_NV2080_CTRL_GC6_EXIT_PARAMS.register_fields([('flavorId', NV2080_CTRL_GC6_FLAVOR_ID, 0), ('params', struct_NV2080_CTRL_GC6_EXIT_PARAMS_params, 4)])
|
|
NV2080_CTRL_GC6_EXIT_PARAMS: TypeAlias = struct_NV2080_CTRL_GC6_EXIT_PARAMS
|
|
enum_NV2080_CTRL_GC6_STEP_ID: dict[int, str] = {(NV2080_CTRL_GC6_STEP_ID_SR_ENTRY:=0): 'NV2080_CTRL_GC6_STEP_ID_SR_ENTRY', (NV2080_CTRL_GC6_STEP_ID_GPU_OFF:=1): 'NV2080_CTRL_GC6_STEP_ID_GPU_OFF', (NV2080_CTRL_GC6_STEP_ID_MAX:=2): 'NV2080_CTRL_GC6_STEP_ID_MAX'}
|
|
NV2080_CTRL_GC6_STEP_ID: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NV2080_CTRL_GC6_FLAVOR_INFO(c.Struct):
|
|
SIZE = 8
|
|
flavorId: int
|
|
stepMask: int
|
|
struct_NV2080_CTRL_GC6_FLAVOR_INFO.register_fields([('flavorId', NV2080_CTRL_GC6_FLAVOR_ID, 0), ('stepMask', NvU32, 4)])
|
|
NV2080_CTRL_GC6_FLAVOR_INFO: TypeAlias = struct_NV2080_CTRL_GC6_FLAVOR_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hChannel: int
|
|
virtAddress: int
|
|
bufferPtr: ctypes.c_void_p
|
|
bufferSize: int
|
|
struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS.register_fields([('hChannel', NvHandle, 0), ('virtAddress', NvU64, 8), ('bufferPtr', NvP64, 16), ('bufferSize', NvU32, 24)])
|
|
NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS: TypeAlias = struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
errorCount: int
|
|
struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS.register_fields([('errorCount', NvU32, 0)])
|
|
NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS: TypeAlias = struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS(c.Struct):
|
|
SIZE = 8200
|
|
whichBuffer: int
|
|
outputRecordSize: int
|
|
recordBuffer: c.Array[ctypes.c_ubyte, Literal[8192]]
|
|
struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS.register_fields([('whichBuffer', NvU32, 0), ('outputRecordSize', NvU32, 4), ('recordBuffer', c.Array[NvU8, Literal[8192]], 8)])
|
|
NV2080_CTRL_RC_GET_ERROR_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
watchdogStatusFlags: int
|
|
struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS.register_fields([('watchdogStatusFlags', NvU32, 0)])
|
|
NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rcEnable: int
|
|
struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS.register_fields([('rcEnable', NvU32, 0)])
|
|
NV2080_CTRL_CMD_RC_RECOVERY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS
|
|
NV2080_CTRL_SET_RC_RECOVERY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS
|
|
NV2080_CTRL_GET_RC_RECOVERY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
cmd: int
|
|
status: int
|
|
struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS.register_fields([('cmd', NvU32, 0), ('status', NvS32, 4)])
|
|
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_RC_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
rcMode: int
|
|
rcBreak: int
|
|
struct_NV2080_CTRL_CMD_RC_INFO_PARAMS.register_fields([('rcMode', NvU32, 0), ('rcBreak', NvU32, 4)])
|
|
NV2080_CTRL_CMD_RC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS
|
|
NV2080_CTRL_SET_RC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS
|
|
NV2080_CTRL_GET_RC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
channelTestInterval: int
|
|
thwapChannelMask: int
|
|
stompChannelMask: int
|
|
thwapRepeatMask: int
|
|
stompRepeatMask: int
|
|
allocFailMask: int
|
|
struct_NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS.register_fields([('channelTestInterval', NvU32, 0), ('thwapChannelMask', NvU32, 4), ('stompChannelMask', NvU32, 8), ('thwapRepeatMask', NvU32, 12), ('stompRepeatMask', NvU32, 16), ('allocFailMask', NvU32, 20)])
|
|
NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS
|
|
NV2080_CTRL_SET_RC_WATCHDOG_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS
|
|
NV2080_CTRL_GET_RC_WATCHDOG_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_WATCHDOG_INFO_PARAMS
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_CMD_CC_INIT(c.Struct):
|
|
SIZE = 1
|
|
cmdType: int
|
|
struct_RM_GSP_SPDM_CMD_CC_INIT.register_fields([('cmdType', NvU8, 0)])
|
|
RM_GSP_SPDM_CMD_CC_INIT: TypeAlias = struct_RM_GSP_SPDM_CMD_CC_INIT
|
|
PRM_GSP_SPDM_CMD_CC_INIT: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_CMD_CC_INIT]
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_CMD_CC_DEINIT(c.Struct):
|
|
SIZE = 1
|
|
cmdType: int
|
|
struct_RM_GSP_SPDM_CMD_CC_DEINIT.register_fields([('cmdType', NvU8, 0)])
|
|
RM_GSP_SPDM_CMD_CC_DEINIT: TypeAlias = struct_RM_GSP_SPDM_CMD_CC_DEINIT
|
|
PRM_GSP_SPDM_CMD_CC_DEINIT: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_CMD_CC_DEINIT]
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_CMD_CC_CTRL(c.Struct):
|
|
SIZE = 1
|
|
cmdType: int
|
|
struct_RM_GSP_SPDM_CMD_CC_CTRL.register_fields([('cmdType', NvU8, 0)])
|
|
RM_GSP_SPDM_CMD_CC_CTRL: TypeAlias = struct_RM_GSP_SPDM_CMD_CC_CTRL
|
|
PRM_GSP_SPDM_CMD_CC_CTRL: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_CMD_CC_CTRL]
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA(c.Struct):
|
|
SIZE = 68
|
|
cmdType: int
|
|
rsvd0: c.Array[ctypes.c_uint32, Literal[2]]
|
|
rsvd1: int
|
|
rsvd2: c.Array[ctypes.c_char, Literal[9]]
|
|
rsvd3: c.Array[ctypes.c_char, Literal[5]]
|
|
rsvd4: c.Array[ctypes.c_char, Literal[5]]
|
|
rsvd5: c.Array[ctypes.c_char, Literal[5]]
|
|
rsvd6: c.Array[ctypes.c_char, Literal[2]]
|
|
rsvd7: c.Array[ctypes.c_char, Literal[16]]
|
|
rsvd8: c.Array[ctypes.c_uint32, Literal[2]]
|
|
struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA.register_fields([('cmdType', NvU8, 0), ('rsvd0', c.Array[NvU32, Literal[2]], 4), ('rsvd1', NvU32, 12), ('rsvd2', c.Array[ctypes.c_char, Literal[9]], 16), ('rsvd3', c.Array[ctypes.c_char, Literal[5]], 25), ('rsvd4', c.Array[ctypes.c_char, Literal[5]], 30), ('rsvd5', c.Array[ctypes.c_char, Literal[5]], 35), ('rsvd6', c.Array[ctypes.c_char, Literal[2]], 40), ('rsvd7', c.Array[ctypes.c_char, Literal[16]], 42), ('rsvd8', c.Array[NvU32, Literal[2]], 60)])
|
|
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA: TypeAlias = struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA
|
|
PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA]
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL(c.Struct):
|
|
SIZE = 2
|
|
cmdType: int
|
|
bEnable: int
|
|
struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL.register_fields([('cmdType', NvU8, 0), ('bEnable', NvBool, 1)])
|
|
RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL: TypeAlias = struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL
|
|
PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL]
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST(c.Struct):
|
|
SIZE = 160
|
|
cmdType: int
|
|
isEnc: int
|
|
kmb: struct_CC_KMB
|
|
text: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
authTag: c.Array[ctypes.c_ubyte, Literal[16]]
|
|
@c.record
|
|
class struct_CC_KMB(c.Struct):
|
|
SIZE = 124
|
|
encryptBundle: struct_CC_AES_CRYPTOBUNDLE
|
|
hmacBundle: struct_CC_HMAC_CRYPTOBUNDLE
|
|
decryptBundle: struct_CC_AES_CRYPTOBUNDLE
|
|
bIsWorkLaunch: int
|
|
CC_KMB: TypeAlias = struct_CC_KMB
|
|
@c.record
|
|
class struct_CC_AES_CRYPTOBUNDLE(c.Struct):
|
|
SIZE = 56
|
|
iv: c.Array[ctypes.c_uint32, Literal[3]]
|
|
key: c.Array[ctypes.c_uint32, Literal[8]]
|
|
ivMask: c.Array[ctypes.c_uint32, Literal[3]]
|
|
CC_AES_CRYPTOBUNDLE: TypeAlias = struct_CC_AES_CRYPTOBUNDLE
|
|
struct_CC_AES_CRYPTOBUNDLE.register_fields([('iv', c.Array[NvU32, Literal[3]], 0), ('key', c.Array[NvU32, Literal[8]], 12), ('ivMask', c.Array[NvU32, Literal[3]], 44)])
|
|
@c.record
|
|
class struct_CC_HMAC_CRYPTOBUNDLE(c.Struct):
|
|
SIZE = 64
|
|
nonce: c.Array[ctypes.c_uint32, Literal[8]]
|
|
key: c.Array[ctypes.c_uint32, Literal[8]]
|
|
CC_HMAC_CRYPTOBUNDLE: TypeAlias = struct_CC_HMAC_CRYPTOBUNDLE
|
|
struct_CC_HMAC_CRYPTOBUNDLE.register_fields([('nonce', c.Array[NvU32, Literal[8]], 0), ('key', c.Array[NvU32, Literal[8]], 32)])
|
|
struct_CC_KMB.register_fields([('encryptBundle', CC_AES_CRYPTOBUNDLE, 0), ('hmacBundle', CC_HMAC_CRYPTOBUNDLE, 56), ('decryptBundle', CC_AES_CRYPTOBUNDLE, 56), ('bIsWorkLaunch', NvBool, 120)])
|
|
struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST.register_fields([('cmdType', NvU8, 0), ('isEnc', NvU8, 1), ('kmb', CC_KMB, 4), ('text', c.Array[NvU8, Literal[16]], 128), ('authTag', c.Array[NvU8, Literal[16]], 144)])
|
|
RM_GSP_SPDM_CMD_FIPS_SELFTEST: TypeAlias = struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST
|
|
PRM_GSP_SPDM_CMD_FIPS_SELFTEST: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST]
|
|
@c.record
|
|
class union_RM_GSP_SPDM_CMD(c.Struct):
|
|
SIZE = 160
|
|
cmdType: int
|
|
ccInit: struct_RM_GSP_SPDM_CMD_CC_INIT
|
|
ccDeinit: struct_RM_GSP_SPDM_CMD_CC_DEINIT
|
|
ccCtrl: struct_RM_GSP_SPDM_CMD_CC_CTRL
|
|
rmDataInitCmd: struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA
|
|
ccHeartbeatCtrl: struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL
|
|
ccFipsTest: struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST
|
|
union_RM_GSP_SPDM_CMD.register_fields([('cmdType', NvU8, 0), ('ccInit', RM_GSP_SPDM_CMD_CC_INIT, 0), ('ccDeinit', RM_GSP_SPDM_CMD_CC_DEINIT, 0), ('ccCtrl', RM_GSP_SPDM_CMD_CC_CTRL, 0), ('rmDataInitCmd', RM_GSP_SPDM_CMD_CC_INIT_RM_DATA, 0), ('ccHeartbeatCtrl', RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL, 0), ('ccFipsTest', RM_GSP_SPDM_CMD_FIPS_SELFTEST, 0)])
|
|
RM_GSP_SPDM_CMD: TypeAlias = union_RM_GSP_SPDM_CMD
|
|
PRM_GSP_SPDM_CMD: TypeAlias = c.POINTER[union_RM_GSP_SPDM_CMD]
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_MSG(c.Struct):
|
|
SIZE = 28
|
|
msgType: int
|
|
status: int
|
|
rsvd1: int
|
|
rsvd2: int
|
|
rsvd3: int
|
|
rsvd4: int
|
|
rsvd5: int
|
|
struct_RM_GSP_SPDM_MSG.register_fields([('msgType', NvU8, 0), ('status', NvU32, 4), ('rsvd1', NvU32, 8), ('rsvd2', NvU32, 12), ('rsvd3', NvU32, 16), ('rsvd4', NvU32, 20), ('rsvd5', NvU32, 24)])
|
|
RM_GSP_SPDM_MSG: TypeAlias = struct_RM_GSP_SPDM_MSG
|
|
PRM_GSP_SPDM_MSG: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_MSG]
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS(c.Struct):
|
|
SIZE = 192
|
|
index: int
|
|
cmd: union_RM_GSP_SPDM_CMD
|
|
msg: struct_RM_GSP_SPDM_MSG
|
|
struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS.register_fields([('index', NvU8, 0), ('cmd', RM_GSP_SPDM_CMD, 4), ('msg', RM_GSP_SPDM_MSG, 164)])
|
|
NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS(c.Struct):
|
|
SIZE = 9220
|
|
transcript: c.Array[ctypes.c_ubyte, Literal[9216]]
|
|
transcriptSize: int
|
|
struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS.register_fields([('transcript', c.Array[NvU8, Literal[9216]], 0), ('transcriptSize', NvU32, 9216)])
|
|
NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS(c.Struct):
|
|
SIZE = 4
|
|
availableTargets: int
|
|
struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS.register_fields([('availableTargets', NvU32, 0)])
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS: TypeAlias = struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS
|
|
@c.record
|
|
class struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS(c.Struct):
|
|
SIZE = 8
|
|
targetIndex: int
|
|
type: int
|
|
struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS.register_fields([('targetIndex', NvU32, 0), ('type', NvU32, 4)])
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS: TypeAlias = struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS
|
|
@c.record
|
|
class struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS(c.Struct):
|
|
SIZE = 8
|
|
providerIndex: int
|
|
type: int
|
|
struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS.register_fields([('providerIndex', NvU32, 0), ('type', NvU32, 4)])
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS: TypeAlias = struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS
|
|
@c.record
|
|
class struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS(c.Struct):
|
|
SIZE = 4
|
|
availableSensors: int
|
|
struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS.register_fields([('availableSensors', NvU32, 0)])
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS: TypeAlias = struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS
|
|
@c.record
|
|
class struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS(c.Struct):
|
|
SIZE = 8
|
|
sensorIndex: int
|
|
providerIndex: int
|
|
struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS.register_fields([('sensorIndex', NvU32, 0), ('providerIndex', NvU32, 4)])
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS: TypeAlias = struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS
|
|
@c.record
|
|
class struct_NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS(c.Struct):
|
|
SIZE = 8
|
|
sensorIndex: int
|
|
value: int
|
|
struct_NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS.register_fields([('sensorIndex', NvU32, 0), ('value', NvS32, 4)])
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS: TypeAlias = struct_NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS
|
|
@c.record
|
|
class struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS(c.Struct):
|
|
SIZE = 8
|
|
sensorIndex: int
|
|
targetIndex: int
|
|
struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS.register_fields([('sensorIndex', NvU32, 0), ('targetIndex', NvU32, 4)])
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS: TypeAlias = struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS
|
|
@c.record
|
|
class struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS(c.Struct):
|
|
SIZE = 12
|
|
sensorIndex: int
|
|
minimum: int
|
|
maximum: int
|
|
struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS.register_fields([('sensorIndex', NvU32, 0), ('minimum', NvS32, 4), ('maximum', NvS32, 8)])
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS: TypeAlias = struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS
|
|
@c.record
|
|
class union_NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS(c.Struct):
|
|
SIZE = 32
|
|
getInfoTargetsAvailable: struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS
|
|
getInfoTargetType: struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS
|
|
getInfoProviderType: struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS
|
|
getInfoSensorsAvailable: struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS
|
|
getInfoSensorProvider: struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS
|
|
getInfoSensorTarget: struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS
|
|
getInfoSensorReadingRange: struct_NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS
|
|
getStatusSensorReading: struct_NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS
|
|
space: c.Array[ctypes.c_uint32, Literal[8]]
|
|
union_NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS.register_fields([('getInfoTargetsAvailable', NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS, 0), ('getInfoTargetType', NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS, 0), ('getInfoProviderType', NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS, 0), ('getInfoSensorsAvailable', NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS, 0), ('getInfoSensorProvider', NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS, 0), ('getInfoSensorTarget', NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS, 0), ('getInfoSensorReadingRange', NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS, 0), ('getStatusSensorReading', NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS, 0), ('space', c.Array[NvU32, Literal[8]], 0)])
|
|
NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS: TypeAlias = union_NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS
|
|
@c.record
|
|
class struct_NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION(c.Struct):
|
|
SIZE = 44
|
|
result: int
|
|
executed: int
|
|
opcode: int
|
|
operands: union_NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS
|
|
struct_NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION.register_fields([('result', NvU32, 0), ('executed', NvU32, 4), ('opcode', NvU32, 8), ('operands', NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS, 12)])
|
|
NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION: TypeAlias = struct_NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION
|
|
@c.record
|
|
class struct_NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS(c.Struct):
|
|
SIZE = 1432
|
|
clientAPIVersion: int
|
|
clientAPIRevision: int
|
|
clientInstructionSizeOf: int
|
|
executeFlags: int
|
|
successfulInstructions: int
|
|
instructionListSize: int
|
|
instructionList: c.Array[struct_NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION, Literal[32]]
|
|
struct_NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS.register_fields([('clientAPIVersion', NvU32, 0), ('clientAPIRevision', NvU32, 4), ('clientInstructionSizeOf', NvU32, 8), ('executeFlags', NvU32, 12), ('successfulInstructions', NvU32, 16), ('instructionListSize', NvU32, 20), ('instructionList', c.Array[NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION, Literal[32]], 24)])
|
|
NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
time_nsec: int
|
|
flags: int
|
|
struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS.register_fields([('time_nsec', NvU64, 0), ('flags', NvU32, 8)])
|
|
NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
time_nsec: int
|
|
struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS.register_fields([('time_nsec', NvU64, 0)])
|
|
NV2080_CTRL_TIMER_GET_TIME_PARAMS: TypeAlias = struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
tmr_offset: int
|
|
struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS.register_fields([('tmr_offset', NvU32, 0)])
|
|
NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS: TypeAlias = struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE(c.Struct):
|
|
SIZE = 16
|
|
cpuTime: int
|
|
gpuTime: int
|
|
struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE.register_fields([('cpuTime', NvU64, 0), ('gpuTime', NvU64, 8)])
|
|
NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE: TypeAlias = struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE
|
|
@c.record
|
|
class struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS(c.Struct):
|
|
SIZE = 264
|
|
cpuClkId: int
|
|
sampleCount: int
|
|
samples: c.Array[struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE, Literal[16]]
|
|
struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS.register_fields([('cpuClkId', NvU8, 0), ('sampleCount', NvU8, 1), ('samples', c.Array[NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE, Literal[16]], 8)])
|
|
NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bSetMaxFreq: int
|
|
struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS.register_fields([('bSetMaxFreq', NvBool, 0)])
|
|
NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
action: int
|
|
struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS.register_fields([('action', NvU32, 0)])
|
|
NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS: TypeAlias = struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
action: int
|
|
struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS.register_fields([('action', NvU32, 0)])
|
|
NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS: TypeAlias = struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnter: int
|
|
struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS.register_fields([('bEnter', NvBool, 0)])
|
|
NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS: TypeAlias = struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hNotifierResource: int
|
|
notifyDataSize: int
|
|
hNotifyDataMemory: int
|
|
perfmonIdCount: int
|
|
snapshotBufferSize: int
|
|
hSnapshotMemory: int
|
|
struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS.register_fields([('hNotifierResource', NvHandle, 0), ('notifyDataSize', NvU32, 4), ('hNotifyDataMemory', NvHandle, 8), ('perfmonIdCount', NvU32, 12), ('snapshotBufferSize', NvU32, 16), ('hSnapshotMemory', NvHandle, 20)])
|
|
NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS: TypeAlias = struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bVidmemPersistent: int
|
|
struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS.register_fields([('bVidmemPersistent', NvBool, 0)])
|
|
NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bUpdateTGP: int
|
|
struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS.register_fields([('bUpdateTGP', NvBool, 0)])
|
|
NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS(c.Struct):
|
|
SIZE = 6616
|
|
dbdf: int
|
|
gfid: int
|
|
vgpuType: int
|
|
vmPid: int
|
|
swizzId: int
|
|
numChannels: int
|
|
numPluginChannels: int
|
|
chidOffset: c.Array[ctypes.c_uint32, Literal[84]]
|
|
bDisableDefaultSmcExecPartRestore: int
|
|
numGuestFbSegments: int
|
|
guestFbPhysAddrList: c.Array[ctypes.c_uint64, Literal[384]]
|
|
guestFbLengthList: c.Array[ctypes.c_uint64, Literal[384]]
|
|
pluginHeapMemoryPhysAddr: int
|
|
pluginHeapMemoryLength: int
|
|
ctrlBuffOffset: int
|
|
initTaskLogBuffOffset: int
|
|
initTaskLogBuffSize: int
|
|
vgpuTaskLogBuffOffset: int
|
|
vgpuTaskLogBuffSize: int
|
|
kernelLogBuffOffset: int
|
|
kernelLogBuffSize: int
|
|
migRmHeapMemoryPhysAddr: int
|
|
migRmHeapMemoryLength: int
|
|
bDeviceProfilingEnabled: int
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS.register_fields([('dbdf', NvU32, 0), ('gfid', NvU32, 4), ('vgpuType', NvU32, 8), ('vmPid', NvU32, 12), ('swizzId', NvU32, 16), ('numChannels', NvU32, 20), ('numPluginChannels', NvU32, 24), ('chidOffset', c.Array[NvU32, Literal[84]], 28), ('bDisableDefaultSmcExecPartRestore', NvBool, 364), ('numGuestFbSegments', NvU32, 368), ('guestFbPhysAddrList', c.Array[NvU64, Literal[384]], 376), ('guestFbLengthList', c.Array[NvU64, Literal[384]], 3448), ('pluginHeapMemoryPhysAddr', NvU64, 6520), ('pluginHeapMemoryLength', NvU64, 6528), ('ctrlBuffOffset', NvU64, 6536), ('initTaskLogBuffOffset', NvU64, 6544), ('initTaskLogBuffSize', NvU64, 6552), ('vgpuTaskLogBuffOffset', NvU64, 6560), ('vgpuTaskLogBuffSize', NvU64, 6568), ('kernelLogBuffOffset', NvU64, 6576), ('kernelLogBuffSize', NvU64, 6584), ('migRmHeapMemoryPhysAddr', NvU64, 6592), ('migRmHeapMemoryLength', NvU64, 6600), ('bDeviceProfilingEnabled', NvBool, 6608)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gfid: int
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS.register_fields([('gfid', NvU32, 0)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS(c.Struct):
|
|
SIZE = 694280
|
|
discardVgpuTypes: int
|
|
vgpuInfoCount: int
|
|
vgpuInfo: c.Array[struct_NVA081_CTRL_VGPU_INFO, Literal[128]]
|
|
@c.record
|
|
class struct_NVA081_CTRL_VGPU_INFO(c.Struct):
|
|
SIZE = 5424
|
|
vgpuType: int
|
|
vgpuName: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
vgpuClass: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
vgpuSignature: c.Array[ctypes.c_ubyte, Literal[128]]
|
|
license: c.Array[ctypes.c_ubyte, Literal[128]]
|
|
maxInstance: int
|
|
numHeads: int
|
|
maxResolutionX: int
|
|
maxResolutionY: int
|
|
maxPixels: int
|
|
frlConfig: int
|
|
cudaEnabled: int
|
|
eccSupported: int
|
|
gpuInstanceSize: int
|
|
nominalFbRegionSize: int
|
|
multiVgpuSupported: int
|
|
vdevId: int
|
|
pdevId: int
|
|
profileSize: int
|
|
fbLength: int
|
|
gspHeapSize: int
|
|
fbReservation: int
|
|
mappableVideoSize: int
|
|
encoderCapacity: int
|
|
bar1Length: int
|
|
frlEnable: int
|
|
vgpuSsvid: int
|
|
adapterName: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
adapterName_Unicode: c.Array[ctypes.c_uint16, Literal[64]]
|
|
shortGpuNameString: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
licensedProductName: c.Array[ctypes.c_ubyte, Literal[128]]
|
|
vgpuExtraParams: c.Array[ctypes.c_uint32, Literal[1024]]
|
|
ftraceEnable: int
|
|
gpuDirectSupported: int
|
|
nvlinkP2PSupported: int
|
|
maxInstancePerGI: int
|
|
multiVgpuExclusive: int
|
|
exclusiveType: int
|
|
exclusiveSize: int
|
|
gpuInstanceProfileId: int
|
|
placementSize: int
|
|
homogeneousPlacementCount: int
|
|
homogeneousPlacementIds: c.Array[ctypes.c_uint32, Literal[48]]
|
|
heterogeneousPlacementCount: int
|
|
heterogeneousPlacementIds: c.Array[ctypes.c_uint32, Literal[48]]
|
|
NVA081_CTRL_VGPU_INFO: TypeAlias = struct_NVA081_CTRL_VGPU_INFO
|
|
struct_NVA081_CTRL_VGPU_INFO.register_fields([('vgpuType', NvU32, 0), ('vgpuName', c.Array[NvU8, Literal[64]], 4), ('vgpuClass', c.Array[NvU8, Literal[64]], 68), ('vgpuSignature', c.Array[NvU8, Literal[128]], 132), ('license', c.Array[NvU8, Literal[128]], 260), ('maxInstance', NvU32, 388), ('numHeads', NvU32, 392), ('maxResolutionX', NvU32, 396), ('maxResolutionY', NvU32, 400), ('maxPixels', NvU32, 404), ('frlConfig', NvU32, 408), ('cudaEnabled', NvU32, 412), ('eccSupported', NvU32, 416), ('gpuInstanceSize', NvU32, 420), ('nominalFbRegionSize', NvU32, 424), ('multiVgpuSupported', NvU32, 428), ('vdevId', NvU64, 432), ('pdevId', NvU64, 440), ('profileSize', NvU64, 448), ('fbLength', NvU64, 456), ('gspHeapSize', NvU64, 464), ('fbReservation', NvU64, 472), ('mappableVideoSize', NvU64, 480), ('encoderCapacity', NvU32, 488), ('bar1Length', NvU64, 496), ('frlEnable', NvU32, 504), ('vgpuSsvid', NvU16, 508), ('adapterName', c.Array[NvU8, Literal[64]], 510), ('adapterName_Unicode', c.Array[NvU16, Literal[64]], 574), ('shortGpuNameString', c.Array[NvU8, Literal[64]], 702), ('licensedProductName', c.Array[NvU8, Literal[128]], 766), ('vgpuExtraParams', c.Array[NvU32, Literal[1024]], 896), ('ftraceEnable', NvU32, 4992), ('gpuDirectSupported', NvU32, 4996), ('nvlinkP2PSupported', NvU32, 5000), ('maxInstancePerGI', NvU32, 5004), ('multiVgpuExclusive', NvU32, 5008), ('exclusiveType', NvU32, 5012), ('exclusiveSize', NvU32, 5016), ('gpuInstanceProfileId', NvU32, 5020), ('placementSize', NvU32, 5024), ('homogeneousPlacementCount', NvU32, 5028), ('homogeneousPlacementIds', c.Array[NvU32, Literal[48]], 5032), ('heterogeneousPlacementCount', NvU32, 5224), ('heterogeneousPlacementIds', c.Array[NvU32, Literal[48]], 5228)])
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS.register_fields([('discardVgpuTypes', NvBool, 0), ('vgpuInfoCount', NvU32, 4), ('vgpuInfo', c.Array[NVA081_CTRL_VGPU_INFO, Literal[128]], 8)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_GUEST_VM_INFO(c.Struct):
|
|
SIZE = 168
|
|
vmPid: int
|
|
guestOs: int
|
|
migrationProhibited: int
|
|
guestNegotiatedVgpuVersion: int
|
|
frameRateLimit: int
|
|
licensed: int
|
|
licenseState: int
|
|
licenseExpiryTimestamp: int
|
|
licenseExpiryStatus: int
|
|
guestDriverVersion: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
guestDriverBranch: c.Array[ctypes.c_ubyte, Literal[64]]
|
|
guestVmInfoState: int
|
|
enum_GUEST_VM_INFO_STATE: dict[int, str] = {(GUEST_VM_INFO_STATE_UNINITIALIZED:=0): 'GUEST_VM_INFO_STATE_UNINITIALIZED', (GUEST_VM_INFO_STATE_INITIALIZED:=1): 'GUEST_VM_INFO_STATE_INITIALIZED'}
|
|
GUEST_VM_INFO_STATE: TypeAlias = ctypes.c_uint32
|
|
struct_NV2080_GUEST_VM_INFO.register_fields([('vmPid', NvU32, 0), ('guestOs', NvU32, 4), ('migrationProhibited', NvU32, 8), ('guestNegotiatedVgpuVersion', NvU32, 12), ('frameRateLimit', NvU32, 16), ('licensed', NvBool, 20), ('licenseState', NvU32, 24), ('licenseExpiryTimestamp', NvU32, 28), ('licenseExpiryStatus', NvU8, 32), ('guestDriverVersion', c.Array[NvU8, Literal[64]], 33), ('guestDriverBranch', c.Array[NvU8, Literal[64]], 97), ('guestVmInfoState', GUEST_VM_INFO_STATE, 164)])
|
|
NV2080_GUEST_VM_INFO: TypeAlias = struct_NV2080_GUEST_VM_INFO
|
|
@c.record
|
|
class struct_NV2080_HOST_VGPU_DEVICE(c.Struct):
|
|
SIZE = 48
|
|
gfid: int
|
|
vgpuPciId: int
|
|
vgpuDeviceInstanceId: int
|
|
accountingPid: int
|
|
fbUsed: int
|
|
encoderCapacity: int
|
|
eccState: int
|
|
bDriverLoaded: int
|
|
struct_NV2080_HOST_VGPU_DEVICE.register_fields([('gfid', NvU32, 0), ('vgpuPciId', NvU64, 8), ('vgpuDeviceInstanceId', NvU32, 16), ('accountingPid', NvU32, 20), ('fbUsed', NvU64, 24), ('encoderCapacity', NvU32, 32), ('eccState', NvU32, 36), ('bDriverLoaded', NvBool, 40)])
|
|
NV2080_HOST_VGPU_DEVICE: TypeAlias = struct_NV2080_HOST_VGPU_DEVICE
|
|
@c.record
|
|
class struct_NV2080_VGPU_GUEST(c.Struct):
|
|
SIZE = 216
|
|
guestVmInfo: struct_NV2080_GUEST_VM_INFO
|
|
vgpuDevice: struct_NV2080_HOST_VGPU_DEVICE
|
|
struct_NV2080_VGPU_GUEST.register_fields([('guestVmInfo', NV2080_GUEST_VM_INFO, 0), ('vgpuDevice', NV2080_HOST_VGPU_DEVICE, 168)])
|
|
NV2080_VGPU_GUEST: TypeAlias = struct_NV2080_VGPU_GUEST
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS(c.Struct):
|
|
SIZE = 10376
|
|
numVgpu: int
|
|
vgpuGuest: c.Array[struct_NV2080_VGPU_GUEST, Literal[48]]
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS.register_fields([('numVgpu', NvU32, 0), ('vgpuGuest', c.Array[NV2080_VGPU_GUEST, Literal[48]], 8)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gfid: int
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS.register_fields([('gfid', NvU32, 0)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_VGPU_FB_USAGE(c.Struct):
|
|
SIZE = 16
|
|
gfid: int
|
|
fbUsed: int
|
|
struct_NV2080_VGPU_FB_USAGE.register_fields([('gfid', NvU32, 0), ('fbUsed', NvU64, 8)])
|
|
NV2080_VGPU_FB_USAGE: TypeAlias = struct_NV2080_VGPU_FB_USAGE
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS(c.Struct):
|
|
SIZE = 776
|
|
vgpuCount: int
|
|
vgpuFbUsage: c.Array[struct_NV2080_VGPU_FB_USAGE, Literal[48]]
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS.register_fields([('vgpuCount', NvU32, 0), ('vgpuFbUsage', c.Array[NV2080_VGPU_FB_USAGE, Literal[48]], 8)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gfid: int
|
|
encoderCapacity: int
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS.register_fields([('gfid', NvU32, 0), ('encoderCapacity', NvU32, 4)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gfid: int
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS.register_fields([('gfid', NvU32, 0)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS(c.Struct):
|
|
SIZE = 260
|
|
pgpuString: c.Array[ctypes.c_ubyte, Literal[256]]
|
|
pgpuStringSize: int
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS.register_fields([('pgpuString', c.Array[NvU8, Literal[256]], 0), ('pgpuStringSize', NvU32, 256)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bIsMigrationSupported: int
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS.register_fields([('bIsMigrationSupported', NvBool, 0)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bSupportHeterogeneousTimeSlicedVgpuTypes: int
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS.register_fields([('bSupportHeterogeneousTimeSlicedVgpuTypes', NvBool, 0)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gfid: int
|
|
flags: int
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS.register_fields([('gfid', NvU32, 0), ('flags', NvU32, 4)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bFlrDisabled: int
|
|
struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS.register_fields([('bFlrDisabled', NvBool, 0)])
|
|
NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bHeterogeneousMode: int
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS.register_fields([('bHeterogeneousMode', NvBool, 0)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bMigTimeslicingModeEnabled: int
|
|
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS.register_fields([('bMigTimeslicingModeEnabled', NvBool, 0)])
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
state: int
|
|
struct_NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS.register_fields([('state', NvU32, 0)])
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
action: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS.register_fields([('action', NvU32, 0)])
|
|
NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
value: int
|
|
struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS.register_fields([('value', NvU32, 0)])
|
|
NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
exceptionMask: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS.register_fields([('exceptionMask', NvU32, 0)])
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_SM_ERROR_STATE_REGISTERS(c.Struct):
|
|
SIZE = 48
|
|
hwwGlobalEsr: int
|
|
hwwWarpEsr: int
|
|
hwwWarpEsrPc: int
|
|
hwwGlobalEsrReportMask: int
|
|
hwwWarpEsrReportMask: int
|
|
hwwEsrAddr: int
|
|
hwwWarpEsrPc64: int
|
|
hwwCgaEsr: int
|
|
hwwCgaEsrReportMask: int
|
|
struct_NV83DE_SM_ERROR_STATE_REGISTERS.register_fields([('hwwGlobalEsr', NvU32, 0), ('hwwWarpEsr', NvU32, 4), ('hwwWarpEsrPc', NvU32, 8), ('hwwGlobalEsrReportMask', NvU32, 12), ('hwwWarpEsrReportMask', NvU32, 16), ('hwwEsrAddr', NvU64, 24), ('hwwWarpEsrPc64', NvU64, 32), ('hwwCgaEsr', NvU32, 40), ('hwwCgaEsrReportMask', NvU32, 44)])
|
|
NV83DE_SM_ERROR_STATE_REGISTERS: TypeAlias = struct_NV83DE_SM_ERROR_STATE_REGISTERS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
hTargetChannel: int
|
|
smID: int
|
|
smErrorState: struct_NV83DE_SM_ERROR_STATE_REGISTERS
|
|
struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS.register_fields([('hTargetChannel', NvHandle, 0), ('smID', NvU32, 4), ('smErrorState', NV83DE_SM_ERROR_STATE_REGISTERS, 8)])
|
|
NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_MMU_FAULT_INFO(c.Struct):
|
|
SIZE = 8
|
|
valid: int
|
|
faultInfo: int
|
|
struct_NV83DE_MMU_FAULT_INFO.register_fields([('valid', NvBool, 0), ('faultInfo', NvU32, 4)])
|
|
NV83DE_MMU_FAULT_INFO: TypeAlias = struct_NV83DE_MMU_FAULT_INFO
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS(c.Struct):
|
|
SIZE = 4824
|
|
hTargetChannel: int
|
|
numSMsToRead: int
|
|
smErrorStateArray: c.Array[struct_NV83DE_SM_ERROR_STATE_REGISTERS, Literal[100]]
|
|
mmuFaultInfo: int
|
|
mmuFault: struct_NV83DE_MMU_FAULT_INFO
|
|
startingSM: int
|
|
struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS.register_fields([('hTargetChannel', NvHandle, 0), ('numSMsToRead', NvU32, 4), ('smErrorStateArray', c.Array[NV83DE_SM_ERROR_STATE_REGISTERS, Literal[100]], 8), ('mmuFaultInfo', NvU32, 4808), ('mmuFault', NV83DE_MMU_FAULT_INFO, 4812), ('startingSM', NvU32, 4820)])
|
|
NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hTargetChannel: int
|
|
smID: int
|
|
struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS.register_fields([('hTargetChannel', NvHandle, 0), ('smID', NvU32, 4)])
|
|
NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hTargetChannel: int
|
|
numSMsToClear: int
|
|
struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS.register_fields([('hTargetChannel', NvHandle, 0), ('numSMsToClear', NvU32, 4)])
|
|
NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
waitForEvent: int
|
|
hResidentChannel: int
|
|
struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS.register_fields([('waitForEvent', NvU32, 0), ('hResidentChannel', NvHandle, 4)])
|
|
NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS: TypeAlias = struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
stopTriggerType: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS.register_fields([('stopTriggerType', NvU32, 0)])
|
|
NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
singleStepHandling: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS.register_fields([('singleStepHandling', NvU32, 0)])
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hMemory: int
|
|
length: int
|
|
offset: int
|
|
buffer: ctypes.c_void_p
|
|
struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS.register_fields([('hMemory', NvU32, 0), ('length', NvU32, 4), ('offset', NvU64, 8), ('buffer', NvP64, 16)])
|
|
NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hMemory: int
|
|
length: int
|
|
offset: int
|
|
buffer: ctypes.c_void_p
|
|
struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS.register_fields([('hMemory', NvU32, 0), ('length', NvU32, 4), ('offset', NvU64, 8), ('buffer', NvP64, 16)])
|
|
NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS
|
|
NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS: TypeAlias = struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hChannel: int
|
|
hSubdevice: int
|
|
struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS.register_fields([('hChannel', NvHandle, 0), ('hSubdevice', NvHandle, 4)])
|
|
NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_ACCESS_OP(c.Struct):
|
|
SIZE = 24
|
|
gpuVA: int
|
|
pCpuVA: ctypes.c_void_p
|
|
size: int
|
|
valid: int
|
|
struct_NV83DE_CTRL_DEBUG_ACCESS_OP.register_fields([('gpuVA', NvU64, 0), ('pCpuVA', NvP64, 8), ('size', NvU32, 16), ('valid', NvU32, 20)])
|
|
NV83DE_CTRL_DEBUG_ACCESS_OP: TypeAlias = struct_NV83DE_CTRL_DEBUG_ACCESS_OP
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS(c.Struct):
|
|
SIZE = 1544
|
|
count: int
|
|
opsBuffer: c.Array[struct_NV83DE_CTRL_DEBUG_ACCESS_OP, Literal[64]]
|
|
struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS.register_fields([('count', NvU32, 0), ('opsBuffer', c.Array[NV83DE_CTRL_DEBUG_ACCESS_OP, Literal[64]], 8)])
|
|
NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS: TypeAlias = struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP(c.Struct):
|
|
SIZE = 16
|
|
gpuVA: int
|
|
size: int
|
|
struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP.register_fields([('gpuVA', NvU64, 0), ('size', NvU32, 8)])
|
|
NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS(c.Struct):
|
|
SIZE = 1048
|
|
vaLo: int
|
|
vaHi: int
|
|
count: int
|
|
hasMore: int
|
|
opsBuffer: c.Array[struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP, Literal[64]]
|
|
struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS.register_fields([('vaLo', NvU64, 0), ('vaHi', NvU64, 8), ('count', NvU32, 16), ('hasMore', NvU32, 20), ('opsBuffer', c.Array[NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP, Literal[64]], 24)])
|
|
NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS(c.Struct):
|
|
SIZE = 3208
|
|
bNonTransactional: int
|
|
regOpCount: int
|
|
regOps: c.Array[struct_NV2080_CTRL_GPU_REG_OP, Literal[100]]
|
|
struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS.register_fields([('bNonTransactional', NvBool, 0), ('regOpCount', NvU32, 4), ('regOps', c.Array[NV2080_CTRL_GPU_REG_OP, Literal[100]], 8)])
|
|
NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
action: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS.register_fields([('action', NvU32, 0)])
|
|
NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
value: int
|
|
struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS.register_fields([('value', NvU32, 0)])
|
|
NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
smID: int
|
|
bSingleStep: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS.register_fields([('smID', NvU32, 0), ('bSingleStep', NvBool, 4)])
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
smID: int
|
|
bStopTrigger: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS.register_fields([('smID', NvU32, 0), ('bStopTrigger', NvBool, 4)])
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
smID: int
|
|
bRunTrigger: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS.register_fields([('smID', NvU32, 0), ('bRunTrigger', NvBool, 4)])
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
smID: int
|
|
bSkipIdleWarpDetect: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS.register_fields([('smID', NvU32, 0), ('bSkipIdleWarpDetect', NvBool, 4)])
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS(c.Struct):
|
|
SIZE = 5
|
|
bInTrapMode: int
|
|
bCrsFlushDone: int
|
|
bRunTriggerInProgress: int
|
|
bComputeContext: int
|
|
bLockedDown: int
|
|
struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS.register_fields([('bInTrapMode', NvBool, 0), ('bCrsFlushDone', NvBool, 1), ('bRunTriggerInProgress', NvBool, 2), ('bComputeContext', NvBool, 3), ('bLockedDown', NvBool, 4)])
|
|
NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
smID: int
|
|
smDebuggerStatus: struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS
|
|
struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS.register_fields([('smID', NvU32, 0), ('smDebuggerStatus', NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS, 4)])
|
|
NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY(c.Struct):
|
|
SIZE = 24
|
|
hMemory: int
|
|
length: int
|
|
memOffset: int
|
|
dataOffset: int
|
|
status: int
|
|
struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY.register_fields([('hMemory', NvHandle, 0), ('length', NvU32, 4), ('memOffset', NvU64, 8), ('dataOffset', NvU32, 16), ('status', NV_STATUS, 20)])
|
|
NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY: TypeAlias = struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 3616
|
|
pData: ctypes.c_void_p
|
|
dataLength: int
|
|
count: int
|
|
entries: c.Array[struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY, Literal[150]]
|
|
struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS.register_fields([('pData', NvP64, 0), ('dataLength', NvU32, 8), ('count', NvU32, 12), ('entries', c.Array[NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY, Literal[150]], 16)])
|
|
NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY(c.Struct):
|
|
SIZE = 16
|
|
faultAddress: int
|
|
faultType: int
|
|
accessType: int
|
|
struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY.register_fields([('faultAddress', NvU64, 0), ('faultType', NvU32, 8), ('accessType', NvU32, 12)])
|
|
NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY: TypeAlias = struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
mmuFaultInfoList: c.Array[struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY, Literal[4]]
|
|
count: int
|
|
struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS.register_fields([('mmuFaultInfoList', c.Array[NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY, Literal[4]], 0), ('count', NvU32, 64)])
|
|
NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bDropDeferredRc: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS.register_fields([('bDropDeferredRc', NvBool, 0)])
|
|
NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
action: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS.register_fields([('action', NvU32, 0)])
|
|
NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
value: int
|
|
struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS.register_fields([('value', NvU32, 0)])
|
|
NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
state: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_PARAMS.register_fields([('state', NvBool, 0)])
|
|
NV83DE_CTRL_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_RECOVERY_SUPPRESSION_TIMEOUT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
timeoutSec: int
|
|
struct_NV83DE_CTRL_DEBUG_SET_RECOVERY_SUPPRESSION_TIMEOUT_PARAMS.register_fields([('timeoutSec', NvU32, 0)])
|
|
NV83DE_CTRL_DEBUG_SET_RECOVERY_SUPPRESSION_TIMEOUT_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_RECOVERY_SUPPRESSION_TIMEOUT_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
params: struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
hMemPmaBuffer: int
|
|
pmaBufferOffset: int
|
|
pmaBufferSize: int
|
|
hMemPmaBytesAvailable: int
|
|
pmaBytesAvailableOffset: int
|
|
ctxsw: int
|
|
pmaChannelIdx: int
|
|
pmaBufferVA: int
|
|
NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS: TypeAlias = struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS
|
|
struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS.register_fields([('hMemPmaBuffer', NvHandle, 0), ('pmaBufferOffset', NvU64, 8), ('pmaBufferSize', NvU64, 16), ('hMemPmaBytesAvailable', NvHandle, 24), ('pmaBytesAvailableOffset', NvU64, 32), ('ctxsw', NvBool, 40), ('pmaChannelIdx', NvU32, 44), ('pmaBufferVA', NvU64, 48)])
|
|
struct_NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS.register_fields([('params', NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS, 0)])
|
|
NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS: TypeAlias = struct_NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pmaChannelIdx: int
|
|
bMembytesPollingRequired: int
|
|
struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS.register_fields([('pmaChannelIdx', NvU32, 0), ('bMembytesPollingRequired', NvBool, 4)])
|
|
NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
pmaChannelIdx: int
|
|
pmaBufferVA: int
|
|
pmaBufferSize: int
|
|
membytesVA: int
|
|
hwpmIBPA: int
|
|
hwpmIBAperture: int
|
|
struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS.register_fields([('pmaChannelIdx', NvU32, 0), ('pmaBufferVA', NvU64, 8), ('pmaBufferSize', NvU64, 16), ('membytesVA', NvU64, 24), ('hwpmIBPA', NvU64, 32), ('hwpmIBAperture', NvU8, 40)])
|
|
NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS(c.Struct):
|
|
SIZE = 7
|
|
bAdminProfilingPermitted: int
|
|
bDevProfilingPermitted: int
|
|
bDevTracePermitted: int
|
|
bCtxProfilingPermitted: int
|
|
bVideoMemoryProfilingPermitted: int
|
|
bSysMemoryProfilingPermitted: int
|
|
bAsyncCeProfilingPermitted: int
|
|
struct_NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS.register_fields([('bAdminProfilingPermitted', NvBool, 0), ('bDevProfilingPermitted', NvBool, 1), ('bDevTracePermitted', NvBool, 2), ('bCtxProfilingPermitted', NvBool, 3), ('bVideoMemoryProfilingPermitted', NvBool, 4), ('bSysMemoryProfilingPermitted', NvBool, 5), ('bAsyncCeProfilingPermitted', NvBool, 6)])
|
|
NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS(c.Struct):
|
|
SIZE = 64
|
|
hMemPmaBuffer: int
|
|
pmaBufferOffset: int
|
|
pmaBufferSize: int
|
|
hMemPmaBytesAvailable: int
|
|
pmaBytesAvailableOffset: int
|
|
ctxsw: int
|
|
pmaChannelIdx: int
|
|
pmaBufferVA: int
|
|
bInputPmaChIdx: int
|
|
struct_NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS.register_fields([('hMemPmaBuffer', NvHandle, 0), ('pmaBufferOffset', NvU64, 8), ('pmaBufferSize', NvU64, 16), ('hMemPmaBytesAvailable', NvHandle, 24), ('pmaBytesAvailableOffset', NvU64, 32), ('ctxsw', NvBool, 40), ('pmaChannelIdx', NvU32, 44), ('pmaBufferVA', NvU64, 48), ('bInputPmaChIdx', NvBool, 56)])
|
|
NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
pmaChannelIdx: int
|
|
struct_NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS.register_fields([('pmaChannelIdx', NvU32, 0)])
|
|
NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
maxPmaChannels: int
|
|
struct_NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS.register_fields([('maxPmaChannels', NvU32, 0)])
|
|
NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
ctxsw: int
|
|
struct_NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS.register_fields([('ctxsw', NvBool, 0)])
|
|
NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
globalStatus: int
|
|
controlMask: int
|
|
statusMask: int
|
|
struct_NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS.register_fields([('globalStatus', NvU32, 0), ('controlMask', NvU32, 4), ('statusMask', NvU32, 8)])
|
|
NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS: TypeAlias = struct_NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
controlMask: int
|
|
struct_NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS.register_fields([('controlMask', NvU32, 0)])
|
|
NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS: TypeAlias = struct_NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
ctxsw: int
|
|
struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS.register_fields([('ctxsw', NvBool, 0)])
|
|
NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
ctxsw: int
|
|
struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS.register_fields([('ctxsw', NvBool, 0)])
|
|
NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
pmaChannelIdx: int
|
|
struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS.register_fields([('pmaChannelIdx', NvU32, 0)])
|
|
NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS: TypeAlias = struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
bytesConsumed: int
|
|
bUpdateAvailableBytes: int
|
|
bWait: int
|
|
bytesAvailable: int
|
|
bReturnPut: int
|
|
putPtr: int
|
|
pmaChannelIdx: int
|
|
bOverflowStatus: int
|
|
struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS.register_fields([('bytesConsumed', NvU64, 0), ('bUpdateAvailableBytes', NvBool, 8), ('bWait', NvBool, 9), ('bytesAvailable', NvU64, 16), ('bReturnPut', NvBool, 24), ('putPtr', NvU64, 32), ('pmaChannelIdx', NvU32, 40), ('bOverflowStatus', NvBool, 44)])
|
|
NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS: TypeAlias = struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS
|
|
NVB0CC_GPU_REG_OP: TypeAlias = struct_NV2080_CTRL_GPU_REG_OP
|
|
enum_NVB0CC_REGOPS_MODE: dict[int, str] = {(NVB0CC_REGOPS_MODE_ALL_OR_NONE:=0): 'NVB0CC_REGOPS_MODE_ALL_OR_NONE', (NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR:=1): 'NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR'}
|
|
NVB0CC_REGOPS_MODE: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS(c.Struct):
|
|
SIZE = 3980
|
|
regOpCount: int
|
|
mode: int
|
|
bPassed: int
|
|
bDirect: int
|
|
regOps: c.Array[struct_NV2080_CTRL_GPU_REG_OP, Literal[124]]
|
|
struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS.register_fields([('regOpCount', NvU32, 0), ('mode', NVB0CC_REGOPS_MODE, 4), ('bPassed', NvBool, 8), ('bDirect', NvBool, 9), ('regOps', c.Array[NVB0CC_GPU_REG_OP, Literal[124]], 12)])
|
|
NVB0CC_CTRL_EXEC_REG_OPS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
numCredits: int
|
|
struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS.register_fields([('numCredits', NvU32, 0)])
|
|
NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS
|
|
enum_NVB0CC_CHIPLET_TYPE: dict[int, str] = {(NVB0CC_CHIPLET_TYPE_INVALID:=0): 'NVB0CC_CHIPLET_TYPE_INVALID', (NVB0CC_CHIPLET_TYPE_FBP:=1): 'NVB0CC_CHIPLET_TYPE_FBP', (NVB0CC_CHIPLET_TYPE_GPC:=2): 'NVB0CC_CHIPLET_TYPE_GPC', (NVB0CC_CHIPLET_TYPE_SYS:=3): 'NVB0CC_CHIPLET_TYPE_SYS', (NVB0CC_CHIPLET_TYPE_IODN:=4): 'NVB0CC_CHIPLET_TYPE_IODN', (NVB0CC_CHIPLET_TYPE_IODS:=5): 'NVB0CC_CHIPLET_TYPE_IODS'}
|
|
NVB0CC_CHIPLET_TYPE: TypeAlias = ctypes.c_uint32
|
|
enum_NVB0CC_HS_CREDITS_CMD_STATUS: dict[int, str] = {(NVB0CC_HS_CREDITS_CMD_STATUS_OK:=0): 'NVB0CC_HS_CREDITS_CMD_STATUS_OK', (NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CREDITS:=1): 'NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CREDITS', (NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET:=2): 'NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET'}
|
|
NVB0CC_HS_CREDITS_CMD_STATUS: TypeAlias = ctypes.c_uint32
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO(c.Struct):
|
|
SIZE = 4
|
|
chipletType: int
|
|
chipletIndex: int
|
|
numCredits: int
|
|
struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO.register_fields([('chipletType', NvU8, 0), ('chipletIndex', NvU8, 1), ('numCredits', NvU16, 2)])
|
|
NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO: TypeAlias = struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS(c.Struct):
|
|
SIZE = 2
|
|
status: int
|
|
entryIndex: int
|
|
struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS.register_fields([('status', NvU8, 0), ('entryIndex', NvU8, 1)])
|
|
NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS: TypeAlias = struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_HS_CREDITS_PARAMS(c.Struct):
|
|
SIZE = 256
|
|
pmaChannelIdx: int
|
|
numEntries: int
|
|
statusInfo: struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS
|
|
creditInfo: c.Array[struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO, Literal[63]]
|
|
struct_NVB0CC_CTRL_HS_CREDITS_PARAMS.register_fields([('pmaChannelIdx', NvU8, 0), ('numEntries', NvU8, 1), ('statusInfo', NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS, 2), ('creditInfo', c.Array[NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO, Literal[63]], 4)])
|
|
NVB0CC_CTRL_HS_CREDITS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_HS_CREDITS_PARAMS
|
|
NVB0CC_CTRL_SET_HS_CREDITS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_HS_CREDITS_PARAMS
|
|
NVB0CC_CTRL_GET_HS_CREDITS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_HS_CREDITS_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
ctxsw: int
|
|
struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS.register_fields([('ctxsw', NvBool, 0)])
|
|
NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RESERVE_HES_TPC_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
ctxsw: int
|
|
struct_NVB0CC_CTRL_RESERVE_HES_TPC_PARAMS.register_fields([('ctxsw', NvBool, 0)])
|
|
NVB0CC_CTRL_RESERVE_HES_TPC_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RESERVE_HES_TPC_PARAMS
|
|
@c.record
|
|
class union_NVB0CC_CTRL_HES_RESERVATION_UNION(c.Struct):
|
|
SIZE = 1
|
|
cwd: struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS
|
|
tpc: struct_NVB0CC_CTRL_RESERVE_HES_TPC_PARAMS
|
|
union_NVB0CC_CTRL_HES_RESERVATION_UNION.register_fields([('cwd', NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS, 0), ('tpc', NVB0CC_CTRL_RESERVE_HES_TPC_PARAMS, 0)])
|
|
NVB0CC_CTRL_HES_RESERVATION_UNION: TypeAlias = union_NVB0CC_CTRL_HES_RESERVATION_UNION
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RESERVE_HES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
type: int
|
|
reserveParams: union_NVB0CC_CTRL_HES_RESERVATION_UNION
|
|
struct_NVB0CC_CTRL_RESERVE_HES_PARAMS.register_fields([('type', NvU32, 0), ('reserveParams', NVB0CC_CTRL_HES_RESERVATION_UNION, 4)])
|
|
NVB0CC_CTRL_RESERVE_HES_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RESERVE_HES_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RELEASE_HES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
type: int
|
|
struct_NVB0CC_CTRL_RELEASE_HES_PARAMS.register_fields([('type', NvU32, 0)])
|
|
NVB0CC_CTRL_RELEASE_HES_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RELEASE_HES_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_CREDIT_POOL_INFO(c.Struct):
|
|
SIZE = 4
|
|
numCredits: int
|
|
poolIndex: int
|
|
chipletType: int
|
|
struct_NVB0CC_CTRL_CREDIT_POOL_INFO.register_fields([('numCredits', NvU16, 0), ('poolIndex', NvU8, 2), ('chipletType', NvU8, 3)])
|
|
NVB0CC_CTRL_CREDIT_POOL_INFO: TypeAlias = struct_NVB0CC_CTRL_CREDIT_POOL_INFO
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL(c.Struct):
|
|
SIZE = 124
|
|
poolInfos: c.Array[struct_NVB0CC_CTRL_CREDIT_POOL_INFO, Literal[30]]
|
|
poolInfosCount: int
|
|
struct_NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL.register_fields([('poolInfos', c.Array[NVB0CC_CTRL_CREDIT_POOL_INFO, Literal[30]], 0), ('poolInfosCount', NvU32, 120)])
|
|
NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL: TypeAlias = struct_NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO(c.Struct):
|
|
SIZE = 3
|
|
chipletType: int
|
|
chipletIndex: int
|
|
poolIndex: int
|
|
struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO.register_fields([('chipletType', NvU8, 0), ('chipletIndex', NvU8, 1), ('poolIndex', NvU8, 2)])
|
|
NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO: TypeAlias = struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 194
|
|
numQueries: int
|
|
statusInfo: struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS
|
|
queries: c.Array[struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO, Literal[63]]
|
|
struct_NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS.register_fields([('numQueries', NvU16, 0), ('statusInfo', NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS, 2), ('queries', c.Array[NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO, Literal[63]], 4)])
|
|
NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS: TypeAlias = struct_NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
disable: int
|
|
struct_NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS.register_fields([('disable', NvBool, 0)])
|
|
NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS: TypeAlias = struct_NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
enabled: int
|
|
struct_NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS.register_fields([('enabled', NvBool, 0)])
|
|
NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
ctxsw: int
|
|
struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS.register_fields([('ctxsw', NvBool, 0)])
|
|
NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS
|
|
nv_status_codes: dict[int, str] = {(NV_OK:=0): 'NV_OK', (NV_ERR_GENERIC:=65535): 'NV_ERR_GENERIC', (NV_ERR_BROKEN_FB:=1): 'NV_ERR_BROKEN_FB', (NV_ERR_BUFFER_TOO_SMALL:=2): 'NV_ERR_BUFFER_TOO_SMALL', (NV_ERR_BUSY_RETRY:=3): 'NV_ERR_BUSY_RETRY', (NV_ERR_CALLBACK_NOT_SCHEDULED:=4): 'NV_ERR_CALLBACK_NOT_SCHEDULED', (NV_ERR_CARD_NOT_PRESENT:=5): 'NV_ERR_CARD_NOT_PRESENT', (NV_ERR_CYCLE_DETECTED:=6): 'NV_ERR_CYCLE_DETECTED', (NV_ERR_DMA_IN_USE:=7): 'NV_ERR_DMA_IN_USE', (NV_ERR_DMA_MEM_NOT_LOCKED:=8): 'NV_ERR_DMA_MEM_NOT_LOCKED', (NV_ERR_DMA_MEM_NOT_UNLOCKED:=9): 'NV_ERR_DMA_MEM_NOT_UNLOCKED', (NV_ERR_DUAL_LINK_INUSE:=10): 'NV_ERR_DUAL_LINK_INUSE', (NV_ERR_ECC_ERROR:=11): 'NV_ERR_ECC_ERROR', (NV_ERR_FIFO_BAD_ACCESS:=12): 'NV_ERR_FIFO_BAD_ACCESS', (NV_ERR_FREQ_NOT_SUPPORTED:=13): 'NV_ERR_FREQ_NOT_SUPPORTED', (NV_ERR_GPU_DMA_NOT_INITIALIZED:=14): 'NV_ERR_GPU_DMA_NOT_INITIALIZED', (NV_ERR_GPU_IS_LOST:=15): 'NV_ERR_GPU_IS_LOST', (NV_ERR_GPU_IN_FULLCHIP_RESET:=16): 'NV_ERR_GPU_IN_FULLCHIP_RESET', (NV_ERR_GPU_NOT_FULL_POWER:=17): 'NV_ERR_GPU_NOT_FULL_POWER', (NV_ERR_GPU_UUID_NOT_FOUND:=18): 'NV_ERR_GPU_UUID_NOT_FOUND', (NV_ERR_HOT_SWITCH:=19): 'NV_ERR_HOT_SWITCH', (NV_ERR_I2C_ERROR:=20): 'NV_ERR_I2C_ERROR', (NV_ERR_I2C_SPEED_TOO_HIGH:=21): 'NV_ERR_I2C_SPEED_TOO_HIGH', (NV_ERR_ILLEGAL_ACTION:=22): 'NV_ERR_ILLEGAL_ACTION', (NV_ERR_IN_USE:=23): 'NV_ERR_IN_USE', (NV_ERR_INFLATE_COMPRESSED_DATA_FAILED:=24): 'NV_ERR_INFLATE_COMPRESSED_DATA_FAILED', (NV_ERR_INSERT_DUPLICATE_NAME:=25): 'NV_ERR_INSERT_DUPLICATE_NAME', (NV_ERR_INSUFFICIENT_RESOURCES:=26): 'NV_ERR_INSUFFICIENT_RESOURCES', (NV_ERR_INSUFFICIENT_PERMISSIONS:=27): 'NV_ERR_INSUFFICIENT_PERMISSIONS', (NV_ERR_INSUFFICIENT_POWER:=28): 'NV_ERR_INSUFFICIENT_POWER', (NV_ERR_INVALID_ACCESS_TYPE:=29): 'NV_ERR_INVALID_ACCESS_TYPE', (NV_ERR_INVALID_ADDRESS:=30): 'NV_ERR_INVALID_ADDRESS', (NV_ERR_INVALID_ARGUMENT:=31): 'NV_ERR_INVALID_ARGUMENT', (NV_ERR_INVALID_BASE:=32): 'NV_ERR_INVALID_BASE', (NV_ERR_INVALID_CHANNEL:=33): 'NV_ERR_INVALID_CHANNEL', (NV_ERR_INVALID_CLASS:=34): 'NV_ERR_INVALID_CLASS', (NV_ERR_INVALID_CLIENT:=35): 'NV_ERR_INVALID_CLIENT', (NV_ERR_INVALID_COMMAND:=36): 'NV_ERR_INVALID_COMMAND', (NV_ERR_INVALID_DATA:=37): 'NV_ERR_INVALID_DATA', (NV_ERR_INVALID_DEVICE:=38): 'NV_ERR_INVALID_DEVICE', (NV_ERR_INVALID_DMA_SPECIFIER:=39): 'NV_ERR_INVALID_DMA_SPECIFIER', (NV_ERR_INVALID_EVENT:=40): 'NV_ERR_INVALID_EVENT', (NV_ERR_INVALID_FLAGS:=41): 'NV_ERR_INVALID_FLAGS', (NV_ERR_INVALID_FUNCTION:=42): 'NV_ERR_INVALID_FUNCTION', (NV_ERR_INVALID_HEAP:=43): 'NV_ERR_INVALID_HEAP', (NV_ERR_INVALID_INDEX:=44): 'NV_ERR_INVALID_INDEX', (NV_ERR_INVALID_IRQ_LEVEL:=45): 'NV_ERR_INVALID_IRQ_LEVEL', (NV_ERR_INVALID_LIMIT:=46): 'NV_ERR_INVALID_LIMIT', (NV_ERR_INVALID_LOCK_STATE:=47): 'NV_ERR_INVALID_LOCK_STATE', (NV_ERR_INVALID_METHOD:=48): 'NV_ERR_INVALID_METHOD', (NV_ERR_INVALID_OBJECT:=49): 'NV_ERR_INVALID_OBJECT', (NV_ERR_INVALID_OBJECT_BUFFER:=50): 'NV_ERR_INVALID_OBJECT_BUFFER', (NV_ERR_INVALID_OBJECT_HANDLE:=51): 'NV_ERR_INVALID_OBJECT_HANDLE', (NV_ERR_INVALID_OBJECT_NEW:=52): 'NV_ERR_INVALID_OBJECT_NEW', (NV_ERR_INVALID_OBJECT_OLD:=53): 'NV_ERR_INVALID_OBJECT_OLD', (NV_ERR_INVALID_OBJECT_PARENT:=54): 'NV_ERR_INVALID_OBJECT_PARENT', (NV_ERR_INVALID_OFFSET:=55): 'NV_ERR_INVALID_OFFSET', (NV_ERR_INVALID_OPERATION:=56): 'NV_ERR_INVALID_OPERATION', (NV_ERR_INVALID_OWNER:=57): 'NV_ERR_INVALID_OWNER', (NV_ERR_INVALID_PARAM_STRUCT:=58): 'NV_ERR_INVALID_PARAM_STRUCT', (NV_ERR_INVALID_PARAMETER:=59): 'NV_ERR_INVALID_PARAMETER', (NV_ERR_INVALID_PATH:=60): 'NV_ERR_INVALID_PATH', (NV_ERR_INVALID_POINTER:=61): 'NV_ERR_INVALID_POINTER', (NV_ERR_INVALID_REGISTRY_KEY:=62): 'NV_ERR_INVALID_REGISTRY_KEY', (NV_ERR_INVALID_REQUEST:=63): 'NV_ERR_INVALID_REQUEST', (NV_ERR_INVALID_STATE:=64): 'NV_ERR_INVALID_STATE', (NV_ERR_INVALID_STRING_LENGTH:=65): 'NV_ERR_INVALID_STRING_LENGTH', (NV_ERR_INVALID_READ:=66): 'NV_ERR_INVALID_READ', (NV_ERR_INVALID_WRITE:=67): 'NV_ERR_INVALID_WRITE', (NV_ERR_INVALID_XLATE:=68): 'NV_ERR_INVALID_XLATE', (NV_ERR_IRQ_NOT_FIRING:=69): 'NV_ERR_IRQ_NOT_FIRING', (NV_ERR_IRQ_EDGE_TRIGGERED:=70): 'NV_ERR_IRQ_EDGE_TRIGGERED', (NV_ERR_MEMORY_TRAINING_FAILED:=71): 'NV_ERR_MEMORY_TRAINING_FAILED', (NV_ERR_MISMATCHED_SLAVE:=72): 'NV_ERR_MISMATCHED_SLAVE', (NV_ERR_MISMATCHED_TARGET:=73): 'NV_ERR_MISMATCHED_TARGET', (NV_ERR_MISSING_TABLE_ENTRY:=74): 'NV_ERR_MISSING_TABLE_ENTRY', (NV_ERR_MODULE_LOAD_FAILED:=75): 'NV_ERR_MODULE_LOAD_FAILED', (NV_ERR_MORE_DATA_AVAILABLE:=76): 'NV_ERR_MORE_DATA_AVAILABLE', (NV_ERR_MORE_PROCESSING_REQUIRED:=77): 'NV_ERR_MORE_PROCESSING_REQUIRED', (NV_ERR_MULTIPLE_MEMORY_TYPES:=78): 'NV_ERR_MULTIPLE_MEMORY_TYPES', (NV_ERR_NO_FREE_FIFOS:=79): 'NV_ERR_NO_FREE_FIFOS', (NV_ERR_NO_INTR_PENDING:=80): 'NV_ERR_NO_INTR_PENDING', (NV_ERR_NO_MEMORY:=81): 'NV_ERR_NO_MEMORY', (NV_ERR_NO_SUCH_DOMAIN:=82): 'NV_ERR_NO_SUCH_DOMAIN', (NV_ERR_NO_VALID_PATH:=83): 'NV_ERR_NO_VALID_PATH', (NV_ERR_NOT_COMPATIBLE:=84): 'NV_ERR_NOT_COMPATIBLE', (NV_ERR_NOT_READY:=85): 'NV_ERR_NOT_READY', (NV_ERR_NOT_SUPPORTED:=86): 'NV_ERR_NOT_SUPPORTED', (NV_ERR_OBJECT_NOT_FOUND:=87): 'NV_ERR_OBJECT_NOT_FOUND', (NV_ERR_OBJECT_TYPE_MISMATCH:=88): 'NV_ERR_OBJECT_TYPE_MISMATCH', (NV_ERR_OPERATING_SYSTEM:=89): 'NV_ERR_OPERATING_SYSTEM', (NV_ERR_OTHER_DEVICE_FOUND:=90): 'NV_ERR_OTHER_DEVICE_FOUND', (NV_ERR_OUT_OF_RANGE:=91): 'NV_ERR_OUT_OF_RANGE', (NV_ERR_OVERLAPPING_UVM_COMMIT:=92): 'NV_ERR_OVERLAPPING_UVM_COMMIT', (NV_ERR_PAGE_TABLE_NOT_AVAIL:=93): 'NV_ERR_PAGE_TABLE_NOT_AVAIL', (NV_ERR_PID_NOT_FOUND:=94): 'NV_ERR_PID_NOT_FOUND', (NV_ERR_PROTECTION_FAULT:=95): 'NV_ERR_PROTECTION_FAULT', (NV_ERR_RC_ERROR:=96): 'NV_ERR_RC_ERROR', (NV_ERR_REJECTED_VBIOS:=97): 'NV_ERR_REJECTED_VBIOS', (NV_ERR_RESET_REQUIRED:=98): 'NV_ERR_RESET_REQUIRED', (NV_ERR_STATE_IN_USE:=99): 'NV_ERR_STATE_IN_USE', (NV_ERR_SIGNAL_PENDING:=100): 'NV_ERR_SIGNAL_PENDING', (NV_ERR_TIMEOUT:=101): 'NV_ERR_TIMEOUT', (NV_ERR_TIMEOUT_RETRY:=102): 'NV_ERR_TIMEOUT_RETRY', (NV_ERR_TOO_MANY_PRIMARIES:=103): 'NV_ERR_TOO_MANY_PRIMARIES', (NV_ERR_UVM_ADDRESS_IN_USE:=104): 'NV_ERR_UVM_ADDRESS_IN_USE', (NV_ERR_MAX_SESSION_LIMIT_REACHED:=105): 'NV_ERR_MAX_SESSION_LIMIT_REACHED', (NV_ERR_LIB_RM_VERSION_MISMATCH:=106): 'NV_ERR_LIB_RM_VERSION_MISMATCH', (NV_ERR_PRIV_SEC_VIOLATION:=107): 'NV_ERR_PRIV_SEC_VIOLATION', (NV_ERR_GPU_IN_DEBUG_MODE:=108): 'NV_ERR_GPU_IN_DEBUG_MODE', (NV_ERR_FEATURE_NOT_ENABLED:=109): 'NV_ERR_FEATURE_NOT_ENABLED', (NV_ERR_RESOURCE_LOST:=110): 'NV_ERR_RESOURCE_LOST', (NV_ERR_PMU_NOT_READY:=111): 'NV_ERR_PMU_NOT_READY', (NV_ERR_FLCN_ERROR:=112): 'NV_ERR_FLCN_ERROR', (NV_ERR_FATAL_ERROR:=113): 'NV_ERR_FATAL_ERROR', (NV_ERR_MEMORY_ERROR:=114): 'NV_ERR_MEMORY_ERROR', (NV_ERR_INVALID_LICENSE:=115): 'NV_ERR_INVALID_LICENSE', (NV_ERR_NVLINK_INIT_ERROR:=116): 'NV_ERR_NVLINK_INIT_ERROR', (NV_ERR_NVLINK_MINION_ERROR:=117): 'NV_ERR_NVLINK_MINION_ERROR', (NV_ERR_NVLINK_CLOCK_ERROR:=118): 'NV_ERR_NVLINK_CLOCK_ERROR', (NV_ERR_NVLINK_TRAINING_ERROR:=119): 'NV_ERR_NVLINK_TRAINING_ERROR', (NV_ERR_NVLINK_CONFIGURATION_ERROR:=120): 'NV_ERR_NVLINK_CONFIGURATION_ERROR', (NV_ERR_RISCV_ERROR:=121): 'NV_ERR_RISCV_ERROR', (NV_ERR_FABRIC_MANAGER_NOT_PRESENT:=122): 'NV_ERR_FABRIC_MANAGER_NOT_PRESENT', (NV_ERR_ALREADY_SIGNALLED:=123): 'NV_ERR_ALREADY_SIGNALLED', (NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE:=124): 'NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE', (NV_ERR_KEY_ROTATION_IN_PROGRESS:=125): 'NV_ERR_KEY_ROTATION_IN_PROGRESS', (NV_ERR_TEST_ONLY_CODE_NOT_ENABLED:=126): 'NV_ERR_TEST_ONLY_CODE_NOT_ENABLED', (NV_ERR_SECURE_BOOT_FAILED:=127): 'NV_ERR_SECURE_BOOT_FAILED', (NV_ERR_INSUFFICIENT_ZBC_ENTRY:=128): 'NV_ERR_INSUFFICIENT_ZBC_ENTRY', (NV_ERR_NVLINK_FABRIC_NOT_READY:=129): 'NV_ERR_NVLINK_FABRIC_NOT_READY', (NV_ERR_NVLINK_FABRIC_FAILURE:=130): 'NV_ERR_NVLINK_FABRIC_FAILURE', (NV_ERR_GPU_MEMORY_ONLINING_FAILURE:=131): 'NV_ERR_GPU_MEMORY_ONLINING_FAILURE', (NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE:=132): 'NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE', (NV_ERR_THRESHOLD_CROSSED:=133): 'NV_ERR_THRESHOLD_CROSSED', (NV_ERR_RESOURCE_RETIREMENT_ERROR:=134): 'NV_ERR_RESOURCE_RETIREMENT_ERROR', (NV_ERR_FABRIC_STATE_OUT_OF_SYNC:=135): 'NV_ERR_FABRIC_STATE_OUT_OF_SYNC', (NV_ERR_BUFFER_FULL:=136): 'NV_ERR_BUFFER_FULL', (NV_ERR_BUFFER_EMPTY:=137): 'NV_ERR_BUFFER_EMPTY', (NV_ERR_MC_FLA_OFFSET_TABLE_FULL:=138): 'NV_ERR_MC_FLA_OFFSET_TABLE_FULL', (NV_ERR_OPERATION_ABORTED:=139): 'NV_ERR_OPERATION_ABORTED', (NV_ERR_DMA_XFER_FAILED:=140): 'NV_ERR_DMA_XFER_FAILED', (NV_ERR_RESOURCE_ACCOUNTING_HARD_LIMIT_EXCEEDED:=141): 'NV_ERR_RESOURCE_ACCOUNTING_HARD_LIMIT_EXCEEDED', (NV_WARN_HOT_SWITCH:=65537): 'NV_WARN_HOT_SWITCH', (NV_WARN_INCORRECT_PERFMON_DATA:=65538): 'NV_WARN_INCORRECT_PERFMON_DATA', (NV_WARN_MISMATCHED_SLAVE:=65539): 'NV_WARN_MISMATCHED_SLAVE', (NV_WARN_MISMATCHED_TARGET:=65540): 'NV_WARN_MISMATCHED_TARGET', (NV_WARN_MORE_PROCESSING_REQUIRED:=65541): 'NV_WARN_MORE_PROCESSING_REQUIRED', (NV_WARN_NOTHING_TO_DO:=65542): 'NV_WARN_NOTHING_TO_DO', (NV_WARN_NULL_OBJECT:=65543): 'NV_WARN_NULL_OBJECT', (NV_WARN_OUT_OF_RANGE:=65544): 'NV_WARN_OUT_OF_RANGE', (NV_WARN_THRESHOLD_CROSSED:=65545): 'NV_WARN_THRESHOLD_CROSSED', (NV_WARN_RESOURCE_ACCOUNTING_SOFT_LIMIT_EXCEEDED:=65546): 'NV_WARN_RESOURCE_ACCOUNTING_SOFT_LIMIT_EXCEEDED'}
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NVC9B0_VIDEO_DECODER = (0x0000C9B0)
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NVC9B0_NOP = (0x00000100)
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NVC9B0_NOP_PARAMETER = (31, 0)
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NVC9B0_PM_TRIGGER = (0x00000140)
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NVC9B0_PM_TRIGGER_V = (31, 0)
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NVC9B0_SET_APPLICATION_ID = (0x00000200)
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NVC9B0_SET_APPLICATION_ID_ID = (31, 0)
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NVC9B0_SET_APPLICATION_ID_ID_MPEG12 = (0x00000001)
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NVC9B0_SET_APPLICATION_ID_ID_VC1 = (0x00000002)
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NVC9B0_SET_APPLICATION_ID_ID_H264 = (0x00000003)
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NVC9B0_SET_APPLICATION_ID_ID_MPEG4 = (0x00000004)
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NVC9B0_SET_APPLICATION_ID_ID_VP8 = (0x00000005)
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NVC9B0_SET_APPLICATION_ID_ID_CTR64 = (0x00000006)
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NVC9B0_SET_APPLICATION_ID_ID_HEVC = (0x00000007)
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NVC9B0_SET_APPLICATION_ID_ID_NEW_H264 = (0x00000008)
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NVC9B0_SET_APPLICATION_ID_ID_VP9 = (0x00000009)
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NVC9B0_SET_APPLICATION_ID_ID_PASS1 = (0x0000000A)
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NVC9B0_SET_APPLICATION_ID_ID_HEVC_PARSER = (0x0000000C)
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NVC9B0_SET_APPLICATION_ID_ID_UCODE_TEST = (0x0000000D)
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NVC9B0_SET_APPLICATION_ID_ID_HWDRM_PR_DECRYPTAUDIO = (0x0000000E)
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NVC9B0_SET_APPLICATION_ID_ID_HWDRM_PR_DECRYPTAUDIOMULTIPLE = (0x0000000F)
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NVC9B0_SET_APPLICATION_ID_ID_HWDRM_PR_PREPROCESSENCRYPTEDDATA = (0x00000010)
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NVC9B0_SET_APPLICATION_ID_ID_VP9_WITH_PARSER = (0x00000011)
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NVC9B0_SET_APPLICATION_ID_ID_AVD = (0x00000012)
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NVC9B0_SET_APPLICATION_ID_ID_HW_DRM_PR4_DECRYPTCONTENTMULTIPLE = (0x00000013)
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NVC9B0_SET_APPLICATION_ID_ID_DHKE = (0x00000020)
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NVC9B0_SET_WATCHDOG_TIMER = (0x00000204)
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NVC9B0_SET_WATCHDOG_TIMER_TIMER = (31, 0)
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NVC9B0_SEMAPHORE_A = (0x00000240)
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NVC9B0_SEMAPHORE_A_UPPER = (7, 0)
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NVC9B0_SEMAPHORE_B = (0x00000244)
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NVC9B0_SEMAPHORE_B_LOWER = (31, 0)
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NVC9B0_SEMAPHORE_C = (0x00000248)
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NVC9B0_SEMAPHORE_C_PAYLOAD = (31, 0)
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NVC9B0_CTX_SAVE_AREA = (0x0000024C)
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NVC9B0_CTX_SAVE_AREA_OFFSET = (31, 0)
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NVC9B0_CTX_SWITCH = (0x00000250)
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NVC9B0_CTX_SWITCH_OP = (1, 0)
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NVC9B0_CTX_SWITCH_OP_CTX_UPDATE = (0x00000000)
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NVC9B0_CTX_SWITCH_OP_CTX_SAVE = (0x00000001)
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NVC9B0_CTX_SWITCH_OP_CTX_RESTORE = (0x00000002)
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NVC9B0_CTX_SWITCH_OP_CTX_FORCERESTORE = (0x00000003)
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NVC9B0_CTX_SWITCH_CTXID_VALID = (2, 2)
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NVC9B0_CTX_SWITCH_CTXID_VALID_FALSE = (0x00000000)
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NVC9B0_CTX_SWITCH_CTXID_VALID_TRUE = (0x00000001)
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NVC9B0_CTX_SWITCH_RESERVED0 = (7, 3)
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NVC9B0_CTX_SWITCH_CTX_ID = (23, 8)
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NVC9B0_CTX_SWITCH_RESERVED1 = (31, 24)
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NVC9B0_SET_SEMAPHORE_PAYLOAD_LOWER = (0x00000254)
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NVC9B0_SET_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER = (31, 0)
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NVC9B0_SET_SEMAPHORE_PAYLOAD_UPPER = (0x00000258)
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NVC9B0_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER = (31, 0)
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NVC9B0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_A = (0x0000025C)
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NVC9B0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_A_LOWER = (31, 0)
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NVC9B0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_B = (0x00000260)
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NVC9B0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_B_UPPER = (31, 0)
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NVC9B0_EXECUTE = (0x00000300)
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NVC9B0_EXECUTE_NOTIFY = (0, 0)
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NVC9B0_EXECUTE_NOTIFY_DISABLE = (0x00000000)
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NVC9B0_EXECUTE_NOTIFY_ENABLE = (0x00000001)
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NVC9B0_EXECUTE_NOTIFY_ON = (1, 1)
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NVC9B0_EXECUTE_NOTIFY_ON_END = (0x00000000)
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NVC9B0_EXECUTE_NOTIFY_ON_BEGIN = (0x00000001)
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NVC9B0_EXECUTE_PREDICATION = (2, 2)
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NVC9B0_EXECUTE_PREDICATION_DISABLE = (0x00000000)
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NVC9B0_EXECUTE_PREDICATION_ENABLE = (0x00000001)
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NVC9B0_EXECUTE_PREDICATION_OP = (3, 3)
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NVC9B0_EXECUTE_PREDICATION_OP_EQUAL_ZERO = (0x00000000)
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NVC9B0_EXECUTE_PREDICATION_OP_NOT_EQUAL_ZERO = (0x00000001)
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NVC9B0_EXECUTE_AWAKEN = (8, 8)
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NVC9B0_EXECUTE_AWAKEN_DISABLE = (0x00000000)
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NVC9B0_EXECUTE_AWAKEN_ENABLE = (0x00000001)
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NVC9B0_SEMAPHORE_D = (0x00000304)
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NVC9B0_SEMAPHORE_D_STRUCTURE_SIZE = (1, 0)
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NVC9B0_SEMAPHORE_D_STRUCTURE_SIZE_ONE = (0x00000000)
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NVC9B0_SEMAPHORE_D_STRUCTURE_SIZE_FOUR = (0x00000001)
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NVC9B0_SEMAPHORE_D_STRUCTURE_SIZE_TWO = (0x00000002)
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NVC9B0_SEMAPHORE_D_AWAKEN_ENABLE = (8, 8)
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NVC9B0_SEMAPHORE_D_AWAKEN_ENABLE_FALSE = (0x00000000)
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NVC9B0_SEMAPHORE_D_AWAKEN_ENABLE_TRUE = (0x00000001)
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NVC9B0_SEMAPHORE_D_OPERATION = (17, 16)
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NVC9B0_SEMAPHORE_D_OPERATION_RELEASE = (0x00000000)
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NVC9B0_SEMAPHORE_D_OPERATION_RESERVED_0 = (0x00000001)
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NVC9B0_SEMAPHORE_D_OPERATION_RESERVED_1 = (0x00000002)
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NVC9B0_SEMAPHORE_D_OPERATION_TRAP = (0x00000003)
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NVC9B0_SEMAPHORE_D_FLUSH_DISABLE = (21, 21)
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NVC9B0_SEMAPHORE_D_FLUSH_DISABLE_FALSE = (0x00000000)
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NVC9B0_SEMAPHORE_D_FLUSH_DISABLE_TRUE = (0x00000001)
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NVC9B0_SEMAPHORE_D_TRAP_TYPE = (23, 22)
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NVC9B0_SEMAPHORE_D_TRAP_TYPE_UNCONDITIONAL = (0x00000000)
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NVC9B0_SEMAPHORE_D_TRAP_TYPE_CONDITIONAL = (0x00000001)
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NVC9B0_SEMAPHORE_D_TRAP_TYPE_CONDITIONAL_EXT = (0x00000002)
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NVC9B0_SEMAPHORE_D_PAYLOAD_SIZE = (24, 24)
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NVC9B0_SEMAPHORE_D_PAYLOAD_SIZE_32BIT = (0x00000000)
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NVC9B0_SEMAPHORE_D_PAYLOAD_SIZE_64BIT = (0x00000001)
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NVC9B0_SET_PREDICATION_OFFSET_UPPER = (0x00000308)
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NVC9B0_SET_PREDICATION_OFFSET_UPPER_OFFSET = (7, 0)
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NVC9B0_SET_PREDICATION_OFFSET_LOWER = (0x0000030C)
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NVC9B0_SET_PREDICATION_OFFSET_LOWER_OFFSET = (31, 0)
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NVC9B0_SET_AUXILIARY_DATA_BUFFER = (0x00000310)
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NVC9B0_SET_AUXILIARY_DATA_BUFFER_OFFSET = (31, 0)
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NVC9B0_SET_CONTROL_PARAMS = (0x00000400)
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NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE = (3, 0)
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NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_MPEG1 = (0x00000000)
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NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_MPEG2 = (0x00000001)
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NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_VC1 = (0x00000002)
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NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_H264 = (0x00000003)
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NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_MPEG4 = (0x00000004)
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NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_DIVX3 = (0x00000004)
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NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_VP8 = (0x00000005)
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NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_HEVC = (0x00000007)
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NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_VP9 = (0x00000009)
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NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_AV1 = (0x0000000A)
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NVC9B0_SET_CONTROL_PARAMS_GPTIMER_ON = (4, 4)
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NVC9B0_SET_CONTROL_PARAMS_RET_ERROR = (5, 5)
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NVC9B0_SET_CONTROL_PARAMS_ERR_CONCEAL_ON = (6, 6)
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NVC9B0_SET_CONTROL_PARAMS_ERROR_FRM_IDX = (12, 7)
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NVC9B0_SET_CONTROL_PARAMS_MBTIMER_ON = (13, 13)
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NVC9B0_SET_CONTROL_PARAMS_EC_INTRA_FRAME_USING_PSLC = (14, 14)
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NVC9B0_SET_CONTROL_PARAMS_IGNORE_SOME_FIELDS_CRC_CHECK = (15, 15)
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NVC9B0_SET_CONTROL_PARAMS_EVENT_TRACE_LOGGING_ON = (16, 16)
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NVC9B0_SET_CONTROL_PARAMS_ALL_INTRA_FRAME = (17, 17)
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NVC9B0_SET_CONTROL_PARAMS_TESTRUN_ENV = (19, 18)
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NVC9B0_SET_CONTROL_PARAMS_TESTRUN_ENV_TRACE3D_RUN = (0x00000000)
|
|
NVC9B0_SET_CONTROL_PARAMS_TESTRUN_ENV_PROD_RUN = (0x00000001)
|
|
NVC9B0_SET_CONTROL_PARAMS_HINT_DUMP_EN = (20, 20)
|
|
NVC9B0_SET_CONTROL_PARAMS_RESERVED = (25, 21)
|
|
NVC9B0_SET_CONTROL_PARAMS_NVDECSIM_SKIP_SCP = (26, 26)
|
|
NVC9B0_SET_CONTROL_PARAMS_ENABLE_ENCRYPT = (27, 27)
|
|
NVC9B0_SET_CONTROL_PARAMS_ENCRYPTMODE = (31, 28)
|
|
NVC9B0_SET_DRV_PIC_SETUP_OFFSET = (0x00000404)
|
|
NVC9B0_SET_DRV_PIC_SETUP_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_IN_BUF_BASE_OFFSET = (0x00000408)
|
|
NVC9B0_SET_IN_BUF_BASE_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_INDEX = (0x0000040C)
|
|
NVC9B0_SET_PICTURE_INDEX_INDEX = (31, 0)
|
|
NVC9B0_SET_SLICE_OFFSETS_BUF_OFFSET = (0x00000410)
|
|
NVC9B0_SET_SLICE_OFFSETS_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_COLOC_DATA_OFFSET = (0x00000414)
|
|
NVC9B0_SET_COLOC_DATA_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_HISTORY_OFFSET = (0x00000418)
|
|
NVC9B0_SET_HISTORY_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_DISPLAY_BUF_SIZE = (0x0000041C)
|
|
NVC9B0_SET_DISPLAY_BUF_SIZE_SIZE = (31, 0)
|
|
NVC9B0_SET_HISTOGRAM_OFFSET = (0x00000420)
|
|
NVC9B0_SET_HISTOGRAM_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_NVDEC_STATUS_OFFSET = (0x00000424)
|
|
NVC9B0_SET_NVDEC_STATUS_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_DISPLAY_BUF_LUMA_OFFSET = (0x00000428)
|
|
NVC9B0_SET_DISPLAY_BUF_LUMA_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_DISPLAY_BUF_CHROMA_OFFSET = (0x0000042C)
|
|
NVC9B0_SET_DISPLAY_BUF_CHROMA_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET0 = (0x00000430)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET0_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET1 = (0x00000434)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET1_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET2 = (0x00000438)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET2_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET3 = (0x0000043C)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET3_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET4 = (0x00000440)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET4_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET5 = (0x00000444)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET5_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET6 = (0x00000448)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET6_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET7 = (0x0000044C)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET7_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET8 = (0x00000450)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET8_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET9 = (0x00000454)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET9_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET10 = (0x00000458)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET10_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET11 = (0x0000045C)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET11_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET12 = (0x00000460)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET12_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET13 = (0x00000464)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET13_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET14 = (0x00000468)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET14_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET15 = (0x0000046C)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET15_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET16 = (0x00000470)
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET16_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET0 = (0x00000474)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET0_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET1 = (0x00000478)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET1_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET2 = (0x0000047C)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET2_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET3 = (0x00000480)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET3_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET4 = (0x00000484)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET4_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET5 = (0x00000488)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET5_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET6 = (0x0000048C)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET6_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET7 = (0x00000490)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET7_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET8 = (0x00000494)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET8_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET9 = (0x00000498)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET9_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET10 = (0x0000049C)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET10_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET11 = (0x000004A0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET11_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET12 = (0x000004A4)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET12_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET13 = (0x000004A8)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET13_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET14 = (0x000004AC)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET14_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET15 = (0x000004B0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET15_OFFSET = (31, 0)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET16 = (0x000004B4)
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET16_OFFSET = (31, 0)
|
|
NVC9B0_SET_PIC_SCRATCH_BUF_OFFSET = (0x000004B8)
|
|
NVC9B0_SET_PIC_SCRATCH_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_EXTERNAL_MVBUFFER_OFFSET = (0x000004BC)
|
|
NVC9B0_SET_EXTERNAL_MVBUFFER_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_SUB_SAMPLE_MAP_OFFSET = (0x000004C0)
|
|
NVC9B0_SET_SUB_SAMPLE_MAP_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_SUB_SAMPLE_MAP_IV_OFFSET = (0x000004C4)
|
|
NVC9B0_SET_SUB_SAMPLE_MAP_IV_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_INTRA_TOP_BUF_OFFSET = (0x000004C8)
|
|
NVC9B0_SET_INTRA_TOP_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_TILE_SIZE_BUF_OFFSET = (0x000004CC)
|
|
NVC9B0_SET_TILE_SIZE_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_FILTER_BUFFER_OFFSET = (0x000004D0)
|
|
NVC9B0_SET_FILTER_BUFFER_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_CRC_STRUCT_OFFSET = (0x000004D4)
|
|
NVC9B0_SET_CRC_STRUCT_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_PR_SSM_CONTENT_INFO_BUF_OFFSET = (0x000004D8)
|
|
NVC9B0_SET_PR_SSM_CONTENT_INFO_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_H264_SET_MBHIST_BUF_OFFSET = (0x00000500)
|
|
NVC9B0_H264_SET_MBHIST_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP8_SET_PROB_DATA_OFFSET = (0x00000540)
|
|
NVC9B0_VP8_SET_PROB_DATA_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP8_SET_HEADER_PARTITION_BUF_BASE_OFFSET = (0x00000544)
|
|
NVC9B0_VP8_SET_HEADER_PARTITION_BUF_BASE_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_HEVC_SET_SCALING_LIST_OFFSET = (0x00000580)
|
|
NVC9B0_HEVC_SET_SCALING_LIST_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_HEVC_SET_TILE_SIZES_OFFSET = (0x00000584)
|
|
NVC9B0_HEVC_SET_TILE_SIZES_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_HEVC_SET_FILTER_BUFFER_OFFSET = (0x00000588)
|
|
NVC9B0_HEVC_SET_FILTER_BUFFER_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_HEVC_SET_SAO_BUFFER_OFFSET = (0x0000058C)
|
|
NVC9B0_HEVC_SET_SAO_BUFFER_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_HEVC_SET_SLICE_INFO_BUFFER_OFFSET = (0x00000590)
|
|
NVC9B0_HEVC_SET_SLICE_INFO_BUFFER_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_HEVC_SET_SLICE_GROUP_INDEX = (0x00000594)
|
|
NVC9B0_HEVC_SET_SLICE_GROUP_INDEX_OFFSET = (31, 0)
|
|
NVC9B0_VP9_SET_PROB_TAB_BUF_OFFSET = (0x000005C0)
|
|
NVC9B0_VP9_SET_PROB_TAB_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP9_SET_CTX_COUNTER_BUF_OFFSET = (0x000005C4)
|
|
NVC9B0_VP9_SET_CTX_COUNTER_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP9_SET_SEGMENT_READ_BUF_OFFSET = (0x000005C8)
|
|
NVC9B0_VP9_SET_SEGMENT_READ_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP9_SET_SEGMENT_WRITE_BUF_OFFSET = (0x000005CC)
|
|
NVC9B0_VP9_SET_SEGMENT_WRITE_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP9_SET_TILE_SIZE_BUF_OFFSET = (0x000005D0)
|
|
NVC9B0_VP9_SET_TILE_SIZE_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP9_SET_COL_MVWRITE_BUF_OFFSET = (0x000005D4)
|
|
NVC9B0_VP9_SET_COL_MVWRITE_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP9_SET_COL_MVREAD_BUF_OFFSET = (0x000005D8)
|
|
NVC9B0_VP9_SET_COL_MVREAD_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP9_SET_FILTER_BUFFER_OFFSET = (0x000005DC)
|
|
NVC9B0_VP9_SET_FILTER_BUFFER_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP9_PARSER_SET_PIC_SETUP_OFFSET = (0x000005E0)
|
|
NVC9B0_VP9_PARSER_SET_PIC_SETUP_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP9_PARSER_SET_PREV_PIC_SETUP_OFFSET = (0x000005E4)
|
|
NVC9B0_VP9_PARSER_SET_PREV_PIC_SETUP_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP9_PARSER_SET_PROB_TAB_BUF_OFFSET = (0x000005E8)
|
|
NVC9B0_VP9_PARSER_SET_PROB_TAB_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_VP9_SET_HINT_DUMP_BUF_OFFSET = (0x000005EC)
|
|
NVC9B0_VP9_SET_HINT_DUMP_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_PASS1_SET_CLEAR_HEADER_OFFSET = (0x00000600)
|
|
NVC9B0_PASS1_SET_CLEAR_HEADER_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_PASS1_SET_RE_ENCRYPT_OFFSET = (0x00000604)
|
|
NVC9B0_PASS1_SET_RE_ENCRYPT_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_PASS1_SET_VP8_TOKEN_OFFSET = (0x00000608)
|
|
NVC9B0_PASS1_SET_VP8_TOKEN_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_PASS1_SET_INPUT_DATA_OFFSET = (0x0000060C)
|
|
NVC9B0_PASS1_SET_INPUT_DATA_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_PASS1_SET_OUTPUT_DATA_SIZE_OFFSET = (0x00000610)
|
|
NVC9B0_PASS1_SET_OUTPUT_DATA_SIZE_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_PROB_TAB_READ_BUF_OFFSET = (0x00000640)
|
|
NVC9B0_AV1_SET_PROB_TAB_READ_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_PROB_TAB_WRITE_BUF_OFFSET = (0x00000644)
|
|
NVC9B0_AV1_SET_PROB_TAB_WRITE_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_SEGMENT_READ_BUF_OFFSET = (0x00000648)
|
|
NVC9B0_AV1_SET_SEGMENT_READ_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_SEGMENT_WRITE_BUF_OFFSET = (0x0000064C)
|
|
NVC9B0_AV1_SET_SEGMENT_WRITE_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_COL_MV0_READ_BUF_OFFSET = (0x00000650)
|
|
NVC9B0_AV1_SET_COL_MV0_READ_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_COL_MV1_READ_BUF_OFFSET = (0x00000654)
|
|
NVC9B0_AV1_SET_COL_MV1_READ_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_COL_MV2_READ_BUF_OFFSET = (0x00000658)
|
|
NVC9B0_AV1_SET_COL_MV2_READ_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_COL_MVWRITE_BUF_OFFSET = (0x0000065C)
|
|
NVC9B0_AV1_SET_COL_MVWRITE_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_GLOBAL_MODEL_BUF_OFFSET = (0x00000660)
|
|
NVC9B0_AV1_SET_GLOBAL_MODEL_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_FILM_GRAIN_BUF_OFFSET = (0x00000664)
|
|
NVC9B0_AV1_SET_FILM_GRAIN_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_TILE_STREAM_INFO_BUF_OFFSET = (0x00000668)
|
|
NVC9B0_AV1_SET_TILE_STREAM_INFO_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_SUB_STREAM_ENTRY_BUF_OFFSET = (0x0000066C)
|
|
NVC9B0_AV1_SET_SUB_STREAM_ENTRY_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_AV1_SET_HINT_DUMP_BUF_OFFSET = (0x00000670)
|
|
NVC9B0_AV1_SET_HINT_DUMP_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_H264_SET_SCALING_LIST_OFFSET = (0x00000680)
|
|
NVC9B0_H264_SET_SCALING_LIST_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_H264_SET_VLDHIST_BUF_OFFSET = (0x00000684)
|
|
NVC9B0_H264_SET_VLDHIST_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_H264_SET_EDOBOFFSET0 = (0x00000688)
|
|
NVC9B0_H264_SET_EDOBOFFSET0_OFFSET = (31, 0)
|
|
NVC9B0_H264_SET_EDOBOFFSET1 = (0x0000068C)
|
|
NVC9B0_H264_SET_EDOBOFFSET1_OFFSET = (31, 0)
|
|
NVC9B0_H264_SET_EDOBOFFSET2 = (0x00000690)
|
|
NVC9B0_H264_SET_EDOBOFFSET2_OFFSET = (31, 0)
|
|
NVC9B0_H264_SET_EDOBOFFSET3 = (0x00000694)
|
|
NVC9B0_H264_SET_EDOBOFFSET3_OFFSET = (31, 0)
|
|
NVC9B0_SET_CONTENT_INITIAL_VECTOR = lambda b: (0x00000C00 + (b)*0x00000004) # type: ignore
|
|
NVC9B0_SET_CONTENT_INITIAL_VECTOR_VALUE = (31, 0)
|
|
NVC9B0_SET_CTL_COUNT = (0x00000C10)
|
|
NVC9B0_SET_CTL_COUNT_VALUE = (31, 0)
|
|
NVC9B0_SET_UPPER_SRC = (0x00000C14)
|
|
NVC9B0_SET_UPPER_SRC_OFFSET = (7, 0)
|
|
NVC9B0_SET_LOWER_SRC = (0x00000C18)
|
|
NVC9B0_SET_LOWER_SRC_OFFSET = (31, 0)
|
|
NVC9B0_SET_UPPER_DST = (0x00000C1C)
|
|
NVC9B0_SET_UPPER_DST_OFFSET = (7, 0)
|
|
NVC9B0_SET_LOWER_DST = (0x00000C20)
|
|
NVC9B0_SET_LOWER_DST_OFFSET = (31, 0)
|
|
NVC9B0_SET_BLOCK_COUNT = (0x00000C24)
|
|
NVC9B0_SET_BLOCK_COUNT_VALUE = (31, 0)
|
|
NVC9B0_PR_SET_REQUEST_BUF_OFFSET = (0x00000D00)
|
|
NVC9B0_PR_SET_REQUEST_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_PR_SET_REQUEST_BUF_SIZE = (0x00000D04)
|
|
NVC9B0_PR_SET_REQUEST_BUF_SIZE_SIZE = (31, 0)
|
|
NVC9B0_PR_SET_RESPONSE_BUF_OFFSET = (0x00000D08)
|
|
NVC9B0_PR_SET_RESPONSE_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_PR_SET_RESPONSE_BUF_SIZE = (0x00000D0C)
|
|
NVC9B0_PR_SET_RESPONSE_BUF_SIZE_SIZE = (31, 0)
|
|
NVC9B0_PR_SET_REQUEST_MESSAGE_BUF_OFFSET = (0x00000D10)
|
|
NVC9B0_PR_SET_REQUEST_MESSAGE_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_PR_SET_RESPONSE_MESSAGE_BUF_OFFSET = (0x00000D14)
|
|
NVC9B0_PR_SET_RESPONSE_MESSAGE_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_PR_SET_LOCAL_DECRYPT_BUF_OFFSET = (0x00000D18)
|
|
NVC9B0_PR_SET_LOCAL_DECRYPT_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_PR_SET_LOCAL_DECRYPT_BUF_SIZE = (0x00000D1C)
|
|
NVC9B0_PR_SET_LOCAL_DECRYPT_BUF_SIZE_SIZE = (31, 0)
|
|
NVC9B0_PR_SET_CONTENT_DECRYPT_INFO_BUF_OFFSET = (0x00000D20)
|
|
NVC9B0_PR_SET_CONTENT_DECRYPT_INFO_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_PR_SET_REENCRYPTED_BITSTREAM_BUF_OFFSET = (0x00000D24)
|
|
NVC9B0_PR_SET_REENCRYPTED_BITSTREAM_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_DH_KE_SET_CHALLENGE_BUF_OFFSET = (0x00000E00)
|
|
NVC9B0_DH_KE_SET_CHALLENGE_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_DH_KE_SET_RESPONSE_BUF_OFFSET = (0x00000E04)
|
|
NVC9B0_DH_KE_SET_RESPONSE_BUF_OFFSET_OFFSET = (31, 0)
|
|
NVC9B0_SET_SESSION_KEY = lambda b: (0x00000F00 + (b)*0x00000004) # type: ignore
|
|
NVC9B0_SET_SESSION_KEY_VALUE = (31, 0)
|
|
NVC9B0_SET_CONTENT_KEY = lambda b: (0x00000F10 + (b)*0x00000004) # type: ignore
|
|
NVC9B0_SET_CONTENT_KEY_VALUE = (31, 0)
|
|
NVC9B0_PM_TRIGGER_END = (0x00001114)
|
|
NVC9B0_PM_TRIGGER_END_V = (31, 0)
|
|
NVC9B0_ERROR_NONE = (0x00000000)
|
|
NVC9B0_OS_ERROR_EXECUTE_INSUFFICIENT_DATA = (0x00000001)
|
|
NVC9B0_OS_ERROR_SEMAPHORE_INSUFFICIENT_DATA = (0x00000002)
|
|
NVC9B0_OS_ERROR_INVALID_METHOD = (0x00000003)
|
|
NVC9B0_OS_ERROR_INVALID_DMA_PAGE = (0x00000004)
|
|
NVC9B0_OS_ERROR_UNHANDLED_INTERRUPT = (0x00000005)
|
|
NVC9B0_OS_ERROR_EXCEPTION = (0x00000006)
|
|
NVC9B0_OS_ERROR_INVALID_CTXSW_REQUEST = (0x00000007)
|
|
NVC9B0_OS_ERROR_APPLICATION = (0x00000008)
|
|
NVC9B0_OS_ERROR_SW_BREAKPT = (0x00000009)
|
|
NVC9B0_OS_INTERRUPT_EXECUTE_AWAKEN = (0x00000100)
|
|
NVC9B0_OS_INTERRUPT_BACKEND_SEMAPHORE_AWAKEN = (0x00000200)
|
|
NVC9B0_OS_INTERRUPT_CTX_ERROR_FBIF = (0x00000300)
|
|
NVC9B0_OS_INTERRUPT_LIMIT_VIOLATION = (0x00000400)
|
|
NVC9B0_OS_INTERRUPT_LIMIT_AND_FBIF_CTX_ERROR = (0x00000500)
|
|
NVC9B0_OS_INTERRUPT_HALT_ENGINE = (0x00000600)
|
|
NVC9B0_OS_INTERRUPT_TRAP_NONSTALL = (0x00000700)
|
|
NVC9B0_H264_VLD_ERR_SEQ_DATA_INCONSISTENT = (0x00004001)
|
|
NVC9B0_H264_VLD_ERR_PIC_DATA_INCONSISTENT = (0x00004002)
|
|
NVC9B0_H264_VLD_ERR_SLC_DATA_BUF_ADDR_OUT_OF_BOUNDS = (0x00004100)
|
|
NVC9B0_H264_VLD_ERR_BITSTREAM_ERROR = (0x00004101)
|
|
NVC9B0_H264_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID = (0x000041F8)
|
|
NVC9B0_H264_VLD_ERR_SLC_HDR_OUT_SIZE_NOT_MULT256 = (0x00004200)
|
|
NVC9B0_H264_VLD_ERR_SLC_DATA_OUT_SIZE_NOT_MULT256 = (0x00004201)
|
|
NVC9B0_H264_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID = (0x00004203)
|
|
NVC9B0_H264_VLD_ERR_CTX_DMA_ID_SLC_HDR_OUT_INVALID = (0x00004204)
|
|
NVC9B0_H264_VLD_ERR_SLC_HDR_OUT_BUF_TOO_SMALL = (0x00004205)
|
|
NVC9B0_H264_VLD_ERR_SLC_HDR_OUT_BUF_ALREADY_VALID = (0x00004206)
|
|
NVC9B0_H264_VLD_ERR_SLC_DATA_OUT_BUF_TOO_SMALL = (0x00004207)
|
|
NVC9B0_H264_VLD_ERR_DATA_BUF_CNT_TOO_SMALL = (0x00004208)
|
|
NVC9B0_H264_VLD_ERR_BITSTREAM_EMPTY = (0x00004209)
|
|
NVC9B0_H264_VLD_ERR_FRAME_WIDTH_TOO_LARGE = (0x0000420A)
|
|
NVC9B0_H264_VLD_ERR_FRAME_HEIGHT_TOO_LARGE = (0x0000420B)
|
|
NVC9B0_H264_VLD_ERR_HIST_BUF_TOO_SMALL = (0x00004300)
|
|
NVC9B0_VC1_VLD_ERR_PIC_DATA_BUF_ADDR_OUT_OF_BOUND = (0x00005100)
|
|
NVC9B0_VC1_VLD_ERR_BITSTREAM_ERROR = (0x00005101)
|
|
NVC9B0_VC1_VLD_ERR_PIC_HDR_OUT_SIZE_NOT_MULT256 = (0x00005200)
|
|
NVC9B0_VC1_VLD_ERR_PIC_DATA_OUT_SIZE_NOT_MULT256 = (0x00005201)
|
|
NVC9B0_VC1_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID = (0x00005202)
|
|
NVC9B0_VC1_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID = (0x00005203)
|
|
NVC9B0_VC1_VLD_ERR_CTX_DMA_ID_PIC_HDR_OUT_INVALID = (0x00005204)
|
|
NVC9B0_VC1_VLD_ERR_SLC_HDR_OUT_BUF_TOO_SMALL = (0x00005205)
|
|
NVC9B0_VC1_VLD_ERR_PIC_HDR_OUT_BUF_ALREADY_VALID = (0x00005206)
|
|
NVC9B0_VC1_VLD_ERR_PIC_DATA_OUT_BUF_TOO_SMALL = (0x00005207)
|
|
NVC9B0_VC1_VLD_ERR_DATA_INFO_IN_BUF_TOO_SMALL = (0x00005208)
|
|
NVC9B0_VC1_VLD_ERR_BITSTREAM_EMPTY = (0x00005209)
|
|
NVC9B0_VC1_VLD_ERR_FRAME_WIDTH_TOO_LARGE = (0x0000520A)
|
|
NVC9B0_VC1_VLD_ERR_FRAME_HEIGHT_TOO_LARGE = (0x0000520B)
|
|
NVC9B0_VC1_VLD_ERR_PIC_DATA_OUT_BUF_FULL_TIME_OUT = (0x00005300)
|
|
NVC9B0_MPEG12_VLD_ERR_SLC_DATA_BUF_ADDR_OUT_OF_BOUNDS = (0x00006100)
|
|
NVC9B0_MPEG12_VLD_ERR_BITSTREAM_ERROR = (0x00006101)
|
|
NVC9B0_MPEG12_VLD_ERR_SLC_DATA_OUT_SIZE_NOT_MULT256 = (0x00006200)
|
|
NVC9B0_MPEG12_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID = (0x00006201)
|
|
NVC9B0_MPEG12_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID = (0x00006202)
|
|
NVC9B0_MPEG12_VLD_ERR_SLC_DATA_OUT_BUF_TOO_SMALL = (0x00006203)
|
|
NVC9B0_MPEG12_VLD_ERR_DATA_INFO_IN_BUF_TOO_SMALL = (0x00006204)
|
|
NVC9B0_MPEG12_VLD_ERR_BITSTREAM_EMPTY = (0x00006205)
|
|
NVC9B0_MPEG12_VLD_ERR_INVALID_PIC_STRUCTURE = (0x00006206)
|
|
NVC9B0_MPEG12_VLD_ERR_INVALID_PIC_CODING_TYPE = (0x00006207)
|
|
NVC9B0_MPEG12_VLD_ERR_FRAME_WIDTH_TOO_LARGE = (0x00006208)
|
|
NVC9B0_MPEG12_VLD_ERR_FRAME_HEIGHT_TOO_LARGE = (0x00006209)
|
|
NVC9B0_MPEG12_VLD_ERR_SLC_DATA_OUT_BUF_FULL_TIME_OUT = (0x00006300)
|
|
NVC9B0_CMN_VLD_ERR_PDEC_RETURNED_ERROR = (0x00007101)
|
|
NVC9B0_CMN_VLD_ERR_EDOB_FLUSH_TIME_OUT = (0x00007102)
|
|
NVC9B0_CMN_VLD_ERR_EDOB_REWIND_TIME_OUT = (0x00007103)
|
|
NVC9B0_CMN_VLD_ERR_VLD_WD_TIME_OUT = (0x00007104)
|
|
NVC9B0_CMN_VLD_ERR_NUM_SLICES_ZERO = (0x00007105)
|
|
NVC9B0_MPEG4_VLD_ERR_PIC_DATA_BUF_ADDR_OUT_OF_BOUND = (0x00008100)
|
|
NVC9B0_MPEG4_VLD_ERR_BITSTREAM_ERROR = (0x00008101)
|
|
NVC9B0_MPEG4_VLD_ERR_PIC_HDR_OUT_SIZE_NOT_MULT256 = (0x00008200)
|
|
NVC9B0_MPEG4_VLD_ERR_PIC_DATA_OUT_SIZE_NOT_MULT256 = (0x00008201)
|
|
NVC9B0_MPEG4_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID = (0x00008202)
|
|
NVC9B0_MPEG4_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID = (0x00008203)
|
|
NVC9B0_MPEG4_VLD_ERR_CTX_DMA_ID_PIC_HDR_OUT_INVALID = (0x00008204)
|
|
NVC9B0_MPEG4_VLD_ERR_SLC_HDR_OUT_BUF_TOO_SMALL = (0x00008205)
|
|
NVC9B0_MPEG4_VLD_ERR_PIC_HDR_OUT_BUF_ALREADY_VALID = (0x00008206)
|
|
NVC9B0_MPEG4_VLD_ERR_PIC_DATA_OUT_BUF_TOO_SMALL = (0x00008207)
|
|
NVC9B0_MPEG4_VLD_ERR_DATA_INFO_IN_BUF_TOO_SMALL = (0x00008208)
|
|
NVC9B0_MPEG4_VLD_ERR_BITSTREAM_EMPTY = (0x00008209)
|
|
NVC9B0_MPEG4_VLD_ERR_FRAME_WIDTH_TOO_LARGE = (0x0000820A)
|
|
NVC9B0_MPEG4_VLD_ERR_FRAME_HEIGHT_TOO_LARGE = (0x0000820B)
|
|
NVC9B0_MPEG4_VLD_ERR_PIC_DATA_OUT_BUF_FULL_TIME_OUT = (0x00051E01)
|
|
NVC9B0_DEC_ERROR_MPEG12_APPTIMER_EXPIRED = (0xDEC10001)
|
|
NVC9B0_DEC_ERROR_MPEG12_MVTIMER_EXPIRED = (0xDEC10002)
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_TOKEN = (0xDEC10003)
|
|
NVC9B0_DEC_ERROR_MPEG12_SLICEDATA_MISSING = (0xDEC10004)
|
|
NVC9B0_DEC_ERROR_MPEG12_HWERR_INTERRUPT = (0xDEC10005)
|
|
NVC9B0_DEC_ERROR_MPEG12_DETECTED_VLD_FAILURE = (0xDEC10006)
|
|
NVC9B0_DEC_ERROR_MPEG12_PICTURE_INIT = (0xDEC10100)
|
|
NVC9B0_DEC_ERROR_MPEG12_STATEMACHINE_FAILURE = (0xDEC10101)
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_CTXID_PIC = (0xDEC10901)
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_CTXID_UCODE = (0xDEC10902)
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_CTXID_FC = (0xDEC10903)
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_CTXID_SLH = (0xDEC10904)
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_UCODE_SIZE = (0xDEC10905)
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_SLICE_COUNT = (0xDEC10906)
|
|
NVC9B0_DEC_ERROR_VC1_APPTIMER_EXPIRED = (0xDEC20001)
|
|
NVC9B0_DEC_ERROR_VC1_MVTIMER_EXPIRED = (0xDEC20002)
|
|
NVC9B0_DEC_ERROR_VC1_INVALID_TOKEN = (0xDEC20003)
|
|
NVC9B0_DEC_ERROR_VC1_SLICEDATA_MISSING = (0xDEC20004)
|
|
NVC9B0_DEC_ERROR_VC1_HWERR_INTERRUPT = (0xDEC20005)
|
|
NVC9B0_DEC_ERROR_VC1_DETECTED_VLD_FAILURE = (0xDEC20006)
|
|
NVC9B0_DEC_ERROR_VC1_TIMEOUT_POLLING_FOR_DATA = (0xDEC20007)
|
|
NVC9B0_DEC_ERROR_VC1_PDEC_PIC_END_UNALIGNED = (0xDEC20008)
|
|
NVC9B0_DEC_ERROR_VC1_WDTIMER_EXPIRED = (0xDEC20009)
|
|
NVC9B0_DEC_ERROR_VC1_ERRINTSTART = (0xDEC20010)
|
|
NVC9B0_DEC_ERROR_VC1_IQT_ERRINT = (0xDEC20011)
|
|
NVC9B0_DEC_ERROR_VC1_MC_ERRINT = (0xDEC20012)
|
|
NVC9B0_DEC_ERROR_VC1_MC_IQT_ERRINT = (0xDEC20013)
|
|
NVC9B0_DEC_ERROR_VC1_REC_ERRINT = (0xDEC20014)
|
|
NVC9B0_DEC_ERROR_VC1_REC_IQT_ERRINT = (0xDEC20015)
|
|
NVC9B0_DEC_ERROR_VC1_REC_MC_ERRINT = (0xDEC20016)
|
|
NVC9B0_DEC_ERROR_VC1_REC_MC_IQT_ERRINT = (0xDEC20017)
|
|
NVC9B0_DEC_ERROR_VC1_DBF_ERRINT = (0xDEC20018)
|
|
NVC9B0_DEC_ERROR_VC1_DBF_IQT_ERRINT = (0xDEC20019)
|
|
NVC9B0_DEC_ERROR_VC1_DBF_MC_ERRINT = (0xDEC2001A)
|
|
NVC9B0_DEC_ERROR_VC1_DBF_MC_IQT_ERRINT = (0xDEC2001B)
|
|
NVC9B0_DEC_ERROR_VC1_DBF_REC_ERRINT = (0xDEC2001C)
|
|
NVC9B0_DEC_ERROR_VC1_DBF_REC_IQT_ERRINT = (0xDEC2001D)
|
|
NVC9B0_DEC_ERROR_VC1_DBF_REC_MC_ERRINT = (0xDEC2001E)
|
|
NVC9B0_DEC_ERROR_VC1_DBF_REC_MC_IQT_ERRINT = (0xDEC2001F)
|
|
NVC9B0_DEC_ERROR_VC1_PICTURE_INIT = (0xDEC20100)
|
|
NVC9B0_DEC_ERROR_VC1_STATEMACHINE_FAILURE = (0xDEC20101)
|
|
NVC9B0_DEC_ERROR_VC1_INVALID_CTXID_PIC = (0xDEC20901)
|
|
NVC9B0_DEC_ERROR_VC1_INVALID_CTXID_UCODE = (0xDEC20902)
|
|
NVC9B0_DEC_ERROR_VC1_INVALID_CTXID_FC = (0xDEC20903)
|
|
NVC9B0_DEC_ERROR_VC1_INVAILD_CTXID_SLH = (0xDEC20904)
|
|
NVC9B0_DEC_ERROR_VC1_INVALID_UCODE_SIZE = (0xDEC20905)
|
|
NVC9B0_DEC_ERROR_VC1_INVALID_SLICE_COUNT = (0xDEC20906)
|
|
NVC9B0_DEC_ERROR_H264_APPTIMER_EXPIRED = (0xDEC30001)
|
|
NVC9B0_DEC_ERROR_H264_MVTIMER_EXPIRED = (0xDEC30002)
|
|
NVC9B0_DEC_ERROR_H264_INVALID_TOKEN = (0xDEC30003)
|
|
NVC9B0_DEC_ERROR_H264_SLICEDATA_MISSING = (0xDEC30004)
|
|
NVC9B0_DEC_ERROR_H264_HWERR_INTERRUPT = (0xDEC30005)
|
|
NVC9B0_DEC_ERROR_H264_DETECTED_VLD_FAILURE = (0xDEC30006)
|
|
NVC9B0_DEC_ERROR_H264_ERRINTSTART = (0xDEC30010)
|
|
NVC9B0_DEC_ERROR_H264_IQT_ERRINT = (0xDEC30011)
|
|
NVC9B0_DEC_ERROR_H264_MC_ERRINT = (0xDEC30012)
|
|
NVC9B0_DEC_ERROR_H264_MC_IQT_ERRINT = (0xDEC30013)
|
|
NVC9B0_DEC_ERROR_H264_REC_ERRINT = (0xDEC30014)
|
|
NVC9B0_DEC_ERROR_H264_REC_IQT_ERRINT = (0xDEC30015)
|
|
NVC9B0_DEC_ERROR_H264_REC_MC_ERRINT = (0xDEC30016)
|
|
NVC9B0_DEC_ERROR_H264_REC_MC_IQT_ERRINT = (0xDEC30017)
|
|
NVC9B0_DEC_ERROR_H264_DBF_ERRINT = (0xDEC30018)
|
|
NVC9B0_DEC_ERROR_H264_DBF_IQT_ERRINT = (0xDEC30019)
|
|
NVC9B0_DEC_ERROR_H264_DBF_MC_ERRINT = (0xDEC3001A)
|
|
NVC9B0_DEC_ERROR_H264_DBF_MC_IQT_ERRINT = (0xDEC3001B)
|
|
NVC9B0_DEC_ERROR_H264_DBF_REC_ERRINT = (0xDEC3001C)
|
|
NVC9B0_DEC_ERROR_H264_DBF_REC_IQT_ERRINT = (0xDEC3001D)
|
|
NVC9B0_DEC_ERROR_H264_DBF_REC_MC_ERRINT = (0xDEC3001E)
|
|
NVC9B0_DEC_ERROR_H264_DBF_REC_MC_IQT_ERRINT = (0xDEC3001F)
|
|
NVC9B0_DEC_ERROR_H264_PICTURE_INIT = (0xDEC30100)
|
|
NVC9B0_DEC_ERROR_H264_STATEMACHINE_FAILURE = (0xDEC30101)
|
|
NVC9B0_DEC_ERROR_H264_INVALID_CTXID_PIC = (0xDEC30901)
|
|
NVC9B0_DEC_ERROR_H264_INVALID_CTXID_UCODE = (0xDEC30902)
|
|
NVC9B0_DEC_ERROR_H264_INVALID_CTXID_FC = (0xDEC30903)
|
|
NVC9B0_DEC_ERROR_H264_INVALID_CTXID_SLH = (0xDEC30904)
|
|
NVC9B0_DEC_ERROR_H264_INVALID_UCODE_SIZE = (0xDEC30905)
|
|
NVC9B0_DEC_ERROR_H264_INVALID_SLICE_COUNT = (0xDEC30906)
|
|
NVC9B0_DEC_ERROR_MPEG4_APPTIMER_EXPIRED = (0xDEC40001)
|
|
NVC9B0_DEC_ERROR_MPEG4_MVTIMER_EXPIRED = (0xDEC40002)
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_TOKEN = (0xDEC40003)
|
|
NVC9B0_DEC_ERROR_MPEG4_SLICEDATA_MISSING = (0xDEC40004)
|
|
NVC9B0_DEC_ERROR_MPEG4_HWERR_INTERRUPT = (0xDEC40005)
|
|
NVC9B0_DEC_ERROR_MPEG4_DETECTED_VLD_FAILURE = (0xDEC40006)
|
|
NVC9B0_DEC_ERROR_MPEG4_TIMEOUT_POLLING_FOR_DATA = (0xDEC40007)
|
|
NVC9B0_DEC_ERROR_MPEG4_PDEC_PIC_END_UNALIGNED = (0xDEC40008)
|
|
NVC9B0_DEC_ERROR_MPEG4_WDTIMER_EXPIRED = (0xDEC40009)
|
|
NVC9B0_DEC_ERROR_MPEG4_ERRINTSTART = (0xDEC40010)
|
|
NVC9B0_DEC_ERROR_MPEG4_IQT_ERRINT = (0xDEC40011)
|
|
NVC9B0_DEC_ERROR_MPEG4_MC_ERRINT = (0xDEC40012)
|
|
NVC9B0_DEC_ERROR_MPEG4_MC_IQT_ERRINT = (0xDEC40013)
|
|
NVC9B0_DEC_ERROR_MPEG4_REC_ERRINT = (0xDEC40014)
|
|
NVC9B0_DEC_ERROR_MPEG4_REC_IQT_ERRINT = (0xDEC40015)
|
|
NVC9B0_DEC_ERROR_MPEG4_REC_MC_ERRINT = (0xDEC40016)
|
|
NVC9B0_DEC_ERROR_MPEG4_REC_MC_IQT_ERRINT = (0xDEC40017)
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_ERRINT = (0xDEC40018)
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_IQT_ERRINT = (0xDEC40019)
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_MC_ERRINT = (0xDEC4001A)
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_MC_IQT_ERRINT = (0xDEC4001B)
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_REC_ERRINT = (0xDEC4001C)
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_REC_IQT_ERRINT = (0xDEC4001D)
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_REC_MC_ERRINT = (0xDEC4001E)
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_REC_MC_IQT_ERRINT = (0xDEC4001F)
|
|
NVC9B0_DEC_ERROR_MPEG4_PICTURE_INIT = (0xDEC40100)
|
|
NVC9B0_DEC_ERROR_MPEG4_STATEMACHINE_FAILURE = (0xDEC40101)
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_CTXID_PIC = (0xDEC40901)
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_CTXID_UCODE = (0xDEC40902)
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_CTXID_FC = (0xDEC40903)
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_CTXID_SLH = (0xDEC40904)
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_UCODE_SIZE = (0xDEC40905)
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_SLICE_COUNT = (0xDEC40906)
|
|
NVC6C0_QMDV02_03_OUTER_PUT = (30, 0)
|
|
NVC6C0_QMDV02_03_OUTER_OVERFLOW = (31, 31)
|
|
NVC6C0_QMDV02_03_OUTER_GET = (62, 32)
|
|
NVC6C0_QMDV02_03_OUTER_STICKY_OVERFLOW = (63, 63)
|
|
NVC6C0_QMDV02_03_INNER_GET = (94, 64)
|
|
NVC6C0_QMDV02_03_INNER_OVERFLOW = (95, 95)
|
|
NVC6C0_QMDV02_03_INNER_PUT = (126, 96)
|
|
NVC6C0_QMDV02_03_INNER_STICKY_OVERFLOW = (127, 127)
|
|
NVC6C0_QMDV02_03_QMD_GROUP_ID = (133, 128)
|
|
NVC6C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE = (134, 134)
|
|
NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION = (135, 135)
|
|
NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_IS_QUEUE = (136, 136)
|
|
NVC6C0_QMDV02_03_IS_QUEUE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_IS_QUEUE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137, 137)
|
|
NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 = (138, 138)
|
|
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 = (139, 139)
|
|
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS = (140, 140)
|
|
NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE = (141, 141)
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE = (142, 142)
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE = 0x00000000
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID = 0x00000001
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY = (143, 143)
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_B = (159, 144)
|
|
NVC6C0_QMDV02_03_CIRCULAR_QUEUE_SIZE = (184, 160)
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_C = (185, 185)
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE = (186, 186)
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187, 187)
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE = (188, 188)
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE = (189, 189)
|
|
NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE = (190, 190)
|
|
NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE = (191, 191)
|
|
NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME = (223, 192)
|
|
NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME = (239, 224)
|
|
NVC6C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME = (255, 240)
|
|
NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287, 256)
|
|
NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER = (319, 288)
|
|
NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER = (327, 320)
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_D = (335, 328)
|
|
NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE = (351, 336)
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_ID = (357, 352)
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365, 358)
|
|
NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE = (366, 366)
|
|
NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000
|
|
NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE = (367, 367)
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE = (369, 368)
|
|
NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000
|
|
NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001
|
|
NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003
|
|
NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS = (370, 370)
|
|
NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE = (371, 371)
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT = (378, 378)
|
|
NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 = 0x00000000
|
|
NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001
|
|
NVC6C0_QMDV02_03_SAMPLER_INDEX = (382, 382)
|
|
NVC6C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000
|
|
NVC6C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001
|
|
NVC6C0_QMDV02_03_CTA_RASTER_WIDTH = (415, 384)
|
|
NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT = (431, 416)
|
|
NVC6C0_QMDV02_03_QMD_RESERVED13A = (447, 432)
|
|
NVC6C0_QMDV02_03_CTA_RASTER_DEPTH = (463, 448)
|
|
NVC6C0_QMDV02_03_QMD_RESERVED14A = (479, 464)
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_POINTER = (511, 480)
|
|
NVC6C0_QMDV02_03_COALESCE_WAITING_PERIOD = (529, 522)
|
|
NVC6C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 = (534, 530)
|
|
NVC6C0_QMDV02_03_SHARED_MEMORY_SIZE = (561, 544)
|
|
NVC6C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE = (568, 562)
|
|
NVC6C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE = (575, 569)
|
|
NVC6C0_QMDV02_03_QMD_VERSION = (579, 576)
|
|
NVC6C0_QMDV02_03_QMD_MAJOR_VERSION = (583, 580)
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_H = (591, 584)
|
|
NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION0 = (607, 592)
|
|
NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION1 = (623, 608)
|
|
NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION2 = (639, 624)
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID = lambda i: ((640+(i)*1), (640+(i)*1)) # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_REGISTER_COUNT_V = (656, 648)
|
|
NVC6C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (663, 657)
|
|
NVC6C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM = (671, 664)
|
|
NVC6C0_QMDV02_03_SM_DISABLE_MASK_LOWER = (703, 672)
|
|
NVC6C0_QMDV02_03_SM_DISABLE_MASK_UPPER = (735, 704)
|
|
NVC6C0_QMDV02_03_RELEASE0_ADDRESS_LOWER = (767, 736)
|
|
NVC6C0_QMDV02_03_RELEASE0_ADDRESS_UPPER = (775, 768)
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_J = (783, 776)
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP = (790, 788)
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_K = (791, 791)
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT = (793, 792)
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE = (794, 794)
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE = (799, 799)
|
|
NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000
|
|
NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD = 0x00000001
|
|
NVC6C0_QMDV02_03_RELEASE0_PAYLOAD = (831, 800)
|
|
NVC6C0_QMDV02_03_RELEASE1_ADDRESS_LOWER = (863, 832)
|
|
NVC6C0_QMDV02_03_RELEASE1_ADDRESS_UPPER = (871, 864)
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_L = (879, 872)
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP = (886, 884)
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_M = (887, 887)
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT = (889, 888)
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE = (890, 890)
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE = (895, 895)
|
|
NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000
|
|
NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD = 0x00000001
|
|
NVC6C0_QMDV02_03_RELEASE1_PAYLOAD = (927, 896)
|
|
NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE = (951, 928)
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_N = (954, 952)
|
|
NVC6C0_QMDV02_03_BARRIER_COUNT = (959, 955)
|
|
NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE = (983, 960)
|
|
NVC6C0_QMDV02_03_REGISTER_COUNT = (991, 984)
|
|
NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1000, 992)
|
|
NVC6C0_QMDV02_03_PROGRAM_PREFETCH_SIZE = (1009, 1001)
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_A = (1015, 1010)
|
|
NVC6C0_QMDV02_03_SASS_VERSION = (1023, 1016)
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER = lambda i: ((1055+(i)*64), (1024+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER = lambda i: ((1072+(i)*64), (1056+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST = lambda i: ((1073+(i)*64), (1073+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1074+(i)*64), (1074+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1087+(i)*64), (1075+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_03_PROGRAM_ADDRESS_LOWER = (1567, 1536)
|
|
NVC6C0_QMDV02_03_PROGRAM_ADDRESS_UPPER = (1584, 1568)
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_S = (1599, 1585)
|
|
NVC6C0_QMDV02_03_HW_ONLY_INNER_GET = (1630, 1600)
|
|
NVC6C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1631, 1631)
|
|
NVC6C0_QMDV02_03_HW_ONLY_INNER_PUT = (1662, 1632)
|
|
NVC6C0_QMDV02_03_HW_ONLY_SCG_TYPE = (1663, 1663)
|
|
NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1693, 1664)
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_Q = (1694, 1694)
|
|
NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1695, 1695)
|
|
NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER = (1727, 1696)
|
|
NVC6C0_QMDV02_03_QMD_SPARE_G = (1759, 1728)
|
|
NVC6C0_QMDV02_03_QMD_SPARE_H = (1791, 1760)
|
|
NVC6C0_QMDV02_03_QMD_SPARE_I = (1823, 1792)
|
|
NVC6C0_QMDV02_03_QMD_SPARE_J = (1855, 1824)
|
|
NVC6C0_QMDV02_03_QMD_SPARE_K = (1887, 1856)
|
|
NVC6C0_QMDV02_03_QMD_SPARE_L = (1919, 1888)
|
|
NVC6C0_QMDV02_03_QMD_SPARE_M = (1951, 1920)
|
|
NVC6C0_QMDV02_03_QMD_SPARE_N = (1983, 1952)
|
|
NVC6C0_QMDV02_03_DEBUG_ID_UPPER = (2015, 1984)
|
|
NVC6C0_QMDV02_03_DEBUG_ID_LOWER = (2047, 2016)
|
|
NVC6C0_QMDV02_04_OUTER_PUT = (30, 0)
|
|
NVC6C0_QMDV02_04_OUTER_OVERFLOW = (31, 31)
|
|
NVC6C0_QMDV02_04_OUTER_GET = (62, 32)
|
|
NVC6C0_QMDV02_04_OUTER_STICKY_OVERFLOW = (63, 63)
|
|
NVC6C0_QMDV02_04_INNER_GET = (94, 64)
|
|
NVC6C0_QMDV02_04_INNER_OVERFLOW = (95, 95)
|
|
NVC6C0_QMDV02_04_INNER_PUT = (126, 96)
|
|
NVC6C0_QMDV02_04_INNER_STICKY_OVERFLOW = (127, 127)
|
|
NVC6C0_QMDV02_04_QMD_GROUP_ID = (133, 128)
|
|
NVC6C0_QMDV02_04_SM_GLOBAL_CACHING_ENABLE = (134, 134)
|
|
NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION = (135, 135)
|
|
NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_IS_QUEUE = (136, 136)
|
|
NVC6C0_QMDV02_04_IS_QUEUE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_IS_QUEUE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137, 137)
|
|
NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0 = (138, 138)
|
|
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1 = (139, 139)
|
|
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS = (140, 140)
|
|
NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE = (141, 141)
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION = (144, 142)
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH = (145, 145)
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE = (146, 146)
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION = (149, 147)
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH = (150, 150)
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_DEPENDENCE_COUNTER = (157, 151)
|
|
NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION = (158, 158)
|
|
NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_B = (159, 159)
|
|
NVC6C0_QMDV02_04_CIRCULAR_QUEUE_SIZE = (184, 160)
|
|
NVC6C0_QMDV02_04_DEMOTE_L2_EVICT_LAST = (185, 185)
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE = (186, 186)
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187, 187)
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE = (188, 188)
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE = (189, 189)
|
|
NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE = (190, 190)
|
|
NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE = (191, 191)
|
|
NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_CTA_RASTER_WIDTH_RESUME = (223, 192)
|
|
NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT_RESUME = (239, 224)
|
|
NVC6C0_QMDV02_04_CTA_RASTER_DEPTH_RESUME = (255, 240)
|
|
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287, 256)
|
|
NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_LOWER = (319, 288)
|
|
NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_UPPER = (327, 320)
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_D = (335, 328)
|
|
NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ENTRY_SIZE = (351, 336)
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_ID = (357, 352)
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365, 358)
|
|
NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE = (366, 366)
|
|
NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000
|
|
NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE = (367, 367)
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE = (369, 368)
|
|
NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000
|
|
NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001
|
|
NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003
|
|
NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS = (370, 370)
|
|
NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE = (371, 371)
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT = (378, 378)
|
|
NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT__32 = 0x00000000
|
|
NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001
|
|
NVC6C0_QMDV02_04_SAMPLER_INDEX = (382, 382)
|
|
NVC6C0_QMDV02_04_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000
|
|
NVC6C0_QMDV02_04_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001
|
|
NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE = (383, 383)
|
|
NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_CTA_RASTER_WIDTH = (415, 384)
|
|
NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT = (431, 416)
|
|
NVC6C0_QMDV02_04_QMD_RESERVED13A = (447, 432)
|
|
NVC6C0_QMDV02_04_CTA_RASTER_DEPTH = (463, 448)
|
|
NVC6C0_QMDV02_04_QMD_RESERVED14A = (479, 464)
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_POINTER = (511, 480)
|
|
NVC6C0_QMDV02_04_COALESCE_WAITING_PERIOD = (529, 522)
|
|
NVC6C0_QMDV02_04_QUEUE_ENTRIES_PER_CTA_LOG2 = (534, 530)
|
|
NVC6C0_QMDV02_04_SHARED_MEMORY_SIZE = (561, 544)
|
|
NVC6C0_QMDV02_04_MIN_SM_CONFIG_SHARED_MEM_SIZE = (568, 562)
|
|
NVC6C0_QMDV02_04_MAX_SM_CONFIG_SHARED_MEM_SIZE = (575, 569)
|
|
NVC6C0_QMDV02_04_QMD_VERSION = (579, 576)
|
|
NVC6C0_QMDV02_04_QMD_MAJOR_VERSION = (583, 580)
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_H = (591, 584)
|
|
NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION0 = (607, 592)
|
|
NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION1 = (623, 608)
|
|
NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION2 = (639, 624)
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID = lambda i: ((640+(i)*1), (640+(i)*1)) # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_REGISTER_COUNT_V = (656, 648)
|
|
NVC6C0_QMDV02_04_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (663, 657)
|
|
NVC6C0_QMDV02_04_FREE_CTA_SLOTS_EMPTY_SM = (671, 664)
|
|
NVC6C0_QMDV02_04_SM_DISABLE_MASK_LOWER = (703, 672)
|
|
NVC6C0_QMDV02_04_SM_DISABLE_MASK_UPPER = (735, 704)
|
|
NVC6C0_QMDV02_04_RELEASE0_ADDRESS_LOWER = (767, 736)
|
|
NVC6C0_QMDV02_04_RELEASE0_ADDRESS_UPPER = (775, 768)
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_J = (783, 776)
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP = (790, 788)
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_K = (791, 791)
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT = (793, 792)
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE = (794, 794)
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE = (799, 799)
|
|
NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000
|
|
NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_ONE_WORD = 0x00000001
|
|
NVC6C0_QMDV02_04_RELEASE0_PAYLOAD = (831, 800)
|
|
NVC6C0_QMDV02_04_RELEASE1_ADDRESS_LOWER = (863, 832)
|
|
NVC6C0_QMDV02_04_RELEASE1_ADDRESS_UPPER = (871, 864)
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_L = (879, 872)
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP = (886, 884)
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_M = (887, 887)
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT = (889, 888)
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE = (890, 890)
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE = (895, 895)
|
|
NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000
|
|
NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_ONE_WORD = 0x00000001
|
|
NVC6C0_QMDV02_04_RELEASE1_PAYLOAD = (927, 896)
|
|
NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_LOW_SIZE = (951, 928)
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_N = (954, 952)
|
|
NVC6C0_QMDV02_04_BARRIER_COUNT = (959, 955)
|
|
NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_HIGH_SIZE = (983, 960)
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_G = (991, 984)
|
|
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1000, 992)
|
|
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_SIZE = (1009, 1001)
|
|
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE = (1011, 1010)
|
|
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000
|
|
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_A = (1015, 1012)
|
|
NVC6C0_QMDV02_04_SASS_VERSION = (1023, 1016)
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_LOWER = lambda i: ((1055+(i)*64), (1024+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_UPPER = lambda i: ((1072+(i)*64), (1056+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST = lambda i: ((1073+(i)*64), (1073+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1074+(i)*64), (1074+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1087+(i)*64), (1075+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_04_PROGRAM_ADDRESS_LOWER = (1567, 1536)
|
|
NVC6C0_QMDV02_04_PROGRAM_ADDRESS_UPPER = (1584, 1568)
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_S = (1599, 1585)
|
|
NVC6C0_QMDV02_04_HW_ONLY_INNER_GET = (1630, 1600)
|
|
NVC6C0_QMDV02_04_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1631, 1631)
|
|
NVC6C0_QMDV02_04_HW_ONLY_INNER_PUT = (1662, 1632)
|
|
NVC6C0_QMDV02_04_HW_ONLY_SCG_TYPE = (1663, 1663)
|
|
NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1693, 1664)
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_Q = (1694, 1694)
|
|
NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1695, 1695)
|
|
NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000
|
|
NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001
|
|
NVC6C0_QMDV02_04_HW_ONLY_SKED_NEXT_QMD_POINTER = (1727, 1696)
|
|
NVC6C0_QMDV02_04_HW_ONLY_DEPENDENCE_COUNTER = (1734, 1728)
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_I = (1759, 1735)
|
|
NVC6C0_QMDV02_04_QMD_SPARE_H = (1791, 1760)
|
|
NVC6C0_QMDV02_04_QMD_SPARE_I = (1823, 1792)
|
|
NVC6C0_QMDV02_04_QMD_SPARE_J = (1855, 1824)
|
|
NVC6C0_QMDV02_04_QMD_SPARE_K = (1887, 1856)
|
|
NVC6C0_QMDV02_04_QMD_SPARE_L = (1919, 1888)
|
|
NVC6C0_QMDV02_04_QMD_SPARE_M = (1951, 1920)
|
|
NVC6C0_QMDV02_04_QMD_SPARE_N = (1983, 1952)
|
|
NVC6C0_QMDV02_04_DEBUG_ID_UPPER = (2015, 1984)
|
|
NVC6C0_QMDV02_04_DEBUG_ID_LOWER = (2047, 2016)
|
|
NVC6C0_QMDV03_00_OUTER_PUT = (30, 0)
|
|
NVC6C0_QMDV03_00_OUTER_OVERFLOW = (31, 31)
|
|
NVC6C0_QMDV03_00_OUTER_GET = (62, 32)
|
|
NVC6C0_QMDV03_00_OUTER_STICKY_OVERFLOW = (63, 63)
|
|
NVC6C0_QMDV03_00_INNER_GET = (94, 64)
|
|
NVC6C0_QMDV03_00_INNER_OVERFLOW = (95, 95)
|
|
NVC6C0_QMDV03_00_INNER_PUT = (126, 96)
|
|
NVC6C0_QMDV03_00_INNER_STICKY_OVERFLOW = (127, 127)
|
|
NVC6C0_QMDV03_00_QMD_GROUP_ID = (133, 128)
|
|
NVC6C0_QMDV03_00_SM_GLOBAL_CACHING_ENABLE = (134, 134)
|
|
NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION = (135, 135)
|
|
NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_IS_QUEUE = (136, 136)
|
|
NVC6C0_QMDV03_00_IS_QUEUE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_IS_QUEUE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137, 137)
|
|
NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_QMD_RESERVED04A = (139, 138)
|
|
NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS = (140, 140)
|
|
NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_QMD_RESERVED04B = (141, 141)
|
|
NVC6C0_QMDV03_00_DEPENDENCE_COUNTER = (157, 142)
|
|
NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION = (158, 158)
|
|
NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_QMD_RESERVED04C = (159, 159)
|
|
NVC6C0_QMDV03_00_CIRCULAR_QUEUE_SIZE = (184, 160)
|
|
NVC6C0_QMDV03_00_DEMOTE_L2_EVICT_LAST = (185, 185)
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE = (186, 186)
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187, 187)
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE = (188, 188)
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE = (189, 189)
|
|
NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE = (190, 190)
|
|
NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE = (191, 191)
|
|
NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_CTA_RASTER_WIDTH_RESUME = (223, 192)
|
|
NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT_RESUME = (239, 224)
|
|
NVC6C0_QMDV03_00_CTA_RASTER_DEPTH_RESUME = (255, 240)
|
|
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287, 256)
|
|
NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_LOWER = (319, 288)
|
|
NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_UPPER = (327, 320)
|
|
NVC6C0_QMDV03_00_QMD_RESERVED_D = (335, 328)
|
|
NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ENTRY_SIZE = (351, 336)
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_ID = (357, 352)
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365, 358)
|
|
NVC6C0_QMDV03_00_QMD_RESERVED11A = (366, 366)
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE = (367, 367)
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE = (369, 368)
|
|
NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000
|
|
NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001
|
|
NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003
|
|
NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS = (370, 370)
|
|
NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE = (371, 371)
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_QMD_RESERVED11B = (377, 372)
|
|
NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT = (378, 378)
|
|
NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32 = 0x00000000
|
|
NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001
|
|
NVC6C0_QMDV03_00_QMD_RESERVED11C = (381, 379)
|
|
NVC6C0_QMDV03_00_SAMPLER_INDEX = (382, 382)
|
|
NVC6C0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000
|
|
NVC6C0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001
|
|
NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE = (383, 383)
|
|
NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_CTA_RASTER_WIDTH = (415, 384)
|
|
NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT = (431, 416)
|
|
NVC6C0_QMDV03_00_CTA_RASTER_DEPTH = (463, 448)
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_POINTER = (511, 480)
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE = (512, 512)
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION = (515, 513)
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH = (516, 516)
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE = (517, 517)
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION = (520, 518)
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH = (521, 521)
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_COALESCE_WAITING_PERIOD = (529, 522)
|
|
NVC6C0_QMDV03_00_QUEUE_ENTRIES_PER_CTA_LOG2 = (534, 530)
|
|
NVC6C0_QMDV03_00_SHARED_MEMORY_SIZE = (561, 544)
|
|
NVC6C0_QMDV03_00_MIN_SM_CONFIG_SHARED_MEM_SIZE = (567, 562)
|
|
NVC6C0_QMDV03_00_QMD_RESERVED17A = (568, 568)
|
|
NVC6C0_QMDV03_00_MAX_SM_CONFIG_SHARED_MEM_SIZE = (574, 569)
|
|
NVC6C0_QMDV03_00_QMD_RESERVED17B = (575, 575)
|
|
NVC6C0_QMDV03_00_QMD_VERSION = (579, 576)
|
|
NVC6C0_QMDV03_00_QMD_MAJOR_VERSION = (583, 580)
|
|
NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION0 = (607, 592)
|
|
NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION1 = (623, 608)
|
|
NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION2 = (639, 624)
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID = lambda i: ((640+(i)*1), (640+(i)*1)) # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_REGISTER_COUNT_V = (656, 648)
|
|
NVC6C0_QMDV03_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (662, 657)
|
|
NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE = (663, 663)
|
|
NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_FREE_CTA_SLOTS_EMPTY_SM = (671, 664)
|
|
NVC6C0_QMDV03_00_SM_DISABLE_MASK_LOWER = (703, 672)
|
|
NVC6C0_QMDV03_00_SM_DISABLE_MASK_UPPER = (735, 704)
|
|
NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_LOW_SIZE = (759, 736)
|
|
NVC6C0_QMDV03_00_BARRIER_COUNT = (767, 763)
|
|
NVC6C0_QMDV03_00_RELEASE0_ADDRESS_LOWER = (799, 768)
|
|
NVC6C0_QMDV03_00_RELEASE0_ADDRESS_UPPER = (807, 800)
|
|
NVC6C0_QMDV03_00_SEMAPHORE_RESERVED25A = (818, 808)
|
|
NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE = (819, 819)
|
|
NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP = (822, 820)
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVC6C0_QMDV03_00_RELEASE0_ENABLE = (823, 823)
|
|
NVC6C0_QMDV03_00_RELEASE0_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE0_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT = (825, 824)
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE = (826, 826)
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE = (828, 827)
|
|
NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002
|
|
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B = (829, 829)
|
|
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE = (831, 830)
|
|
NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
|
|
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_LOWER = (863, 832)
|
|
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_UPPER = (895, 864)
|
|
NVC6C0_QMDV03_00_RELEASE1_ADDRESS_LOWER = (927, 896)
|
|
NVC6C0_QMDV03_00_RELEASE1_ADDRESS_UPPER = (935, 928)
|
|
NVC6C0_QMDV03_00_SEMAPHORE_RESERVED29A = (946, 936)
|
|
NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE = (947, 947)
|
|
NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP = (950, 948)
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVC6C0_QMDV03_00_RELEASE1_ENABLE = (951, 951)
|
|
NVC6C0_QMDV03_00_RELEASE1_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE1_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT = (953, 952)
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE = (954, 954)
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE = (956, 955)
|
|
NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002
|
|
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B = (957, 957)
|
|
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE = (959, 958)
|
|
NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
|
|
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_LOWER = (991, 960)
|
|
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_UPPER = (1023, 992)
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_LOWER = lambda i: ((1055+(i)*64), (1024+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_UPPER = lambda i: ((1072+(i)*64), (1056+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST = lambda i: ((1073+(i)*64), (1073+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1074+(i)*64), (1074+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1087+(i)*64), (1075+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV03_00_PROGRAM_ADDRESS_LOWER = (1567, 1536)
|
|
NVC6C0_QMDV03_00_PROGRAM_ADDRESS_UPPER = (1584, 1568)
|
|
NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_HIGH_SIZE = (1623, 1600)
|
|
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1640, 1632)
|
|
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_SIZE = (1649, 1641)
|
|
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE = (1651, 1650)
|
|
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000
|
|
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001
|
|
NVC6C0_QMDV03_00_SASS_VERSION = (1663, 1656)
|
|
NVC6C0_QMDV03_00_RELEASE2_ADDRESS_LOWER = (1695, 1664)
|
|
NVC6C0_QMDV03_00_RELEASE2_ADDRESS_UPPER = (1703, 1696)
|
|
NVC6C0_QMDV03_00_SEMAPHORE_RESERVED53A = (1714, 1704)
|
|
NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE = (1715, 1715)
|
|
NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP = (1718, 1716)
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVC6C0_QMDV03_00_RELEASE2_ENABLE = (1719, 1719)
|
|
NVC6C0_QMDV03_00_RELEASE2_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE2_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT = (1721, 1720)
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE = (1722, 1722)
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE = (1724, 1723)
|
|
NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002
|
|
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B = (1725, 1725)
|
|
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE = (1727, 1726)
|
|
NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
|
|
NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
|
|
NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
|
|
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_LOWER = (1759, 1728)
|
|
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_UPPER = (1791, 1760)
|
|
NVC6C0_QMDV03_00_QMD_SPARE_I = (1823, 1792)
|
|
NVC6C0_QMDV03_00_HW_ONLY_INNER_GET = (1854, 1824)
|
|
NVC6C0_QMDV03_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1855, 1855)
|
|
NVC6C0_QMDV03_00_HW_ONLY_INNER_PUT = (1886, 1856)
|
|
NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1917, 1888)
|
|
NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1919, 1919)
|
|
NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000
|
|
NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001
|
|
NVC6C0_QMDV03_00_HW_ONLY_SKED_NEXT_QMD_POINTER = (1951, 1920)
|
|
NVC6C0_QMDV03_00_HW_ONLY_DEPENDENCE_COUNTER = (1958, 1952)
|
|
NVC6C0_QMDV03_00_DEBUG_ID_UPPER = (2015, 1984)
|
|
NVC6C0_QMDV03_00_DEBUG_ID_LOWER = (2047, 2016)
|
|
NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX = (29, 0)
|
|
NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (30, 30)
|
|
NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (31, 31)
|
|
NVCEC0_QMDV05_00_HW_ONLY_SKED_NEXT_QMD_POINTER = (63, 32)
|
|
NVCEC0_QMDV05_00_INNER_GET = (94, 64)
|
|
NVCEC0_QMDV05_00_INNER_OVERFLOW = (95, 95)
|
|
NVCEC0_QMDV05_00_INNER_PUT = (126, 96)
|
|
NVCEC0_QMDV05_00_INNER_STICKY_OVERFLOW = (127, 127)
|
|
NVCEC0_QMDV05_00_DEPENDENCE_COUNTER = (143, 128)
|
|
NVCEC0_QMDV05_00_QMD_GROUP_ID = (149, 144)
|
|
NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (150, 150)
|
|
NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_QMD_TYPE = (153, 151)
|
|
NVCEC0_QMDV05_00_QMD_TYPE_QUEUE = 0x00000000
|
|
NVCEC0_QMDV05_00_QMD_TYPE_GRID_NULL = 0x00000001
|
|
NVCEC0_QMDV05_00_QMD_TYPE_GRID_CTA = 0x00000002
|
|
NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPC_CGA = 0x00000003
|
|
NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_CGA = 0x00000004
|
|
NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005
|
|
NVCEC0_QMDV05_00_NUM_SUB_TASKS_PER_TASK = (157, 154)
|
|
NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS = (158, 158)
|
|
NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID = (159, 159)
|
|
NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_CIRCULAR_QUEUE_SIZE = (184, 160)
|
|
NVCEC0_QMDV05_00_HW_ONLY_DEPENDENCE_COUNTER = (207, 192)
|
|
NVCEC0_QMDV05_00_RESUME_SUB_TASK_ID = (210, 208)
|
|
NVCEC0_QMDV05_00_COMPLETED_SUB_TASK_MASK = (218, 211)
|
|
NVCEC0_QMDV05_00_GRID_WIDTH_RESUME = (255, 224)
|
|
NVCEC0_QMDV05_00_GRID_HEIGHT_RESUME = (271, 256)
|
|
NVCEC0_QMDV05_00_GRID_DEPTH_RESUME = (287, 272)
|
|
NVCEC0_QMDV05_00_RELEASE_ENABLE = lambda i: ((288+(i)*16), (288+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE0_ENABLE = NVCEC0_QMDV05_00_RELEASE_ENABLE(0)
|
|
NVCEC0_QMDV05_00_RELEASE1_ENABLE = NVCEC0_QMDV05_00_RELEASE_ENABLE(1)
|
|
NVCEC0_QMDV05_00_RELEASE_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_RELEASE_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE = lambda i: ((290+(i)*16), (289+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
|
|
NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
|
|
NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
|
|
NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE = lambda i: ((291+(i)*16), (291+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000
|
|
NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE = lambda i: ((292+(i)*16), (292+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP = lambda i: ((295+(i)*16), (293+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT = lambda i: ((297+(i)*16), (296+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001
|
|
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE = lambda i: ((299+(i)*16), (298+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000
|
|
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001
|
|
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002
|
|
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003
|
|
NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B = lambda i: ((300+(i)*16), (300+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_RELEASE_RESERVED_INFO = lambda i: ((303+(i)*16), (301+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE = (336, 336)
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION = (339, 337)
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH = (340, 340)
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION = (341, 341)
|
|
NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST = (342, 342)
|
|
NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE = (343, 343)
|
|
NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE = (344, 344)
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION = (347, 345)
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH = (348, 348)
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL = (349, 349)
|
|
NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE = (350, 350)
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE = (351, 351)
|
|
NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_CORRELATION_ID = (383, 352)
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_POINTER = (415, 384)
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_POINTER = (447, 416)
|
|
NVCEC0_QMDV05_00_SASS_VERSION = (455, 448)
|
|
NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT = (456, 456)
|
|
NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT__32 = 0x00000000
|
|
NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001
|
|
NVCEC0_QMDV05_00_SAMPLER_INDEX = (457, 457)
|
|
NVCEC0_QMDV05_00_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000
|
|
NVCEC0_QMDV05_00_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001
|
|
NVCEC0_QMDV05_00_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (463, 458)
|
|
NVCEC0_QMDV05_00_QMD_MINOR_VERSION = (467, 464)
|
|
NVCEC0_QMDV05_00_QMD_MAJOR_VERSION = (471, 468)
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE = (472, 472)
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE = (473, 473)
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE = (474, 474)
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE = (475, 475)
|
|
NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE = (476, 476)
|
|
NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE = (477, 477)
|
|
NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (478, 478)
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (479, 479)
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_LOWER = (511, 480)
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_UPPER = (536, 512)
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (575, 544)
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (607, 576)
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (615, 608)
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_ID = (621, 616)
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE = (622, 622)
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE = (623, 623)
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE = (625, 624)
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE = (626, 626)
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_CTA_LAUNCH_QUEUE = (627, 627)
|
|
NVCEC0_QMDV05_00_FREE_CTA_SLOTS_EMPTY_SM = (635, 628)
|
|
NVCEC0_QMDV05_00_SYNC_DOMAIN_ID = (637, 636)
|
|
NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH = (638, 638)
|
|
NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT = (639, 639)
|
|
NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_ID = (671, 640)
|
|
NVCEC0_QMDV05_00_WAIT_ON_LATCH_ID = (703, 672)
|
|
NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_SHARED_MEM = (721, 714)
|
|
NVCEC0_QMDV05_00_OCCUPANCY_MAX_SHARED_MEM = (729, 722)
|
|
NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID = (730, 730)
|
|
NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID = (731, 731)
|
|
NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE = (732, 732)
|
|
NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE = (733, 733)
|
|
NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE = (734, 734)
|
|
NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE = (735, 735)
|
|
NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_WARP = (743, 736)
|
|
NVCEC0_QMDV05_00_OCCUPANCY_MAX_WARP = (751, 744)
|
|
NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_REGISTER = (759, 752)
|
|
NVCEC0_QMDV05_00_OCCUPANCY_MAX_REGISTER = (767, 760)
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_LOWER = (799, 768)
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_UPPER = (824, 800)
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_LOWER = (863, 832)
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_UPPER = (895, 864)
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_LOWER = (927, 896)
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_UPPER = (952, 928)
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_LOWER = (991, 960)
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_UPPER = (1023, 992)
|
|
NVCEC0_QMDV05_00_PROGRAM_ADDRESS_LOWER_SHIFTED4 = (1055, 1024)
|
|
NVCEC0_QMDV05_00_PROGRAM_ADDRESS_UPPER_SHIFTED4 = (1076, 1056)
|
|
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_SIZE = (1085, 1077)
|
|
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE = (1087, 1086)
|
|
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000
|
|
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001
|
|
NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION0 = (1103, 1088)
|
|
NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION1 = (1119, 1104)
|
|
NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION2 = (1127, 1120)
|
|
NVCEC0_QMDV05_00_REGISTER_COUNT = (1136, 1128)
|
|
NVCEC0_QMDV05_00_BARRIER_COUNT = (1141, 1137)
|
|
NVCEC0_QMDV05_00_ICC_PREFETCH_SIZE = (1147, 1142)
|
|
NVCEC0_QMDV05_00_SHARED_MEMORY_SIZE_SHIFTED7 = (1162, 1152)
|
|
NVCEC0_QMDV05_00_MIN_SM_CONFIG_SHARED_MEM_SIZE = (1168, 1163)
|
|
NVCEC0_QMDV05_00_MAX_SM_CONFIG_SHARED_MEM_SIZE = (1174, 1169)
|
|
NVCEC0_QMDV05_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (1180, 1175)
|
|
NVCEC0_QMDV05_00_SHARED_MEM_BARRIER_INIT_ENABLE = (1181, 1181)
|
|
NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4 = (1199, 1184)
|
|
NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4 = (1215, 1200)
|
|
NVCEC0_QMDV05_00_VIRTUAL_RESOURCE_COUNT = (1223, 1216)
|
|
NVCEC0_QMDV05_00_GRID_WIDTH = (1279, 1248)
|
|
NVCEC0_QMDV05_00_GRID_HEIGHT = (1295, 1280)
|
|
NVCEC0_QMDV05_00_GRID_DEPTH = (1327, 1312)
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6 = lambda i: ((1375+(i)*64), (1344+(i)*64)) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6 = lambda i: ((1394+(i)*64), (1376+(i)*64)) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1407+(i)*64), (1395+(i)*64)) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID = lambda i: ((1856+(i)*4), (1856+(i)*4)) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH = lambda i: ((1858+(i)*4), (1857+(i)*4)) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE = 0x00000000
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE = 0x00000001
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST = 0x00000002
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1859+(i)*4), (1859+(i)*4)) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (1919, 1888)
|
|
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1936, 1920)
|
|
NVCEC0_QMDV05_00_GPC_CGA_WIDTH = (2053, 2048)
|
|
NVCEC0_QMDV05_00_GPC_CGA_HEIGHT = (2061, 2056)
|
|
NVCEC0_QMDV05_00_GPC_CGA_DEPTH = (2069, 2064)
|
|
NVCEC0_QMDV05_00_LARGE_GPC_CGA_WIDTH_MINUS_ONE = (2075, 2072)
|
|
NVCEC0_QMDV05_00_LARGE_GPC_CGA_HEIGHT_MINUS_ONE = (2079, 2076)
|
|
NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE = (2111, 2111)
|
|
NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING = 0x00000000
|
|
NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST = 0x00000001
|
|
NVCEC0_QMDV05_00_GPU_CGA_WIDTH = (2127, 2112)
|
|
NVCEC0_QMDV05_00_GPU_CGA_HEIGHT = (2143, 2128)
|
|
NVCEC0_QMDV05_00_GPU_CGA_DEPTH = (2159, 2144)
|
|
NVCEC0_QMDV05_00_DEBUG_ID_LOWER = (2207, 2176)
|
|
NVCEC0_QMDV05_00_DEBUG_ID_UPPER = (2239, 2208)
|
|
NVCEC0_QMDV05_00_TPC_DISABLE_MASK = lambda i: ((2271+(i)*32), (2240+(i)*32)) # type: ignore
|
|
NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_WIDTH_RESUME = (2527, 2496)
|
|
NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_HEIGHT_RESUME = (2543, 2528)
|
|
NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_DEPTH_RESUME = (2559, 2544)
|
|
NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME = (2563, 2560)
|
|
NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME = (2567, 2564)
|
|
NVCEC0_QMDV05_00_QUEUE_ENTRIES_PER_CTA_LOG2 = (2596, 2592)
|
|
NVCEC0_QMDV05_00_HW_ONLY_INNER_GET = (2654, 2624)
|
|
NVCEC0_QMDV05_00_HW_ONLY_INNER_PUT = (2686, 2656)
|
|
NVCEC0_QMDV05_00_OUTER_PUT = (3038, 3008)
|
|
NVCEC0_QMDV05_00_OUTER_OVERFLOW = (3039, 3039)
|
|
NVCEC0_QMDV05_00_OUTER_GET = (3070, 3040)
|
|
NVCEC0_QMDV05_00_OUTER_STICKY_OVERFLOW = (3071, 3071)
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE = lambda i: ((336+(i)*8), (336+(i)*8)) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION = lambda i: ((339+(i)*8), (337+(i)*8)) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH = lambda i: ((340+(i)*8), (340+(i)*8)) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_POINTER = lambda i: ((415+(i)*32), (384+(i)*32)) # type: ignore
|
|
NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX = (29, 0)
|
|
NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (30, 30)
|
|
NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (31, 31)
|
|
NVCEC0_QMDV05_01_HW_ONLY_SKED_NEXT_QMD_POINTER = (63, 32)
|
|
NVCEC0_QMDV05_01_INNER_GET = (94, 64)
|
|
NVCEC0_QMDV05_01_INNER_OVERFLOW = (95, 95)
|
|
NVCEC0_QMDV05_01_INNER_PUT = (126, 96)
|
|
NVCEC0_QMDV05_01_INNER_STICKY_OVERFLOW = (127, 127)
|
|
NVCEC0_QMDV05_01_DEPENDENCE_COUNTER = (143, 128)
|
|
NVCEC0_QMDV05_01_QMD_GROUP_ID = (149, 144)
|
|
NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (150, 150)
|
|
NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_QMD_TYPE = (153, 151)
|
|
NVCEC0_QMDV05_01_QMD_TYPE_QUEUE = 0x00000000
|
|
NVCEC0_QMDV05_01_QMD_TYPE_GRID_NULL = 0x00000001
|
|
NVCEC0_QMDV05_01_QMD_TYPE_GRID_CTA = 0x00000002
|
|
NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPC_CGA = 0x00000003
|
|
NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_CGA = 0x00000004
|
|
NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005
|
|
NVCEC0_QMDV05_01_NUM_SUB_TASKS_PER_TASK = (157, 154)
|
|
NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS = (158, 158)
|
|
NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID = (159, 159)
|
|
NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_CIRCULAR_QUEUE_SIZE = (184, 160)
|
|
NVCEC0_QMDV05_01_HW_ONLY_DEPENDENCE_COUNTER = (207, 192)
|
|
NVCEC0_QMDV05_01_RESUME_SUB_TASK_ID = (210, 208)
|
|
NVCEC0_QMDV05_01_COMPLETED_SUB_TASK_MASK = (218, 211)
|
|
NVCEC0_QMDV05_01_GRID_WIDTH_RESUME = (255, 224)
|
|
NVCEC0_QMDV05_01_GRID_HEIGHT_RESUME = (271, 256)
|
|
NVCEC0_QMDV05_01_GRID_DEPTH_RESUME = (287, 272)
|
|
NVCEC0_QMDV05_01_RELEASE_ENABLE = lambda i: ((288+(i)*16), (288+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_RELEASE_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE = lambda i: ((290+(i)*16), (289+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
|
|
NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
|
|
NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
|
|
NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE = lambda i: ((291+(i)*16), (291+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000
|
|
NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE = lambda i: ((292+(i)*16), (292+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP = lambda i: ((295+(i)*16), (293+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT = lambda i: ((297+(i)*16), (296+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001
|
|
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE = lambda i: ((299+(i)*16), (298+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000
|
|
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001
|
|
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002
|
|
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003
|
|
NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B = lambda i: ((300+(i)*16), (300+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_RELEASE_RESERVED_INFO = lambda i: ((303+(i)*16), (301+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE = (336, 336)
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION = (339, 337)
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH = (340, 340)
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION = (341, 341)
|
|
NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST = (342, 342)
|
|
NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE = (343, 343)
|
|
NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE = (344, 344)
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION = (347, 345)
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH = (348, 348)
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL = (349, 349)
|
|
NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE = (350, 350)
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE = (351, 351)
|
|
NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_CORRELATION_ID = (383, 352)
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_POINTER = (415, 384)
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_POINTER = (447, 416)
|
|
NVCEC0_QMDV05_01_SASS_VERSION = (455, 448)
|
|
NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT = (456, 456)
|
|
NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT__32 = 0x00000000
|
|
NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001
|
|
NVCEC0_QMDV05_01_SAMPLER_INDEX = (457, 457)
|
|
NVCEC0_QMDV05_01_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000
|
|
NVCEC0_QMDV05_01_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001
|
|
NVCEC0_QMDV05_01_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (463, 458)
|
|
NVCEC0_QMDV05_01_QMD_MINOR_VERSION = (467, 464)
|
|
NVCEC0_QMDV05_01_QMD_MAJOR_VERSION = (471, 468)
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE = (472, 472)
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE = (473, 473)
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE = (474, 474)
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE = (475, 475)
|
|
NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE = (476, 476)
|
|
NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE = (477, 477)
|
|
NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (478, 478)
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (479, 479)
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_LOWER = (511, 480)
|
|
NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_UPPER = (536, 512)
|
|
NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (575, 544)
|
|
NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (607, 576)
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (615, 608)
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_ID = (621, 616)
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE = (622, 622)
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE = (623, 623)
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE = (625, 624)
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE = (626, 626)
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_CTA_LAUNCH_QUEUE = (627, 627)
|
|
NVCEC0_QMDV05_01_FREE_CTA_SLOTS_EMPTY_SM = (635, 628)
|
|
NVCEC0_QMDV05_01_SYNC_DOMAIN_ID = (637, 636)
|
|
NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH = (638, 638)
|
|
NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT = (639, 639)
|
|
NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_ID = (671, 640)
|
|
NVCEC0_QMDV05_01_WAIT_ON_LATCH_ID = (703, 672)
|
|
NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_SHARED_MEM = (721, 714)
|
|
NVCEC0_QMDV05_01_OCCUPANCY_MAX_SHARED_MEM = (729, 722)
|
|
NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID = (730, 730)
|
|
NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID = (731, 731)
|
|
NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE = (732, 732)
|
|
NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE = (733, 733)
|
|
NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE = (734, 734)
|
|
NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE = (735, 735)
|
|
NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_WARP = (743, 736)
|
|
NVCEC0_QMDV05_01_OCCUPANCY_MAX_WARP = (751, 744)
|
|
NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_REGISTER = (759, 752)
|
|
NVCEC0_QMDV05_01_OCCUPANCY_MAX_REGISTER = (767, 760)
|
|
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_LOWER_SHIFTED4 = lambda i: ((799+(i)*416), (768+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_UPPER_SHIFTED4 = lambda i: ((820+(i)*416), (800+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_SIZE = lambda i: ((829+(i)*416), (821+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE = lambda i: ((831+(i)*416), (830+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000
|
|
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001
|
|
NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION0 = lambda i: ((847+(i)*416), (832+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION1 = lambda i: ((863+(i)*416), (848+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION2 = lambda i: ((871+(i)*416), (864+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_REGISTER_COUNT = lambda i: ((880+(i)*416), (872+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_BARRIER_COUNT = lambda i: ((885+(i)*416), (881+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID = lambda i: ((886+(i)*416), (886+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH = lambda i: ((888+(i)*416), (887+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_NONE = 0x00000000
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_PRE = 0x00000001
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_POST = 0x00000002
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE = lambda i: ((889+(i)*416), (889+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_SUB_TASK_ICC_PREFETCH_SIZE = lambda i: ((895+(i)*416), (890+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEMORY_SIZE_SHIFTED7 = lambda i: ((906+(i)*416), (896+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_MIN_SM_CONFIG_SHARED_MEM_SIZE = lambda i: ((912+(i)*416), (907+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_MAX_SM_CONFIG_SHARED_MEM_SIZE = lambda i: ((918+(i)*416), (913+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_TARGET_SM_CONFIG_SHARED_MEM_SIZE = lambda i: ((924+(i)*416), (919+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEM_BARRIER_INIT_ENABLE = lambda i: ((925+(i)*416), (925+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4 = lambda i: ((943+(i)*416), (928+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4 = lambda i: ((959+(i)*416), (944+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_LOWER_SHIFTED6 = lambda i: ((991+(i)*416), (960+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_UPPER_SHIFTED6 = lambda i: ((1010+(i)*416), (992+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_SIZE_SHIFTED4 = lambda i: ((1023+(i)*416), (1011+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_LOWER_SHIFTED6 = lambda i: ((1055+(i)*416), (1024+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_UPPER_SHIFTED6 = lambda i: ((1074+(i)*416), (1056+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_SIZE_SHIFTED4 = lambda i: ((1087+(i)*416), (1075+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID = lambda i: ((1088+(i)*416), (1088+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH = lambda i: ((1090+(i)*416), (1089+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_NONE = 0x00000000
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_PRE = 0x00000001
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_POST = 0x00000002
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE = lambda i: ((1091+(i)*416), (1091+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_SUB_TASK_VIRTUAL_RESOURCE_COUNT = lambda i: ((1099+(i)*416), (1092+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_GRID_WIDTH = lambda i: ((1151+(i)*416), (1120+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_GRID_HEIGHT = lambda i: ((1167+(i)*416), (1152+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_GRID_DEPTH = lambda i: ((1183+(i)*416), (1168+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE = lambda i: ((336+(i)*8), (336+(i)*8)) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION = lambda i: ((339+(i)*8), (337+(i)*8)) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH = lambda i: ((340+(i)*8), (340+(i)*8)) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_POINTER = lambda i: ((415+(i)*32), (384+(i)*32)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID = lambda i,j: ((886+(i)*416+(j)*202), (886+(i)*416+(j)*202)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH = lambda i,j: ((888+(i)*416+(j)*202), (887+(i)*416+(j)*202)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_NONE = 0x00000000
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_PRE = 0x00000001
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_POST = 0x00000002
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE = lambda i,j: ((889+(i)*416+(j)*202), (889+(i)*416+(j)*202)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_FALSE = 0x00000000
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_TRUE = 0x00000001
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_LOWER_SHIFTED6 = lambda i,j: ((991+(i)*416+(j)*64), (960+(i)*416+(j)*64)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_UPPER_SHIFTED6 = lambda i,j: ((1010+(i)*416+(j)*64), (992+(i)*416+(j)*64)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_SIZE_SHIFTED4 = lambda i,j: ((1023+(i)*416+(j)*64), (1011+(i)*416+(j)*64)) # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENCE_COUNTER = (15, 0)
|
|
NVCEC0_QMDV04_01_QMD_GROUP_ID = (21, 16)
|
|
NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (22, 22)
|
|
NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_QMD_TYPE = (25, 23)
|
|
NVCEC0_QMDV04_01_QMD_TYPE_QUEUE = 0x00000000
|
|
NVCEC0_QMDV04_01_QMD_TYPE_GRID_NULL = 0x00000001
|
|
NVCEC0_QMDV04_01_QMD_TYPE_GRID_CTA = 0x00000002
|
|
NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPC_CGA = 0x00000003
|
|
NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_CGA = 0x00000004
|
|
NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005
|
|
NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_VALID = (28, 28)
|
|
NVCEC0_QMDV04_01_WAIT_ON_LATCH_VALID = (29, 29)
|
|
NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS = (30, 30)
|
|
NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID = (31, 31)
|
|
NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_CIRCULAR_QUEUE_SIZE = (56, 32)
|
|
NVCEC0_QMDV04_01_INNER_GET = (94, 64)
|
|
NVCEC0_QMDV04_01_INNER_OVERFLOW = (95, 95)
|
|
NVCEC0_QMDV04_01_INNER_PUT = (126, 96)
|
|
NVCEC0_QMDV04_01_INNER_STICKY_OVERFLOW = (127, 127)
|
|
NVCEC0_QMDV04_01_HW_ONLY_INNER_GET = (190, 160)
|
|
NVCEC0_QMDV04_01_HW_ONLY_INNER_PUT = (222, 192)
|
|
NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX = (253, 224)
|
|
NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (254, 254)
|
|
NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_HW_ONLY_SKED_NEXT_QMD_POINTER = (287, 256)
|
|
NVCEC0_QMDV04_01_HW_ONLY_DEPENDENCE_COUNTER = (303, 288)
|
|
NVCEC0_QMDV04_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (304, 304)
|
|
NVCEC0_QMDV04_01_RELEASE_ENABLE = lambda i: ((320+(i)*16), (320+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_RELEASE_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE = lambda i: ((322+(i)*16), (321+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
|
|
NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
|
|
NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
|
|
NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE = lambda i: ((323+(i)*16), (323+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000
|
|
NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE = lambda i: ((324+(i)*16), (324+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP = lambda i: ((327+(i)*16), (325+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT = lambda i: ((329+(i)*16), (328+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001
|
|
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE = lambda i: ((331+(i)*16), (330+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000
|
|
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001
|
|
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002
|
|
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003
|
|
NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B = lambda i: ((332+(i)*16), (332+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_RELEASE_RESERVED_INFO = lambda i: ((335+(i)*16), (333+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE = lambda i: ((368+(i)*5), (368+(i)*5)) # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION = lambda i: ((371+(i)*5), (369+(i)*5)) # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH = lambda i: ((372+(i)*5), (372+(i)*5)) # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION = (378, 378)
|
|
NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST = (379, 379)
|
|
NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE = (380, 380)
|
|
NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL = (381, 381)
|
|
NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE = (382, 382)
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_CORRELATION_ID = (415, 384)
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID = lambda i: ((416+(i)*4), (416+(i)*4)) # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH = lambda i: ((418+(i)*4), (417+(i)*4)) # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE = 0x00000000
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE = 0x00000001
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST = 0x00000002
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE = lambda i: ((419+(i)*4), (419+(i)*4)) # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD0_POINTER = (479, 448)
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD1_POINTER = (511, 480)
|
|
NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_LOW_SIZE = (535, 512)
|
|
NVCEC0_QMDV04_01_SASS_VERSION = (543, 536)
|
|
NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_HIGH_SIZE = (567, 544)
|
|
NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT = (568, 568)
|
|
NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT__32 = 0x00000000
|
|
NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001
|
|
NVCEC0_QMDV04_01_SAMPLER_INDEX = (569, 569)
|
|
NVCEC0_QMDV04_01_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000
|
|
NVCEC0_QMDV04_01_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (575, 570)
|
|
NVCEC0_QMDV04_01_QMD_MINOR_VERSION = (579, 576)
|
|
NVCEC0_QMDV04_01_QMD_MAJOR_VERSION = (583, 580)
|
|
NVCEC0_QMDV04_01_SHARED_MEMORY_SIZE = (601, 584)
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE = (602, 602)
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE = (603, 603)
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE = (604, 604)
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE = (605, 605)
|
|
NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE = (606, 606)
|
|
NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE = (607, 607)
|
|
NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_MIN_SM_CONFIG_SHARED_MEM_SIZE = (613, 608)
|
|
NVCEC0_QMDV04_01_MAX_SM_CONFIG_SHARED_MEM_SIZE = (619, 614)
|
|
NVCEC0_QMDV04_01_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (625, 620)
|
|
NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE = (626, 626)
|
|
NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_LOWER = (671, 640)
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_UPPER = (696, 672)
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (735, 704)
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (767, 736)
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_LOWER = (799, 768)
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_UPPER = (824, 800)
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_LOWER = (863, 832)
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_UPPER = (895, 864)
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_LOWER = (927, 896)
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_UPPER = (952, 928)
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_LOWER = (991, 960)
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_UPPER = (1023, 992)
|
|
NVCEC0_QMDV04_01_GRID_WIDTH = (1055, 1024)
|
|
NVCEC0_QMDV04_01_GRID_HEIGHT = (1071, 1056)
|
|
NVCEC0_QMDV04_01_GRID_DEPTH = (1103, 1088)
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (1127, 1120)
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_ID = (1133, 1128)
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE = (1134, 1134)
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE = (1135, 1135)
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE = (1137, 1136)
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003
|
|
NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS = (1138, 1138)
|
|
NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_CTA_LAUNCH_QUEUE = (1139, 1139)
|
|
NVCEC0_QMDV04_01_FREE_CTA_SLOTS_EMPTY_SM = (1147, 1140)
|
|
NVCEC0_QMDV04_01_SYNC_DOMAIN_ID = (1149, 1148)
|
|
NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH = (1150, 1150)
|
|
NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT = (1151, 1151)
|
|
NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION0 = (1167, 1152)
|
|
NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION1 = (1183, 1168)
|
|
NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION2 = (1191, 1184)
|
|
NVCEC0_QMDV04_01_VIRTUAL_RESOURCE_COUNT = (1199, 1192)
|
|
NVCEC0_QMDV04_01_REGISTER_COUNT = (1208, 1200)
|
|
NVCEC0_QMDV04_01_SHARED_MEM_BARRIER_INIT_ENABLE = (1210, 1210)
|
|
NVCEC0_QMDV04_01_BARRIER_COUNT = (1215, 1211)
|
|
NVCEC0_QMDV04_01_PROGRAM_ADDRESS_LOWER = (1247, 1216)
|
|
NVCEC0_QMDV04_01_PROGRAM_ADDRESS_UPPER = (1272, 1248)
|
|
NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_WARP = (1287, 1280)
|
|
NVCEC0_QMDV04_01_OCCUPANCY_MAX_WARP = (1295, 1288)
|
|
NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_REGISTER = (1303, 1296)
|
|
NVCEC0_QMDV04_01_OCCUPANCY_MAX_REGISTER = (1311, 1304)
|
|
NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_SHARED_MEM = (1319, 1312)
|
|
NVCEC0_QMDV04_01_OCCUPANCY_MAX_SHARED_MEM = (1327, 1320)
|
|
NVCEC0_QMDV04_01_ICC_PREFETCH_SIZE = (1333, 1328)
|
|
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (1375, 1344)
|
|
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1392, 1376)
|
|
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_SIZE = (1401, 1393)
|
|
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE = (1403, 1402)
|
|
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000
|
|
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001
|
|
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (1406, 1406)
|
|
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (1407, 1407)
|
|
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
|
|
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
|
|
NVCEC0_QMDV04_01_GRID_WIDTH_RESUME = (1439, 1408)
|
|
NVCEC0_QMDV04_01_GRID_HEIGHT_RESUME = (1455, 1440)
|
|
NVCEC0_QMDV04_01_GRID_DEPTH_RESUME = (1471, 1456)
|
|
NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_ID = (1503, 1472)
|
|
NVCEC0_QMDV04_01_WAIT_ON_LATCH_ID = (1535, 1504)
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6 = lambda i: ((1567+(i)*64), (1536+(i)*64)) # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6 = lambda i: ((1586+(i)*64), (1568+(i)*64)) # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1599+(i)*64), (1587+(i)*64)) # type: ignore
|
|
NVCEC0_QMDV04_01_COALESCE_WAITING_PERIOD = (2135, 2128)
|
|
NVCEC0_QMDV04_01_QUEUE_ENTRIES_PER_CTA_LOG2 = (2140, 2136)
|
|
NVCEC0_QMDV04_01_GPC_CGA_WIDTH = (2149, 2144)
|
|
NVCEC0_QMDV04_01_GPC_CGA_HEIGHT = (2157, 2152)
|
|
NVCEC0_QMDV04_01_GPC_CGA_DEPTH = (2165, 2160)
|
|
NVCEC0_QMDV04_01_LARGE_GPC_CGA_WIDTH_MINUS_ONE = (2171, 2168)
|
|
NVCEC0_QMDV04_01_LARGE_GPC_CGA_HEIGHT_MINUS_ONE = (2175, 2172)
|
|
NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE = (2207, 2207)
|
|
NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING = 0x00000000
|
|
NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST = 0x00000001
|
|
NVCEC0_QMDV04_01_GPU_CGA_WIDTH = (2223, 2208)
|
|
NVCEC0_QMDV04_01_GPU_CGA_HEIGHT = (2239, 2224)
|
|
NVCEC0_QMDV04_01_GPU_CGA_DEPTH = (2255, 2240)
|
|
NVCEC0_QMDV04_01_DEBUG_ID_LOWER = (2399, 2368)
|
|
NVCEC0_QMDV04_01_DEBUG_ID_UPPER = (2431, 2400)
|
|
NVCEC0_QMDV04_01_TPC_DISABLE_MASK = lambda i: ((2463+(i)*32), (2432+(i)*32)) # type: ignore
|
|
NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_WIDTH_RESUME = (2591, 2560)
|
|
NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_HEIGHT_RESUME = (2607, 2592)
|
|
NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_DEPTH_RESUME = (2623, 2608)
|
|
NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME = (2627, 2624)
|
|
NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME = (2631, 2628)
|
|
NVCEC0_QMDV04_01_TPC_DISABLE_MASK_UPPER = lambda i: ((2719+(i)*32), (2688+(i)*32)) # type: ignore
|
|
NVCEC0_QMDV04_01_OUTER_PUT = (3038, 3008)
|
|
NVCEC0_QMDV04_01_OUTER_OVERFLOW = (3039, 3039)
|
|
NVCEC0_QMDV04_01_OUTER_GET = (3070, 3040)
|
|
NVCEC0_QMDV04_01_OUTER_STICKY_OVERFLOW = (3071, 3071)
|
|
ALIGN_UP = lambda v,n: (((v) + ((n)-1)) &~ ((n)-1)) # type: ignore
|
|
NVDEC_ALIGN = lambda value: ALIGN_UP(value,256) # type: ignore
|
|
NVDEC_MAX_MPEG2_SLICE = 65536
|
|
NVDEC_CODEC_MPEG1 = 0
|
|
NVDEC_CODEC_MPEG2 = 1
|
|
NVDEC_CODEC_VC1 = 2
|
|
NVDEC_CODEC_H264 = 3
|
|
NVDEC_CODEC_MPEG4 = 4
|
|
NVDEC_CODEC_DIVX = NVDEC_CODEC_MPEG4
|
|
NVDEC_CODEC_VP8 = 5
|
|
NVDEC_CODEC_HEVC = 7
|
|
NVDEC_CODEC_VP9 = 9
|
|
NVDEC_CODEC_HEVC_PARSER = 12
|
|
NVDEC_CODEC_AV1 = 10
|
|
AES_MODE_MASK = 0x7
|
|
AES_CTS_MASK = 0x1
|
|
AES_PADDING_TYPE_MASK = 0x7
|
|
AES_UNWRAP_KEY_MASK = 0x1
|
|
AES_MODE_SHIFT = 0
|
|
AES_CTS_SHIFT = 3
|
|
AES_PADDING_TYPE_SHIFT = 4
|
|
AES_UNWRAP_KEY_SHIFT = 7
|
|
AES_SET_FLAG = lambda M,C,P: ((M & AES_MODE_MASK) << AES_MODE_SHIFT) | ((C & AES_CTS_MASK) << AES_CTS_SHIFT) | ((P & AES_PADDING_TYPE_MASK) << AES_PADDING_TYPE_SHIFT) # type: ignore
|
|
DRM_MODE_MASK = 0x7f
|
|
AES_GET_DRM_MODE = lambda V: (V & DRM_MODE_MASK) # type: ignore
|
|
GIP_ASIC_VERT_FILTER_RAM_SIZE = 16
|
|
GIP_ASIC_BSD_CTRL_RAM_SIZE = 4
|
|
GIP_ASIC_SCALING_LIST_SIZE = (16*64)
|
|
GIP_ASIC_VERT_SAO_RAM_SIZE = 16
|
|
GIP_ASIC_TILE_SIZE = ((20*22*2*2+16+15) & ~0xF)
|
|
GIP_ASIC_VP9_CTB_SEG_SIZE = 32
|
|
HEVC_DBLK_TOP_SIZE_IN_SB16 = ALIGN_UP(632, 128)
|
|
HEVC_DBLK_TOP_BUF_SIZE = lambda w: NVDEC_ALIGN( (ALIGN_UP(w,16)/16 + 2) * HEVC_DBLK_TOP_SIZE_IN_SB16) # type: ignore
|
|
HEVC_DBLK_LEFT_SIZE_IN_SB16 = ALIGN_UP(506, 128)
|
|
HEVC_DBLK_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,16)/16 + 2) * HEVC_DBLK_LEFT_SIZE_IN_SB16) # type: ignore
|
|
HEVC_SAO_LEFT_SIZE_IN_SB16 = ALIGN_UP(713, 128)
|
|
HEVC_SAO_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,16)/16 + 2) * HEVC_SAO_LEFT_SIZE_IN_SB16) # type: ignore
|
|
VP9_DBLK_TOP_SIZE_IN_SB64 = ALIGN_UP(2000, 128)
|
|
VP9_DBLK_TOP_BUF_SIZE = lambda w: NVDEC_ALIGN( (ALIGN_UP(w,64)/64 + 2) * VP9_DBLK_TOP_SIZE_IN_SB64) # type: ignore
|
|
VP9_DBLK_LEFT_SIZE_IN_SB64 = ALIGN_UP(1600, 128)
|
|
VP9_DBLK_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * VP9_DBLK_LEFT_SIZE_IN_SB64) # type: ignore
|
|
VP9_HINT_DUMP_SIZE_IN_SB64 = ((64*64)/(4*4)*8)
|
|
VP9_HINT_DUMP_SIZE = lambda w,h: NVDEC_ALIGN(VP9_HINT_DUMP_SIZE_IN_SB64*((w+63)/64)*((h+63)/64)) # type: ignore
|
|
NUM_SUBSAMPLES = 32
|
|
VP8_MAX_TOKEN_PARTITIONS = 8
|
|
VP9_MAX_FRAMES_IN_SUPERFRAME = 8
|
|
AV1_MAX_TILES = 256
|
|
MAX_SUBSTREAM_ENTRY_SIZE = 32
|
|
AV1_TEMPORAL_MV_SIZE_IN_64x64 = 256
|
|
AV1_TEMPORAL_MV_BUF_SIZE = lambda w,h: ALIGN_UP( ALIGN_UP(w,128) * ALIGN_UP(h,128) / (64*64) * AV1_TEMPORAL_MV_SIZE_IN_64x64, 4096) # type: ignore
|
|
AV1_SEGMENT_ID_SIZE_IN_64x64 = 128
|
|
AV1_SEGMENT_ID_BUF_SIZE = lambda w,h: ALIGN_UP( ALIGN_UP(w,128) * ALIGN_UP(h,128) / (64*64) * AV1_SEGMENT_ID_SIZE_IN_64x64, 4096) # type: ignore
|
|
AV1_GLOBAL_MOTION_BUF_SIZE = NVDEC_ALIGN(7*32)
|
|
AV1_INTRA_TOP_BUF_SIZE = NVDEC_ALIGN(8*8192)
|
|
AV1_HISTOGRAM_BUF_SIZE = NVDEC_ALIGN(1024)
|
|
AV1_DBLK_TOP_SIZE_IN_SB64 = ALIGN_UP(1920, 128)
|
|
AV1_DBLK_TOP_BUF_SIZE = lambda w: NVDEC_ALIGN( (ALIGN_UP(w,64)/64 + 2) * AV1_DBLK_TOP_SIZE_IN_SB64) # type: ignore
|
|
AV1_DBLK_LEFT_SIZE_IN_SB64 = ALIGN_UP(1536, 128)
|
|
AV1_DBLK_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_DBLK_LEFT_SIZE_IN_SB64) # type: ignore
|
|
AV1_CDEF_LEFT_SIZE_IN_SB64 = ALIGN_UP(1792, 128)
|
|
AV1_CDEF_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_CDEF_LEFT_SIZE_IN_SB64) # type: ignore
|
|
AV1_HUS_LEFT_SIZE_IN_SB64 = ALIGN_UP(12544, 128)
|
|
AV1_ASIC_HUS_LEFT_BUFFER_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_HUS_LEFT_SIZE_IN_SB64) # type: ignore
|
|
AV1_HUS_LEFT_BUF_SIZE = lambda h: 2*AV1_ASIC_HUS_LEFT_BUFFER_SIZE(h) # type: ignore
|
|
AV1_LR_LEFT_SIZE_IN_SB64 = ALIGN_UP(1920, 128)
|
|
AV1_LR_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_LR_LEFT_SIZE_IN_SB64) # type: ignore
|
|
AV1_FGS_LEFT_SIZE_IN_SB64 = ALIGN_UP(320, 128)
|
|
AV1_FGS_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_FGS_LEFT_SIZE_IN_SB64) # type: ignore
|
|
AV1_HINT_DUMP_SIZE_IN_SB64 = ((64*64)/(4*4)*8)
|
|
AV1_HINT_DUMP_SIZE_IN_SB128 = ((128*128)/(4*4)*8)
|
|
AV1_HINT_DUMP_SIZE = lambda w,h: NVDEC_ALIGN(AV1_HINT_DUMP_SIZE_IN_SB128*((w+127)/128)*((h+127)/128)) # type: ignore
|
|
NVBIT = lambda b: (1<<(b)) # type: ignore
|
|
NVBIT32 = lambda b: NVBIT_TYPE(b, NvU32) # type: ignore
|
|
NVBIT64 = lambda b: NVBIT_TYPE(b, NvU64) # type: ignore
|
|
NV_BITMASK32_IDX = lambda chId: (((chId) & ~(0x1F)) >> 5) # type: ignore
|
|
NV_BITMASK32_OFFSET = lambda chId: ((chId) & (0x1F)) # type: ignore
|
|
NV_BITMASK32_GET = lambda pChannelMask,chId: ((pChannelMask)[NV_BITMASK32_IDX(chId)] & NVBIT(NV_BITMASK32_OFFSET(chId))) # type: ignore
|
|
DRF_SHIFT = lambda drf: ((DRF_ISBIT(0,drf)) % 32) # type: ignore
|
|
DRF_SHIFT_RT = lambda drf: ((DRF_ISBIT(1,drf)) % 32) # type: ignore
|
|
DRF_SIZE = lambda drf: (DRF_EXTENT(drf)-DRF_BASE(drf)+1) # type: ignore
|
|
DRF_MASK = lambda drf: (0xFFFFFFFF>>(31-((DRF_ISBIT(1,drf)) % 32)+((DRF_ISBIT(0,drf)) % 32))) # type: ignore
|
|
DRF_SHIFTMASK = lambda drf: (DRF_MASK(drf)<<(DRF_SHIFT(drf))) # type: ignore
|
|
DRF_SHIFT64 = lambda drf: ((DRF_ISBIT(0,drf)) % 64) # type: ignore
|
|
DRF_MASK64 = lambda drf: (NV_U64_MAX>>(63-((DRF_ISBIT(1,drf)) % 64)+((DRF_ISBIT(0,drf)) % 64))) # type: ignore
|
|
DRF_SHIFTMASK64 = lambda drf: (DRF_MASK64(drf)<<(DRF_SHIFT64(drf))) # type: ignore
|
|
FLD_TEST_DRF_NUM64 = lambda d,r,f,n,v: (DRF_VAL64(d, r, f, (v)) == (n)) # type: ignore
|
|
REF_VAL64 = lambda drf,v: (((NvU64)(v)>>DRF_SHIFT64(drf))&DRF_MASK64(drf)) # type: ignore
|
|
REF_NUM64 = lambda drf,n: (((NvU64)(n)&DRF_MASK64(drf))<<DRF_SHIFT64(drf)) # type: ignore
|
|
FLD_SET_REF_NUM64 = lambda drf,n,v: (((NvU64)(v) & ~DRF_SHIFTMASK64(drf)) | REF_NUM64(drf,n)) # type: ignore
|
|
FLD_TEST_DRF_NUM = lambda d,r,f,n,v: ((DRF_VAL(d, r, f, (v)) == (n))) # type: ignore
|
|
REF_VAL = lambda drf,v: (((v)>>DRF_SHIFT(drf))&DRF_MASK(drf)) # type: ignore
|
|
REF_NUM = lambda drf,n: (((n)&DRF_MASK(drf))<<DRF_SHIFT(drf)) # type: ignore
|
|
FLD_SET_REF_NUM = lambda drf,n,v: (((v) & ~DRF_SHIFTMASK(drf)) | REF_NUM(drf,n)) # type: ignore
|
|
DRF_EXPAND_MW = lambda drf: drf # type: ignore
|
|
DRF_WORD_MW = lambda drf: (DRF_PICK_MW(drf,0)/32) # type: ignore
|
|
DRF_BASE_MW = lambda drf: (DRF_PICK_MW(drf,0)%32) # type: ignore
|
|
DRF_EXTENT_MW = lambda drf: (DRF_PICK_MW(drf,1)%32) # type: ignore
|
|
DRF_SHIFT_MW = lambda drf: (DRF_PICK_MW(drf,0)%32) # type: ignore
|
|
DRF_MASK_MW = lambda drf: (0xFFFFFFFF>>((31-(DRF_EXTENT_MW(drf))+(DRF_BASE_MW(drf)))%32)) # type: ignore
|
|
DRF_SHIFTMASK_MW = lambda drf: ((DRF_MASK_MW(drf))<<(DRF_SHIFT_MW(drf))) # type: ignore
|
|
DRF_SIZE_MW = lambda drf: (DRF_EXTENT_MW(drf)-DRF_BASE_MW(drf)+1) # type: ignore
|
|
DRF_WORD_MW_LOW = lambda drf: (DRF_PICK_MW(drf,0)/32) # type: ignore
|
|
DRF_WORD_MW_HIGH = lambda drf: (DRF_PICK_MW(drf,1)/32) # type: ignore
|
|
DRF_MASK_MW_LOW = lambda drf: (0xFFFFFFFF) # type: ignore
|
|
DRF_MASK_MW_HIGH = lambda drf: (0xFFFFFFFF>>(31-(DRF_EXTENT_MW(drf)))) # type: ignore
|
|
DRF_SHIFT_MW_LOW = lambda drf: (DRF_PICK_MW(drf,0)%32) # type: ignore
|
|
DRF_SHIFT_MW_HIGH = lambda drf: (0) # type: ignore
|
|
DRF_MERGE_SHIFT = lambda drf: ((32-((DRF_PICK_MW(drf,0)%32)))%32) # type: ignore
|
|
FLD_MERGE_MW = lambda drf,n,v: (((v)[DRF_WORD_MW(drf)] & ~DRF_SHIFTMASK_MW(drf)) | n) # type: ignore
|
|
FLD_IDX_MERGE_MW = lambda drf,i,n,v: (((v)[DRF_WORD_MW(drf(i))] & ~DRF_SHIFTMASK_MW(drf(i))) | n) # type: ignore
|
|
FLD_TEST_DRF_NUM_MW = lambda d,r,f,n,v: ((DRF_VAL_MW(d, r, f, (v)) == n)) # type: ignore
|
|
NV_TWO_N_MINUS_ONE = lambda n: (((1<<(n/2))<<((n+1)/2))-1) # type: ignore
|
|
LOWESTBIT = lambda x: ( (x) & (((x) - 1) ^ (x)) ) # type: ignore
|
|
NV_ANYSIZE_ARRAY = 1
|
|
NV_CEIL = lambda a,b: (((a)+(b)-1)/(b)) # type: ignore
|
|
NV_DIV_AND_CEIL = lambda a,b: NV_CEIL(a,b) # type: ignore
|
|
NV_SIGN = lambda s: ((NvS8)(((s) > 0) - ((s) < 0))) # type: ignore
|
|
NV_ZERO_SIGN = lambda s: ((NvS8)((((s) >= 0) * 2) - 1)) # type: ignore
|
|
NV_UNSIGNED_ROUNDED_DIV = lambda a,b: (((a) + ((b) / 2)) / (b)) # type: ignore
|
|
NV_UNSIGNED_DIV_CEIL = lambda a,b: (((a) + (b - 1)) / (b)) # type: ignore
|
|
NV_ALIGN_DOWN = lambda v,gran: ((v) & ~((v) - (v) + (gran) - 1)) # type: ignore
|
|
NV_ALIGN_UP = lambda v,gran: (((v) + ((gran) - 1)) & ~((v) - (v) + (gran) - 1)) # type: ignore
|
|
NV_IS_ALIGNED = lambda v,gran: (0 == ((v) & ((gran) - 1))) # type: ignore
|
|
NV_BIT_GET = lambda k,x: (((x) >> (k)) & 1) # type: ignore
|
|
NV_ARRAY_ELEMENTS = lambda x: ((sizeof(x)/sizeof((x)[0]))) # type: ignore
|
|
BIT = lambda b: (1<<(b)) # type: ignore
|
|
NV01_NULL_OBJECT = (0x0)
|
|
NV1_NULL_OBJECT = NV01_NULL_OBJECT
|
|
NV01_ROOT = (0x0)
|
|
NV0000_ALLOC_PARAMETERS_MESSAGE_ID = (0x0000)
|
|
NV01_MEMORY_VIRTUAL = (0x70)
|
|
NV01_MEMORY_SYSTEM_DYNAMIC = (0x70)
|
|
NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID = (0x0070)
|
|
NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE = 0xffffffff
|
|
NV01_DEVICE_0 = (0x80)
|
|
NV0080_ALLOC_PARAMETERS_MESSAGE_ID = (0x0080)
|
|
NV20_SUBDEVICE_0 = (0x2080)
|
|
NV2080_ALLOC_PARAMETERS_MESSAGE_ID = (0x2080)
|
|
NV2080_NOTIFIERS_SW = (0)
|
|
NV2080_NOTIFIERS_HOTPLUG = (1)
|
|
NV2080_NOTIFIERS_POWER_CONNECTOR = (2)
|
|
NV2080_NOTIFIERS_THERMAL_SW = (3)
|
|
NV2080_NOTIFIERS_THERMAL_HW = (4)
|
|
NV2080_NOTIFIERS_FULL_SCREEN_CHANGE = (5)
|
|
NV2080_NOTIFIERS_EVENTBUFFER = (6)
|
|
NV2080_NOTIFIERS_DP_IRQ = (7)
|
|
NV2080_NOTIFIERS_GR_DEBUG_INTR = (8)
|
|
NV2080_NOTIFIERS_PMU_EVENT = (9)
|
|
NV2080_NOTIFIERS_PMU_COMMAND = (10)
|
|
NV2080_NOTIFIERS_TIMER = (11)
|
|
NV2080_NOTIFIERS_GRAPHICS = (12)
|
|
NV2080_NOTIFIERS_PPP = (13)
|
|
NV2080_NOTIFIERS_VLD = (14)
|
|
NV2080_NOTIFIERS_NVDEC0 = NV2080_NOTIFIERS_VLD
|
|
NV2080_NOTIFIERS_NVDEC1 = (15)
|
|
NV2080_NOTIFIERS_NVDEC2 = (16)
|
|
NV2080_NOTIFIERS_NVDEC3 = (17)
|
|
NV2080_NOTIFIERS_NVDEC4 = (18)
|
|
NV2080_NOTIFIERS_NVDEC5 = (19)
|
|
NV2080_NOTIFIERS_NVDEC6 = (20)
|
|
NV2080_NOTIFIERS_NVDEC7 = (21)
|
|
NV2080_NOTIFIERS_PDEC = (22)
|
|
NV2080_NOTIFIERS_CE0 = (23)
|
|
NV2080_NOTIFIERS_CE1 = (24)
|
|
NV2080_NOTIFIERS_CE2 = (25)
|
|
NV2080_NOTIFIERS_CE3 = (26)
|
|
NV2080_NOTIFIERS_CE4 = (27)
|
|
NV2080_NOTIFIERS_CE5 = (28)
|
|
NV2080_NOTIFIERS_CE6 = (29)
|
|
NV2080_NOTIFIERS_CE7 = (30)
|
|
NV2080_NOTIFIERS_CE8 = (31)
|
|
NV2080_NOTIFIERS_CE9 = (32)
|
|
NV2080_NOTIFIERS_PSTATE_CHANGE = (33)
|
|
NV2080_NOTIFIERS_HDCP_STATUS_CHANGE = (34)
|
|
NV2080_NOTIFIERS_FIFO_EVENT_MTHD = (35)
|
|
NV2080_NOTIFIERS_PRIV_RING_HANG = (36)
|
|
NV2080_NOTIFIERS_RC_ERROR = (37)
|
|
NV2080_NOTIFIERS_MSENC = (38)
|
|
NV2080_NOTIFIERS_NVENC0 = NV2080_NOTIFIERS_MSENC
|
|
NV2080_NOTIFIERS_NVENC1 = (39)
|
|
NV2080_NOTIFIERS_NVENC2 = (40)
|
|
NV2080_NOTIFIERS_UNUSED_0 = (41)
|
|
NV2080_NOTIFIERS_ACPI_NOTIFY = (42)
|
|
NV2080_NOTIFIERS_COOLER_DIAG_ZONE = (43)
|
|
NV2080_NOTIFIERS_THERMAL_DIAG_ZONE = (44)
|
|
NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST = (45)
|
|
NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE = (46)
|
|
NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT = (47)
|
|
NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT = (48)
|
|
NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT = (49)
|
|
NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT = (50)
|
|
NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT = (51)
|
|
NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT = (52)
|
|
NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT = (53)
|
|
NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT = (54)
|
|
NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT = (55)
|
|
NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT = (56)
|
|
NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT = (57)
|
|
NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT = (58)
|
|
NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT = (59)
|
|
NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT = (60)
|
|
NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT = (61)
|
|
NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT = (62)
|
|
NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT = (63)
|
|
NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT = (64)
|
|
NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT = (65)
|
|
NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT = (66)
|
|
NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT = (67)
|
|
NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT = (68)
|
|
NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT = (69)
|
|
NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT = (70)
|
|
NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT = (71)
|
|
NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT = (72)
|
|
NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT = (73)
|
|
NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT = (74)
|
|
NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT = (75)
|
|
NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT = (76)
|
|
NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT = (77)
|
|
NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT = (78)
|
|
NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT = (79)
|
|
NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT = (80)
|
|
NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT = (81)
|
|
NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT = (82)
|
|
NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT = (83)
|
|
NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT = (84)
|
|
NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT = (85)
|
|
NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT = (86)
|
|
NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT = (87)
|
|
NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT = (88)
|
|
NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT = (89)
|
|
NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT = (90)
|
|
NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT = (91)
|
|
NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT = (92)
|
|
NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT = (93)
|
|
NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT = (94)
|
|
NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT = (95)
|
|
NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT = (96)
|
|
NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT = (97)
|
|
NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT = (98)
|
|
NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT = (99)
|
|
NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT = (100)
|
|
NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT = (101)
|
|
NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT = (102)
|
|
NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT = (103)
|
|
NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT = (104)
|
|
NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT = (105)
|
|
NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT = (106)
|
|
NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT = (107)
|
|
NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT = (108)
|
|
NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT = (109)
|
|
NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT = (110)
|
|
NV2080_NOTIFIERS_ECC_SBE = (111)
|
|
NV2080_NOTIFIERS_ECC_DBE = (112)
|
|
NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION = (113)
|
|
NV2080_NOTIFIERS_GC5_GPU_READY = (114)
|
|
NV2080_NOTIFIERS_SEC2 = (115)
|
|
NV2080_NOTIFIERS_GC6_REFCOUNT_INC = (116)
|
|
NV2080_NOTIFIERS_GC6_REFCOUNT_DEC = (117)
|
|
NV2080_NOTIFIERS_POWER_EVENT = (118)
|
|
NV2080_NOTIFIERS_CLOCKS_CHANGE = (119)
|
|
NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE = (120)
|
|
NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT = (121)
|
|
NV2080_NOTIFIERS_RESERVED122 = (122)
|
|
NV2080_NOTIFIERS_NVLINK_ERROR_FATAL = (123)
|
|
NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT = (124)
|
|
NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED = (125)
|
|
NV2080_NOTIFIERS_NVJPG = (126)
|
|
NV2080_NOTIFIERS_NVJPEG0 = NV2080_NOTIFIERS_NVJPG
|
|
NV2080_NOTIFIERS_NVJPEG1 = (127)
|
|
NV2080_NOTIFIERS_NVJPEG2 = (128)
|
|
NV2080_NOTIFIERS_NVJPEG3 = (129)
|
|
NV2080_NOTIFIERS_NVJPEG4 = (130)
|
|
NV2080_NOTIFIERS_NVJPEG5 = (131)
|
|
NV2080_NOTIFIERS_NVJPEG6 = (132)
|
|
NV2080_NOTIFIERS_NVJPEG7 = (133)
|
|
NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE = (134)
|
|
NV2080_NOTIFIERS_RUNLIST_ACQUIRE = (135)
|
|
NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE = (136)
|
|
NV2080_NOTIFIERS_RUNLIST_IDLE = (137)
|
|
NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE = (138)
|
|
NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE = (139)
|
|
NV2080_NOTIFIERS_CTXSW_TIMEOUT = (140)
|
|
NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED = (141)
|
|
NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT = (142)
|
|
NV2080_NOTIFIERS_DSTATE_XUSB_PPC = (143)
|
|
NV2080_NOTIFIERS_FECS_CTX_SWITCH = (144)
|
|
NV2080_NOTIFIERS_XUSB_PPC_CONNECTED = (145)
|
|
NV2080_NOTIFIERS_GR0 = NV2080_NOTIFIERS_GRAPHICS
|
|
NV2080_NOTIFIERS_GR1 = (146)
|
|
NV2080_NOTIFIERS_GR2 = (147)
|
|
NV2080_NOTIFIERS_GR3 = (148)
|
|
NV2080_NOTIFIERS_GR4 = (149)
|
|
NV2080_NOTIFIERS_GR5 = (150)
|
|
NV2080_NOTIFIERS_GR6 = (151)
|
|
NV2080_NOTIFIERS_GR7 = (152)
|
|
NV2080_NOTIFIERS_OFA = (153)
|
|
NV2080_NOTIFIERS_OFA0 = NV2080_NOTIFIERS_OFA
|
|
NV2080_NOTIFIERS_DSTATE_HDA = (154)
|
|
NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL = (155)
|
|
NV2080_NOTIFIERS_POISON_ERROR_FATAL = (156)
|
|
NV2080_NOTIFIERS_UCODE_RESET = (157)
|
|
NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE = (158)
|
|
NV2080_NOTIFIERS_SMC_CONFIG_UPDATE = (159)
|
|
NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED = (160)
|
|
NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED = (161)
|
|
NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST = (162)
|
|
NV2080_NOTIFIERS_SEC_FAULT_ERROR = (163)
|
|
NV2080_NOTIFIERS_UNUSED_1 = (164)
|
|
NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP = (165)
|
|
NV2080_NOTIFIERS_CE10 = (166)
|
|
NV2080_NOTIFIERS_CE11 = (167)
|
|
NV2080_NOTIFIERS_CE12 = (168)
|
|
NV2080_NOTIFIERS_CE13 = (169)
|
|
NV2080_NOTIFIERS_CE14 = (170)
|
|
NV2080_NOTIFIERS_CE15 = (171)
|
|
NV2080_NOTIFIERS_CE16 = (172)
|
|
NV2080_NOTIFIERS_CE17 = (173)
|
|
NV2080_NOTIFIERS_CE18 = (174)
|
|
NV2080_NOTIFIERS_CE19 = (175)
|
|
NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN = (176)
|
|
NV2080_NOTIFIERS_NVPCF_EVENTS = (177)
|
|
NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST = (178)
|
|
NV2080_NOTIFIERS_OFA1 = (180)
|
|
NV2080_NOTIFIERS_AUX_POWER_EVENT = (181)
|
|
NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE = (182)
|
|
NV2080_NOTIFIERS_NVENC3 = (183)
|
|
NV2080_NOTIFIERS_GSP_PERF_TRACE = (184)
|
|
NV2080_NOTIFIERS_INBAND_RESPONSE = (185)
|
|
NV2080_NOTIFIERS_RESERVED_186 = (186)
|
|
NV2080_NOTIFIERS_ECC_SBE_STORM = (187)
|
|
NV2080_NOTIFIERS_DRAM_RETIREMENT_EVENT = (188)
|
|
NV2080_NOTIFIERS_DRAM_RETIREMENT_FAILURE = (189)
|
|
NV2080_NOTIFIERS_NVLINK_UNCONTAINED_ERROR = (190)
|
|
NV2080_NOTIFIERS_GPU_UNAVAILABLE = (191)
|
|
NV2080_NOTIFIERS_GPU_RECOVERY_ACTION = (192)
|
|
NV2080_NOTIFIERS_POWER_SUSPEND = (193)
|
|
NV2080_NOTIFIERS_POWER_RESUME = (194)
|
|
NV2080_NOTIFIERS_CTXSW_UCODE_ERROR = (195)
|
|
NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD = (196)
|
|
NV2080_NOTIFIERS_GPU_RC_RESET = (197)
|
|
NV2080_NOTIFIERS_RESERVED_198 = (198)
|
|
NV2080_NOTIFIERS_INFOROM_BRL_OBJECT_UPDATED = (199)
|
|
NV2080_NOTIFIERS_MAXCOUNT = (200)
|
|
NV2080_NOTIFIERS_GR_IDX = lambda x: ((x) - NV2080_NOTIFIERS_GR0) # type: ignore
|
|
NV2080_NOTIFIER_TYPE_IS_GR = lambda x: (((x) == NV2080_NOTIFIERS_GR0) or (((x) >= NV2080_NOTIFIERS_GR1) and ((x) <= NV2080_NOTIFIERS_GR7))) # type: ignore
|
|
NV2080_NOTIFIER_TYPE_IS_CE = lambda x: ((((x) >= NV2080_NOTIFIERS_CE0) and ((x) <= NV2080_NOTIFIERS_CE9)) or (((x) >= NV2080_NOTIFIERS_CE10) and ((x) <= NV2080_NOTIFIERS_CE19))) # type: ignore
|
|
NV2080_NOTIFIER_TYPE_IS_NVENC = lambda x: ((((x) >= NV2080_NOTIFIERS_NVENC0) and ((x) <= NV2080_NOTIFIERS_NVENC2)) or (((x) == NV2080_NOTIFIERS_NVENC3))) # type: ignore
|
|
NV2080_NOTIFIERS_NVDEC = lambda x: (NV2080_NOTIFIERS_NVDEC0 + (x)) # type: ignore
|
|
NV2080_NOTIFIERS_NVDEC_IDX = lambda x: ((x) - NV2080_NOTIFIERS_NVDEC0) # type: ignore
|
|
NV2080_NOTIFIER_TYPE_IS_NVDEC = lambda x: (((x) >= NV2080_NOTIFIERS_NVDEC0) and ((x) <= NV2080_NOTIFIERS_NVDEC7)) # type: ignore
|
|
NV2080_NOTIFIERS_NVJPEG = lambda x: (NV2080_NOTIFIERS_NVJPEG0 + (x)) # type: ignore
|
|
NV2080_NOTIFIERS_NVJPEG_IDX = lambda x: ((x) - NV2080_NOTIFIERS_NVJPEG0) # type: ignore
|
|
NV2080_NOTIFIER_TYPE_IS_NVJPEG = lambda x: (((x) >= NV2080_NOTIFIERS_NVJPEG0) and ((x) <= NV2080_NOTIFIERS_NVJPEG7)) # type: ignore
|
|
NV2080_NOTIFIER_TYPE_IS_OFA = lambda x: (((x) == NV2080_NOTIFIERS_OFA0) or ((x) == NV2080_NOTIFIERS_OFA1)) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT = lambda pin: (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT + (pin)) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT = lambda pin: (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT + (pin)) # type: ignore
|
|
NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS = (0x8000)
|
|
NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT = (0x4000)
|
|
NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE = (0x2000)
|
|
NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE = (0x1000)
|
|
NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS = (0x0000)
|
|
NV2080_ENGINE_TYPE_NULL = (0x00000000)
|
|
NV2080_ENGINE_TYPE_GRAPHICS = (0x00000001)
|
|
NV2080_ENGINE_TYPE_GR0 = NV2080_ENGINE_TYPE_GRAPHICS
|
|
NV2080_ENGINE_TYPE_GR1 = (0x00000002)
|
|
NV2080_ENGINE_TYPE_GR2 = (0x00000003)
|
|
NV2080_ENGINE_TYPE_GR3 = (0x00000004)
|
|
NV2080_ENGINE_TYPE_GR4 = (0x00000005)
|
|
NV2080_ENGINE_TYPE_GR5 = (0x00000006)
|
|
NV2080_ENGINE_TYPE_GR6 = (0x00000007)
|
|
NV2080_ENGINE_TYPE_GR7 = (0x00000008)
|
|
NV2080_ENGINE_TYPE_COPY0 = (0x00000009)
|
|
NV2080_ENGINE_TYPE_COPY1 = (0x0000000a)
|
|
NV2080_ENGINE_TYPE_COPY2 = (0x0000000b)
|
|
NV2080_ENGINE_TYPE_COPY3 = (0x0000000c)
|
|
NV2080_ENGINE_TYPE_COPY4 = (0x0000000d)
|
|
NV2080_ENGINE_TYPE_COPY5 = (0x0000000e)
|
|
NV2080_ENGINE_TYPE_COPY6 = (0x0000000f)
|
|
NV2080_ENGINE_TYPE_COPY7 = (0x00000010)
|
|
NV2080_ENGINE_TYPE_COPY8 = (0x00000011)
|
|
NV2080_ENGINE_TYPE_COPY9 = (0x00000012)
|
|
NV2080_ENGINE_TYPE_BSP = (0x00000013)
|
|
NV2080_ENGINE_TYPE_NVDEC0 = NV2080_ENGINE_TYPE_BSP
|
|
NV2080_ENGINE_TYPE_NVDEC1 = (0x00000014)
|
|
NV2080_ENGINE_TYPE_NVDEC2 = (0x00000015)
|
|
NV2080_ENGINE_TYPE_NVDEC3 = (0x00000016)
|
|
NV2080_ENGINE_TYPE_NVDEC4 = (0x00000017)
|
|
NV2080_ENGINE_TYPE_NVDEC5 = (0x00000018)
|
|
NV2080_ENGINE_TYPE_NVDEC6 = (0x00000019)
|
|
NV2080_ENGINE_TYPE_NVDEC7 = (0x0000001a)
|
|
NV2080_ENGINE_TYPE_MSENC = (0x0000001b)
|
|
NV2080_ENGINE_TYPE_NVENC0 = NV2080_ENGINE_TYPE_MSENC
|
|
NV2080_ENGINE_TYPE_NVENC1 = (0x0000001c)
|
|
NV2080_ENGINE_TYPE_NVENC2 = (0x0000001d)
|
|
NV2080_ENGINE_TYPE_VP = (0x0000001e)
|
|
NV2080_ENGINE_TYPE_ME = (0x0000001f)
|
|
NV2080_ENGINE_TYPE_PPP = (0x00000020)
|
|
NV2080_ENGINE_TYPE_MPEG = (0x00000021)
|
|
NV2080_ENGINE_TYPE_SW = (0x00000022)
|
|
NV2080_ENGINE_TYPE_CIPHER = (0x00000023)
|
|
NV2080_ENGINE_TYPE_TSEC = NV2080_ENGINE_TYPE_CIPHER
|
|
NV2080_ENGINE_TYPE_VIC = (0x00000024)
|
|
NV2080_ENGINE_TYPE_MP = (0x00000025)
|
|
NV2080_ENGINE_TYPE_SEC2 = (0x00000026)
|
|
NV2080_ENGINE_TYPE_HOST = (0x00000027)
|
|
NV2080_ENGINE_TYPE_DPU = (0x00000028)
|
|
NV2080_ENGINE_TYPE_PMU = (0x00000029)
|
|
NV2080_ENGINE_TYPE_FBFLCN = (0x0000002a)
|
|
NV2080_ENGINE_TYPE_NVJPG = (0x0000002b)
|
|
NV2080_ENGINE_TYPE_NVJPEG0 = NV2080_ENGINE_TYPE_NVJPG
|
|
NV2080_ENGINE_TYPE_NVJPEG1 = (0x0000002c)
|
|
NV2080_ENGINE_TYPE_NVJPEG2 = (0x0000002d)
|
|
NV2080_ENGINE_TYPE_NVJPEG3 = (0x0000002e)
|
|
NV2080_ENGINE_TYPE_NVJPEG4 = (0x0000002f)
|
|
NV2080_ENGINE_TYPE_NVJPEG5 = (0x00000030)
|
|
NV2080_ENGINE_TYPE_NVJPEG6 = (0x00000031)
|
|
NV2080_ENGINE_TYPE_NVJPEG7 = (0x00000032)
|
|
NV2080_ENGINE_TYPE_OFA = (0x00000033)
|
|
NV2080_ENGINE_TYPE_OFA0 = NV2080_ENGINE_TYPE_OFA
|
|
NV2080_ENGINE_TYPE_COPY10 = (0x00000034)
|
|
NV2080_ENGINE_TYPE_COPY11 = (0x00000035)
|
|
NV2080_ENGINE_TYPE_COPY12 = (0x00000036)
|
|
NV2080_ENGINE_TYPE_COPY13 = (0x00000037)
|
|
NV2080_ENGINE_TYPE_COPY14 = (0x00000038)
|
|
NV2080_ENGINE_TYPE_COPY15 = (0x00000039)
|
|
NV2080_ENGINE_TYPE_COPY16 = (0x0000003a)
|
|
NV2080_ENGINE_TYPE_COPY17 = (0x0000003b)
|
|
NV2080_ENGINE_TYPE_COPY18 = (0x0000003c)
|
|
NV2080_ENGINE_TYPE_COPY19 = (0x0000003d)
|
|
NV2080_ENGINE_TYPE_OFA1 = (0x0000003e)
|
|
NV2080_ENGINE_TYPE_NVENC3 = (0x0000003f)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 = (0x00000040)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY1 = (0x00000041)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY2 = (0x00000042)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY3 = (0x00000043)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY4 = (0x00000044)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY5 = (0x00000045)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY6 = (0x00000046)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY7 = (0x00000047)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY8 = (0x00000048)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY9 = (0x00000049)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY10 = (0x0000004a)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY11 = (0x0000004b)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY12 = (0x0000004c)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY13 = (0x0000004d)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY14 = (0x0000004e)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY15 = (0x0000004f)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY16 = (0x00000050)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY17 = (0x00000051)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY18 = (0x00000052)
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19 = (0x00000053)
|
|
NV2080_ENGINE_TYPE_LAST = (0x00000054)
|
|
NV2080_ENGINE_TYPE_ALLENGINES = (0xffffffff)
|
|
NV2080_ENGINE_TYPE_COPY_SIZE = 64
|
|
NV2080_ENGINE_TYPE_NVENC_SIZE = 4
|
|
NV2080_ENGINE_TYPE_NVJPEG_SIZE = 8
|
|
NV2080_ENGINE_TYPE_NVDEC_SIZE = 8
|
|
NV2080_ENGINE_TYPE_GR_SIZE = 8
|
|
NV2080_ENGINE_TYPE_OFA_SIZE = 2
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY = lambda i: (NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 + (i)) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_COMP_DECOMP_COPY = lambda i: (((i) >= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0) and ((i) <= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19)) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_COPY = lambda i: ((((i) >= NV2080_ENGINE_TYPE_COPY0) and ((i) <= NV2080_ENGINE_TYPE_COPY9)) or (((i) >= NV2080_ENGINE_TYPE_COPY10) and ((i) <= NV2080_ENGINE_TYPE_COPY19))) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_NVENC = lambda i: ((((i) >= NV2080_ENGINE_TYPE_NVENC0) and ((i) <= NV2080_ENGINE_TYPE_NVENC2)) or (((i) == NV2080_ENGINE_TYPE_NVENC3))) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC = lambda i: (NV2080_ENGINE_TYPE_NVDEC0+(i)) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_NVDEC = lambda i: (((i) >= NV2080_ENGINE_TYPE_NVDEC0) and ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE))) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_NVDEC0) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG = lambda i: (NV2080_ENGINE_TYPE_NVJPEG0+(i)) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_NVJPEG = lambda i: (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) and ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE))) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_NVJPEG0) # type: ignore
|
|
NV2080_ENGINE_TYPE_GR = lambda i: (NV2080_ENGINE_TYPE_GR0 + (i)) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_GR = lambda i: (((i) >= NV2080_ENGINE_TYPE_GR0) and ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE))) # type: ignore
|
|
NV2080_ENGINE_TYPE_GR_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_GR0) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_OFA = lambda i: (((i) == NV2080_ENGINE_TYPE_OFA0) or ((i) == NV2080_ENGINE_TYPE_OFA1)) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_VALID = lambda i: (((i) > (NV2080_ENGINE_TYPE_NULL)) and ((i) < (NV2080_ENGINE_TYPE_LAST))) # type: ignore
|
|
NV2080_CLIENT_TYPE_TEX = (0x00000001)
|
|
NV2080_CLIENT_TYPE_COLOR = (0x00000002)
|
|
NV2080_CLIENT_TYPE_DEPTH = (0x00000003)
|
|
NV2080_CLIENT_TYPE_DA = (0x00000004)
|
|
NV2080_CLIENT_TYPE_FE = (0x00000005)
|
|
NV2080_CLIENT_TYPE_SCC = (0x00000006)
|
|
NV2080_CLIENT_TYPE_WID = (0x00000007)
|
|
NV2080_CLIENT_TYPE_MSVLD = (0x00000008)
|
|
NV2080_CLIENT_TYPE_MSPDEC = (0x00000009)
|
|
NV2080_CLIENT_TYPE_MSPPP = (0x0000000a)
|
|
NV2080_CLIENT_TYPE_VIC = (0x0000000b)
|
|
NV2080_CLIENT_TYPE_ALLCLIENTS = (0xffffffff)
|
|
NV2080_GC5_EXIT_COMPLETE = (0x00000001)
|
|
NV2080_GC5_ENTRY_ABORTED = (0x00000002)
|
|
NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION = (0x00000000)
|
|
NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION = (0x00000001)
|
|
NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT = (0x4000)
|
|
NV2080_TYPEDEF = Nv20Subdevice0
|
|
NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX = (7, 0)
|
|
NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK = (15, 8)
|
|
NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON = (23, 16)
|
|
AMPERE_CHANNEL_GPFIFO_A = (0x0000C56F)
|
|
NVC56F_NUMBER_OF_SUBCHANNELS = (8)
|
|
NVC56F_SET_OBJECT = (0x00000000)
|
|
NVC56F_SET_OBJECT_NVCLASS = (15, 0)
|
|
NVC56F_SET_OBJECT_ENGINE = (20, 16)
|
|
NVC56F_SET_OBJECT_ENGINE_SW = 0x0000001f
|
|
NVC56F_ILLEGAL = (0x00000004)
|
|
NVC56F_ILLEGAL_HANDLE = (31, 0)
|
|
NVC56F_NOP = (0x00000008)
|
|
NVC56F_NOP_HANDLE = (31, 0)
|
|
NVC56F_SEMAPHOREA = (0x00000010)
|
|
NVC56F_SEMAPHOREA_OFFSET_UPPER = (7, 0)
|
|
NVC56F_SEMAPHOREB = (0x00000014)
|
|
NVC56F_SEMAPHOREB_OFFSET_LOWER = (31, 2)
|
|
NVC56F_SEMAPHOREC = (0x00000018)
|
|
NVC56F_SEMAPHOREC_PAYLOAD = (31, 0)
|
|
NVC56F_SEMAPHORED = (0x0000001C)
|
|
NVC56F_SEMAPHORED_OPERATION = (4, 0)
|
|
NVC56F_SEMAPHORED_OPERATION_ACQUIRE = 0x00000001
|
|
NVC56F_SEMAPHORED_OPERATION_RELEASE = 0x00000002
|
|
NVC56F_SEMAPHORED_OPERATION_ACQ_GEQ = 0x00000004
|
|
NVC56F_SEMAPHORED_OPERATION_ACQ_AND = 0x00000008
|
|
NVC56F_SEMAPHORED_OPERATION_REDUCTION = 0x00000010
|
|
NVC56F_SEMAPHORED_ACQUIRE_SWITCH = (12, 12)
|
|
NVC56F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED = 0x00000000
|
|
NVC56F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED = 0x00000001
|
|
NVC56F_SEMAPHORED_RELEASE_WFI = (20, 20)
|
|
NVC56F_SEMAPHORED_RELEASE_WFI_EN = 0x00000000
|
|
NVC56F_SEMAPHORED_RELEASE_WFI_DIS = 0x00000001
|
|
NVC56F_SEMAPHORED_RELEASE_SIZE = (24, 24)
|
|
NVC56F_SEMAPHORED_RELEASE_SIZE_16BYTE = 0x00000000
|
|
NVC56F_SEMAPHORED_RELEASE_SIZE_4BYTE = 0x00000001
|
|
NVC56F_SEMAPHORED_REDUCTION = (30, 27)
|
|
NVC56F_SEMAPHORED_REDUCTION_MIN = 0x00000000
|
|
NVC56F_SEMAPHORED_REDUCTION_MAX = 0x00000001
|
|
NVC56F_SEMAPHORED_REDUCTION_XOR = 0x00000002
|
|
NVC56F_SEMAPHORED_REDUCTION_AND = 0x00000003
|
|
NVC56F_SEMAPHORED_REDUCTION_OR = 0x00000004
|
|
NVC56F_SEMAPHORED_REDUCTION_ADD = 0x00000005
|
|
NVC56F_SEMAPHORED_REDUCTION_INC = 0x00000006
|
|
NVC56F_SEMAPHORED_REDUCTION_DEC = 0x00000007
|
|
NVC56F_SEMAPHORED_FORMAT = (31, 31)
|
|
NVC56F_SEMAPHORED_FORMAT_SIGNED = 0x00000000
|
|
NVC56F_SEMAPHORED_FORMAT_UNSIGNED = 0x00000001
|
|
NVC56F_NON_STALL_INTERRUPT = (0x00000020)
|
|
NVC56F_NON_STALL_INTERRUPT_HANDLE = (31, 0)
|
|
NVC56F_FB_FLUSH = (0x00000024)
|
|
NVC56F_FB_FLUSH_HANDLE = (31, 0)
|
|
NVC56F_MEM_OP_A = (0x00000028)
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID = (5, 0)
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE = (5, 0)
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID = (10, 6)
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE = (7, 6)
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS = 0
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS = 1
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD = 3
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID = (6, 0)
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR = (11, 11)
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO = (31, 12)
|
|
NVC56F_MEM_OP_B = (0x0000002c)
|
|
NVC56F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI = (31, 0)
|
|
NVC56F_MEM_OP_C = (0x00000030)
|
|
NVC56F_MEM_OP_C_MEMBAR_TYPE = (2, 0)
|
|
NVC56F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR = 0x00000000
|
|
NVC56F_MEM_OP_C_MEMBAR_TYPE_MEMBAR = 0x00000001
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB = (0, 0)
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC = (1, 1)
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY = (4, 2)
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START = 0x00000001
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL = 0x00000002
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED = 0x00000003
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL = 0x00000004
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL = 0x00000005
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE = (6, 5)
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE = 0x00000002
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE = (9, 7)
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ = 0
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE = 1
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 2
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD = 3
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 4
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL = 5
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC = 6
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL = 7
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL = (9, 7)
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 = 0x00000002
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 = 0x00000003
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 = 0x00000004
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 = 0x00000005
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 = 0x00000007
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE = (11, 10)
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT = 0x00000003
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO = (31, 12)
|
|
NVC56F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG = (19, 0)
|
|
NVC56F_MEM_OP_D = (0x00000034)
|
|
NVC56F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI = (26, 0)
|
|
NVC56F_MEM_OP_D_OPERATION = (31, 27)
|
|
NVC56F_MEM_OP_D_OPERATION_MEMBAR = 0x00000005
|
|
NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009
|
|
NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a
|
|
NVC56F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE = 0x0000000d
|
|
NVC56F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE = 0x0000000e
|
|
NVC56F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES = 0x0000000e
|
|
NVC56F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS = 0x0000000f
|
|
NVC56F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010
|
|
NVC56F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS = 0x00000015
|
|
NVC56F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR = 0x00000016
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE = (1, 0)
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC = 0x00000000
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC = 0x00000001
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL = 0x00000002
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED = 0x00000003
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE = (2, 2)
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC = 0x00000000
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC = 0x00000001
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK = (6, 3)
|
|
NVC56F_SET_REFERENCE = (0x00000050)
|
|
NVC56F_SET_REFERENCE_COUNT = (31, 0)
|
|
NVC56F_SEM_ADDR_LO = (0x0000005c)
|
|
NVC56F_SEM_ADDR_LO_OFFSET = (31, 2)
|
|
NVC56F_SEM_ADDR_HI = (0x00000060)
|
|
NVC56F_SEM_ADDR_HI_OFFSET = (7, 0)
|
|
NVC56F_SEM_PAYLOAD_LO = (0x00000064)
|
|
NVC56F_SEM_PAYLOAD_LO_PAYLOAD = (31, 0)
|
|
NVC56F_SEM_PAYLOAD_HI = (0x00000068)
|
|
NVC56F_SEM_PAYLOAD_HI_PAYLOAD = (31, 0)
|
|
NVC56F_SEM_EXECUTE = (0x0000006c)
|
|
NVC56F_SEM_EXECUTE_OPERATION = (2, 0)
|
|
NVC56F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000
|
|
NVC56F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001
|
|
NVC56F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ = 0x00000002
|
|
NVC56F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ = 0x00000003
|
|
NVC56F_SEM_EXECUTE_OPERATION_ACQ_AND = 0x00000004
|
|
NVC56F_SEM_EXECUTE_OPERATION_ACQ_NOR = 0x00000005
|
|
NVC56F_SEM_EXECUTE_OPERATION_REDUCTION = 0x00000006
|
|
NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG = (12, 12)
|
|
NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS = 0x00000000
|
|
NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN = 0x00000001
|
|
NVC56F_SEM_EXECUTE_RELEASE_WFI = (20, 20)
|
|
NVC56F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000
|
|
NVC56F_SEM_EXECUTE_RELEASE_WFI_EN = 0x00000001
|
|
NVC56F_SEM_EXECUTE_PAYLOAD_SIZE = (24, 24)
|
|
NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000
|
|
NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT = 0x00000001
|
|
NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP = (25, 25)
|
|
NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS = 0x00000000
|
|
NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN = 0x00000001
|
|
NVC56F_SEM_EXECUTE_REDUCTION = (30, 27)
|
|
NVC56F_SEM_EXECUTE_REDUCTION_IMIN = 0x00000000
|
|
NVC56F_SEM_EXECUTE_REDUCTION_IMAX = 0x00000001
|
|
NVC56F_SEM_EXECUTE_REDUCTION_IXOR = 0x00000002
|
|
NVC56F_SEM_EXECUTE_REDUCTION_IAND = 0x00000003
|
|
NVC56F_SEM_EXECUTE_REDUCTION_IOR = 0x00000004
|
|
NVC56F_SEM_EXECUTE_REDUCTION_IADD = 0x00000005
|
|
NVC56F_SEM_EXECUTE_REDUCTION_INC = 0x00000006
|
|
NVC56F_SEM_EXECUTE_REDUCTION_DEC = 0x00000007
|
|
NVC56F_SEM_EXECUTE_REDUCTION_FORMAT = (31, 31)
|
|
NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED = 0x00000000
|
|
NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED = 0x00000001
|
|
NVC56F_WFI = (0x00000078)
|
|
NVC56F_WFI_SCOPE = (0, 0)
|
|
NVC56F_WFI_SCOPE_CURRENT_SCG_TYPE = 0x00000000
|
|
NVC56F_WFI_SCOPE_CURRENT_VEID = 0x00000000
|
|
NVC56F_WFI_SCOPE_ALL = 0x00000001
|
|
NVC56F_YIELD = (0x00000080)
|
|
NVC56F_YIELD_OP = (1, 0)
|
|
NVC56F_YIELD_OP_NOP = 0x00000000
|
|
NVC56F_YIELD_OP_TSG = 0x00000003
|
|
NVC56F_CLEAR_FAULTED = (0x00000084)
|
|
NVC56F_CLEAR_FAULTED_HANDLE = (30, 0)
|
|
NVC56F_CLEAR_FAULTED_TYPE = (31, 31)
|
|
NVC56F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED = 0x00000000
|
|
NVC56F_CLEAR_FAULTED_TYPE_ENG_FAULTED = 0x00000001
|
|
NVC56F_GP_ENTRY__SIZE = 8
|
|
NVC56F_GP_ENTRY0_FETCH = (0, 0)
|
|
NVC56F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000
|
|
NVC56F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001
|
|
NVC56F_GP_ENTRY0_GET = (31, 2)
|
|
NVC56F_GP_ENTRY0_OPERAND = (31, 0)
|
|
NVC56F_GP_ENTRY1_GET_HI = (7, 0)
|
|
NVC56F_GP_ENTRY1_LEVEL = (9, 9)
|
|
NVC56F_GP_ENTRY1_LEVEL_MAIN = 0x00000000
|
|
NVC56F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001
|
|
NVC56F_GP_ENTRY1_LENGTH = (30, 10)
|
|
NVC56F_GP_ENTRY1_SYNC = (31, 31)
|
|
NVC56F_GP_ENTRY1_SYNC_PROCEED = 0x00000000
|
|
NVC56F_GP_ENTRY1_SYNC_WAIT = 0x00000001
|
|
NVC56F_GP_ENTRY1_OPCODE = (7, 0)
|
|
NVC56F_GP_ENTRY1_OPCODE_NOP = 0x00000000
|
|
NVC56F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001
|
|
NVC56F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002
|
|
NVC56F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003
|
|
NVC56F_DMA_METHOD_ADDRESS_OLD = (12, 2)
|
|
NVC56F_DMA_METHOD_ADDRESS = (11, 0)
|
|
NVC56F_DMA_SUBDEVICE_MASK = (15, 4)
|
|
NVC56F_DMA_METHOD_SUBCHANNEL = (15, 13)
|
|
NVC56F_DMA_TERT_OP = (17, 16)
|
|
NVC56F_DMA_TERT_OP_GRP0_INC_METHOD = (0x00000000)
|
|
NVC56F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK = (0x00000001)
|
|
NVC56F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK = (0x00000002)
|
|
NVC56F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK = (0x00000003)
|
|
NVC56F_DMA_TERT_OP_GRP2_NON_INC_METHOD = (0x00000000)
|
|
NVC56F_DMA_METHOD_COUNT_OLD = (28, 18)
|
|
NVC56F_DMA_METHOD_COUNT = (28, 16)
|
|
NVC56F_DMA_IMMD_DATA = (28, 16)
|
|
NVC56F_DMA_SEC_OP = (31, 29)
|
|
NVC56F_DMA_SEC_OP_GRP0_USE_TERT = (0x00000000)
|
|
NVC56F_DMA_SEC_OP_INC_METHOD = (0x00000001)
|
|
NVC56F_DMA_SEC_OP_GRP2_USE_TERT = (0x00000002)
|
|
NVC56F_DMA_SEC_OP_NON_INC_METHOD = (0x00000003)
|
|
NVC56F_DMA_SEC_OP_IMMD_DATA_METHOD = (0x00000004)
|
|
NVC56F_DMA_SEC_OP_ONE_INC = (0x00000005)
|
|
NVC56F_DMA_SEC_OP_RESERVED6 = (0x00000006)
|
|
NVC56F_DMA_SEC_OP_END_PB_SEGMENT = (0x00000007)
|
|
NVC56F_DMA_INCR_ADDRESS = (11, 0)
|
|
NVC56F_DMA_INCR_SUBCHANNEL = (15, 13)
|
|
NVC56F_DMA_INCR_COUNT = (28, 16)
|
|
NVC56F_DMA_INCR_OPCODE = (31, 29)
|
|
NVC56F_DMA_INCR_OPCODE_VALUE = (0x00000001)
|
|
NVC56F_DMA_INCR_DATA = (31, 0)
|
|
NVC56F_DMA_NONINCR_ADDRESS = (11, 0)
|
|
NVC56F_DMA_NONINCR_SUBCHANNEL = (15, 13)
|
|
NVC56F_DMA_NONINCR_COUNT = (28, 16)
|
|
NVC56F_DMA_NONINCR_OPCODE = (31, 29)
|
|
NVC56F_DMA_NONINCR_OPCODE_VALUE = (0x00000003)
|
|
NVC56F_DMA_NONINCR_DATA = (31, 0)
|
|
NVC56F_DMA_ONEINCR_ADDRESS = (11, 0)
|
|
NVC56F_DMA_ONEINCR_SUBCHANNEL = (15, 13)
|
|
NVC56F_DMA_ONEINCR_COUNT = (28, 16)
|
|
NVC56F_DMA_ONEINCR_OPCODE = (31, 29)
|
|
NVC56F_DMA_ONEINCR_OPCODE_VALUE = (0x00000005)
|
|
NVC56F_DMA_ONEINCR_DATA = (31, 0)
|
|
NVC56F_DMA_NOP = (0x00000000)
|
|
NVC56F_DMA_IMMD_ADDRESS = (11, 0)
|
|
NVC56F_DMA_IMMD_SUBCHANNEL = (15, 13)
|
|
NVC56F_DMA_IMMD_DATA = (28, 16)
|
|
NVC56F_DMA_IMMD_OPCODE = (31, 29)
|
|
NVC56F_DMA_IMMD_OPCODE_VALUE = (0x00000004)
|
|
NVC56F_DMA_SET_SUBDEVICE_MASK_VALUE = (15, 4)
|
|
NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE = (31, 16)
|
|
NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000001)
|
|
NVC56F_DMA_STORE_SUBDEVICE_MASK_VALUE = (15, 4)
|
|
NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE = (31, 16)
|
|
NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000002)
|
|
NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE = (31, 16)
|
|
NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000003)
|
|
NVC56F_DMA_ENDSEG_OPCODE = (31, 29)
|
|
NVC56F_DMA_ENDSEG_OPCODE_VALUE = (0x00000007)
|
|
NVC56F_DMA_ADDRESS = (12, 2)
|
|
NVC56F_DMA_SUBCH = (15, 13)
|
|
NVC56F_DMA_OPCODE3 = (17, 16)
|
|
NVC56F_DMA_OPCODE3_NONE = (0x00000000)
|
|
NVC56F_DMA_COUNT = (28, 18)
|
|
NVC56F_DMA_OPCODE = (31, 29)
|
|
NVC56F_DMA_OPCODE_METHOD = (0x00000000)
|
|
NVC56F_DMA_OPCODE_NONINC_METHOD = (0x00000002)
|
|
NVC56F_DMA_DATA = (31, 0)
|
|
HOPPER_CHANNEL_GPFIFO_A = (0x0000C86F)
|
|
NVC86F_SET_OBJECT = (0x00000000)
|
|
NVC86F_MEM_OP_A = (0x00000028)
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID = (5, 0)
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE = (5, 0)
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID = (10, 6)
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE = (7, 6)
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS = 0
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS = 1
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD = 3
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID = (8, 0)
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR = (11, 11)
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO = (31, 12)
|
|
NVC86F_MEM_OP_B = (0x0000002c)
|
|
NVC86F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI = (31, 0)
|
|
NVC86F_MEM_OP_C = (0x00000030)
|
|
NVC86F_MEM_OP_C_MEMBAR_TYPE = (2, 0)
|
|
NVC86F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR = 0x00000000
|
|
NVC86F_MEM_OP_C_MEMBAR_TYPE_MEMBAR = 0x00000001
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB = (0, 0)
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC = (1, 1)
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY = (4, 2)
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START = 0x00000001
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL = 0x00000002
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED = 0x00000003
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL = 0x00000004
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL = 0x00000005
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE = (6, 5)
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE = 0x00000002
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE = (9, 7)
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ = 0
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE = 1
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 2
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD = 3
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 4
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL = 5
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC = 6
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL = 7
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL = (9, 7)
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 = 0x00000002
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 = 0x00000003
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 = 0x00000004
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 = 0x00000005
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 = 0x00000007
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE = (11, 10)
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT = 0x00000003
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO = (31, 12)
|
|
NVC86F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG = (19, 0)
|
|
NVC86F_MEM_OP_D = (0x00000034)
|
|
NVC86F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI = (26, 0)
|
|
NVC86F_MEM_OP_D_OPERATION = (31, 27)
|
|
NVC86F_MEM_OP_D_OPERATION_MEMBAR = 0x00000005
|
|
NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009
|
|
NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a
|
|
NVC86F_MEM_OP_D_OPERATION_MMU_OPERATION = 0x0000000b
|
|
NVC86F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE = 0x0000000d
|
|
NVC86F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE = 0x0000000e
|
|
NVC86F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES = 0x0000000e
|
|
NVC86F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS = 0x0000000f
|
|
NVC86F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010
|
|
NVC86F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS = 0x00000015
|
|
NVC86F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR = 0x00000016
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE = (1, 0)
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC = 0x00000000
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC = 0x00000001
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL = 0x00000002
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED = 0x00000003
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE = (2, 2)
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC = 0x00000000
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC = 0x00000001
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK = (6, 3)
|
|
NVC86F_MEM_OP_D_MMU_OPERATION_TYPE = (23, 20)
|
|
NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED = 0x00000000
|
|
NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP = 0x00000001
|
|
NVC86F_SEM_ADDR_LO = (0x0000005c)
|
|
NVC86F_SEM_ADDR_LO_OFFSET = (31, 2)
|
|
NVC86F_SEM_ADDR_HI = (0x00000060)
|
|
NVC86F_SEM_ADDR_HI_OFFSET = (24, 0)
|
|
NVC86F_SEM_PAYLOAD_LO = (0x00000064)
|
|
NVC86F_SEM_PAYLOAD_HI = (0x00000068)
|
|
NVC86F_SEM_EXECUTE = (0x0000006c)
|
|
NVC86F_SEM_EXECUTE_OPERATION = (2, 0)
|
|
NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000
|
|
NVC86F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001
|
|
NVC86F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ = 0x00000003
|
|
NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG = (12, 12)
|
|
NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN = 0x00000001
|
|
NVC86F_SEM_EXECUTE_RELEASE_WFI = (20, 20)
|
|
NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000
|
|
NVC86F_SEM_EXECUTE_PAYLOAD_SIZE = (24, 24)
|
|
NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000
|
|
NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP = (25, 25)
|
|
NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS = 0x00000000
|
|
NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN = 0x00000001
|
|
NVC86F_WFI = (0x00000078)
|
|
NVC86F_WFI_SCOPE = (0, 0)
|
|
NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE = 0x00000000
|
|
NVC86F_WFI_SCOPE_CURRENT_VEID = 0x00000000
|
|
NVC86F_WFI_SCOPE_ALL = 0x00000001
|
|
NVC86F_GP_ENTRY__SIZE = 8
|
|
NVC86F_GP_ENTRY0_FETCH = (0, 0)
|
|
NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000
|
|
NVC86F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001
|
|
NVC86F_GP_ENTRY0_GET = (31, 2)
|
|
NVC86F_GP_ENTRY0_OPERAND = (31, 0)
|
|
NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND = (24, 8)
|
|
NVC86F_GP_ENTRY1_GET_HI = (7, 0)
|
|
NVC86F_GP_ENTRY1_LEVEL = (9, 9)
|
|
NVC86F_GP_ENTRY1_LEVEL_MAIN = 0x00000000
|
|
NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001
|
|
NVC86F_GP_ENTRY1_LENGTH = (30, 10)
|
|
NVC86F_GP_ENTRY1_SYNC = (31, 31)
|
|
NVC86F_GP_ENTRY1_SYNC_PROCEED = 0x00000000
|
|
NVC86F_GP_ENTRY1_SYNC_WAIT = 0x00000001
|
|
NVC86F_GP_ENTRY1_OPCODE = (7, 0)
|
|
NVC86F_GP_ENTRY1_OPCODE_NOP = 0x00000000
|
|
NVC86F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001
|
|
NVC86F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002
|
|
NVC86F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003
|
|
NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE = 0x00000004
|
|
BLACKWELL_CHANNEL_GPFIFO_A = (0x0000C96F)
|
|
NVC96F_SET_OBJECT = (0x00000000)
|
|
NVC96F_MEM_OP_A = (0x00000028)
|
|
NVC96F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE = (5, 0)
|
|
NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE = (7, 6)
|
|
NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2
|
|
NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR = (11, 11)
|
|
NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001
|
|
NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000
|
|
NVC96F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO = (31, 12)
|
|
NVC96F_MEM_OP_B = (0x0000002c)
|
|
NVC96F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI = (31, 0)
|
|
NVC96F_MEM_OP_C = (0x00000030)
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB = (0, 0)
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC = (1, 1)
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY = (4, 2)
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE = (6, 5)
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL = (9, 7)
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE = (11, 10)
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002
|
|
NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO = (31, 12)
|
|
NVC96F_MEM_OP_D = (0x00000034)
|
|
NVC96F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI = (26, 0)
|
|
NVC96F_MEM_OP_D_OPERATION = (31, 27)
|
|
NVC96F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009
|
|
NVC96F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a
|
|
NVC96F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010
|
|
NVC96F_MEM_OP_D_OPERATION_L2_SYSMEM_NCOH_INVALIDATE = 0x00000011
|
|
NVC96F_SEM_ADDR_LO = (0x0000005c)
|
|
NVC96F_SEM_ADDR_LO_OFFSET = (31, 2)
|
|
NVC96F_SEM_ADDR_HI = (0x00000060)
|
|
NVC96F_SEM_ADDR_HI_OFFSET = (24, 0)
|
|
NVC96F_SEM_PAYLOAD_LO = (0x00000064)
|
|
NVC96F_SEM_PAYLOAD_HI = (0x00000068)
|
|
NVC96F_SEM_EXECUTE = (0x0000006c)
|
|
NVC96F_SEM_EXECUTE_OPERATION = (2, 0)
|
|
NVC96F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000
|
|
NVC96F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001
|
|
NVC96F_SEM_EXECUTE_RELEASE_WFI = (20, 20)
|
|
NVC96F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000
|
|
NVC96F_SEM_EXECUTE_PAYLOAD_SIZE = (24, 24)
|
|
NVC96F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000
|
|
NVC96F_GP_ENTRY__SIZE = 8
|
|
NVC96F_GP_ENTRY0_FETCH = (0, 0)
|
|
NVC96F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000
|
|
NVC96F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001
|
|
NVC96F_GP_ENTRY0_GET = (31, 2)
|
|
NVC96F_GP_ENTRY0_OPERAND = (31, 0)
|
|
NVC96F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND = (24, 8)
|
|
NVC96F_GP_ENTRY1_GET_HI = (7, 0)
|
|
NVC96F_GP_ENTRY1_LEVEL = (9, 9)
|
|
NVC96F_GP_ENTRY1_LEVEL_MAIN = 0x00000000
|
|
NVC96F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001
|
|
NVC96F_GP_ENTRY1_LENGTH = (30, 10)
|
|
NVC96F_GP_ENTRY1_SYNC = (31, 31)
|
|
NVC96F_GP_ENTRY1_SYNC_PROCEED = 0x00000000
|
|
NVC96F_GP_ENTRY1_SYNC_WAIT = 0x00000001
|
|
NVC96F_GP_ENTRY1_OPCODE = (7, 0)
|
|
NVC96F_GP_ENTRY1_OPCODE_NOP = 0x00000000
|
|
NVC96F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001
|
|
NVC96F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002
|
|
NVC96F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003
|
|
NVC96F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE = 0x00000004
|
|
BLACKWELL_USERMODE_A = (0xc761)
|
|
GT200_DEBUGGER = (0x83de)
|
|
NV83DE_ALLOC_PARAMETERS_MESSAGE_ID = (0x83de)
|
|
MAXWELL_PROFILER_DEVICE = (0xb2cc)
|
|
NVB2CC_ALLOC_PARAMETERS_MESSAGE_ID = (0xb2cc)
|
|
AMPERE_COMPUTE_A = 0xC6C0
|
|
NVC6C0_SET_OBJECT = 0x0000
|
|
NVC6C0_SET_OBJECT_CLASS_ID = (15, 0)
|
|
NVC6C0_SET_OBJECT_ENGINE_ID = (20, 16)
|
|
NVC6C0_NO_OPERATION = 0x0100
|
|
NVC6C0_NO_OPERATION_V = (31, 0)
|
|
NVC6C0_SET_NOTIFY_A = 0x0104
|
|
NVC6C0_SET_NOTIFY_A_ADDRESS_UPPER = (7, 0)
|
|
NVC6C0_SET_NOTIFY_B = 0x0108
|
|
NVC6C0_SET_NOTIFY_B_ADDRESS_LOWER = (31, 0)
|
|
NVC6C0_NOTIFY = 0x010c
|
|
NVC6C0_NOTIFY_TYPE = (31, 0)
|
|
NVC6C0_NOTIFY_TYPE_WRITE_ONLY = 0x00000000
|
|
NVC6C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN = 0x00000001
|
|
NVC6C0_WAIT_FOR_IDLE = 0x0110
|
|
NVC6C0_WAIT_FOR_IDLE_V = (31, 0)
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_A = 0x0130
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER = (7, 0)
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_B = 0x0134
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER = (31, 0)
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C = 0x0138
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE = (2, 0)
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE = 0x00000000
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE = 0x00000001
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004
|
|
NVC6C0_SEND_GO_IDLE = 0x013c
|
|
NVC6C0_SEND_GO_IDLE_V = (31, 0)
|
|
NVC6C0_PM_TRIGGER = 0x0140
|
|
NVC6C0_PM_TRIGGER_V = (31, 0)
|
|
NVC6C0_PM_TRIGGER_WFI = 0x0144
|
|
NVC6C0_PM_TRIGGER_WFI_V = (31, 0)
|
|
NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN = 0x0148
|
|
NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN_V = (31, 0)
|
|
NVC6C0_FE_ATOMIC_SEQUENCE_END = 0x014c
|
|
NVC6C0_FE_ATOMIC_SEQUENCE_END_V = (31, 0)
|
|
NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER = 0x0150
|
|
NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER_V = (31, 0)
|
|
NVC6C0_SET_INSTRUMENTATION_METHOD_DATA = 0x0154
|
|
NVC6C0_SET_INSTRUMENTATION_METHOD_DATA_V = (31, 0)
|
|
NVC6C0_LINE_LENGTH_IN = 0x0180
|
|
NVC6C0_LINE_LENGTH_IN_VALUE = (31, 0)
|
|
NVC6C0_LINE_COUNT = 0x0184
|
|
NVC6C0_LINE_COUNT_VALUE = (31, 0)
|
|
NVC6C0_OFFSET_OUT_UPPER = 0x0188
|
|
NVC6C0_OFFSET_OUT_UPPER_VALUE = (16, 0)
|
|
NVC6C0_OFFSET_OUT = 0x018c
|
|
NVC6C0_OFFSET_OUT_VALUE = (31, 0)
|
|
NVC6C0_PITCH_OUT = 0x0190
|
|
NVC6C0_PITCH_OUT_VALUE = (31, 0)
|
|
NVC6C0_SET_DST_BLOCK_SIZE = 0x0194
|
|
NVC6C0_SET_DST_BLOCK_SIZE_WIDTH = (3, 0)
|
|
NVC6C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = 0x00000000
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT = (7, 4)
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = 0x00000000
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = 0x00000001
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = 0x00000002
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = 0x00000003
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = 0x00000004
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = 0x00000005
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH = (11, 8)
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = 0x00000000
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = 0x00000001
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = 0x00000002
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = 0x00000003
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = 0x00000004
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = 0x00000005
|
|
NVC6C0_SET_DST_WIDTH = 0x0198
|
|
NVC6C0_SET_DST_WIDTH_V = (31, 0)
|
|
NVC6C0_SET_DST_HEIGHT = 0x019c
|
|
NVC6C0_SET_DST_HEIGHT_V = (31, 0)
|
|
NVC6C0_SET_DST_DEPTH = 0x01a0
|
|
NVC6C0_SET_DST_DEPTH_V = (31, 0)
|
|
NVC6C0_SET_DST_LAYER = 0x01a4
|
|
NVC6C0_SET_DST_LAYER_V = (31, 0)
|
|
NVC6C0_SET_DST_ORIGIN_BYTES_X = 0x01a8
|
|
NVC6C0_SET_DST_ORIGIN_BYTES_X_V = (20, 0)
|
|
NVC6C0_SET_DST_ORIGIN_SAMPLES_Y = 0x01ac
|
|
NVC6C0_SET_DST_ORIGIN_SAMPLES_Y_V = (16, 0)
|
|
NVC6C0_LAUNCH_DMA = 0x01b0
|
|
NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT = (0, 0)
|
|
NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = 0x00000000
|
|
NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = 0x00000001
|
|
NVC6C0_LAUNCH_DMA_COMPLETION_TYPE = (5, 4)
|
|
NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE = 0x00000000
|
|
NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY = 0x00000001
|
|
NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE = 0x00000002
|
|
NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE = (9, 8)
|
|
NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE = 0x00000000
|
|
NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT = 0x00000001
|
|
NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE = (12, 12)
|
|
NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS = 0x00000000
|
|
NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD = 0x00000001
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE = (1, 1)
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP = (15, 13)
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT = (3, 2)
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
|
|
NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE = (6, 6)
|
|
NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE = 0x00000000
|
|
NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE = 0x00000001
|
|
NVC6C0_LOAD_INLINE_DATA = 0x01b4
|
|
NVC6C0_LOAD_INLINE_DATA_V = (31, 0)
|
|
NVC6C0_SET_I2M_SEMAPHORE_A = 0x01dc
|
|
NVC6C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER = (7, 0)
|
|
NVC6C0_SET_I2M_SEMAPHORE_B = 0x01e0
|
|
NVC6C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER = (31, 0)
|
|
NVC6C0_SET_I2M_SEMAPHORE_C = 0x01e4
|
|
NVC6C0_SET_I2M_SEMAPHORE_C_PAYLOAD = (31, 0)
|
|
NVC6C0_SET_SM_SCG_CONTROL = 0x01e8
|
|
NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS = (0, 0)
|
|
NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE = 0x00000000
|
|
NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE = 0x00000001
|
|
NVC6C0_SET_I2M_SPARE_NOOP00 = 0x01f0
|
|
NVC6C0_SET_I2M_SPARE_NOOP00_V = (31, 0)
|
|
NVC6C0_SET_I2M_SPARE_NOOP01 = 0x01f4
|
|
NVC6C0_SET_I2M_SPARE_NOOP01_V = (31, 0)
|
|
NVC6C0_SET_I2M_SPARE_NOOP02 = 0x01f8
|
|
NVC6C0_SET_I2M_SPARE_NOOP02_V = (31, 0)
|
|
NVC6C0_SET_I2M_SPARE_NOOP03 = 0x01fc
|
|
NVC6C0_SET_I2M_SPARE_NOOP03_V = (31, 0)
|
|
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A = 0x0200
|
|
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER = (7, 0)
|
|
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B = 0x0204
|
|
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER = (31, 0)
|
|
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C = 0x0208
|
|
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE = (31, 0)
|
|
NVC6C0_PERFMON_TRANSFER = 0x0210
|
|
NVC6C0_PERFMON_TRANSFER_V = (31, 0)
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A = 0x0214
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER = (7, 0)
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B = 0x0218
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER = (31, 0)
|
|
NVC6C0_INVALIDATE_SHADER_CACHES = 0x021c
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION = (0, 0)
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE = 0x00000000
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE = 0x00000001
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_DATA = (4, 4)
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_DATA_FALSE = 0x00000000
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_DATA_TRUE = 0x00000001
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT = (12, 12)
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE = 0x00000000
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE = 0x00000001
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS = (1, 1)
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE = 0x00000000
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE = 0x00000001
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA = (2, 2)
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE = 0x00000000
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE = 0x00000001
|
|
NVC6C0_SET_RESERVED_SW_METHOD00 = 0x0220
|
|
NVC6C0_SET_RESERVED_SW_METHOD00_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD01 = 0x0224
|
|
NVC6C0_SET_RESERVED_SW_METHOD01_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD02 = 0x0228
|
|
NVC6C0_SET_RESERVED_SW_METHOD02_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD03 = 0x022c
|
|
NVC6C0_SET_RESERVED_SW_METHOD03_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD04 = 0x0230
|
|
NVC6C0_SET_RESERVED_SW_METHOD04_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD05 = 0x0234
|
|
NVC6C0_SET_RESERVED_SW_METHOD05_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD06 = 0x0238
|
|
NVC6C0_SET_RESERVED_SW_METHOD06_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD07 = 0x023c
|
|
NVC6C0_SET_RESERVED_SW_METHOD07_V = (31, 0)
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI = 0x0244
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES = (0, 0)
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL = 0x00000000
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE = 0x00000001
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG = (25, 4)
|
|
NVC6C0_SET_CWD_REF_COUNTER = 0x0248
|
|
NVC6C0_SET_CWD_REF_COUNTER_SELECT = (5, 0)
|
|
NVC6C0_SET_CWD_REF_COUNTER_VALUE = (23, 8)
|
|
NVC6C0_SET_RESERVED_SW_METHOD08 = 0x024c
|
|
NVC6C0_SET_RESERVED_SW_METHOD08_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD09 = 0x0250
|
|
NVC6C0_SET_RESERVED_SW_METHOD09_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD10 = 0x0254
|
|
NVC6C0_SET_RESERVED_SW_METHOD10_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD11 = 0x0258
|
|
NVC6C0_SET_RESERVED_SW_METHOD11_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD12 = 0x025c
|
|
NVC6C0_SET_RESERVED_SW_METHOD12_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD13 = 0x0260
|
|
NVC6C0_SET_RESERVED_SW_METHOD13_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD14 = 0x0264
|
|
NVC6C0_SET_RESERVED_SW_METHOD14_V = (31, 0)
|
|
NVC6C0_SET_RESERVED_SW_METHOD15 = 0x0268
|
|
NVC6C0_SET_RESERVED_SW_METHOD15_V = (31, 0)
|
|
NVC6C0_SET_SCG_CONTROL = 0x0270
|
|
NVC6C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT = (8, 0)
|
|
NVC6C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT = (20, 12)
|
|
NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE = (24, 24)
|
|
NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE = 0x00000000
|
|
NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE = 0x00000001
|
|
NVC6C0_SET_COMPUTE_CLASS_VERSION = 0x0280
|
|
NVC6C0_SET_COMPUTE_CLASS_VERSION_CURRENT = (15, 0)
|
|
NVC6C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED = (31, 16)
|
|
NVC6C0_CHECK_COMPUTE_CLASS_VERSION = 0x0284
|
|
NVC6C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT = (15, 0)
|
|
NVC6C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED = (31, 16)
|
|
NVC6C0_SET_QMD_VERSION = 0x0288
|
|
NVC6C0_SET_QMD_VERSION_CURRENT = (15, 0)
|
|
NVC6C0_SET_QMD_VERSION_OLDEST_SUPPORTED = (31, 16)
|
|
NVC6C0_CHECK_QMD_VERSION = 0x0290
|
|
NVC6C0_CHECK_QMD_VERSION_CURRENT = (15, 0)
|
|
NVC6C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED = (31, 16)
|
|
NVC6C0_INVALIDATE_SKED_CACHES = 0x0298
|
|
NVC6C0_INVALIDATE_SKED_CACHES_V = (0, 0)
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL = 0x029c
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK = (7, 0)
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE = (8, 8)
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE = (12, 12)
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE = (16, 16)
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE = (20, 20)
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE = (24, 24)
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A = 0x02a0
|
|
NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER = (16, 0)
|
|
NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B = 0x02a4
|
|
NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS = (31, 0)
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL = 0x02a8
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE = (0, 0)
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE = 0x00000000
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE = 0x00000001
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE = (1, 1)
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE = 0x00000000
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE = 0x00000001
|
|
NVC6C0_SET_CWD_SLOT_COUNT = 0x02b0
|
|
NVC6C0_SET_CWD_SLOT_COUNT_V = (7, 0)
|
|
NVC6C0_SEND_PCAS_A = 0x02b4
|
|
NVC6C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 = (31, 0)
|
|
NVC6C0_SEND_PCAS_B = 0x02b8
|
|
NVC6C0_SEND_PCAS_B_FROM = (23, 0)
|
|
NVC6C0_SEND_PCAS_B_DELTA = (31, 24)
|
|
NVC6C0_SEND_SIGNALING_PCAS_B = 0x02bc
|
|
NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE = (0, 0)
|
|
NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE = 0x00000000
|
|
NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE = 0x00000001
|
|
NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE = (1, 1)
|
|
NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE = 0x00000000
|
|
NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE = 0x00000001
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B = 0x02c0
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION = (3, 0)
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP = 0x00000000
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE = 0x00000001
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE = 0x00000002
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT = 0x00000006
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE = 0x00000007
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH = 0x00000008
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE = 0x00000009
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE = 0x0000000A
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING = 0x0000000B
|
|
NVC6C0_SET_SKED_CACHE_CONTROL = 0x02cc
|
|
NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID = (0, 0)
|
|
NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE = 0x00000000
|
|
NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE = 0x00000001
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A = 0x02e4
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER = (7, 0)
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B = 0x02e8
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER = (31, 0)
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C = 0x02ec
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT = (8, 0)
|
|
NVC6C0_SET_SPA_VERSION = 0x0310
|
|
NVC6C0_SET_SPA_VERSION_MINOR = (7, 0)
|
|
NVC6C0_SET_SPA_VERSION_MAJOR = (15, 8)
|
|
NVC6C0_SET_INLINE_QMD_ADDRESS_A = 0x0318
|
|
NVC6C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER = (31, 0)
|
|
NVC6C0_SET_INLINE_QMD_ADDRESS_B = 0x031c
|
|
NVC6C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER = (31, 0)
|
|
NVC6C0_LOAD_INLINE_QMD_DATA = lambda i: (0x0320+(i)*4) # type: ignore
|
|
NVC6C0_LOAD_INLINE_QMD_DATA_V = (31, 0)
|
|
NVC6C0_SET_FALCON00 = 0x0500
|
|
NVC6C0_SET_FALCON00_V = (31, 0)
|
|
NVC6C0_SET_FALCON01 = 0x0504
|
|
NVC6C0_SET_FALCON01_V = (31, 0)
|
|
NVC6C0_SET_FALCON02 = 0x0508
|
|
NVC6C0_SET_FALCON02_V = (31, 0)
|
|
NVC6C0_SET_FALCON03 = 0x050c
|
|
NVC6C0_SET_FALCON03_V = (31, 0)
|
|
NVC6C0_SET_FALCON04 = 0x0510
|
|
NVC6C0_SET_FALCON04_V = (31, 0)
|
|
NVC6C0_SET_FALCON05 = 0x0514
|
|
NVC6C0_SET_FALCON05_V = (31, 0)
|
|
NVC6C0_SET_FALCON06 = 0x0518
|
|
NVC6C0_SET_FALCON06_V = (31, 0)
|
|
NVC6C0_SET_FALCON07 = 0x051c
|
|
NVC6C0_SET_FALCON07_V = (31, 0)
|
|
NVC6C0_SET_FALCON08 = 0x0520
|
|
NVC6C0_SET_FALCON08_V = (31, 0)
|
|
NVC6C0_SET_FALCON09 = 0x0524
|
|
NVC6C0_SET_FALCON09_V = (31, 0)
|
|
NVC6C0_SET_FALCON10 = 0x0528
|
|
NVC6C0_SET_FALCON10_V = (31, 0)
|
|
NVC6C0_SET_FALCON11 = 0x052c
|
|
NVC6C0_SET_FALCON11_V = (31, 0)
|
|
NVC6C0_SET_FALCON12 = 0x0530
|
|
NVC6C0_SET_FALCON12_V = (31, 0)
|
|
NVC6C0_SET_FALCON13 = 0x0534
|
|
NVC6C0_SET_FALCON13_V = (31, 0)
|
|
NVC6C0_SET_FALCON14 = 0x0538
|
|
NVC6C0_SET_FALCON14_V = (31, 0)
|
|
NVC6C0_SET_FALCON15 = 0x053c
|
|
NVC6C0_SET_FALCON15_V = (31, 0)
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_A = 0x0790
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER = (16, 0)
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_B = 0x0794
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER = (31, 0)
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A = 0x07b0
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER = (16, 0)
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B = 0x07b4
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS = (31, 0)
|
|
NVC6C0_SET_SHADER_CACHE_CONTROL = 0x0d94
|
|
NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE = (0, 0)
|
|
NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS = lambda i: (0x0da0+(i)*4) # type: ignore
|
|
NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V = (31, 0)
|
|
NVC6C0_SET_SM_TIMEOUT_INTERVAL = 0x0de4
|
|
NVC6C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT = (5, 0)
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI = 0x1288
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES = (0, 0)
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL = 0x00000000
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE = 0x00000001
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG = (25, 4)
|
|
NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT = 0x12a8
|
|
NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL = (0, 0)
|
|
NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE = 0x00000000
|
|
NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE = 0x00000001
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE = 0x1330
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES = (0, 0)
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL = 0x00000000
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE = 0x00000001
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_TAG = (25, 4)
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE = 0x1334
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES = (0, 0)
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL = 0x00000000
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE = 0x00000001
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG = (25, 4)
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE = 0x1338
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES = (0, 0)
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL = 0x00000000
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE = 0x00000001
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG = (25, 4)
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI = 0x1424
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES = (0, 0)
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL = 0x00000000
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE = 0x00000001
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG = (25, 4)
|
|
NVC6C0_SET_SHADER_EXCEPTIONS = 0x1528
|
|
NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE = (0, 0)
|
|
NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_SET_RENDER_ENABLE_A = 0x1550
|
|
NVC6C0_SET_RENDER_ENABLE_A_OFFSET_UPPER = (7, 0)
|
|
NVC6C0_SET_RENDER_ENABLE_B = 0x1554
|
|
NVC6C0_SET_RENDER_ENABLE_B_OFFSET_LOWER = (31, 0)
|
|
NVC6C0_SET_RENDER_ENABLE_C = 0x1558
|
|
NVC6C0_SET_RENDER_ENABLE_C_MODE = (2, 0)
|
|
NVC6C0_SET_RENDER_ENABLE_C_MODE_FALSE = 0x00000000
|
|
NVC6C0_SET_RENDER_ENABLE_C_MODE_TRUE = 0x00000001
|
|
NVC6C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002
|
|
NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003
|
|
NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004
|
|
NVC6C0_SET_TEX_SAMPLER_POOL_A = 0x155c
|
|
NVC6C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER = (16, 0)
|
|
NVC6C0_SET_TEX_SAMPLER_POOL_B = 0x1560
|
|
NVC6C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER = (31, 0)
|
|
NVC6C0_SET_TEX_SAMPLER_POOL_C = 0x1564
|
|
NVC6C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX = (19, 0)
|
|
NVC6C0_SET_TEX_HEADER_POOL_A = 0x1574
|
|
NVC6C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER = (16, 0)
|
|
NVC6C0_SET_TEX_HEADER_POOL_B = 0x1578
|
|
NVC6C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER = (31, 0)
|
|
NVC6C0_SET_TEX_HEADER_POOL_C = 0x157c
|
|
NVC6C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX = (21, 0)
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI = 0x1698
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION = (0, 0)
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE = 0x00000000
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE = 0x00000001
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA = (4, 4)
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE = 0x00000000
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE = 0x00000001
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT = (12, 12)
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE = 0x00000000
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE = 0x00000001
|
|
NVC6C0_SET_RENDER_ENABLE_OVERRIDE = 0x1944
|
|
NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE = (1, 0)
|
|
NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE = 0x00000000
|
|
NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER = 0x00000001
|
|
NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER = 0x00000002
|
|
NVC6C0_PIPE_NOP = 0x1a2c
|
|
NVC6C0_PIPE_NOP_V = (31, 0)
|
|
NVC6C0_SET_SPARE00 = 0x1a30
|
|
NVC6C0_SET_SPARE00_V = (31, 0)
|
|
NVC6C0_SET_SPARE01 = 0x1a34
|
|
NVC6C0_SET_SPARE01_V = (31, 0)
|
|
NVC6C0_SET_SPARE02 = 0x1a38
|
|
NVC6C0_SET_SPARE02_V = (31, 0)
|
|
NVC6C0_SET_SPARE03 = 0x1a3c
|
|
NVC6C0_SET_SPARE03_V = (31, 0)
|
|
NVC6C0_SET_REPORT_SEMAPHORE_A = 0x1b00
|
|
NVC6C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER = (7, 0)
|
|
NVC6C0_SET_REPORT_SEMAPHORE_B = 0x1b04
|
|
NVC6C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER = (31, 0)
|
|
NVC6C0_SET_REPORT_SEMAPHORE_C = 0x1b08
|
|
NVC6C0_SET_REPORT_SEMAPHORE_C_PAYLOAD = (31, 0)
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D = 0x1b0c
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION = (1, 0)
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE = 0x00000000
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP = 0x00000003
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE = (20, 20)
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE = (28, 28)
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD = 0x00000001
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE = (2, 2)
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE = 0x00000000
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE = 0x00000001
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE = (3, 3)
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP = (11, 9)
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT = (18, 17)
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP = (19, 19)
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE = 0x00000000
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE = 0x00000001
|
|
NVC6C0_SET_TRAP_HANDLER_A = 0x25f8
|
|
NVC6C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER = (16, 0)
|
|
NVC6C0_SET_TRAP_HANDLER_B = 0x25fc
|
|
NVC6C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER = (31, 0)
|
|
NVC6C0_SET_BINDLESS_TEXTURE = 0x2608
|
|
NVC6C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT = (2, 0)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE = lambda i: (0x32f4+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V = (31, 0)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER = lambda i: (0x3314+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V = (31, 0)
|
|
NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3334
|
|
NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V = (0, 0)
|
|
NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3338
|
|
NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V = (0, 0)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER = lambda i: (0x333c+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V = (31, 0)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE = lambda i: (0x335c+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V = (31, 0)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT = lambda i: (0x337c+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT = (7, 0)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A = lambda i: (0x339c+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 = (1, 0)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 = (4, 2)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 = (6, 5)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 = (9, 7)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 = (11, 10)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 = (14, 12)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 = (16, 15)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 = (19, 17)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 = (21, 20)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 = (24, 22)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 = (26, 25)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 = (29, 27)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE = (31, 30)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B = lambda i: (0x33bc+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE = (0, 0)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE = (2, 1)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED = (3, 3)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC = (19, 4)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL = 0x33dc
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK = (7, 0)
|
|
NVC6C0_START_SHADER_PERFORMANCE_COUNTER = 0x33e0
|
|
NVC6C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK = (7, 0)
|
|
NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER = 0x33e4
|
|
NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK = (7, 0)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER = 0x33e8
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V = (31, 0)
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER = 0x33ec
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V = (31, 0)
|
|
NVC6C0_SET_MME_SHADOW_SCRATCH = lambda i: (0x3400+(i)*4) # type: ignore
|
|
NVC6C0_SET_MME_SHADOW_SCRATCH_V = (31, 0)
|
|
BLACKWELL_COMPUTE_A = 0xCDC0
|
|
NVCDC0_SET_OBJECT = 0x0000
|
|
NVCDC0_SET_OBJECT_CLASS_ID = (15, 0)
|
|
NVCDC0_SET_OBJECT_ENGINE_ID = (20, 16)
|
|
NVCDC0_NO_OPERATION = 0x0100
|
|
NVCDC0_NO_OPERATION_V = (31, 0)
|
|
NVCDC0_SET_NOTIFY_A = 0x0104
|
|
NVCDC0_SET_NOTIFY_A_ADDRESS_UPPER = (24, 0)
|
|
NVCDC0_SET_NOTIFY_B = 0x0108
|
|
NVCDC0_SET_NOTIFY_B_ADDRESS_LOWER = (31, 0)
|
|
NVCDC0_NOTIFY = 0x010c
|
|
NVCDC0_NOTIFY_TYPE = (31, 0)
|
|
NVCDC0_NOTIFY_TYPE_WRITE_ONLY = 0x00000000
|
|
NVCDC0_NOTIFY_TYPE_WRITE_THEN_AWAKEN = 0x00000001
|
|
NVCDC0_WAIT_FOR_IDLE = 0x0110
|
|
NVCDC0_WAIT_FOR_IDLE_V = (31, 0)
|
|
NVCDC0_LOAD_MME_INSTRUCTION_RAM_POINTER = 0x0114
|
|
NVCDC0_LOAD_MME_INSTRUCTION_RAM_POINTER_V = (31, 0)
|
|
NVCDC0_LOAD_MME_INSTRUCTION_RAM = 0x0118
|
|
NVCDC0_LOAD_MME_INSTRUCTION_RAM_V = (31, 0)
|
|
NVCDC0_LOAD_MME_START_ADDRESS_RAM_POINTER = 0x011c
|
|
NVCDC0_LOAD_MME_START_ADDRESS_RAM_POINTER_V = (31, 0)
|
|
NVCDC0_LOAD_MME_START_ADDRESS_RAM = 0x0120
|
|
NVCDC0_LOAD_MME_START_ADDRESS_RAM_V = (31, 0)
|
|
NVCDC0_SET_MME_SHADOW_RAM_CONTROL = 0x0124
|
|
NVCDC0_SET_MME_SHADOW_RAM_CONTROL_MODE = (1, 0)
|
|
NVCDC0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK = 0x00000000
|
|
NVCDC0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER = 0x00000001
|
|
NVCDC0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH = 0x00000002
|
|
NVCDC0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY = 0x00000003
|
|
NVCDC0_SET_GLOBAL_RENDER_ENABLE_A = 0x0130
|
|
NVCDC0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER = (7, 0)
|
|
NVCDC0_SET_GLOBAL_RENDER_ENABLE_B = 0x0134
|
|
NVCDC0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER = (31, 0)
|
|
NVCDC0_SET_GLOBAL_RENDER_ENABLE_C = 0x0138
|
|
NVCDC0_SET_GLOBAL_RENDER_ENABLE_C_MODE = (2, 0)
|
|
NVCDC0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE = 0x00000000
|
|
NVCDC0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE = 0x00000001
|
|
NVCDC0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002
|
|
NVCDC0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003
|
|
NVCDC0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004
|
|
NVCDC0_SEND_GO_IDLE = 0x013c
|
|
NVCDC0_SEND_GO_IDLE_V = (31, 0)
|
|
NVCDC0_PM_TRIGGER = 0x0140
|
|
NVCDC0_PM_TRIGGER_V = (31, 0)
|
|
NVCDC0_PM_TRIGGER_WFI = 0x0144
|
|
NVCDC0_PM_TRIGGER_WFI_V = (31, 0)
|
|
NVCDC0_FE_ATOMIC_SEQUENCE_BEGIN = 0x0148
|
|
NVCDC0_FE_ATOMIC_SEQUENCE_BEGIN_V = (31, 0)
|
|
NVCDC0_FE_ATOMIC_SEQUENCE_END = 0x014c
|
|
NVCDC0_FE_ATOMIC_SEQUENCE_END_V = (31, 0)
|
|
NVCDC0_SET_INSTRUMENTATION_METHOD_HEADER = 0x0150
|
|
NVCDC0_SET_INSTRUMENTATION_METHOD_HEADER_V = (31, 0)
|
|
NVCDC0_SET_INSTRUMENTATION_METHOD_DATA = 0x0154
|
|
NVCDC0_SET_INSTRUMENTATION_METHOD_DATA_V = (31, 0)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER = 0x0158
|
|
NVCDC0_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER = (31, 0)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER = 0x015c
|
|
NVCDC0_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER = (31, 0)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_ADDRESS_LOWER = 0x0160
|
|
NVCDC0_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER = (31, 0)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_ADDRESS_UPPER = 0x0164
|
|
NVCDC0_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER = (24, 0)
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE = 0x0168
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_OPERATION = (1, 0)
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE = 0x00000000
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE = 0x00000001
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY = 0x00000002
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP = 0x00000003
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE = (2, 2)
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE = 0x00000000
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE = 0x00000001
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE = (4, 3)
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE = (5, 5)
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE = 0x00000000
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE = 0x00000001
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE = (6, 6)
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP = (9, 7)
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT = (11, 10)
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED = 0x00000000
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED = 0x00000001
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 = (12, 12)
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE = 0x00000000
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE = 0x00000001
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE = (14, 13)
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE = 0x00000000
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002
|
|
NVCDC0_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003
|
|
NVCDC0_LINE_LENGTH_IN = 0x0180
|
|
NVCDC0_LINE_LENGTH_IN_VALUE = (31, 0)
|
|
NVCDC0_LINE_COUNT = 0x0184
|
|
NVCDC0_LINE_COUNT_VALUE = (31, 0)
|
|
NVCDC0_OFFSET_OUT_UPPER = 0x0188
|
|
NVCDC0_OFFSET_OUT_UPPER_VALUE = (24, 0)
|
|
NVCDC0_OFFSET_OUT = 0x018c
|
|
NVCDC0_OFFSET_OUT_VALUE = (31, 0)
|
|
NVCDC0_PITCH_OUT = 0x0190
|
|
NVCDC0_PITCH_OUT_VALUE = (31, 0)
|
|
NVCDC0_LAUNCH_DMA = 0x01b0
|
|
NVCDC0_LAUNCH_DMA_DST_MEMORY_LAYOUT = (0, 0)
|
|
NVCDC0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = 0x00000000
|
|
NVCDC0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = 0x00000001
|
|
NVCDC0_LAUNCH_DMA_COMPLETION_TYPE = (5, 4)
|
|
NVCDC0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE = 0x00000000
|
|
NVCDC0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY = 0x00000001
|
|
NVCDC0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE = 0x00000002
|
|
NVCDC0_LAUNCH_DMA_INTERRUPT_TYPE = (9, 8)
|
|
NVCDC0_LAUNCH_DMA_INTERRUPT_TYPE_NONE = 0x00000000
|
|
NVCDC0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT = 0x00000001
|
|
NVCDC0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE = (12, 12)
|
|
NVCDC0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS = 0x00000000
|
|
NVCDC0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD = 0x00000001
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_ENABLE = (1, 1)
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_OP = (15, 13)
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_FORMAT = (3, 2)
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
|
|
NVCDC0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
|
|
NVCDC0_LAUNCH_DMA_SYSMEMBAR_DISABLE = (6, 6)
|
|
NVCDC0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE = 0x00000000
|
|
NVCDC0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE = 0x00000001
|
|
NVCDC0_LOAD_INLINE_DATA = 0x01b4
|
|
NVCDC0_LOAD_INLINE_DATA_V = (31, 0)
|
|
NVCDC0_SET_I2M_SEMAPHORE_A = 0x01dc
|
|
NVCDC0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER = (24, 0)
|
|
NVCDC0_SET_I2M_SEMAPHORE_B = 0x01e0
|
|
NVCDC0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER = (31, 0)
|
|
NVCDC0_SET_I2M_SEMAPHORE_C = 0x01e4
|
|
NVCDC0_SET_I2M_SEMAPHORE_C_PAYLOAD = (31, 0)
|
|
NVCDC0_SET_SM_SCG_CONTROL = 0x01e8
|
|
NVCDC0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS = (0, 0)
|
|
NVCDC0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE = 0x00000000
|
|
NVCDC0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE = 0x00000001
|
|
NVCDC0_SET_MME_SWITCH_STATE = 0x01ec
|
|
NVCDC0_SET_MME_SWITCH_STATE_VALID = (0, 0)
|
|
NVCDC0_SET_MME_SWITCH_STATE_VALID_FALSE = 0x00000000
|
|
NVCDC0_SET_MME_SWITCH_STATE_VALID_TRUE = 0x00000001
|
|
NVCDC0_SET_MME_SWITCH_STATE_SAVE_MACRO = (11, 4)
|
|
NVCDC0_SET_MME_SWITCH_STATE_RESTORE_MACRO = (19, 12)
|
|
NVCDC0_SET_I2M_SPARE_NOOP00 = 0x01f0
|
|
NVCDC0_SET_I2M_SPARE_NOOP00_V = (31, 0)
|
|
NVCDC0_SET_I2M_SPARE_NOOP01 = 0x01f4
|
|
NVCDC0_SET_I2M_SPARE_NOOP01_V = (31, 0)
|
|
NVCDC0_SET_I2M_SPARE_NOOP02 = 0x01f8
|
|
NVCDC0_SET_I2M_SPARE_NOOP02_V = (31, 0)
|
|
NVCDC0_SET_I2M_SPARE_NOOP03 = 0x01fc
|
|
NVCDC0_SET_I2M_SPARE_NOOP03_V = (31, 0)
|
|
NVCDC0_SET_VALID_SPAN_OVERFLOW_AREA_A = 0x0200
|
|
NVCDC0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER = (7, 0)
|
|
NVCDC0_SET_VALID_SPAN_OVERFLOW_AREA_B = 0x0204
|
|
NVCDC0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER = (31, 0)
|
|
NVCDC0_SET_VALID_SPAN_OVERFLOW_AREA_C = 0x0208
|
|
NVCDC0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE = (31, 0)
|
|
NVCDC0_PERFMON_TRANSFER = 0x0210
|
|
NVCDC0_PERFMON_TRANSFER_V = (31, 0)
|
|
NVCDC0_INVALIDATE_SHADER_CACHES = 0x021c
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_INSTRUCTION = (0, 0)
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE = 0x00000000
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE = 0x00000001
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_DATA = (4, 4)
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_DATA_FALSE = 0x00000000
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_DATA_TRUE = 0x00000001
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_CONSTANT = (12, 12)
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE = 0x00000000
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE = 0x00000001
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_LOCKS = (1, 1)
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE = 0x00000000
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE = 0x00000001
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_FLUSH_DATA = (2, 2)
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE = 0x00000000
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE = 0x00000001
|
|
NVCDC0_SET_RESERVED_SW_METHOD00 = 0x0220
|
|
NVCDC0_SET_RESERVED_SW_METHOD00_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD01 = 0x0224
|
|
NVCDC0_SET_RESERVED_SW_METHOD01_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD02 = 0x0228
|
|
NVCDC0_SET_RESERVED_SW_METHOD02_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD03 = 0x022c
|
|
NVCDC0_SET_RESERVED_SW_METHOD03_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD04 = 0x0230
|
|
NVCDC0_SET_RESERVED_SW_METHOD04_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD05 = 0x0234
|
|
NVCDC0_SET_RESERVED_SW_METHOD05_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD06 = 0x0238
|
|
NVCDC0_SET_RESERVED_SW_METHOD06_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD07 = 0x023c
|
|
NVCDC0_SET_RESERVED_SW_METHOD07_V = (31, 0)
|
|
NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI = 0x0244
|
|
NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES = (0, 0)
|
|
NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL = 0x00000000
|
|
NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE = 0x00000001
|
|
NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG = (25, 4)
|
|
NVCDC0_SET_CWD_REF_COUNTER = 0x0248
|
|
NVCDC0_SET_CWD_REF_COUNTER_SELECT = (5, 0)
|
|
NVCDC0_SET_CWD_REF_COUNTER_VALUE = (23, 8)
|
|
NVCDC0_SET_RESERVED_SW_METHOD08 = 0x024c
|
|
NVCDC0_SET_RESERVED_SW_METHOD08_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD09 = 0x0250
|
|
NVCDC0_SET_RESERVED_SW_METHOD09_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD10 = 0x0254
|
|
NVCDC0_SET_RESERVED_SW_METHOD10_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD11 = 0x0258
|
|
NVCDC0_SET_RESERVED_SW_METHOD11_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD12 = 0x025c
|
|
NVCDC0_SET_RESERVED_SW_METHOD12_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD13 = 0x0260
|
|
NVCDC0_SET_RESERVED_SW_METHOD13_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD14 = 0x0264
|
|
NVCDC0_SET_RESERVED_SW_METHOD14_V = (31, 0)
|
|
NVCDC0_SET_RESERVED_SW_METHOD15 = 0x0268
|
|
NVCDC0_SET_RESERVED_SW_METHOD15_V = (31, 0)
|
|
NVCDC0_SET_COMPUTE_CLASS_VERSION = 0x0280
|
|
NVCDC0_SET_COMPUTE_CLASS_VERSION_CURRENT = (15, 0)
|
|
NVCDC0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED = (31, 16)
|
|
NVCDC0_CHECK_COMPUTE_CLASS_VERSION = 0x0284
|
|
NVCDC0_CHECK_COMPUTE_CLASS_VERSION_CURRENT = (15, 0)
|
|
NVCDC0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED = (31, 16)
|
|
NVCDC0_SET_QMD_VERSION = 0x0288
|
|
NVCDC0_SET_QMD_VERSION_CURRENT = (15, 0)
|
|
NVCDC0_SET_QMD_VERSION_OLDEST_SUPPORTED = (31, 16)
|
|
NVCDC0_INVALIDATE_SKED_CACHES = 0x0298
|
|
NVCDC0_INVALIDATE_SKED_CACHES_FORCE_IGNORE_VEID = (0, 0)
|
|
NVCDC0_INVALIDATE_SKED_CACHES_FORCE_IGNORE_VEID_FALSE = 0x00000000
|
|
NVCDC0_INVALIDATE_SKED_CACHES_FORCE_IGNORE_VEID_TRUE = 0x00000001
|
|
NVCDC0_SET_SHADER_SHARED_MEMORY_WINDOW_A = 0x02a0
|
|
NVCDC0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER = (16, 0)
|
|
NVCDC0_SET_SHADER_SHARED_MEMORY_WINDOW_B = 0x02a4
|
|
NVCDC0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS = (31, 0)
|
|
NVCDC0_SET_CWD_SLOT_COUNT = 0x02b0
|
|
NVCDC0_SET_CWD_SLOT_COUNT_V = (7, 0)
|
|
NVCDC0_SEND_PCAS_A = 0x02b4
|
|
NVCDC0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 = (31, 0)
|
|
NVCDC0_SEND_PCAS_B = 0x02b8
|
|
NVCDC0_SEND_PCAS_B_FROM = (23, 0)
|
|
NVCDC0_SEND_PCAS_B_DELTA = (31, 24)
|
|
NVCDC0_SEND_SIGNALING_PCAS_B = 0x02bc
|
|
NVCDC0_SEND_SIGNALING_PCAS_B_INVALIDATE = (0, 0)
|
|
NVCDC0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE = 0x00000000
|
|
NVCDC0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE = 0x00000001
|
|
NVCDC0_SEND_SIGNALING_PCAS_B_SCHEDULE = (1, 1)
|
|
NVCDC0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE = 0x00000000
|
|
NVCDC0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE = 0x00000001
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B = 0x02c0
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION = (3, 0)
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP = 0x00000000
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE = 0x00000001
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE = 0x00000002
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE = 0x00000003
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT = 0x00000006
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE = 0x00000007
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH = 0x00000008
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE = 0x00000009
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE = 0x0000000A
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING = 0x0000000B
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_DEPENDENCE = 0x0000000C
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_CWD_REF_COUNTER = 0x0000000D
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_SELECT = (13, 8)
|
|
NVCDC0_SEND_SIGNALING_PCAS2_B_OFFSET_MINUS_ONE = (23, 14)
|
|
NVCDC0_SET_SKED_CACHE_CONTROL = 0x02cc
|
|
NVCDC0_SET_SKED_CACHE_CONTROL_IGNORE_VEID = (0, 0)
|
|
NVCDC0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE = 0x00000000
|
|
NVCDC0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE = 0x00000001
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A = 0x02e4
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER = (7, 0)
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B = 0x02e8
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER = (31, 0)
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C = 0x02ec
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT = (8, 0)
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_PLURAL_TPC_GPC_COUNT = (23, 16)
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SINGLETON_TPC_GPC_COUNT = (31, 24)
|
|
NVCDC0_SET_SPA_VERSION = 0x0310
|
|
NVCDC0_SET_SPA_VERSION_MINOR = (7, 0)
|
|
NVCDC0_SET_SPA_VERSION_MAJOR = (15, 8)
|
|
NVCDC0_SET_INLINE_QMD_ADDRESS_A = 0x0318
|
|
NVCDC0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER = (8, 0)
|
|
NVCDC0_SET_INLINE_QMD_ADDRESS_A_INLINE_SIZE = (30, 30)
|
|
NVCDC0_SET_INLINE_QMD_ADDRESS_A_INLINE_SIZE_INLINE_256 = 0x00000000
|
|
NVCDC0_SET_INLINE_QMD_ADDRESS_A_INLINE_SIZE_INLINE_384 = 0x00000001
|
|
NVCDC0_SET_INLINE_QMD_ADDRESS_B = 0x031c
|
|
NVCDC0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER = (31, 0)
|
|
NVCDC0_LOAD_INLINE_QMD_DATA = lambda i: (0x0320+(i)*4) # type: ignore
|
|
NVCDC0_LOAD_INLINE_QMD_DATA_V = (31, 0)
|
|
NVCDC0_SET_FALCON00 = 0x0500
|
|
NVCDC0_SET_FALCON00_V = (31, 0)
|
|
NVCDC0_SET_FALCON01 = 0x0504
|
|
NVCDC0_SET_FALCON01_V = (31, 0)
|
|
NVCDC0_SET_FALCON02 = 0x0508
|
|
NVCDC0_SET_FALCON02_V = (31, 0)
|
|
NVCDC0_SET_FALCON03 = 0x050c
|
|
NVCDC0_SET_FALCON03_V = (31, 0)
|
|
NVCDC0_SET_FALCON04 = 0x0510
|
|
NVCDC0_SET_FALCON04_V = (31, 0)
|
|
NVCDC0_SET_FALCON05 = 0x0514
|
|
NVCDC0_SET_FALCON05_V = (31, 0)
|
|
NVCDC0_SET_FALCON06 = 0x0518
|
|
NVCDC0_SET_FALCON06_V = (31, 0)
|
|
NVCDC0_SET_FALCON07 = 0x051c
|
|
NVCDC0_SET_FALCON07_V = (31, 0)
|
|
NVCDC0_SET_FALCON08 = 0x0520
|
|
NVCDC0_SET_FALCON08_V = (31, 0)
|
|
NVCDC0_SET_FALCON09 = 0x0524
|
|
NVCDC0_SET_FALCON09_V = (31, 0)
|
|
NVCDC0_SET_FALCON10 = 0x0528
|
|
NVCDC0_SET_FALCON10_V = (31, 0)
|
|
NVCDC0_SET_FALCON11 = 0x052c
|
|
NVCDC0_SET_FALCON11_V = (31, 0)
|
|
NVCDC0_SET_FALCON12 = 0x0530
|
|
NVCDC0_SET_FALCON12_V = (31, 0)
|
|
NVCDC0_SET_FALCON13 = 0x0534
|
|
NVCDC0_SET_FALCON13_V = (31, 0)
|
|
NVCDC0_SET_FALCON14 = 0x0538
|
|
NVCDC0_SET_FALCON14_V = (31, 0)
|
|
NVCDC0_SET_FALCON15 = 0x053c
|
|
NVCDC0_SET_FALCON15_V = (31, 0)
|
|
NVCDC0_SET_MME_MEM_ADDRESS_A = 0x0550
|
|
NVCDC0_SET_MME_MEM_ADDRESS_A_UPPER = (24, 0)
|
|
NVCDC0_SET_MME_MEM_ADDRESS_B = 0x0554
|
|
NVCDC0_SET_MME_MEM_ADDRESS_B_LOWER = (31, 0)
|
|
NVCDC0_SET_MME_DATA_RAM_ADDRESS = 0x0558
|
|
NVCDC0_SET_MME_DATA_RAM_ADDRESS_WORD = (31, 0)
|
|
NVCDC0_MME_DMA_READ = 0x055c
|
|
NVCDC0_MME_DMA_READ_LENGTH = (31, 0)
|
|
NVCDC0_MME_DMA_READ_FIFOED = 0x0560
|
|
NVCDC0_MME_DMA_READ_FIFOED_LENGTH = (31, 0)
|
|
NVCDC0_MME_DMA_WRITE = 0x0564
|
|
NVCDC0_MME_DMA_WRITE_LENGTH = (31, 0)
|
|
NVCDC0_MME_DMA_REDUCTION = 0x0568
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP = (2, 0)
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_FORMAT = (5, 4)
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED = 0x00000000
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED = 0x00000001
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_SIZE = (8, 8)
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES = 0x00000000
|
|
NVCDC0_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES = 0x00000001
|
|
NVCDC0_MME_DMA_SYSMEMBAR = 0x056c
|
|
NVCDC0_MME_DMA_SYSMEMBAR_V = (0, 0)
|
|
NVCDC0_MME_DMA_SYNC = 0x0570
|
|
NVCDC0_MME_DMA_SYNC_VALUE = (31, 0)
|
|
NVCDC0_EVENT_START_TRIGGER = 0x074c
|
|
NVCDC0_EVENT_START_TRIGGER_V = (31, 0)
|
|
NVCDC0_EVENT_STOP_TRIGGER = 0x075c
|
|
NVCDC0_EVENT_STOP_TRIGGER_V = (31, 0)
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_A = 0x0790
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER = (24, 0)
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_B = 0x0794
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER = (31, 0)
|
|
NVCDC0_SET_TEXTURE_HEADER_VERSION = 0x07ac
|
|
NVCDC0_SET_TEXTURE_HEADER_VERSION_MAJOR = (7, 0)
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_WINDOW_A = 0x07b0
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER = (16, 0)
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_WINDOW_B = 0x07b4
|
|
NVCDC0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS = (31, 0)
|
|
NVCDC0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_A = 0x07b8
|
|
NVCDC0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_A_LOWER = (31, 0)
|
|
NVCDC0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_B = 0x07bc
|
|
NVCDC0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_B_UPPER = (24, 0)
|
|
NVCDC0_THROTTLE_SM = 0x07fc
|
|
NVCDC0_THROTTLE_SM_MULTIPLY_ADD = (0, 0)
|
|
NVCDC0_THROTTLE_SM_MULTIPLY_ADD_FALSE = 0x00000000
|
|
NVCDC0_THROTTLE_SM_MULTIPLY_ADD_TRUE = 0x00000001
|
|
NVCDC0_SET_SHADER_CACHE_CONTROL = 0x0d94
|
|
NVCDC0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE = (0, 0)
|
|
NVCDC0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE = 0x00000000
|
|
NVCDC0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE = 0x00000001
|
|
NVCDC0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS = lambda i: (0x0da0+(i)*4) # type: ignore
|
|
NVCDC0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V = (31, 0)
|
|
NVCDC0_SET_SM_TIMEOUT_INTERVAL = 0x0de4
|
|
NVCDC0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT = (5, 0)
|
|
NVCDC0_MME_DMA_WRITE_METHOD_BARRIER = 0x0dec
|
|
NVCDC0_MME_DMA_WRITE_METHOD_BARRIER_V = (0, 0)
|
|
NVCDC0_EVENT_STOP_TRIGGER_WFI = 0x0ffc
|
|
NVCDC0_EVENT_STOP_TRIGGER_WFI_V = (31, 0)
|
|
NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI = 0x1288
|
|
NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES = (0, 0)
|
|
NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL = 0x00000000
|
|
NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE = 0x00000001
|
|
NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG = (25, 4)
|
|
NVCDC0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT = 0x12a8
|
|
NVCDC0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL = (0, 0)
|
|
NVCDC0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE = 0x00000000
|
|
NVCDC0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE = 0x00000001
|
|
NVCDC0_INVALIDATE_SAMPLER_CACHE = 0x1330
|
|
NVCDC0_INVALIDATE_SAMPLER_CACHE_LINES = (0, 0)
|
|
NVCDC0_INVALIDATE_SAMPLER_CACHE_LINES_ALL = 0x00000000
|
|
NVCDC0_INVALIDATE_SAMPLER_CACHE_LINES_ONE = 0x00000001
|
|
NVCDC0_INVALIDATE_SAMPLER_CACHE_TAG = (25, 4)
|
|
NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE = 0x1334
|
|
NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES = (0, 0)
|
|
NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL = 0x00000000
|
|
NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE = 0x00000001
|
|
NVCDC0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG = (25, 4)
|
|
NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE = 0x1338
|
|
NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_LINES = (0, 0)
|
|
NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL = 0x00000000
|
|
NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE = 0x00000001
|
|
NVCDC0_INVALIDATE_TEXTURE_DATA_CACHE_TAG = (25, 4)
|
|
NVCDC0_INVALIDATE_SAMPLER_CACHE_NO_WFI = 0x1424
|
|
NVCDC0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES = (0, 0)
|
|
NVCDC0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL = 0x00000000
|
|
NVCDC0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE = 0x00000001
|
|
NVCDC0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG = (25, 4)
|
|
NVCDC0_SET_SHADER_EXCEPTIONS = 0x1528
|
|
NVCDC0_SET_SHADER_EXCEPTIONS_ENABLE = (0, 0)
|
|
NVCDC0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE = 0x00000000
|
|
NVCDC0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE = 0x00000001
|
|
NVCDC0_SET_RENDER_ENABLE_A = 0x1550
|
|
NVCDC0_SET_RENDER_ENABLE_A_OFFSET_UPPER = (7, 0)
|
|
NVCDC0_SET_RENDER_ENABLE_B = 0x1554
|
|
NVCDC0_SET_RENDER_ENABLE_B_OFFSET_LOWER = (31, 0)
|
|
NVCDC0_SET_RENDER_ENABLE_C = 0x1558
|
|
NVCDC0_SET_RENDER_ENABLE_C_MODE = (2, 0)
|
|
NVCDC0_SET_RENDER_ENABLE_C_MODE_FALSE = 0x00000000
|
|
NVCDC0_SET_RENDER_ENABLE_C_MODE_TRUE = 0x00000001
|
|
NVCDC0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002
|
|
NVCDC0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003
|
|
NVCDC0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004
|
|
NVCDC0_SET_TEX_SAMPLER_POOL_A = 0x155c
|
|
NVCDC0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER = (24, 0)
|
|
NVCDC0_SET_TEX_SAMPLER_POOL_B = 0x1560
|
|
NVCDC0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER = (31, 0)
|
|
NVCDC0_SET_TEX_SAMPLER_POOL_C = 0x1564
|
|
NVCDC0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX = (31, 0)
|
|
NVCDC0_SET_TEX_HEADER_POOL_A = 0x1574
|
|
NVCDC0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER = (24, 0)
|
|
NVCDC0_SET_TEX_HEADER_POOL_B = 0x1578
|
|
NVCDC0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER = (31, 0)
|
|
NVCDC0_SET_TEX_HEADER_POOL_C = 0x157c
|
|
NVCDC0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX = (31, 0)
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI = 0x1698
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION = (0, 0)
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE = 0x00000000
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE = 0x00000001
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA = (4, 4)
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE = 0x00000000
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE = 0x00000001
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT = (12, 12)
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE = 0x00000000
|
|
NVCDC0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE = 0x00000001
|
|
NVCDC0_SET_RENDER_ENABLE_OVERRIDE = 0x1944
|
|
NVCDC0_SET_RENDER_ENABLE_OVERRIDE_MODE = (1, 0)
|
|
NVCDC0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE = 0x00000000
|
|
NVCDC0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER = 0x00000001
|
|
NVCDC0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER = 0x00000002
|
|
NVCDC0_PIPE_NOP = 0x1a2c
|
|
NVCDC0_PIPE_NOP_V = (31, 0)
|
|
NVCDC0_SET_SPARE00 = 0x1a30
|
|
NVCDC0_SET_SPARE00_V = (31, 0)
|
|
NVCDC0_SET_SPARE01 = 0x1a34
|
|
NVCDC0_SET_SPARE01_V = (31, 0)
|
|
NVCDC0_SET_SPARE02 = 0x1a38
|
|
NVCDC0_SET_SPARE02_V = (31, 0)
|
|
NVCDC0_SET_SPARE03 = 0x1a3c
|
|
NVCDC0_SET_SPARE03_V = (31, 0)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_A = 0x1b00
|
|
NVCDC0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER = (24, 0)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_B = 0x1b04
|
|
NVCDC0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER = (31, 0)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_C = 0x1b08
|
|
NVCDC0_SET_REPORT_SEMAPHORE_C_PAYLOAD = (31, 0)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D = 0x1b0c
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_OPERATION = (1, 0)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE = 0x00000000
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP = 0x00000003
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE = (20, 20)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE = 0x00000000
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE = 0x00000001
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE = (28, 28)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD = 0x00000001
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE = (2, 2)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE = 0x00000000
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE = 0x00000001
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE = (3, 3)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE = 0x00000000
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE = 0x00000001
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP = (11, 9)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD = 0x00000000
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN = 0x00000001
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX = 0x00000002
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC = 0x00000003
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC = 0x00000004
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND = 0x00000005
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR = 0x00000006
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR = 0x00000007
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT = (18, 17)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP = (19, 19)
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE = 0x00000000
|
|
NVCDC0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE = 0x00000001
|
|
NVCDC0_SET_TRAP_HANDLER_A = 0x25f8
|
|
NVCDC0_SET_TRAP_HANDLER_A_ADDRESS_UPPER = (24, 0)
|
|
NVCDC0_SET_TRAP_HANDLER_B = 0x25fc
|
|
NVCDC0_SET_TRAP_HANDLER_B_ADDRESS_LOWER = (31, 0)
|
|
NVCDC0_SET_BINDLESS_TEXTURE = 0x2608
|
|
NVCDC0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT = (2, 0)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE = lambda i: (0x32f4+(i)*4) # type: ignore
|
|
NVCDC0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V = (31, 0)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER = lambda i: (0x3314+(i)*4) # type: ignore
|
|
NVCDC0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V = (31, 0)
|
|
NVCDC0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3334
|
|
NVCDC0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V = (0, 0)
|
|
NVCDC0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3338
|
|
NVCDC0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V = (0, 0)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER = lambda i: (0x333c+(i)*4) # type: ignore
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V = (31, 0)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_VALUE = lambda i: (0x335c+(i)*4) # type: ignore
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V = (31, 0)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_EVENT = lambda i: (0x337c+(i)*4) # type: ignore
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT = (7, 0)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A = lambda i: (0x339c+(i)*4) # type: ignore
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 = (1, 0)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 = (4, 2)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 = (6, 5)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 = (9, 7)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 = (11, 10)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 = (14, 12)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 = (16, 15)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 = (19, 17)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 = (21, 20)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 = (24, 22)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 = (26, 25)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 = (29, 27)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE = (31, 30)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B = lambda i: (0x33bc+(i)*4) # type: ignore
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE = (0, 0)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE = (2, 1)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED = (3, 3)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC = (19, 4)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL = 0x33dc
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK = (7, 0)
|
|
NVCDC0_START_SHADER_PERFORMANCE_COUNTER = 0x33e0
|
|
NVCDC0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK = (7, 0)
|
|
NVCDC0_STOP_SHADER_PERFORMANCE_COUNTER = 0x33e4
|
|
NVCDC0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK = (7, 0)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER = 0x33e8
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V = (31, 0)
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER = 0x33ec
|
|
NVCDC0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V = (31, 0)
|
|
NVCDC0_SET_MME_SHADOW_SCRATCH = lambda i: (0x3400+(i)*4) # type: ignore
|
|
NVCDC0_SET_MME_SHADOW_SCRATCH_V = (31, 0)
|
|
NVCDC0_CALL_MME_MACRO = lambda j: (0x3800+(j)*8) # type: ignore
|
|
NVCDC0_CALL_MME_MACRO_V = (31, 0)
|
|
NVCDC0_CALL_MME_DATA = lambda j: (0x3804+(j)*8) # type: ignore
|
|
NVCDC0_CALL_MME_DATA_V = (31, 0)
|
|
AMPERE_DMA_COPY_A = (0x0000C6B5)
|
|
NVC6B5_NOP = (0x00000100)
|
|
NVC6B5_NOP_PARAMETER = (31, 0)
|
|
NVC6B5_PM_TRIGGER = (0x00000140)
|
|
NVC6B5_PM_TRIGGER_V = (31, 0)
|
|
NVC6B5_SET_SEMAPHORE_A = (0x00000240)
|
|
NVC6B5_SET_SEMAPHORE_A_UPPER = (16, 0)
|
|
NVC6B5_SET_SEMAPHORE_B = (0x00000244)
|
|
NVC6B5_SET_SEMAPHORE_B_LOWER = (31, 0)
|
|
NVC6B5_SET_SEMAPHORE_PAYLOAD = (0x00000248)
|
|
NVC6B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD = (31, 0)
|
|
NVC6B5_SET_RENDER_ENABLE_A = (0x00000254)
|
|
NVC6B5_SET_RENDER_ENABLE_A_UPPER = (7, 0)
|
|
NVC6B5_SET_RENDER_ENABLE_B = (0x00000258)
|
|
NVC6B5_SET_RENDER_ENABLE_B_LOWER = (31, 0)
|
|
NVC6B5_SET_RENDER_ENABLE_C = (0x0000025C)
|
|
NVC6B5_SET_RENDER_ENABLE_C_MODE = (2, 0)
|
|
NVC6B5_SET_RENDER_ENABLE_C_MODE_FALSE = (0x00000000)
|
|
NVC6B5_SET_RENDER_ENABLE_C_MODE_TRUE = (0x00000001)
|
|
NVC6B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = (0x00000002)
|
|
NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = (0x00000003)
|
|
NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = (0x00000004)
|
|
NVC6B5_SET_SRC_PHYS_MODE = (0x00000260)
|
|
NVC6B5_SET_SRC_PHYS_MODE_TARGET = (1, 0)
|
|
NVC6B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000)
|
|
NVC6B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001)
|
|
NVC6B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002)
|
|
NVC6B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM = (0x00000003)
|
|
NVC6B5_SET_SRC_PHYS_MODE_BASIC_KIND = (5, 2)
|
|
NVC6B5_SET_SRC_PHYS_MODE_PEER_ID = (8, 6)
|
|
NVC6B5_SET_SRC_PHYS_MODE_FLA = (9, 9)
|
|
NVC6B5_SET_DST_PHYS_MODE = (0x00000264)
|
|
NVC6B5_SET_DST_PHYS_MODE_TARGET = (1, 0)
|
|
NVC6B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000)
|
|
NVC6B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001)
|
|
NVC6B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002)
|
|
NVC6B5_SET_DST_PHYS_MODE_TARGET_PEERMEM = (0x00000003)
|
|
NVC6B5_SET_DST_PHYS_MODE_BASIC_KIND = (5, 2)
|
|
NVC6B5_SET_DST_PHYS_MODE_PEER_ID = (8, 6)
|
|
NVC6B5_SET_DST_PHYS_MODE_FLA = (9, 9)
|
|
NVC6B5_LAUNCH_DMA = (0x00000300)
|
|
NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE = (1, 0)
|
|
NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED = (0x00000002)
|
|
NVC6B5_LAUNCH_DMA_FLUSH_ENABLE = (2, 2)
|
|
NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_FLUSH_TYPE = (25, 25)
|
|
NVC6B5_LAUNCH_DMA_FLUSH_TYPE_SYS = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_FLUSH_TYPE_GL = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE = (4, 3)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE = (0x00000002)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE = (0x00000003)
|
|
NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE = (6, 5)
|
|
NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING = (0x00000002)
|
|
NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT = (7, 7)
|
|
NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT = (8, 8)
|
|
NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE = (9, 9)
|
|
NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_REMAP_ENABLE = (10, 10)
|
|
NVC6B5_LAUNCH_DMA_REMAP_ENABLE_FALSE = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_REMAP_ENABLE_TRUE = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE = (11, 11)
|
|
NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_SRC_TYPE = (12, 12)
|
|
NVC6B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_DST_TYPE = (13, 13)
|
|
NVC6B5_LAUNCH_DMA_DST_TYPE_VIRTUAL = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_DST_TYPE_PHYSICAL = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION = (17, 14)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR = (0x00000002)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND = (0x00000003)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR = (0x00000004)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD = (0x00000005)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC = (0x00000006)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC = (0x00000007)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD = (0x0000000A)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN = (18, 18)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE = (19, 19)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_VPRMODE = (23, 22)
|
|
NVC6B5_LAUNCH_DMA_VPRMODE_VPR_NONE = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_RESERVED_START_OF_COPY = (24, 24)
|
|
NVC6B5_LAUNCH_DMA_DISABLE_PLC = (26, 26)
|
|
NVC6B5_LAUNCH_DMA_DISABLE_PLC_FALSE = (0x00000000)
|
|
NVC6B5_LAUNCH_DMA_DISABLE_PLC_TRUE = (0x00000001)
|
|
NVC6B5_LAUNCH_DMA_RESERVED_ERR_CODE = (31, 28)
|
|
NVC6B5_OFFSET_IN_UPPER = (0x00000400)
|
|
NVC6B5_OFFSET_IN_UPPER_UPPER = (16, 0)
|
|
NVC6B5_OFFSET_IN_LOWER = (0x00000404)
|
|
NVC6B5_OFFSET_IN_LOWER_VALUE = (31, 0)
|
|
NVC6B5_OFFSET_OUT_UPPER = (0x00000408)
|
|
NVC6B5_OFFSET_OUT_UPPER_UPPER = (16, 0)
|
|
NVC6B5_OFFSET_OUT_LOWER = (0x0000040C)
|
|
NVC6B5_OFFSET_OUT_LOWER_VALUE = (31, 0)
|
|
NVC6B5_PITCH_IN = (0x00000410)
|
|
NVC6B5_PITCH_IN_VALUE = (31, 0)
|
|
NVC6B5_PITCH_OUT = (0x00000414)
|
|
NVC6B5_PITCH_OUT_VALUE = (31, 0)
|
|
NVC6B5_LINE_LENGTH_IN = (0x00000418)
|
|
NVC6B5_LINE_LENGTH_IN_VALUE = (31, 0)
|
|
NVC6B5_LINE_COUNT = (0x0000041C)
|
|
NVC6B5_LINE_COUNT_VALUE = (31, 0)
|
|
NVC6B5_SET_REMAP_CONST_A = (0x00000700)
|
|
NVC6B5_SET_REMAP_CONST_A_V = (31, 0)
|
|
NVC6B5_SET_REMAP_CONST_B = (0x00000704)
|
|
NVC6B5_SET_REMAP_CONST_B_V = (31, 0)
|
|
NVC6B5_SET_REMAP_COMPONENTS = (0x00000708)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X = (2, 0)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_X = (0x00000000)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y = (0x00000001)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z = (0x00000002)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_W = (0x00000003)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_A = (0x00000004)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_B = (0x00000005)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE = (0x00000006)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y = (6, 4)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X = (0x00000000)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y = (0x00000001)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z = (0x00000002)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W = (0x00000003)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A = (0x00000004)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B = (0x00000005)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE = (0x00000006)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z = (10, 8)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X = (0x00000000)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y = (0x00000001)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z = (0x00000002)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W = (0x00000003)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A = (0x00000004)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B = (0x00000005)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE = (0x00000006)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W = (14, 12)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_X = (0x00000000)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y = (0x00000001)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z = (0x00000002)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_W = (0x00000003)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_A = (0x00000004)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_B = (0x00000005)
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE = (0x00000006)
|
|
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE = (17, 16)
|
|
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE = (0x00000000)
|
|
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO = (0x00000001)
|
|
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE = (0x00000002)
|
|
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR = (0x00000003)
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS = (21, 20)
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE = (0x00000000)
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO = (0x00000001)
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE = (0x00000002)
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR = (0x00000003)
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS = (25, 24)
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE = (0x00000000)
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO = (0x00000001)
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE = (0x00000002)
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR = (0x00000003)
|
|
NVC6B5_SET_DST_BLOCK_SIZE = (0x0000070C)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_WIDTH = (3, 0)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT = (7, 4)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH = (11, 8)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT = (15, 12)
|
|
NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001)
|
|
NVC6B5_SET_DST_WIDTH = (0x00000710)
|
|
NVC6B5_SET_DST_WIDTH_V = (31, 0)
|
|
NVC6B5_SET_DST_HEIGHT = (0x00000714)
|
|
NVC6B5_SET_DST_HEIGHT_V = (31, 0)
|
|
NVC6B5_SET_DST_DEPTH = (0x00000718)
|
|
NVC6B5_SET_DST_DEPTH_V = (31, 0)
|
|
NVC6B5_SET_DST_LAYER = (0x0000071C)
|
|
NVC6B5_SET_DST_LAYER_V = (31, 0)
|
|
NVC6B5_SET_DST_ORIGIN = (0x00000720)
|
|
NVC6B5_SET_DST_ORIGIN_X = (15, 0)
|
|
NVC6B5_SET_DST_ORIGIN_Y = (31, 16)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE = (0x00000728)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH = (3, 0)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT = (7, 4)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH = (11, 8)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT = (15, 12)
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001)
|
|
NVC6B5_SET_SRC_WIDTH = (0x0000072C)
|
|
NVC6B5_SET_SRC_WIDTH_V = (31, 0)
|
|
NVC6B5_SET_SRC_HEIGHT = (0x00000730)
|
|
NVC6B5_SET_SRC_HEIGHT_V = (31, 0)
|
|
NVC6B5_SET_SRC_DEPTH = (0x00000734)
|
|
NVC6B5_SET_SRC_DEPTH_V = (31, 0)
|
|
NVC6B5_SET_SRC_LAYER = (0x00000738)
|
|
NVC6B5_SET_SRC_LAYER_V = (31, 0)
|
|
NVC6B5_SET_SRC_ORIGIN = (0x0000073C)
|
|
NVC6B5_SET_SRC_ORIGIN_X = (15, 0)
|
|
NVC6B5_SET_SRC_ORIGIN_Y = (31, 16)
|
|
NVC6B5_SRC_ORIGIN_X = (0x00000744)
|
|
NVC6B5_SRC_ORIGIN_X_VALUE = (31, 0)
|
|
NVC6B5_SRC_ORIGIN_Y = (0x00000748)
|
|
NVC6B5_SRC_ORIGIN_Y_VALUE = (31, 0)
|
|
NVC6B5_DST_ORIGIN_X = (0x0000074C)
|
|
NVC6B5_DST_ORIGIN_X_VALUE = (31, 0)
|
|
NVC6B5_DST_ORIGIN_Y = (0x00000750)
|
|
NVC6B5_DST_ORIGIN_Y_VALUE = (31, 0)
|
|
NVC6B5_PM_TRIGGER_END = (0x00001114)
|
|
NVC6B5_PM_TRIGGER_END_V = (31, 0)
|
|
BLACKWELL_DMA_COPY_A = (0x0000C9B5)
|
|
UVM_IOCTL_BASE = lambda i: i # type: ignore
|
|
UVM_RESERVE_VA = UVM_IOCTL_BASE(1)
|
|
UVM_RELEASE_VA = UVM_IOCTL_BASE(2)
|
|
UVM_REGION_COMMIT = UVM_IOCTL_BASE(3)
|
|
UVM_REGION_DECOMMIT = UVM_IOCTL_BASE(4)
|
|
UVM_REGION_SET_STREAM = UVM_IOCTL_BASE(5)
|
|
UVM_SET_STREAM_RUNNING = UVM_IOCTL_BASE(6)
|
|
UVM_MAX_STREAMS_PER_IOCTL_CALL = 32
|
|
UVM_SET_STREAM_STOPPED = UVM_IOCTL_BASE(7)
|
|
UVM_ADD_SESSION = UVM_IOCTL_BASE(10)
|
|
UVM_MAX_COUNTERS_PER_IOCTL_CALL = 32
|
|
UVM_ENABLE_COUNTERS = UVM_IOCTL_BASE(12)
|
|
UVM_MAP_COUNTER = UVM_IOCTL_BASE(13)
|
|
UVM_CREATE_EVENT_QUEUE = UVM_IOCTL_BASE(14)
|
|
UVM_REMOVE_EVENT_QUEUE = UVM_IOCTL_BASE(15)
|
|
UVM_MAP_EVENT_QUEUE = UVM_IOCTL_BASE(16)
|
|
UVM_EVENT_CTRL = UVM_IOCTL_BASE(17)
|
|
UVM_GET_GPU_UUID_TABLE = UVM_IOCTL_BASE(20)
|
|
UVM_REGISTER_GPU_VASPACE = UVM_IOCTL_BASE(25)
|
|
UVM_UNREGISTER_GPU_VASPACE = UVM_IOCTL_BASE(26)
|
|
UVM_REGISTER_CHANNEL = UVM_IOCTL_BASE(27)
|
|
UVM_UNREGISTER_CHANNEL = UVM_IOCTL_BASE(28)
|
|
UVM_ENABLE_PEER_ACCESS = UVM_IOCTL_BASE(29)
|
|
UVM_DISABLE_PEER_ACCESS = UVM_IOCTL_BASE(30)
|
|
UVM_MAP_EXTERNAL_ALLOCATION = UVM_IOCTL_BASE(33)
|
|
UVM_FREE = UVM_IOCTL_BASE(34)
|
|
UVM_MEM_MAP = UVM_IOCTL_BASE(35)
|
|
UVM_REGISTER_GPU = UVM_IOCTL_BASE(37)
|
|
UVM_UNREGISTER_GPU = UVM_IOCTL_BASE(38)
|
|
UVM_PAGEABLE_MEM_ACCESS = UVM_IOCTL_BASE(39)
|
|
UVM_SET_PREFERRED_LOCATION = UVM_IOCTL_BASE(42)
|
|
UVM_UNSET_PREFERRED_LOCATION = UVM_IOCTL_BASE(43)
|
|
UVM_ENABLE_READ_DUPLICATION = UVM_IOCTL_BASE(44)
|
|
UVM_DISABLE_READ_DUPLICATION = UVM_IOCTL_BASE(45)
|
|
UVM_SET_ACCESSED_BY = UVM_IOCTL_BASE(46)
|
|
UVM_UNSET_ACCESSED_BY = UVM_IOCTL_BASE(47)
|
|
UVM_MIGRATE_FLAG_ASYNC = 0x00000001
|
|
UVM_MIGRATE_FLAG_SKIP_CPU_MAP = 0x00000002
|
|
UVM_MIGRATE_FLAG_NO_GPU_VA_SPACE = 0x00000004
|
|
UVM_MIGRATE_FLAGS_TEST_ALL = (UVM_MIGRATE_FLAG_SKIP_CPU_MAP | UVM_MIGRATE_FLAG_NO_GPU_VA_SPACE)
|
|
UVM_MIGRATE_FLAGS_ALL = (UVM_MIGRATE_FLAG_ASYNC | UVM_MIGRATE_FLAGS_TEST_ALL)
|
|
UVM_MIGRATE = UVM_IOCTL_BASE(51)
|
|
UVM_TOOLS_INIT_EVENT_TRACKER = UVM_IOCTL_BASE(56)
|
|
UVM_TOOLS_SET_NOTIFICATION_THRESHOLD = UVM_IOCTL_BASE(57)
|
|
UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS = UVM_IOCTL_BASE(58)
|
|
UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS = UVM_IOCTL_BASE(59)
|
|
UVM_TOOLS_ENABLE_COUNTERS = UVM_IOCTL_BASE(60)
|
|
UVM_TOOLS_DISABLE_COUNTERS = UVM_IOCTL_BASE(61)
|
|
UVM_TOOLS_READ_PROCESS_MEMORY = UVM_IOCTL_BASE(62)
|
|
UVM_TOOLS_WRITE_PROCESS_MEMORY = UVM_IOCTL_BASE(63)
|
|
UVM_TOOLS_GET_PROCESSOR_UUID_TABLE = UVM_IOCTL_BASE(64)
|
|
UVM_MAP_DYNAMIC_PARALLELISM_REGION = UVM_IOCTL_BASE(65)
|
|
UVM_UNMAP_EXTERNAL = UVM_IOCTL_BASE(66)
|
|
UVM_TOOLS_FLUSH_EVENTS = UVM_IOCTL_BASE(67)
|
|
UVM_ALLOC_SEMAPHORE_POOL = UVM_IOCTL_BASE(68)
|
|
UVM_CLEAN_UP_ZOMBIE_RESOURCES = UVM_IOCTL_BASE(69)
|
|
UVM_PAGEABLE_MEM_ACCESS_ON_GPU = UVM_IOCTL_BASE(70)
|
|
UVM_POPULATE_PAGEABLE = UVM_IOCTL_BASE(71)
|
|
UVM_POPULATE_PAGEABLE_FLAG_ALLOW_MANAGED = 0x00000001
|
|
UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK = 0x00000002
|
|
UVM_POPULATE_PAGEABLE_FLAG_ALLOW_SPECIAL = 0x00000004
|
|
UVM_POPULATE_PAGEABLE_FLAGS_INTERNAL = UVM_POPULATE_PAGEABLE_FLAG_ALLOW_SPECIAL
|
|
UVM_POPULATE_PAGEABLE_FLAGS_TEST = (UVM_POPULATE_PAGEABLE_FLAG_ALLOW_MANAGED | UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK)
|
|
UVM_POPULATE_PAGEABLE_FLAGS_ALL = (UVM_POPULATE_PAGEABLE_FLAGS_INTERNAL | UVM_POPULATE_PAGEABLE_FLAGS_TEST)
|
|
UVM_VALIDATE_VA_RANGE = UVM_IOCTL_BASE(72)
|
|
UVM_CREATE_EXTERNAL_RANGE = UVM_IOCTL_BASE(73)
|
|
UVM_MAP_EXTERNAL_SPARSE = UVM_IOCTL_BASE(74)
|
|
UVM_MM_INITIALIZE = UVM_IOCTL_BASE(75)
|
|
UVM_TOOLS_INIT_EVENT_TRACKER_V2 = UVM_IOCTL_BASE(76)
|
|
UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2 = UVM_IOCTL_BASE(77)
|
|
UVM_ALLOC_DEVICE_P2P = UVM_IOCTL_BASE(78)
|
|
UVM_CLEAR_ALL_ACCESS_COUNTERS = UVM_IOCTL_BASE(79)
|
|
UVM_DISCARD = UVM_IOCTL_BASE(80)
|
|
UVM_QUERY_RESIDENCY = UVM_IOCTL_BASE(81)
|
|
UVM_IS_8_SUPPORTED = UVM_IOCTL_BASE(2047)
|
|
UVM_INITIALIZE = 0x30000001
|
|
UVM_DEINITIALIZE = 0x30000002
|
|
NV_PFAULT_MMU_ENG_ID_GRAPHICS = 64
|
|
NV_PFAULT_MMU_ENG_ID_DISPLAY = 1
|
|
NV_PFAULT_MMU_ENG_ID_GSP = 2
|
|
NV_PFAULT_MMU_ENG_ID_IFB = 9
|
|
NV_PFAULT_MMU_ENG_ID_FLA = 4
|
|
NV_PFAULT_MMU_ENG_ID_BAR1 = 128
|
|
NV_PFAULT_MMU_ENG_ID_BAR2 = 192
|
|
NV_PFAULT_MMU_ENG_ID_SEC = 14
|
|
NV_PFAULT_MMU_ENG_ID_PERF = 8
|
|
NV_PFAULT_MMU_ENG_ID_NVDEC = 25
|
|
NV_PFAULT_MMU_ENG_ID_NVDEC0 = 25
|
|
NV_PFAULT_MMU_ENG_ID_NVDEC1 = 26
|
|
NV_PFAULT_MMU_ENG_ID_NVDEC2 = 27
|
|
NV_PFAULT_MMU_ENG_ID_NVDEC3 = 28
|
|
NV_PFAULT_MMU_ENG_ID_NVDEC4 = 29
|
|
NV_PFAULT_MMU_ENG_ID_NVJPG0 = 30
|
|
NV_PFAULT_MMU_ENG_ID_GRCOPY = 15
|
|
NV_PFAULT_MMU_ENG_ID_CE0 = 15
|
|
NV_PFAULT_MMU_ENG_ID_CE1 = 16
|
|
NV_PFAULT_MMU_ENG_ID_CE2 = 17
|
|
NV_PFAULT_MMU_ENG_ID_CE3 = 18
|
|
NV_PFAULT_MMU_ENG_ID_CE4 = 19
|
|
NV_PFAULT_MMU_ENG_ID_CE5 = 20
|
|
NV_PFAULT_MMU_ENG_ID_CE6 = 21
|
|
NV_PFAULT_MMU_ENG_ID_CE7 = 22
|
|
NV_PFAULT_MMU_ENG_ID_CE8 = 23
|
|
NV_PFAULT_MMU_ENG_ID_CE9 = 24
|
|
NV_PFAULT_MMU_ENG_ID_PWR_PMU = 6
|
|
NV_PFAULT_MMU_ENG_ID_PTP = 3
|
|
NV_PFAULT_MMU_ENG_ID_NVENC0 = 11
|
|
NV_PFAULT_MMU_ENG_ID_NVENC1 = 12
|
|
NV_PFAULT_MMU_ENG_ID_NVENC2 = 13
|
|
NV_PFAULT_MMU_ENG_ID_OFA0 = 10
|
|
NV_PFAULT_MMU_ENG_ID_PHYSICAL = 31
|
|
NV_PFAULT_MMU_ENG_ID_HOST0 = 32
|
|
NV_PFAULT_MMU_ENG_ID_HOST1 = 33
|
|
NV_PFAULT_MMU_ENG_ID_HOST2 = 34
|
|
NV_PFAULT_MMU_ENG_ID_HOST3 = 35
|
|
NV_PFAULT_MMU_ENG_ID_HOST4 = 36
|
|
NV_PFAULT_MMU_ENG_ID_HOST5 = 37
|
|
NV_PFAULT_MMU_ENG_ID_HOST6 = 38
|
|
NV_PFAULT_MMU_ENG_ID_HOST7 = 39
|
|
NV_PFAULT_MMU_ENG_ID_HOST8 = 40
|
|
NV_PFAULT_MMU_ENG_ID_HOST9 = 41
|
|
NV_PFAULT_MMU_ENG_ID_HOST10 = 42
|
|
NV_PFAULT_MMU_ENG_ID_HOST11 = 43
|
|
NV_PFAULT_MMU_ENG_ID_HOST12 = 44
|
|
NV_PFAULT_MMU_ENG_ID_HOST13 = 45
|
|
NV_PFAULT_MMU_ENG_ID_HOST14 = 46
|
|
NV_PFAULT_MMU_ENG_ID_HOST15 = 47
|
|
NV_PFAULT_MMU_ENG_ID_HOST16 = 48
|
|
NV_PFAULT_MMU_ENG_ID_HOST17 = 49
|
|
NV_PFAULT_MMU_ENG_ID_HOST18 = 50
|
|
NV_PFAULT_MMU_ENG_ID_HOST19 = 51
|
|
NV_PFAULT_MMU_ENG_ID_HOST20 = 52
|
|
NV_PFAULT_MMU_ENG_ID_HOST21 = 53
|
|
NV_PFAULT_MMU_ENG_ID_HOST22 = 54
|
|
NV_PFAULT_MMU_ENG_ID_HOST23 = 55
|
|
NV_PFAULT_MMU_ENG_ID_HOST24 = 56
|
|
NV_PFAULT_MMU_ENG_ID_HOST25 = 57
|
|
NV_PFAULT_MMU_ENG_ID_HOST26 = 58
|
|
NV_PFAULT_MMU_ENG_ID_HOST27 = 59
|
|
NV_PFAULT_MMU_ENG_ID_HOST28 = 60
|
|
NV_PFAULT_MMU_ENG_ID_HOST29 = 61
|
|
NV_PFAULT_MMU_ENG_ID_HOST30 = 62
|
|
NV_PFAULT_MMU_ENG_ID_HOST31 = 63
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN0 = 128
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN1 = 129
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN2 = 130
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN3 = 131
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN4 = 132
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN5 = 133
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN6 = 134
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN7 = 135
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN8 = 136
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN9 = 137
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN10 = 138
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN11 = 139
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN12 = 140
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN13 = 141
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN14 = 142
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN15 = 143
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN16 = 144
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN17 = 145
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN18 = 146
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN19 = 147
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN20 = 148
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN21 = 149
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN22 = 150
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN23 = 151
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN24 = 152
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN25 = 153
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN26 = 154
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN27 = 155
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN28 = 156
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN29 = 157
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN30 = 158
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN31 = 159
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN32 = 160
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN33 = 161
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN34 = 162
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN35 = 163
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN36 = 164
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN37 = 165
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN38 = 166
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN39 = 167
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN40 = 168
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN41 = 169
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN42 = 170
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN43 = 171
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN44 = 172
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN45 = 173
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN46 = 174
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN47 = 175
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN48 = 176
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN49 = 177
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN50 = 178
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN51 = 179
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN52 = 180
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN53 = 181
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN54 = 182
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN55 = 183
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN56 = 184
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN57 = 185
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN58 = 186
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN59 = 187
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN60 = 188
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN61 = 189
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN62 = 190
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN63 = 191
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN0 = 192
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN1 = 193
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN2 = 194
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN3 = 195
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN4 = 196
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN5 = 197
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN6 = 198
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN7 = 199
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN8 = 200
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN9 = 201
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN10 = 202
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN11 = 203
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN12 = 204
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN13 = 205
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN14 = 206
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN15 = 207
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN16 = 208
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN17 = 209
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN18 = 210
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN19 = 211
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN20 = 212
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN21 = 213
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN22 = 214
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN23 = 215
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN24 = 216
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN25 = 217
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN26 = 218
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN27 = 219
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN28 = 220
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN29 = 221
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN30 = 222
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN31 = 223
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN32 = 224
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN33 = 225
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN34 = 226
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN35 = 227
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN36 = 228
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN37 = 229
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN38 = 230
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN39 = 231
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN40 = 232
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN41 = 233
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN42 = 234
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN43 = 235
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN44 = 236
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN45 = 237
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN46 = 238
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN47 = 239
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN48 = 240
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN49 = 241
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN50 = 242
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN51 = 243
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN52 = 244
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN53 = 245
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN54 = 246
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN55 = 247
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN56 = 248
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN57 = 249
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN58 = 250
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN59 = 251
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN60 = 252
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN61 = 253
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN62 = 254
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN63 = 255
|
|
NV_PFAULT_FAULT_TYPE = (4, 0)
|
|
NV_PFAULT_FAULT_TYPE_PDE = 0x00000000
|
|
NV_PFAULT_FAULT_TYPE_PDE_SIZE = 0x00000001
|
|
NV_PFAULT_FAULT_TYPE_PTE = 0x00000002
|
|
NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION = 0x00000003
|
|
NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK = 0x00000004
|
|
NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION = 0x00000005
|
|
NV_PFAULT_FAULT_TYPE_RO_VIOLATION = 0x00000006
|
|
NV_PFAULT_FAULT_TYPE_WO_VIOLATION = 0x00000007
|
|
NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION = 0x00000008
|
|
NV_PFAULT_FAULT_TYPE_WORK_CREATION = 0x00000009
|
|
NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE = 0x0000000a
|
|
NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE = 0x0000000b
|
|
NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND = 0x0000000c
|
|
NV_PFAULT_FAULT_TYPE_REGION_VIOLATION = 0x0000000d
|
|
NV_PFAULT_FAULT_TYPE_POISONED = 0x0000000e
|
|
NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION = 0x0000000f
|
|
NV_PFAULT_CLIENT = (14, 8)
|
|
NV_PFAULT_CLIENT_GPC_T1_0 = 0x00000000
|
|
NV_PFAULT_CLIENT_GPC_T1_1 = 0x00000001
|
|
NV_PFAULT_CLIENT_GPC_T1_2 = 0x00000002
|
|
NV_PFAULT_CLIENT_GPC_T1_3 = 0x00000003
|
|
NV_PFAULT_CLIENT_GPC_T1_4 = 0x00000004
|
|
NV_PFAULT_CLIENT_GPC_T1_5 = 0x00000005
|
|
NV_PFAULT_CLIENT_GPC_T1_6 = 0x00000006
|
|
NV_PFAULT_CLIENT_GPC_T1_7 = 0x00000007
|
|
NV_PFAULT_CLIENT_GPC_PE_0 = 0x00000008
|
|
NV_PFAULT_CLIENT_GPC_PE_1 = 0x00000009
|
|
NV_PFAULT_CLIENT_GPC_PE_2 = 0x0000000A
|
|
NV_PFAULT_CLIENT_GPC_PE_3 = 0x0000000B
|
|
NV_PFAULT_CLIENT_GPC_PE_4 = 0x0000000C
|
|
NV_PFAULT_CLIENT_GPC_PE_5 = 0x0000000D
|
|
NV_PFAULT_CLIENT_GPC_PE_6 = 0x0000000E
|
|
NV_PFAULT_CLIENT_GPC_PE_7 = 0x0000000F
|
|
NV_PFAULT_CLIENT_GPC_RAST = 0x00000010
|
|
NV_PFAULT_CLIENT_GPC_GCC = 0x00000011
|
|
NV_PFAULT_CLIENT_GPC_GPCCS = 0x00000012
|
|
NV_PFAULT_CLIENT_GPC_PROP_0 = 0x00000013
|
|
NV_PFAULT_CLIENT_GPC_PROP_1 = 0x00000014
|
|
NV_PFAULT_CLIENT_GPC_PROP_2 = 0x00000015
|
|
NV_PFAULT_CLIENT_GPC_PROP_3 = 0x00000016
|
|
NV_PFAULT_CLIENT_GPC_T1_8 = 0x00000021
|
|
NV_PFAULT_CLIENT_GPC_T1_9 = 0x00000022
|
|
NV_PFAULT_CLIENT_GPC_T1_10 = 0x00000023
|
|
NV_PFAULT_CLIENT_GPC_T1_11 = 0x00000024
|
|
NV_PFAULT_CLIENT_GPC_T1_12 = 0x00000025
|
|
NV_PFAULT_CLIENT_GPC_T1_13 = 0x00000026
|
|
NV_PFAULT_CLIENT_GPC_T1_14 = 0x00000027
|
|
NV_PFAULT_CLIENT_GPC_T1_15 = 0x00000028
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_0 = 0x00000029
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_1 = 0x0000002A
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_2 = 0x0000002B
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_3 = 0x0000002C
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_4 = 0x0000002D
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_5 = 0x0000002E
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_6 = 0x0000002F
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_7 = 0x00000030
|
|
NV_PFAULT_CLIENT_GPC_PE_8 = 0x00000031
|
|
NV_PFAULT_CLIENT_GPC_PE_9 = 0x00000032
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_8 = 0x00000033
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_9 = 0x00000034
|
|
NV_PFAULT_CLIENT_GPC_T1_16 = 0x00000035
|
|
NV_PFAULT_CLIENT_GPC_T1_17 = 0x00000036
|
|
NV_PFAULT_CLIENT_GPC_T1_18 = 0x00000037
|
|
NV_PFAULT_CLIENT_GPC_T1_19 = 0x00000038
|
|
NV_PFAULT_CLIENT_GPC_PE_10 = 0x00000039
|
|
NV_PFAULT_CLIENT_GPC_PE_11 = 0x0000003A
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_10 = 0x0000003B
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_11 = 0x0000003C
|
|
NV_PFAULT_CLIENT_GPC_T1_20 = 0x0000003D
|
|
NV_PFAULT_CLIENT_GPC_T1_21 = 0x0000003E
|
|
NV_PFAULT_CLIENT_GPC_T1_22 = 0x0000003F
|
|
NV_PFAULT_CLIENT_GPC_T1_23 = 0x00000040
|
|
NV_PFAULT_CLIENT_GPC_PE_12 = 0x00000041
|
|
NV_PFAULT_CLIENT_GPC_PE_13 = 0x00000042
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_12 = 0x00000043
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_13 = 0x00000044
|
|
NV_PFAULT_CLIENT_GPC_T1_24 = 0x00000045
|
|
NV_PFAULT_CLIENT_GPC_T1_25 = 0x00000046
|
|
NV_PFAULT_CLIENT_GPC_T1_26 = 0x00000047
|
|
NV_PFAULT_CLIENT_GPC_T1_27 = 0x00000048
|
|
NV_PFAULT_CLIENT_GPC_PE_14 = 0x00000049
|
|
NV_PFAULT_CLIENT_GPC_PE_15 = 0x0000004A
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_14 = 0x0000004B
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_15 = 0x0000004C
|
|
NV_PFAULT_CLIENT_GPC_T1_28 = 0x0000004D
|
|
NV_PFAULT_CLIENT_GPC_T1_29 = 0x0000004E
|
|
NV_PFAULT_CLIENT_GPC_T1_30 = 0x0000004F
|
|
NV_PFAULT_CLIENT_GPC_T1_31 = 0x00000050
|
|
NV_PFAULT_CLIENT_GPC_PE_16 = 0x00000051
|
|
NV_PFAULT_CLIENT_GPC_PE_17 = 0x00000052
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_16 = 0x00000053
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_17 = 0x00000054
|
|
NV_PFAULT_CLIENT_GPC_T1_32 = 0x00000055
|
|
NV_PFAULT_CLIENT_GPC_T1_33 = 0x00000056
|
|
NV_PFAULT_CLIENT_GPC_T1_34 = 0x00000057
|
|
NV_PFAULT_CLIENT_GPC_T1_35 = 0x00000058
|
|
NV_PFAULT_CLIENT_GPC_PE_18 = 0x00000059
|
|
NV_PFAULT_CLIENT_GPC_PE_19 = 0x0000005A
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_18 = 0x0000005B
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_19 = 0x0000005C
|
|
NV_PFAULT_CLIENT_GPC_T1_36 = 0x0000005D
|
|
NV_PFAULT_CLIENT_GPC_T1_37 = 0x0000005E
|
|
NV_PFAULT_CLIENT_GPC_T1_38 = 0x0000005F
|
|
NV_PFAULT_CLIENT_GPC_T1_39 = 0x00000060
|
|
NV_PFAULT_CLIENT_GPC_ROP_0 = 0x00000070
|
|
NV_PFAULT_CLIENT_GPC_ROP_1 = 0x00000071
|
|
NV_PFAULT_CLIENT_GPC_ROP_2 = 0x00000072
|
|
NV_PFAULT_CLIENT_GPC_ROP_3 = 0x00000073
|
|
NV_PFAULT_CLIENT_GPC_GPM = 0x00000017
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_0 = 0x00000018
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_1 = 0x00000019
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_2 = 0x0000001A
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_3 = 0x0000001B
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_4 = 0x0000001C
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_5 = 0x0000001D
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_6 = 0x0000001E
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_7 = 0x0000001F
|
|
NV_PFAULT_CLIENT_GPC_RGG_UTLB = 0x00000020
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_8 = 0x00000031
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_9 = 0x00000032
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_10 = 0x00000033
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_11 = 0x00000034
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_12 = 0x00000035
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_13 = 0x00000036
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_14 = 0x00000037
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_15 = 0x00000038
|
|
NV_PFAULT_CLIENT_HUB_VIP = 0x00000000
|
|
NV_PFAULT_CLIENT_HUB_CE0 = 0x00000001
|
|
NV_PFAULT_CLIENT_HUB_CE1 = 0x00000002
|
|
NV_PFAULT_CLIENT_HUB_DNISO = 0x00000003
|
|
NV_PFAULT_CLIENT_HUB_DISPNISO = 0x00000003
|
|
NV_PFAULT_CLIENT_HUB_FE0 = 0x00000004
|
|
NV_PFAULT_CLIENT_HUB_FE = 0x00000004
|
|
NV_PFAULT_CLIENT_HUB_FECS0 = 0x00000005
|
|
NV_PFAULT_CLIENT_HUB_FECS = 0x00000005
|
|
NV_PFAULT_CLIENT_HUB_HOST = 0x00000006
|
|
NV_PFAULT_CLIENT_HUB_HOST_CPU = 0x00000007
|
|
NV_PFAULT_CLIENT_HUB_HOST_CPU_NB = 0x00000008
|
|
NV_PFAULT_CLIENT_HUB_ISO = 0x00000009
|
|
NV_PFAULT_CLIENT_HUB_MMU = 0x0000000A
|
|
NV_PFAULT_CLIENT_HUB_NVDEC0 = 0x0000000B
|
|
NV_PFAULT_CLIENT_HUB_NVDEC = 0x0000000B
|
|
NV_PFAULT_CLIENT_HUB_NVENC1 = 0x0000000D
|
|
NV_PFAULT_CLIENT_HUB_NISO = 0x0000000E
|
|
NV_PFAULT_CLIENT_HUB_ACTRS = 0x0000000E
|
|
NV_PFAULT_CLIENT_HUB_P2P = 0x0000000F
|
|
NV_PFAULT_CLIENT_HUB_PD = 0x00000010
|
|
NV_PFAULT_CLIENT_HUB_PERF0 = 0x00000011
|
|
NV_PFAULT_CLIENT_HUB_PERF = 0x00000011
|
|
NV_PFAULT_CLIENT_HUB_PMU = 0x00000012
|
|
NV_PFAULT_CLIENT_HUB_RASTERTWOD = 0x00000013
|
|
NV_PFAULT_CLIENT_HUB_SCC = 0x00000014
|
|
NV_PFAULT_CLIENT_HUB_SCC_NB = 0x00000015
|
|
NV_PFAULT_CLIENT_HUB_SEC = 0x00000016
|
|
NV_PFAULT_CLIENT_HUB_SSYNC = 0x00000017
|
|
NV_PFAULT_CLIENT_HUB_GRCOPY = 0x00000018
|
|
NV_PFAULT_CLIENT_HUB_CE2 = 0x00000018
|
|
NV_PFAULT_CLIENT_HUB_XV = 0x00000019
|
|
NV_PFAULT_CLIENT_HUB_MMU_NB = 0x0000001A
|
|
NV_PFAULT_CLIENT_HUB_NVENC0 = 0x0000001B
|
|
NV_PFAULT_CLIENT_HUB_NVENC = 0x0000001B
|
|
NV_PFAULT_CLIENT_HUB_DFALCON = 0x0000001C
|
|
NV_PFAULT_CLIENT_HUB_SKED0 = 0x0000001D
|
|
NV_PFAULT_CLIENT_HUB_SKED = 0x0000001D
|
|
NV_PFAULT_CLIENT_HUB_AFALCON = 0x0000001E
|
|
NV_PFAULT_CLIENT_HUB_DONT_CARE = 0x0000001F
|
|
NV_PFAULT_CLIENT_HUB_HSCE0 = 0x00000020
|
|
NV_PFAULT_CLIENT_HUB_HSCE1 = 0x00000021
|
|
NV_PFAULT_CLIENT_HUB_HSCE2 = 0x00000022
|
|
NV_PFAULT_CLIENT_HUB_HSCE3 = 0x00000023
|
|
NV_PFAULT_CLIENT_HUB_HSCE4 = 0x00000024
|
|
NV_PFAULT_CLIENT_HUB_HSCE5 = 0x00000025
|
|
NV_PFAULT_CLIENT_HUB_HSCE6 = 0x00000026
|
|
NV_PFAULT_CLIENT_HUB_HSCE7 = 0x00000027
|
|
NV_PFAULT_CLIENT_HUB_HSCE8 = 0x00000028
|
|
NV_PFAULT_CLIENT_HUB_HSCE9 = 0x00000029
|
|
NV_PFAULT_CLIENT_HUB_HSHUB = 0x0000002A
|
|
NV_PFAULT_CLIENT_HUB_PTP_X0 = 0x0000002B
|
|
NV_PFAULT_CLIENT_HUB_PTP_X1 = 0x0000002C
|
|
NV_PFAULT_CLIENT_HUB_PTP_X2 = 0x0000002D
|
|
NV_PFAULT_CLIENT_HUB_PTP_X3 = 0x0000002E
|
|
NV_PFAULT_CLIENT_HUB_PTP_X4 = 0x0000002F
|
|
NV_PFAULT_CLIENT_HUB_PTP_X5 = 0x00000030
|
|
NV_PFAULT_CLIENT_HUB_PTP_X6 = 0x00000031
|
|
NV_PFAULT_CLIENT_HUB_PTP_X7 = 0x00000032
|
|
NV_PFAULT_CLIENT_HUB_NVENC2 = 0x00000033
|
|
NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 = 0x00000034
|
|
NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 = 0x00000035
|
|
NV_PFAULT_CLIENT_HUB_DWBIF = 0x00000036
|
|
NV_PFAULT_CLIENT_HUB_FBFALCON = 0x00000037
|
|
NV_PFAULT_CLIENT_HUB_CE_SHIM = 0x00000038
|
|
NV_PFAULT_CLIENT_HUB_GSP = 0x00000039
|
|
NV_PFAULT_CLIENT_HUB_NVDEC1 = 0x0000003A
|
|
NV_PFAULT_CLIENT_HUB_NVDEC2 = 0x0000003B
|
|
NV_PFAULT_CLIENT_HUB_NVJPG0 = 0x0000003C
|
|
NV_PFAULT_CLIENT_HUB_NVDEC3 = 0x0000003D
|
|
NV_PFAULT_CLIENT_HUB_NVDEC4 = 0x0000003E
|
|
NV_PFAULT_CLIENT_HUB_OFA0 = 0x0000003F
|
|
NV_PFAULT_CLIENT_HUB_HSCE10 = 0x00000040
|
|
NV_PFAULT_CLIENT_HUB_HSCE11 = 0x00000041
|
|
NV_PFAULT_CLIENT_HUB_HSCE12 = 0x00000042
|
|
NV_PFAULT_CLIENT_HUB_HSCE13 = 0x00000043
|
|
NV_PFAULT_CLIENT_HUB_HSCE14 = 0x00000044
|
|
NV_PFAULT_CLIENT_HUB_HSCE15 = 0x00000045
|
|
NV_PFAULT_CLIENT_HUB_PTP_X8 = 0x00000046
|
|
NV_PFAULT_CLIENT_HUB_PTP_X9 = 0x00000047
|
|
NV_PFAULT_CLIENT_HUB_PTP_X10 = 0x00000048
|
|
NV_PFAULT_CLIENT_HUB_PTP_X11 = 0x00000049
|
|
NV_PFAULT_CLIENT_HUB_PTP_X12 = 0x0000004A
|
|
NV_PFAULT_CLIENT_HUB_PTP_X13 = 0x0000004B
|
|
NV_PFAULT_CLIENT_HUB_PTP_X14 = 0x0000004C
|
|
NV_PFAULT_CLIENT_HUB_PTP_X15 = 0x0000004D
|
|
NV_PFAULT_CLIENT_HUB_FE1 = 0x0000004E
|
|
NV_PFAULT_CLIENT_HUB_FE2 = 0x0000004F
|
|
NV_PFAULT_CLIENT_HUB_FE3 = 0x00000050
|
|
NV_PFAULT_CLIENT_HUB_FE4 = 0x00000051
|
|
NV_PFAULT_CLIENT_HUB_FE5 = 0x00000052
|
|
NV_PFAULT_CLIENT_HUB_FE6 = 0x00000053
|
|
NV_PFAULT_CLIENT_HUB_FE7 = 0x00000054
|
|
NV_PFAULT_CLIENT_HUB_FECS1 = 0x00000055
|
|
NV_PFAULT_CLIENT_HUB_FECS2 = 0x00000056
|
|
NV_PFAULT_CLIENT_HUB_FECS3 = 0x00000057
|
|
NV_PFAULT_CLIENT_HUB_FECS4 = 0x00000058
|
|
NV_PFAULT_CLIENT_HUB_FECS5 = 0x00000059
|
|
NV_PFAULT_CLIENT_HUB_FECS6 = 0x0000005A
|
|
NV_PFAULT_CLIENT_HUB_FECS7 = 0x0000005B
|
|
NV_PFAULT_CLIENT_HUB_SKED1 = 0x0000005C
|
|
NV_PFAULT_CLIENT_HUB_SKED2 = 0x0000005D
|
|
NV_PFAULT_CLIENT_HUB_SKED3 = 0x0000005E
|
|
NV_PFAULT_CLIENT_HUB_SKED4 = 0x0000005F
|
|
NV_PFAULT_CLIENT_HUB_SKED5 = 0x00000060
|
|
NV_PFAULT_CLIENT_HUB_SKED6 = 0x00000061
|
|
NV_PFAULT_CLIENT_HUB_SKED7 = 0x00000062
|
|
NV_PFAULT_CLIENT_HUB_ESC = 0x00000063
|
|
NV_PFAULT_ACCESS_TYPE = (19, 16)
|
|
NV_PFAULT_ACCESS_TYPE_READ = 0x00000000
|
|
NV_PFAULT_ACCESS_TYPE_WRITE = 0x00000001
|
|
NV_PFAULT_ACCESS_TYPE_ATOMIC = 0x00000002
|
|
NV_PFAULT_ACCESS_TYPE_PREFETCH = 0x00000003
|
|
NV_PFAULT_ACCESS_TYPE_VIRT_READ = 0x00000000
|
|
NV_PFAULT_ACCESS_TYPE_VIRT_WRITE = 0x00000001
|
|
NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC = 0x00000002
|
|
NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 0x00000002
|
|
NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH = 0x00000003
|
|
NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 0x00000004
|
|
NV_PFAULT_ACCESS_TYPE_PHYS_READ = 0x00000008
|
|
NV_PFAULT_ACCESS_TYPE_PHYS_WRITE = 0x00000009
|
|
NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC = 0x0000000a
|
|
NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH = 0x0000000b
|
|
NV_PFAULT_MMU_CLIENT_TYPE = (20, 20)
|
|
NV_PFAULT_MMU_CLIENT_TYPE_GPC = 0x00000000
|
|
NV_PFAULT_MMU_CLIENT_TYPE_HUB = 0x00000001
|
|
NV_PFAULT_GPC_ID = (28, 24)
|
|
NV_PFAULT_PROTECTED_MODE = (29, 29)
|
|
NV_PFAULT_REPLAYABLE_FAULT_EN = (30, 30)
|
|
NV_PFAULT_VALID = (31, 31)
|
|
NV_ESC_RM_ALLOC_MEMORY = 0x27
|
|
NV_ESC_RM_ALLOC_OBJECT = 0x28
|
|
NV_ESC_RM_FREE = 0x29
|
|
NV_ESC_RM_CONTROL = 0x2A
|
|
NV_ESC_RM_ALLOC = 0x2B
|
|
NV_ESC_RM_DUP_OBJECT = 0x34
|
|
NV_ESC_RM_SHARE = 0x35
|
|
NV_ESC_RM_I2C_ACCESS = 0x39
|
|
NV_ESC_RM_IDLE_CHANNELS = 0x41
|
|
NV_ESC_RM_VID_HEAP_CONTROL = 0x4A
|
|
NV_ESC_RM_ACCESS_REGISTRY = 0x4D
|
|
NV_ESC_RM_MAP_MEMORY = 0x4E
|
|
NV_ESC_RM_UNMAP_MEMORY = 0x4F
|
|
NV_ESC_RM_GET_EVENT_DATA = 0x52
|
|
NV_ESC_RM_ALLOC_CONTEXT_DMA2 = 0x54
|
|
NV_ESC_RM_ADD_VBLANK_CALLBACK = 0x56
|
|
NV_ESC_RM_MAP_MEMORY_DMA = 0x57
|
|
NV_ESC_RM_UNMAP_MEMORY_DMA = 0x58
|
|
NV_ESC_RM_BIND_CONTEXT_DMA = 0x59
|
|
NV_ESC_RM_EXPORT_OBJECT_TO_FD = 0x5C
|
|
NV_ESC_RM_IMPORT_OBJECT_FROM_FD = 0x5D
|
|
NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO = 0x5E
|
|
NV_ESC_RM_LOCKLESS_DIAGNOSTIC = 0x5F
|
|
NV_RM_API_VERSION_STRING_LENGTH = 64
|
|
NV_RM_API_VERSION_CMD_STRICT = 0
|
|
NV_RM_API_VERSION_CMD_RELAXED = '1'
|
|
NV_RM_API_VERSION_CMD_QUERY = '2'
|
|
NV_RM_API_VERSION_REPLY_UNRECOGNIZED = 0
|
|
NV_RM_API_VERSION_REPLY_RECOGNIZED = 1
|
|
NV_DMABUF_EXPORT_MAX_HANDLES = 128
|
|
NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT = 0
|
|
NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE = 1
|
|
NV_IOCTL_MAGIC = 'F'
|
|
NV_IOCTL_BASE = 200
|
|
NV_ESC_CARD_INFO = (NV_IOCTL_BASE + 0)
|
|
NV_ESC_REGISTER_FD = (NV_IOCTL_BASE + 1)
|
|
NV_ESC_ALLOC_OS_EVENT = (NV_IOCTL_BASE + 6)
|
|
NV_ESC_FREE_OS_EVENT = (NV_IOCTL_BASE + 7)
|
|
NV_ESC_STATUS_CODE = (NV_IOCTL_BASE + 9)
|
|
NV_ESC_CHECK_VERSION_STR = (NV_IOCTL_BASE + 10)
|
|
NV_ESC_IOCTL_XFER_CMD = (NV_IOCTL_BASE + 11)
|
|
NV_ESC_ATTACH_GPUS_TO_FD = (NV_IOCTL_BASE + 12)
|
|
NV_ESC_QUERY_DEVICE_INTR = (NV_IOCTL_BASE + 13)
|
|
NV_ESC_SYS_PARAMS = (NV_IOCTL_BASE + 14)
|
|
NV_ESC_EXPORT_TO_DMABUF_FD = (NV_IOCTL_BASE + 17)
|
|
NV_ESC_WAIT_OPEN_COMPLETE = (NV_IOCTL_BASE + 18)
|
|
__aligned = lambda n: __attribute__((aligned(n))) # type: ignore
|
|
NV_ESC_NUMA_INFO = (NV_IOCTL_BASE + 15)
|
|
NV_ESC_SET_NUMA_STATUS = (NV_IOCTL_BASE + 16)
|
|
NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES = 64
|
|
NV_IOCTL_NUMA_STATUS_DISABLED = 0
|
|
NV_IOCTL_NUMA_STATUS_OFFLINE = 1
|
|
NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS = 2
|
|
NV_IOCTL_NUMA_STATUS_ONLINE = 3
|
|
NV_IOCTL_NUMA_STATUS_ONLINE_FAILED = 4
|
|
NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS = 5
|
|
NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED = 6
|
|
NVOS04_FLAGS_CHANNEL_TYPE = (1, 0)
|
|
NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL = 0x00000000
|
|
NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL = 0x00000001
|
|
NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL = 0x00000002
|
|
NVOS04_FLAGS_VPR = (2, 2)
|
|
NVOS04_FLAGS_VPR_FALSE = 0x00000000
|
|
NVOS04_FLAGS_VPR_TRUE = 0x00000001
|
|
NVOS04_FLAGS_CC_SECURE = (2, 2)
|
|
NVOS04_FLAGS_CC_SECURE_FALSE = 0x00000000
|
|
NVOS04_FLAGS_CC_SECURE_TRUE = 0x00000001
|
|
NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING = (3, 3)
|
|
NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE = 0x00000000
|
|
NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE = 0x00000001
|
|
NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE = (4, 4)
|
|
NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT = 0x00000000
|
|
NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE = 0x00000001
|
|
NVOS04_FLAGS_PRIVILEGED_CHANNEL = (5, 5)
|
|
NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE = 0x00000000
|
|
NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE = 0x00000001
|
|
NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING = (6, 6)
|
|
NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE = 0x00000000
|
|
NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE = 0x00000001
|
|
NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE = (7, 7)
|
|
NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE = 0x00000000
|
|
NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE = 0x00000001
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE = (10, 8)
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED = (11, 11)
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE = 0x00000000
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE = 0x00000001
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE = (20, 12)
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED = (21, 21)
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE = 0x00000000
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE = 0x00000001
|
|
NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV = (22, 22)
|
|
NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE = 0x00000000
|
|
NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE = 0x00000001
|
|
NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER = (23, 23)
|
|
NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE = 0x00000000
|
|
NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE = 0x00000001
|
|
NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO = (24, 24)
|
|
NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE = 0x00000000
|
|
NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE = 0x00000001
|
|
NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL = (25, 25)
|
|
NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE = 0x00000000
|
|
NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE = 0x00000001
|
|
NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT = (26, 26)
|
|
NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE = 0x00000000
|
|
NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE = 0x00000001
|
|
NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT = (27, 27)
|
|
NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE = 0x00000000
|
|
NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE = 0x00000001
|
|
NVOS04_FLAGS_GROUP_CHANNEL_THREAD = (29, 28)
|
|
NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT = 0x00000000
|
|
NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE = 0x00000001
|
|
NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO = 0x00000002
|
|
NVOS04_FLAGS_MAP_CHANNEL = (30, 30)
|
|
NVOS04_FLAGS_MAP_CHANNEL_FALSE = 0x00000000
|
|
NVOS04_FLAGS_MAP_CHANNEL_TRUE = 0x00000001
|
|
NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC = (31, 31)
|
|
NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE = 0x00000000
|
|
NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE = 0x00000001
|
|
CC_CHAN_ALLOC_IV_SIZE_DWORD = 3
|
|
CC_CHAN_ALLOC_NONCE_SIZE_DWORD = 8
|
|
NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID = (0x906f)
|
|
FILE_DEVICE_NV = 0x00008000
|
|
NV_IOCTL_FCT_BASE = 0x00000800
|
|
NVOS_MAX_SUBDEVICES = 8
|
|
UNIFIED_NV_STATUS = 1
|
|
NVOS_STATUS = NV_STATUS
|
|
NVOS_STATUS_SUCCESS = NV_OK
|
|
NVOS_STATUS_ERROR_CARD_NOT_PRESENT = NV_ERR_CARD_NOT_PRESENT
|
|
NVOS_STATUS_ERROR_DUAL_LINK_INUSE = NV_ERR_DUAL_LINK_INUSE
|
|
NVOS_STATUS_ERROR_GENERIC = NV_ERR_GENERIC
|
|
NVOS_STATUS_ERROR_GPU_NOT_FULL_POWER = NV_ERR_GPU_NOT_FULL_POWER
|
|
NVOS_STATUS_ERROR_ILLEGAL_ACTION = NV_ERR_ILLEGAL_ACTION
|
|
NVOS_STATUS_ERROR_IN_USE = NV_ERR_STATE_IN_USE
|
|
NVOS_STATUS_ERROR_INSUFFICIENT_RESOURCES = NV_ERR_INSUFFICIENT_RESOURCES
|
|
NVOS_STATUS_ERROR_INSUFFICIENT_ZBC_ENTRY = NV_ERR_INSUFFICIENT_ZBC_ENTRY
|
|
NVOS_STATUS_ERROR_INVALID_ACCESS_TYPE = NV_ERR_INVALID_ACCESS_TYPE
|
|
NVOS_STATUS_ERROR_INVALID_ARGUMENT = NV_ERR_INVALID_ARGUMENT
|
|
NVOS_STATUS_ERROR_INVALID_BASE = NV_ERR_INVALID_BASE
|
|
NVOS_STATUS_ERROR_INVALID_CHANNEL = NV_ERR_INVALID_CHANNEL
|
|
NVOS_STATUS_ERROR_INVALID_CLASS = NV_ERR_INVALID_CLASS
|
|
NVOS_STATUS_ERROR_INVALID_CLIENT = NV_ERR_INVALID_CLIENT
|
|
NVOS_STATUS_ERROR_INVALID_COMMAND = NV_ERR_INVALID_COMMAND
|
|
NVOS_STATUS_ERROR_INVALID_DATA = NV_ERR_INVALID_DATA
|
|
NVOS_STATUS_ERROR_INVALID_DEVICE = NV_ERR_INVALID_DEVICE
|
|
NVOS_STATUS_ERROR_INVALID_DMA_SPECIFIER = NV_ERR_INVALID_DMA_SPECIFIER
|
|
NVOS_STATUS_ERROR_INVALID_EVENT = NV_ERR_INVALID_EVENT
|
|
NVOS_STATUS_ERROR_INVALID_FLAGS = NV_ERR_INVALID_FLAGS
|
|
NVOS_STATUS_ERROR_INVALID_FUNCTION = NV_ERR_INVALID_FUNCTION
|
|
NVOS_STATUS_ERROR_INVALID_HEAP = NV_ERR_INVALID_HEAP
|
|
NVOS_STATUS_ERROR_INVALID_INDEX = NV_ERR_INVALID_INDEX
|
|
NVOS_STATUS_ERROR_INVALID_LIMIT = NV_ERR_INVALID_LIMIT
|
|
NVOS_STATUS_ERROR_INVALID_METHOD = NV_ERR_INVALID_METHOD
|
|
NVOS_STATUS_ERROR_INVALID_OBJECT_BUFFER = NV_ERR_BUFFER_TOO_SMALL
|
|
NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR = NV_ERR_INVALID_OBJECT
|
|
NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE = NV_ERR_INVALID_OBJECT_HANDLE
|
|
NVOS_STATUS_ERROR_INVALID_OBJECT_NEW = NV_ERR_INVALID_OBJECT_NEW
|
|
NVOS_STATUS_ERROR_INVALID_OBJECT_OLD = NV_ERR_INVALID_OBJECT_OLD
|
|
NVOS_STATUS_ERROR_INVALID_OBJECT_PARENT = NV_ERR_INVALID_OBJECT_PARENT
|
|
NVOS_STATUS_ERROR_INVALID_OFFSET = NV_ERR_INVALID_OFFSET
|
|
NVOS_STATUS_ERROR_INVALID_OWNER = NV_ERR_INVALID_OWNER
|
|
NVOS_STATUS_ERROR_INVALID_PARAM_STRUCT = NV_ERR_INVALID_PARAM_STRUCT
|
|
NVOS_STATUS_ERROR_INVALID_PARAMETER = NV_ERR_INVALID_PARAMETER
|
|
NVOS_STATUS_ERROR_INVALID_POINTER = NV_ERR_INVALID_POINTER
|
|
NVOS_STATUS_ERROR_INVALID_REGISTRY_KEY = NV_ERR_INVALID_REGISTRY_KEY
|
|
NVOS_STATUS_ERROR_INVALID_STATE = NV_ERR_INVALID_STATE
|
|
NVOS_STATUS_ERROR_INVALID_STRING_LENGTH = NV_ERR_INVALID_STRING_LENGTH
|
|
NVOS_STATUS_ERROR_INVALID_XLATE = NV_ERR_INVALID_XLATE
|
|
NVOS_STATUS_ERROR_IRQ_NOT_FIRING = NV_ERR_IRQ_NOT_FIRING
|
|
NVOS_STATUS_ERROR_MULTIPLE_MEMORY_TYPES = NV_ERR_MULTIPLE_MEMORY_TYPES
|
|
NVOS_STATUS_ERROR_NOT_SUPPORTED = NV_ERR_NOT_SUPPORTED
|
|
NVOS_STATUS_ERROR_OPERATING_SYSTEM = NV_ERR_OPERATING_SYSTEM
|
|
NVOS_STATUS_ERROR_LIB_RM_VERSION_MISMATCH = NV_ERR_LIB_RM_VERSION_MISMATCH
|
|
NVOS_STATUS_ERROR_PROTECTION_FAULT = NV_ERR_PROTECTION_FAULT
|
|
NVOS_STATUS_ERROR_TIMEOUT = NV_ERR_TIMEOUT
|
|
NVOS_STATUS_ERROR_TOO_MANY_PRIMARIES = NV_ERR_TOO_MANY_PRIMARIES
|
|
NVOS_STATUS_ERROR_IRQ_EDGE_TRIGGERED = NV_ERR_IRQ_EDGE_TRIGGERED
|
|
NVOS_STATUS_ERROR_INVALID_OPERATION = NV_ERR_INVALID_OPERATION
|
|
NVOS_STATUS_ERROR_NOT_COMPATIBLE = NV_ERR_NOT_COMPATIBLE
|
|
NVOS_STATUS_ERROR_MORE_PROCESSING_REQUIRED = NV_WARN_MORE_PROCESSING_REQUIRED
|
|
NVOS_STATUS_ERROR_INSUFFICIENT_PERMISSIONS = NV_ERR_INSUFFICIENT_PERMISSIONS
|
|
NVOS_STATUS_ERROR_TIMEOUT_RETRY = NV_ERR_TIMEOUT_RETRY
|
|
NVOS_STATUS_ERROR_NOT_READY = NV_ERR_NOT_READY
|
|
NVOS_STATUS_ERROR_GPU_IS_LOST = NV_ERR_GPU_IS_LOST
|
|
NVOS_STATUS_ERROR_IN_FULLCHIP_RESET = NV_ERR_GPU_IN_FULLCHIP_RESET
|
|
NVOS_STATUS_ERROR_INVALID_LOCK_STATE = NV_ERR_INVALID_LOCK_STATE
|
|
NVOS_STATUS_ERROR_INVALID_ADDRESS = NV_ERR_INVALID_ADDRESS
|
|
NVOS_STATUS_ERROR_INVALID_IRQ_LEVEL = NV_ERR_INVALID_IRQ_LEVEL
|
|
NVOS_STATUS_ERROR_MEMORY_TRAINING_FAILED = NV_ERR_MEMORY_TRAINING_FAILED
|
|
NVOS_STATUS_ERROR_BUSY_RETRY = NV_ERR_BUSY_RETRY
|
|
NVOS_STATUS_ERROR_INSUFFICIENT_POWER = NV_ERR_INSUFFICIENT_POWER
|
|
NVOS_STATUS_ERROR_OBJECT_NOT_FOUND = NV_ERR_OBJECT_NOT_FOUND
|
|
NVOS_STATUS_ERROR_RESOURCE_LOST = NV_ERR_RESOURCE_LOST
|
|
NVOS_STATUS_ERROR_BUFFER_TOO_SMALL = NV_ERR_BUFFER_TOO_SMALL
|
|
NVOS_STATUS_ERROR_RESET_REQUIRED = NV_ERR_RESET_REQUIRED
|
|
NVOS_STATUS_ERROR_INVALID_REQUEST = NV_ERR_INVALID_REQUEST
|
|
NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION = NV_ERR_PRIV_SEC_VIOLATION
|
|
NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE = NV_ERR_GPU_IN_DEBUG_MODE
|
|
NVOS_STATUS_ERROR_ALREADY_SIGNALLED = NV_ERR_ALREADY_SIGNALLED
|
|
NV01_FREE = (0x00000000)
|
|
NV01_ROOT = (0x0)
|
|
NV01_ROOT_NON_PRIV = (0x00000001)
|
|
NV01_ROOT_CLIENT = (0x00000041)
|
|
NV01_ALLOC_MEMORY = (0x00000002)
|
|
NVOS02_FLAGS_PHYSICALITY = (7, 4)
|
|
NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS = (0x00000000)
|
|
NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS = (0x00000001)
|
|
NVOS02_FLAGS_LOCATION = (11, 8)
|
|
NVOS02_FLAGS_LOCATION_PCI = (0x00000000)
|
|
NVOS02_FLAGS_LOCATION_VIDMEM = (0x00000002)
|
|
NVOS02_FLAGS_COHERENCY = (15, 12)
|
|
NVOS02_FLAGS_COHERENCY_UNCACHED = (0x00000000)
|
|
NVOS02_FLAGS_COHERENCY_CACHED = (0x00000001)
|
|
NVOS02_FLAGS_COHERENCY_WRITE_COMBINE = (0x00000002)
|
|
NVOS02_FLAGS_COHERENCY_WRITE_THROUGH = (0x00000003)
|
|
NVOS02_FLAGS_COHERENCY_WRITE_PROTECT = (0x00000004)
|
|
NVOS02_FLAGS_COHERENCY_WRITE_BACK = (0x00000005)
|
|
NVOS02_FLAGS_ALLOC = (17, 16)
|
|
NVOS02_FLAGS_ALLOC_NONE = (0x00000001)
|
|
NVOS02_FLAGS_GPU_CACHEABLE = (18, 18)
|
|
NVOS02_FLAGS_GPU_CACHEABLE_NO = (0x00000000)
|
|
NVOS02_FLAGS_GPU_CACHEABLE_YES = (0x00000001)
|
|
NVOS02_FLAGS_KERNEL_MAPPING = (19, 19)
|
|
NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP = (0x00000000)
|
|
NVOS02_FLAGS_KERNEL_MAPPING_MAP = (0x00000001)
|
|
NVOS02_FLAGS_ALLOC_NISO_DISPLAY = (20, 20)
|
|
NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO = (0x00000000)
|
|
NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES = (0x00000001)
|
|
NVOS02_FLAGS_ALLOC_USER_READ_ONLY = (21, 21)
|
|
NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO = (0x00000000)
|
|
NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES = (0x00000001)
|
|
NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY = (22, 22)
|
|
NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO = (0x00000000)
|
|
NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES = (0x00000001)
|
|
NVOS02_FLAGS_PEER_MAP_OVERRIDE = (23, 23)
|
|
NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT = (0x00000000)
|
|
NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED = (0x00000001)
|
|
NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT = (24, 24)
|
|
NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE = (0x00000001)
|
|
NVOS02_FLAGS_MEMORY_PROTECTION = (26, 25)
|
|
NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT = (0x00000000)
|
|
NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED = (0x00000001)
|
|
NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED = (0x00000002)
|
|
NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM = (27, 27)
|
|
NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_FALSE = (0x00000000)
|
|
NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_TRUE = (0x00000001)
|
|
NVOS02_FLAGS_MAPPING = (31, 30)
|
|
NVOS02_FLAGS_MAPPING_DEFAULT = (0x00000000)
|
|
NVOS02_FLAGS_MAPPING_NO_MAP = (0x00000001)
|
|
NVOS02_FLAGS_MAPPING_NEVER_MAP = (0x00000002)
|
|
NVOS03_FLAGS_ACCESS = (1, 0)
|
|
NVOS03_FLAGS_ACCESS_READ_WRITE = (0x00000000)
|
|
NVOS03_FLAGS_ACCESS_READ_ONLY = (0x00000001)
|
|
NVOS03_FLAGS_ACCESS_WRITE_ONLY = (0x00000002)
|
|
NVOS03_FLAGS_PREALLOCATE = (2, 2)
|
|
NVOS03_FLAGS_PREALLOCATE_DISABLE = (0x00000000)
|
|
NVOS03_FLAGS_PREALLOCATE_ENABLE = (0x00000001)
|
|
NVOS03_FLAGS_GPU_MAPPABLE = (15, 15)
|
|
NVOS03_FLAGS_GPU_MAPPABLE_DISABLE = (0x00000000)
|
|
NVOS03_FLAGS_GPU_MAPPABLE_ENABLE = (0x00000001)
|
|
NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE = (16, 16)
|
|
NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_FALSE = (0x00000000)
|
|
NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_TRUE = (0x00000001)
|
|
NVOS03_FLAGS_PTE_KIND = (17, 16)
|
|
NVOS03_FLAGS_PTE_KIND_NONE = (0x00000000)
|
|
NVOS03_FLAGS_PTE_KIND_BL = (0x00000001)
|
|
NVOS03_FLAGS_PTE_KIND_PITCH = (0x00000002)
|
|
NVOS03_FLAGS_TYPE = (23, 20)
|
|
NVOS03_FLAGS_TYPE_NOTIFIER = (0x00000001)
|
|
NVOS03_FLAGS_MAPPING = (20, 20)
|
|
NVOS03_FLAGS_MAPPING_NONE = (0x00000000)
|
|
NVOS03_FLAGS_MAPPING_KERNEL = (0x00000001)
|
|
NVOS03_FLAGS_CACHE_SNOOP = (28, 28)
|
|
NVOS03_FLAGS_CACHE_SNOOP_ENABLE = (0x00000000)
|
|
NVOS03_FLAGS_CACHE_SNOOP_DISABLE = (0x00000001)
|
|
NVOS03_FLAGS_HASH_TABLE = (29, 29)
|
|
NVOS03_FLAGS_HASH_TABLE_ENABLE = (0x00000000)
|
|
NVOS03_FLAGS_HASH_TABLE_DISABLE = (0x00000001)
|
|
NV01_ALLOC_OBJECT = (0x00000005)
|
|
NV01_EVENT_KERNEL_CALLBACK = (0x00000078)
|
|
NV01_EVENT_OS_EVENT = (0x00000079)
|
|
NV01_EVENT_WIN32_EVENT = NV01_EVENT_OS_EVENT
|
|
NV01_EVENT_KERNEL_CALLBACK_EX = (0x0000007E)
|
|
NV01_EVENT_BROADCAST = (0x80000000)
|
|
NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION = (0x40000000)
|
|
NV01_EVENT_SUBDEVICE_SPECIFIC = (0x20000000)
|
|
NV01_EVENT_WITHOUT_EVENT_DATA = (0x10000000)
|
|
NV01_EVENT_NONSTALL_INTR = (0x08000000)
|
|
NV01_EVENT_CLIENT_RM = (0x04000000)
|
|
NV04_I2C_ACCESS = (0x00000013)
|
|
NVOS_I2C_ACCESS_MAX_BUFFER_SIZE = 2048
|
|
NVOS20_COMMAND_unused0001 = 0x0001
|
|
NVOS20_COMMAND_unused0002 = 0x0002
|
|
NVOS20_COMMAND_STRING_PRINT = 0x0003
|
|
NV04_ALLOC = (0x00000015)
|
|
NVOS64_FLAGS_NONE = (0x00000000)
|
|
NVOS64_FLAGS_FINN_SERIALIZED = (0x00000001)
|
|
NVOS65_PARAMETERS_VERSION_MAGIC = 0x77FEF81E
|
|
NV04_IDLE_CHANNELS = (0x0000001E)
|
|
NVOS30_FLAGS_BEHAVIOR = (3, 0)
|
|
NVOS30_FLAGS_BEHAVIOR_SPIN = (0x00000000)
|
|
NVOS30_FLAGS_BEHAVIOR_SLEEP = (0x00000001)
|
|
NVOS30_FLAGS_BEHAVIOR_QUERY = (0x00000002)
|
|
NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK = (0x00000003)
|
|
NVOS30_FLAGS_CHANNEL = (7, 4)
|
|
NVOS30_FLAGS_CHANNEL_LIST = (0x00000000)
|
|
NVOS30_FLAGS_CHANNEL_SINGLE = (0x00000001)
|
|
NVOS30_FLAGS_IDLE = (30, 8)
|
|
NVOS30_FLAGS_IDLE_PUSH_BUFFER = (0x00000001)
|
|
NVOS30_FLAGS_IDLE_CACHE1 = (0x00000002)
|
|
NVOS30_FLAGS_IDLE_GRAPHICS = (0x00000004)
|
|
NVOS30_FLAGS_IDLE_MPEG = (0x00000008)
|
|
NVOS30_FLAGS_IDLE_MOTION_ESTIMATION = (0x00000010)
|
|
NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR = (0x00000020)
|
|
NVOS30_FLAGS_IDLE_MSPDEC = (0x00000020)
|
|
NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR = (0x00000040)
|
|
NVOS30_FLAGS_IDLE_MSVLD = (0x00000040)
|
|
NVOS30_FLAGS_IDLE_NVDEC0 = NVOS30_FLAGS_IDLE_MSVLD
|
|
NVOS30_FLAGS_IDLE_CIPHER_DMA = (0x00000080)
|
|
NVOS30_FLAGS_IDLE_SEC = (0x00000080)
|
|
NVOS30_FLAGS_IDLE_CALLBACKS = (0x00000100)
|
|
NVOS30_FLAGS_IDLE_MSPPP = (0x00000200)
|
|
NVOS30_FLAGS_IDLE_CE0 = (0x00000400)
|
|
NVOS30_FLAGS_IDLE_CE1 = (0x00000800)
|
|
NVOS30_FLAGS_IDLE_CE2 = (0x00001000)
|
|
NVOS30_FLAGS_IDLE_CE3 = (0x00002000)
|
|
NVOS30_FLAGS_IDLE_CE4 = (0x00004000)
|
|
NVOS30_FLAGS_IDLE_CE5 = (0x00008000)
|
|
NVOS30_FLAGS_IDLE_VIC = (0x00010000)
|
|
NVOS30_FLAGS_IDLE_MSENC = (0x00020000)
|
|
NVOS30_FLAGS_IDLE_NVENC0 = NVOS30_FLAGS_IDLE_MSENC
|
|
NVOS30_FLAGS_IDLE_NVENC1 = (0x00040000)
|
|
NVOS30_FLAGS_IDLE_NVENC2 = (0x00080000)
|
|
NVOS30_FLAGS_IDLE_NVJPG = (0x00100000)
|
|
NVOS30_FLAGS_IDLE_NVDEC1 = (0x00200000)
|
|
NVOS30_FLAGS_IDLE_NVDEC2 = (0x00400000)
|
|
NVOS30_FLAGS_IDLE_ACTIVECHANNELS = (0x00800000)
|
|
NVOS30_FLAGS_IDLE_ALL_ENGINES = (NVOS30_FLAGS_IDLE_GRAPHICS | NVOS30_FLAGS_IDLE_MPEG | NVOS30_FLAGS_IDLE_MOTION_ESTIMATION | NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR | NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR | NVOS30_FLAGS_IDLE_CIPHER_DMA | NVOS30_FLAGS_IDLE_MSPDEC | NVOS30_FLAGS_IDLE_NVDEC0 | NVOS30_FLAGS_IDLE_SEC | NVOS30_FLAGS_IDLE_MSPPP | NVOS30_FLAGS_IDLE_CE0 | NVOS30_FLAGS_IDLE_CE1 | NVOS30_FLAGS_IDLE_CE2 | NVOS30_FLAGS_IDLE_CE3 | NVOS30_FLAGS_IDLE_CE4 | NVOS30_FLAGS_IDLE_CE5 | NVOS30_FLAGS_IDLE_NVENC0 | NVOS30_FLAGS_IDLE_NVENC1 | NVOS30_FLAGS_IDLE_NVENC2 | NVOS30_FLAGS_IDLE_VIC | NVOS30_FLAGS_IDLE_NVJPG | NVOS30_FLAGS_IDLE_NVDEC1 | NVOS30_FLAGS_IDLE_NVDEC2)
|
|
NVOS30_FLAGS_WAIT_FOR_ELPG_ON = (31, 31)
|
|
NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO = (0x00000000)
|
|
NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES = (0x00000001)
|
|
NV04_VID_HEAP_CONTROL = (0x00000020)
|
|
NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS = 0
|
|
NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY = 1
|
|
NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY = 2
|
|
NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR = 3
|
|
NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE = 4
|
|
NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR = 5
|
|
NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR = 6
|
|
NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS = 7
|
|
NVOS32_FUNCTION_ALLOC_SIZE = 2
|
|
NVOS32_FUNCTION_FREE = 3
|
|
NVOS32_FUNCTION_INFO = 5
|
|
NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT = 6
|
|
NVOS32_FUNCTION_ALLOC_SIZE_RANGE = 14
|
|
NVOS32_FUNCTION_REACQUIRE_COMPR = 15
|
|
NVOS32_FUNCTION_RELEASE_COMPR = 16
|
|
NVOS32_FUNCTION_GET_MEM_ALIGNMENT = 18
|
|
NVOS32_FUNCTION_HW_ALLOC = 19
|
|
NVOS32_FUNCTION_HW_FREE = 20
|
|
NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR = 27
|
|
NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP = 0
|
|
NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR = 1
|
|
NVOS32_DELETE_RESOURCES_ALL = 0
|
|
NVOS32_TYPE_IMAGE = 0
|
|
NVOS32_TYPE_DEPTH = 1
|
|
NVOS32_TYPE_TEXTURE = 2
|
|
NVOS32_TYPE_VIDEO = 3
|
|
NVOS32_TYPE_FONT = 4
|
|
NVOS32_TYPE_CURSOR = 5
|
|
NVOS32_TYPE_DMA = 6
|
|
NVOS32_TYPE_INSTANCE = 7
|
|
NVOS32_TYPE_PRIMARY = 8
|
|
NVOS32_TYPE_ZCULL = 9
|
|
NVOS32_TYPE_UNUSED = 10
|
|
NVOS32_TYPE_SHADER_PROGRAM = 11
|
|
NVOS32_TYPE_OWNER_RM = 12
|
|
NVOS32_TYPE_NOTIFIER = 13
|
|
NVOS32_TYPE_RESERVED = 14
|
|
NVOS32_TYPE_PMA = 15
|
|
NVOS32_TYPE_STENCIL = 16
|
|
NVOS32_TYPE_SYNCPOINT = 17
|
|
NVOS32_NUM_MEM_TYPES = 18
|
|
NVOS32_ATTR_NONE = 0x00000000
|
|
NVOS32_ATTR_DEPTH = (2, 0)
|
|
NVOS32_ATTR_DEPTH_UNKNOWN = 0x00000000
|
|
NVOS32_ATTR_DEPTH_8 = 0x00000001
|
|
NVOS32_ATTR_DEPTH_16 = 0x00000002
|
|
NVOS32_ATTR_DEPTH_24 = 0x00000003
|
|
NVOS32_ATTR_DEPTH_32 = 0x00000004
|
|
NVOS32_ATTR_DEPTH_64 = 0x00000005
|
|
NVOS32_ATTR_DEPTH_128 = 0x00000006
|
|
NVOS32_ATTR_COMPR_COVG = (3, 3)
|
|
NVOS32_ATTR_COMPR_COVG_DEFAULT = 0x00000000
|
|
NVOS32_ATTR_COMPR_COVG_PROVIDED = 0x00000001
|
|
NVOS32_ATTR_AA_SAMPLES = (7, 4)
|
|
NVOS32_ATTR_AA_SAMPLES_1 = 0x00000000
|
|
NVOS32_ATTR_AA_SAMPLES_2 = 0x00000001
|
|
NVOS32_ATTR_AA_SAMPLES_4 = 0x00000002
|
|
NVOS32_ATTR_AA_SAMPLES_4_ROTATED = 0x00000003
|
|
NVOS32_ATTR_AA_SAMPLES_6 = 0x00000004
|
|
NVOS32_ATTR_AA_SAMPLES_8 = 0x00000005
|
|
NVOS32_ATTR_AA_SAMPLES_16 = 0x00000006
|
|
NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8 = 0x00000007
|
|
NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 = 0x00000008
|
|
NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 = 0x00000009
|
|
NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 = 0x0000000A
|
|
NVOS32_ATTR_GPU_CACHE_SNOOPABLE = (9, 8)
|
|
NVOS32_ATTR_GPU_CACHE_SNOOPABLE_MAPPING = 0x00000000
|
|
NVOS32_ATTR_GPU_CACHE_SNOOPABLE_OFF = 0x00000001
|
|
NVOS32_ATTR_GPU_CACHE_SNOOPABLE_ON = 0x00000002
|
|
NVOS32_ATTR_GPU_CACHE_SNOOPABLE_INVALID = 0x00000003
|
|
NVOS32_ATTR_ZCULL = (11, 10)
|
|
NVOS32_ATTR_ZCULL_NONE = 0x00000000
|
|
NVOS32_ATTR_ZCULL_REQUIRED = 0x00000001
|
|
NVOS32_ATTR_ZCULL_ANY = 0x00000002
|
|
NVOS32_ATTR_ZCULL_SHARED = 0x00000003
|
|
NVOS32_ATTR_COMPR = (13, 12)
|
|
NVOS32_ATTR_COMPR_NONE = 0x00000000
|
|
NVOS32_ATTR_COMPR_REQUIRED = 0x00000001
|
|
NVOS32_ATTR_COMPR_ANY = 0x00000002
|
|
NVOS32_ATTR_COMPR_PLC_REQUIRED = NVOS32_ATTR_COMPR_REQUIRED
|
|
NVOS32_ATTR_COMPR_PLC_ANY = NVOS32_ATTR_COMPR_ANY
|
|
NVOS32_ATTR_COMPR_DISABLE_PLC_ANY = 0x00000003
|
|
NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP = (14, 14)
|
|
NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_NO = 0x00000000
|
|
NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_YES = 0x00000001
|
|
NVOS32_ATTR_FORMAT = (17, 16)
|
|
NVOS32_ATTR_FORMAT_LOW_FIELD = 16
|
|
NVOS32_ATTR_FORMAT_HIGH_FIELD = 17
|
|
NVOS32_ATTR_FORMAT_PITCH = 0x00000000
|
|
NVOS32_ATTR_FORMAT_SWIZZLED = 0x00000001
|
|
NVOS32_ATTR_FORMAT_BLOCK_LINEAR = 0x00000002
|
|
NVOS32_ATTR_Z_TYPE = (18, 18)
|
|
NVOS32_ATTR_Z_TYPE_FIXED = 0x00000000
|
|
NVOS32_ATTR_Z_TYPE_FLOAT = 0x00000001
|
|
NVOS32_ATTR_ZS_PACKING = (21, 19)
|
|
NVOS32_ATTR_ZS_PACKING_S8 = 0x00000000
|
|
NVOS32_ATTR_ZS_PACKING_Z24S8 = 0x00000000
|
|
NVOS32_ATTR_ZS_PACKING_S8Z24 = 0x00000001
|
|
NVOS32_ATTR_ZS_PACKING_Z32 = 0x00000002
|
|
NVOS32_ATTR_ZS_PACKING_Z24X8 = 0x00000003
|
|
NVOS32_ATTR_ZS_PACKING_X8Z24 = 0x00000004
|
|
NVOS32_ATTR_ZS_PACKING_Z32_X24S8 = 0x00000005
|
|
NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8 = 0x00000006
|
|
NVOS32_ATTR_ZS_PACKING_Z16 = 0x00000007
|
|
NVOS32_ATTR_COLOR_PACKING = NVOS32_ATTR_ZS_PACKING
|
|
NVOS32_ATTR_COLOR_PACKING_A8R8G8B8 = 0x00000000
|
|
NVOS32_ATTR_COLOR_PACKING_X8R8G8B8 = 0x00000001
|
|
NVOS32_ATTR_PAGE_SIZE = (24, 23)
|
|
NVOS32_ATTR_PAGE_SIZE_DEFAULT = 0x00000000
|
|
NVOS32_ATTR_PAGE_SIZE_4KB = 0x00000001
|
|
NVOS32_ATTR_PAGE_SIZE_BIG = 0x00000002
|
|
NVOS32_ATTR_PAGE_SIZE_HUGE = 0x00000003
|
|
NVOS32_ATTR_LOCATION = (26, 25)
|
|
NVOS32_ATTR_LOCATION_VIDMEM = 0x00000000
|
|
NVOS32_ATTR_LOCATION_PCI = 0x00000001
|
|
NVOS32_ATTR_LOCATION_ANY = 0x00000003
|
|
NVOS32_ATTR_PHYSICALITY = (28, 27)
|
|
NVOS32_ATTR_PHYSICALITY_DEFAULT = 0x00000000
|
|
NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS = 0x00000001
|
|
NVOS32_ATTR_PHYSICALITY_CONTIGUOUS = 0x00000002
|
|
NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS = 0x00000003
|
|
NVOS32_ATTR_COHERENCY = (31, 29)
|
|
NVOS32_ATTR_COHERENCY_UNCACHED = 0x00000000
|
|
NVOS32_ATTR_COHERENCY_CACHED = 0x00000001
|
|
NVOS32_ATTR_COHERENCY_WRITE_COMBINE = 0x00000002
|
|
NVOS32_ATTR_COHERENCY_WRITE_THROUGH = 0x00000003
|
|
NVOS32_ATTR_COHERENCY_WRITE_PROTECT = 0x00000004
|
|
NVOS32_ATTR_COHERENCY_WRITE_BACK = 0x00000005
|
|
NVOS32_ATTR2_NONE = 0x00000000
|
|
NVOS32_ATTR2_ZBC = (1, 0)
|
|
NVOS32_ATTR2_ZBC_DEFAULT = 0x00000000
|
|
NVOS32_ATTR2_ZBC_PREFER_NO_ZBC = 0x00000001
|
|
NVOS32_ATTR2_ZBC_PREFER_ZBC = 0x00000002
|
|
NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC = 0x00000003
|
|
NVOS32_ATTR2_ZBC_INVALID = 0x00000003
|
|
NVOS32_ATTR2_GPU_CACHEABLE = (3, 2)
|
|
NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT = 0x00000000
|
|
NVOS32_ATTR2_GPU_CACHEABLE_YES = 0x00000001
|
|
NVOS32_ATTR2_GPU_CACHEABLE_NO = 0x00000002
|
|
NVOS32_ATTR2_GPU_CACHEABLE_INVALID = 0x00000003
|
|
NVOS32_ATTR2_P2P_GPU_CACHEABLE = (5, 4)
|
|
NVOS32_ATTR2_P2P_GPU_CACHEABLE_DEFAULT = 0x00000000
|
|
NVOS32_ATTR2_P2P_GPU_CACHEABLE_YES = 0x00000001
|
|
NVOS32_ATTR2_P2P_GPU_CACHEABLE_NO = 0x00000002
|
|
NVOS32_ATTR2_32BIT_POINTER = (6, 6)
|
|
NVOS32_ATTR2_32BIT_POINTER_DISABLE = 0x00000000
|
|
NVOS32_ATTR2_32BIT_POINTER_ENABLE = 0x00000001
|
|
NVOS32_ATTR2_FIXED_NUMA_NODE_ID = (7, 7)
|
|
NVOS32_ATTR2_FIXED_NUMA_NODE_ID_NO = 0x00000000
|
|
NVOS32_ATTR2_FIXED_NUMA_NODE_ID_YES = 0x00000001
|
|
NVOS32_ATTR2_SMMU_ON_GPU = (9, 8)
|
|
NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT = 0x00000000
|
|
NVOS32_ATTR2_SMMU_ON_GPU_DISABLE = 0x00000001
|
|
NVOS32_ATTR2_SMMU_ON_GPU_ENABLE = 0x00000002
|
|
NVOS32_ATTR2_USE_SCANOUT_CARVEOUT = (10, 10)
|
|
NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_FALSE = 0x00000000
|
|
NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_TRUE = 0x00000001
|
|
NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN = (11, 11)
|
|
NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF = 0x0
|
|
NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_ON = 0x1
|
|
NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_DEFAULT = NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF
|
|
NVOS32_ATTR2_PRIORITY = (13, 12)
|
|
NVOS32_ATTR2_PRIORITY_DEFAULT = 0x0
|
|
NVOS32_ATTR2_PRIORITY_HIGH = 0x1
|
|
NVOS32_ATTR2_PRIORITY_LOW = 0x2
|
|
NVOS32_ATTR2_INTERNAL = (14, 14)
|
|
NVOS32_ATTR2_INTERNAL_NO = 0x0
|
|
NVOS32_ATTR2_INTERNAL_YES = 0x1
|
|
NVOS32_ATTR2_PREFER_2C = (15, 15)
|
|
NVOS32_ATTR2_PREFER_2C_NO = 0x00000000
|
|
NVOS32_ATTR2_PREFER_2C_YES = 0x00000001
|
|
NVOS32_ATTR2_NISO_DISPLAY = (16, 16)
|
|
NVOS32_ATTR2_NISO_DISPLAY_NO = 0x00000000
|
|
NVOS32_ATTR2_NISO_DISPLAY_YES = 0x00000001
|
|
NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT = (17, 17)
|
|
NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO = 0x00000000
|
|
NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES = 0x00000001
|
|
NVOS32_ATTR2_ISO = (18, 18)
|
|
NVOS32_ATTR2_ISO_NO = 0x00000000
|
|
NVOS32_ATTR2_ISO_YES = 0x00000001
|
|
NVOS32_ATTR2_BLACKLIST = (19, 19)
|
|
NVOS32_ATTR2_BLACKLIST_ON = 0x00000000
|
|
NVOS32_ATTR2_BLACKLIST_OFF = 0x00000001
|
|
NVOS32_ATTR2_PAGE_OFFLINING = (19, 19)
|
|
NVOS32_ATTR2_PAGE_OFFLINING_ON = 0x00000000
|
|
NVOS32_ATTR2_PAGE_OFFLINING_OFF = 0x00000001
|
|
NVOS32_ATTR2_PAGE_SIZE_HUGE = (21, 20)
|
|
NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT = 0x00000000
|
|
NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB = 0x00000001
|
|
NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB = 0x00000002
|
|
NVOS32_ATTR2_PAGE_SIZE_HUGE_256GB = 0x00000003
|
|
NVOS32_ATTR2_PROTECTION_USER = (22, 22)
|
|
NVOS32_ATTR2_PROTECTION_USER_READ_WRITE = 0x00000000
|
|
NVOS32_ATTR2_PROTECTION_USER_READ_ONLY = 0x00000001
|
|
NVOS32_ATTR2_PROTECTION_DEVICE = (23, 23)
|
|
NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE = 0x00000000
|
|
NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY = 0x00000001
|
|
NVOS32_ATTR2_MEMORY_PROTECTION = (26, 25)
|
|
NVOS32_ATTR2_MEMORY_PROTECTION_DEFAULT = 0x00000000
|
|
NVOS32_ATTR2_MEMORY_PROTECTION_PROTECTED = 0x00000001
|
|
NVOS32_ATTR2_MEMORY_PROTECTION_UNPROTECTED = 0x00000002
|
|
NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP = (27, 27)
|
|
NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO = 0x00000000
|
|
NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES = 0x00000001
|
|
NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY = (30, 29)
|
|
NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY_DEFAULT = 0x00000000
|
|
NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY_UGPU0 = 0x00000001
|
|
NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY_UGPU1 = 0x00000002
|
|
NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY_UGPU_COUNT = 2
|
|
NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM = (31, 31)
|
|
NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_FALSE = 0x00000000
|
|
NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_TRUE = 0x00000001
|
|
NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT = 0x00000001
|
|
NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP = 0x00000002
|
|
NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN = 0x00000004
|
|
NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE = 0x00000008
|
|
NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE = 0x00000010
|
|
NVOS32_ALLOC_FLAGS_BANK_HINT = 0x00000020
|
|
NVOS32_ALLOC_FLAGS_BANK_FORCE = 0x00000040
|
|
NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT = 0x00000080
|
|
NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE = 0x00000100
|
|
NVOS32_ALLOC_FLAGS_BANK_GROW_UP = 0x00000000
|
|
NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN = 0x00000200
|
|
NVOS32_ALLOC_FLAGS_LAZY = 0x00000400
|
|
NVOS32_ALLOC_FLAGS_FORCE_REVERSE_ALLOC = 0x00000800
|
|
NVOS32_ALLOC_FLAGS_NO_SCANOUT = 0x00001000
|
|
NVOS32_ALLOC_FLAGS_PITCH_FORCE = 0x00002000
|
|
NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED = 0x00004000
|
|
NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED = 0x00008000
|
|
NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM = 0x00010000
|
|
NVOS32_ALLOC_FLAGS_USE_BEGIN_END = 0x00020000
|
|
NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED = 0x00040000
|
|
NVOS32_ALLOC_FLAGS_VIRTUAL = 0x00080000
|
|
NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX = 0x00100000
|
|
NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED = 0x00200000
|
|
NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED = 0x00400000
|
|
NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE = 0x00800000
|
|
NVOS32_ALLOC_FLAGS_PROTECTED = 0x01000000
|
|
NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP = 0x02000000
|
|
NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE = 0x02000000
|
|
NVOS32_ALLOC_FLAGS_SPARSE = 0x04000000
|
|
NVOS32_ALLOC_FLAGS_USER_READ_ONLY = 0x04000000
|
|
NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY = 0x08000000
|
|
NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC = 0x10000000
|
|
NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY = 0x20000000
|
|
NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD = 0x40000000
|
|
NVOS32_ALLOC_FLAGS_WPR1 = 0x40000000
|
|
NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X = 0x80000000
|
|
NVOS32_ALLOC_FLAGS_WPR2 = 0x80000000
|
|
NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC = 0x00000001
|
|
NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB = 0x00000004
|
|
NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE = NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE
|
|
NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY = ( NVOS32_ALLOC_FLAGS_VIRTUAL | NVOS32_ALLOC_FLAGS_LAZY | NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED | NVOS32_ALLOC_FLAGS_SPARSE | NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE | NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY )
|
|
NVOS32_ALLOC_COMPR_COVG_SCALE = 10
|
|
NVOS32_ALLOC_COMPR_COVG_BITS = (1, 0)
|
|
NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT = 0x00000000
|
|
NVOS32_ALLOC_COMPR_COVG_BITS_1 = 0x00000001
|
|
NVOS32_ALLOC_COMPR_COVG_BITS_2 = 0x00000002
|
|
NVOS32_ALLOC_COMPR_COVG_BITS_4 = 0x00000003
|
|
NVOS32_ALLOC_COMPR_COVG_MAX = (11, 2)
|
|
NVOS32_ALLOC_COMPR_COVG_MIN = (21, 12)
|
|
NVOS32_ALLOC_COMPR_COVG_START = (31, 22)
|
|
NVOS32_ALLOC_ZCULL_COVG_FORMAT = (3, 0)
|
|
NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z = 0x00000000
|
|
NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z = 0x00000002
|
|
NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS = 0x00000003
|
|
NVOS32_ALLOC_ZCULL_COVG_FALLBACK = (4, 4)
|
|
NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW = 0x00000000
|
|
NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW = 0x00000001
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_START = (19, 0)
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT = 0x00000000
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE = (31, 30)
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT = 0x00000000
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF = 0x00000000
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED = 0x00000001
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN = 0x00000002
|
|
NVOS32_REALLOC_FLAGS_GROW_ALLOCATION = 0x00000000
|
|
NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION = 0x00000001
|
|
NVOS32_REALLOC_FLAGS_REALLOC_UP = 0x00000000
|
|
NVOS32_REALLOC_FLAGS_REALLOC_DOWN = 0x00000002
|
|
NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED = 0x000000001
|
|
NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED = 0x000000001
|
|
NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED = 0x00000001
|
|
NVOS32_DUMP_FLAGS_TYPE = (1, 0)
|
|
NVOS32_DUMP_FLAGS_TYPE_FB = 0x00000000
|
|
NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD = 0x00000001
|
|
NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA = 0x00000002
|
|
NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE = 0x00000003
|
|
NVOS32_BLOCK_TYPE_FREE = 0xFFFFFFFF
|
|
NVOS32_INVALID_BLOCK_FREE_OFFSET = 0xFFFFFFFF
|
|
NVOS32_MEM_TAG_NONE = 0x00000000
|
|
NV04_MAP_MEMORY = (0x00000021)
|
|
NV04_MAP_MEMORY_FLAGS_NONE = (0x00000000)
|
|
NV04_MAP_MEMORY_FLAGS_USER = (0x00004000)
|
|
NVOS33_FLAGS_ACCESS = (1, 0)
|
|
NVOS33_FLAGS_ACCESS_READ_WRITE = (0x00000000)
|
|
NVOS33_FLAGS_ACCESS_READ_ONLY = (0x00000001)
|
|
NVOS33_FLAGS_ACCESS_WRITE_ONLY = (0x00000002)
|
|
NVOS33_FLAGS_PERSISTENT = (4, 4)
|
|
NVOS33_FLAGS_PERSISTENT_DISABLE = (0x00000000)
|
|
NVOS33_FLAGS_PERSISTENT_ENABLE = (0x00000001)
|
|
NVOS33_FLAGS_SKIP_SIZE_CHECK = (8, 8)
|
|
NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE = (0x00000000)
|
|
NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE = (0x00000001)
|
|
NVOS33_FLAGS_MEM_SPACE = (14, 14)
|
|
NVOS33_FLAGS_MEM_SPACE_CLIENT = (0x00000000)
|
|
NVOS33_FLAGS_MEM_SPACE_USER = (0x00000001)
|
|
NVOS33_FLAGS_MAPPING = (16, 15)
|
|
NVOS33_FLAGS_MAPPING_DEFAULT = (0x00000000)
|
|
NVOS33_FLAGS_MAPPING_DIRECT = (0x00000001)
|
|
NVOS33_FLAGS_MAPPING_REFLECTED = (0x00000002)
|
|
NVOS33_FLAGS_FIFO_MAPPING = (17, 17)
|
|
NVOS33_FLAGS_FIFO_MAPPING_DEFAULT = (0x00000000)
|
|
NVOS33_FLAGS_FIFO_MAPPING_ENABLE = (0x00000001)
|
|
NVOS33_FLAGS_MAP_FIXED = (18, 18)
|
|
NVOS33_FLAGS_MAP_FIXED_DISABLE = (0x00000000)
|
|
NVOS33_FLAGS_MAP_FIXED_ENABLE = (0x00000001)
|
|
NVOS33_FLAGS_RESERVE_ON_UNMAP = (19, 19)
|
|
NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE = (0x00000000)
|
|
NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE = (0x00000001)
|
|
NVOS33_FLAGS_BUS = (21, 20)
|
|
NVOS33_FLAGS_BUS_DEFAULT = 0
|
|
NVOS33_FLAGS_BUS_COHERENT_LINK = 1
|
|
NVOS33_FLAGS_BUS_PCIE = 2
|
|
NVOS33_FLAGS_OS_DESCRIPTOR = (22, 22)
|
|
NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE = (0x00000000)
|
|
NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE = (0x00000001)
|
|
NVOS33_FLAGS_CACHING_TYPE = (25, 23)
|
|
NVOS33_FLAGS_CACHING_TYPE_CACHED = 0
|
|
NVOS33_FLAGS_CACHING_TYPE_UNCACHED = 1
|
|
NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED = 2
|
|
NVOS33_FLAGS_CACHING_TYPE_WRITEBACK = 5
|
|
NVOS33_FLAGS_CACHING_TYPE_DEFAULT = 6
|
|
NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK = 7
|
|
NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC = (26, 26)
|
|
NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_NO = (0x00000000)
|
|
NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_YES = (0x00000001)
|
|
NV04_UNMAP_MEMORY = (0x00000022)
|
|
NV04_ACCESS_REGISTRY = (0x00000026)
|
|
NVOS38_ACCESS_TYPE_READ_DWORD = 1
|
|
NVOS38_ACCESS_TYPE_WRITE_DWORD = 2
|
|
NVOS38_ACCESS_TYPE_READ_BINARY = 6
|
|
NVOS38_ACCESS_TYPE_WRITE_BINARY = 7
|
|
NVOS38_MAX_REGISTRY_STRING_LENGTH = 256
|
|
NVOS38_MAX_REGISTRY_BINARY_LENGTH = 256
|
|
NV04_ALLOC_CONTEXT_DMA = (0x00000027)
|
|
NV04_GET_EVENT_DATA = (0x00000028)
|
|
NVSIM01_BUS_XACT = (0x0000002C)
|
|
NV04_MAP_MEMORY_DMA = (0x0000002E)
|
|
NVOS46_FLAGS_ACCESS = (1, 0)
|
|
NVOS46_FLAGS_ACCESS_READ_WRITE = (0x00000000)
|
|
NVOS46_FLAGS_ACCESS_READ_ONLY = (0x00000001)
|
|
NVOS46_FLAGS_ACCESS_WRITE_ONLY = (0x00000002)
|
|
NVOS46_FLAGS_32BIT_POINTER = (2, 2)
|
|
NVOS46_FLAGS_32BIT_POINTER_DISABLE = (0x00000000)
|
|
NVOS46_FLAGS_32BIT_POINTER_ENABLE = (0x00000001)
|
|
NVOS46_FLAGS_PAGE_KIND = (3, 3)
|
|
NVOS46_FLAGS_PAGE_KIND_PHYSICAL = (0x00000000)
|
|
NVOS46_FLAGS_PAGE_KIND_VIRTUAL = (0x00000001)
|
|
NVOS46_FLAGS_CACHE_SNOOP = (4, 4)
|
|
NVOS46_FLAGS_CACHE_SNOOP_DISABLE = (0x00000000)
|
|
NVOS46_FLAGS_CACHE_SNOOP_ENABLE = (0x00000001)
|
|
NVOS46_FLAGS_KERNEL_MAPPING = (5, 5)
|
|
NVOS46_FLAGS_KERNEL_MAPPING_NONE = (0x00000000)
|
|
NVOS46_FLAGS_KERNEL_MAPPING_ENABLE = (0x00000001)
|
|
NVOS46_FLAGS_SHADER_ACCESS = (7, 6)
|
|
NVOS46_FLAGS_SHADER_ACCESS_DEFAULT = (0x00000000)
|
|
NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY = (0x00000001)
|
|
NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY = (0x00000002)
|
|
NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE = (0x00000003)
|
|
NVOS46_FLAGS_PAGE_SIZE = (11, 8)
|
|
NVOS46_FLAGS_PAGE_SIZE_DEFAULT = (0x00000000)
|
|
NVOS46_FLAGS_PAGE_SIZE_4KB = (0x00000001)
|
|
NVOS46_FLAGS_PAGE_SIZE_BIG = (0x00000002)
|
|
NVOS46_FLAGS_PAGE_SIZE_BOTH = (0x00000003)
|
|
NVOS46_FLAGS_PAGE_SIZE_HUGE = (0x00000004)
|
|
NVOS46_FLAGS_PAGE_SIZE_512M = (0x00000005)
|
|
NVOS46_FLAGS_SYSTEM_L3_ALLOC = (13, 13)
|
|
NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT = (0x00000000)
|
|
NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT = (0x00000001)
|
|
NVOS46_FLAGS_DMA_OFFSET_GROWS = (14, 14)
|
|
NVOS46_FLAGS_DMA_OFFSET_GROWS_UP = (0x00000000)
|
|
NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN = (0x00000001)
|
|
NVOS46_FLAGS_DMA_OFFSET_FIXED = (15, 15)
|
|
NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE = (0x00000000)
|
|
NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE = (0x00000001)
|
|
NVOS46_FLAGS_DISABLE_ENCRYPTION = (16, 16)
|
|
NVOS46_FLAGS_DISABLE_ENCRYPTION_FALSE = (0x00000000)
|
|
NVOS46_FLAGS_DISABLE_ENCRYPTION_TRUE = (0x00000001)
|
|
NVOS46_FLAGS_GPU_CACHEABLE = (18, 17)
|
|
NVOS46_FLAGS_GPU_CACHEABLE_DEFAULT = (0x00000000)
|
|
NVOS46_FLAGS_GPU_CACHEABLE_YES = (0x00000001)
|
|
NVOS46_FLAGS_GPU_CACHEABLE_NO = (0x00000002)
|
|
NVOS46_FLAGS_GPU_CACHEABLE_INVALID = (0x00000003)
|
|
NVOS46_FLAGS_PAGE_KIND_OVERRIDE = (19, 19)
|
|
NVOS46_FLAGS_PAGE_KIND_OVERRIDE_NO = (0x00000000)
|
|
NVOS46_FLAGS_PAGE_KIND_OVERRIDE_YES = (0x00000001)
|
|
NVOS46_FLAGS_P2P = (27, 20)
|
|
NVOS46_FLAGS_P2P_ENABLE = (21, 20)
|
|
NVOS46_FLAGS_P2P_ENABLE_NO = (0x00000000)
|
|
NVOS46_FLAGS_P2P_ENABLE_YES = (0x00000001)
|
|
NVOS46_FLAGS_P2P_ENABLE_NONE = NVOS46_FLAGS_P2P_ENABLE_NO
|
|
NVOS46_FLAGS_P2P_ENABLE_SLI = NVOS46_FLAGS_P2P_ENABLE_YES
|
|
NVOS46_FLAGS_P2P_ENABLE_NOSLI = (0x00000002)
|
|
NVOS46_FLAGS_P2P_SUBDEVICE_ID = (24, 22)
|
|
NVOS46_FLAGS_P2P_SUBDEV_ID_SRC = NVOS46_FLAGS_P2P_SUBDEVICE_ID
|
|
NVOS46_FLAGS_P2P_SUBDEV_ID_TGT = (27, 25)
|
|
NVOS46_FLAGS_TLB_LOCK = (28, 28)
|
|
NVOS46_FLAGS_TLB_LOCK_DISABLE = (0x00000000)
|
|
NVOS46_FLAGS_TLB_LOCK_ENABLE = (0x00000001)
|
|
NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC = (29, 29)
|
|
NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE = (0x00000000)
|
|
NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE = (0x00000001)
|
|
NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP = (30, 30)
|
|
NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_FALSE = (0x00000000)
|
|
NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_TRUE = (0x00000001)
|
|
NVOS46_FLAGS_DEFER_TLB_INVALIDATION = (31, 31)
|
|
NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE = (0x00000000)
|
|
NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE = (0x00000001)
|
|
NVOS46_FLAGS2_GPU_CACHE_SNOOP = (1, 0)
|
|
NVOS46_FLAGS2_GPU_CACHE_SNOOP_DEFAULT = (0x00000000)
|
|
NVOS46_FLAGS2_GPU_CACHE_SNOOP_ENABLE = (0x00000001)
|
|
NVOS46_FLAGS2_GPU_CACHE_SNOOP_DISABLE = (0x00000002)
|
|
NV04_UNMAP_MEMORY_DMA = (0x0000002F)
|
|
NVOS47_FLAGS_DEFER_TLB_INVALIDATION = (0, 0)
|
|
NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE = (0x00000000)
|
|
NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE = (0x00000001)
|
|
NV04_BIND_CONTEXT_DMA = (0x00000031)
|
|
NV04_CONTROL = (0x00000036)
|
|
NVOS54_FLAGS_NONE = (0x00000000)
|
|
NVOS54_FLAGS_IRQL_RAISED = (0x00000001)
|
|
NVOS54_FLAGS_LOCK_BYPASS = (0x00000002)
|
|
NVOS54_FLAGS_FINN_SERIALIZED = (0x00000004)
|
|
NV04_DUP_OBJECT = (0x00000037)
|
|
NV04_DUP_HANDLE_FLAGS_NONE = (0x00000000)
|
|
NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE = (0x00000001)
|
|
NV04_UPDATE_DEVICE_MAPPING_INFO = (0x00000038)
|
|
NV04_SHARE = (0x0000003E)
|
|
NVPOWERSTATE_STAGE_NONE = 0
|
|
NVPOWERSTATE_STAGE_WAIT_FOR_GFW_BOOT_OK = 1
|
|
NVPOWERSTATE_STAGE_INIT_LIBOS_LOGGING_STRUCTURES = 2
|
|
NVPOWERSTATE_STAGE_GSP_PREPARE_FOR_BOOTSTRAP = 3
|
|
NVPOWERSTATE_STAGE_GSP_BOOTSTRAP = 4
|
|
NVPOWERSTATE_STAGE_BOOT_GSP_RM_PROXY = 5
|
|
NVPOWERSTATE_STAGE_VBIOS_HANDLE_SECURE_BOOT = 6
|
|
NVPOWERSTATE_STAGE_RESTORE_PCIE_CONFIG_REGISTERS = 7
|
|
NVPOWERSTATE_STAGE_GCX_BOOT_TIMER_CB_SCHEDULE = 8
|
|
NVPOWERSTATE_STAGE_POWER_MANAGEMENT_RESUME_PRE_LOAD_PHYSICAL_UNATTACHED = 9
|
|
NVPOWERSTATE_STAGE_PMS_EXPECTED_CHECKPOINT_DONE = 10
|
|
NVPOWERSTATE_STAGE_POLL_FOR_NVLINK_READY = 11
|
|
NVPOWERSTATE_STAGE_CE_STATE_PRE_LOAD = 12
|
|
NVPOWERSTATE_STAGE_LOAD_PROXY_UCODE_EARLY_INIT = 13
|
|
NVPOWERSTATE_STAGE_RESTORE_NON_WPR_REGION = 14
|
|
NVPOWERSTATE_STAGE_PMU_20_OS_BOOTSTRAP = 15
|
|
NVPOWERSTATE_STAGE_STATE_PRE_LOAD_ENGINE = 16
|
|
NVPOWERSTATE_STAGE_STATE_PRE_LOAD_UNKNOWN = 17
|
|
NVPOWERSTATE_STAGE_STATE_LOAD_ENGINE = 18
|
|
NVPOWERSTATE_STAGE_STATE_LOAD_UNKNOWN = 19
|
|
NVPOWERSTATE_STAGE_STATE_LOAD_PHYSICAL = 20
|
|
NVPOWERSTATE_STAGE_STATE_POST_LOAD_ENGINE = 21
|
|
NVPOWERSTATE_STAGE_STATE_POST_LOAD_UNKNOWN = 22
|
|
NVPOWERSTATE_STAGE_GSP_PREPARE_SUSPEND_RESUME_DATA = 23
|
|
NVPOWERSTATE_STAGE_MC_POINTER_NULL = 24
|
|
NVPOWERSTATE_STAGE_SAVE_PCIE_CONFIG_REGISTERS = 25
|
|
NVPOWERSTATE_STAGE_STATE_PRE_UNLOAD_ENGINE = 26
|
|
NVPOWERSTATE_STAGE_STATE_PRE_UNLOAD_UNKNOWN = 27
|
|
NVPOWERSTATE_STAGE_STATE_UNLOAD_ENGINE = 28
|
|
NVPOWERSTATE_STAGE_STATE_UNLOAD_UNKNOWN = 29
|
|
NVPOWERSTATE_STAGE_STATE_POST_UNLOAD_ENGINE = 30
|
|
NVPOWERSTATE_STAGE_STATE_POST_UNLOAD_UNKNOWN = 31
|
|
NVPOWERSTATE_STAGE_GSP_UNLOAD_RM = 32
|
|
NVPOWERSTATE_STAGE_MONITOR_STATE_0 = 33
|
|
NVPOWERSTATE_STAGE_MONITOR_STATE_1 = 34
|
|
NVPOWERSTATE_STAGE_MONITOR_STATE_HIBERNATE = 35
|
|
NVPOWERSTATE_STAGE_SET_POWER_STATE_UNKNOWN = 36
|
|
NVPOWERSTATE_STAGE__COUNT = 37
|
|
NV_DEVICE_ALLOCATION_SZNAME_MAXLEN = 128
|
|
NV_DEVICE_ALLOCATION_FLAGS_NONE = (0x00000000)
|
|
NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY = (0x00000001)
|
|
NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE = (0x00000002)
|
|
NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS = (0x00000004)
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE = (0x00000008)
|
|
NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE = (0x00000010)
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET = (0x00000020)
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT = (0x00000100)
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k = (0x00000200)
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k = (0x00000400)
|
|
NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS = (0x00000800)
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED = (0x00001000)
|
|
NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE = (0x00002000)
|
|
NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT = (0x00004000)
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET = (0x00008000)
|
|
NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES = (0x00000000)
|
|
NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE = (0x00000001)
|
|
NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES = (0x00000002)
|
|
NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR = 0x00000000
|
|
NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN = 0x00000001
|
|
NV_CHANNELGPFIFO_NOTIFICATION_TYPE_KEY_ROTATION_STATUS = 0x00000002
|
|
NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 = 3
|
|
NV_CHANNELGPFIFO_NOTIFICATION_STATUS_VALUE = (14, 0)
|
|
NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS = (15, 15)
|
|
NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE = 0x1
|
|
NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE = 0x0
|
|
NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB = (1, 1)
|
|
NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES = 0x00000000
|
|
NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO = 0x00000001
|
|
NV_SWRUNLIST_QOS_INTR_NONE = 0x00000000
|
|
NV_BSP_ALLOCATION_PARAMETERS = NV_NVDEC_ALLOCATION_PARAMETERS
|
|
NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE = (0x00000000)
|
|
NV_VP_ALLOCATION_FLAGS_STATIC_UCODE = (0x00000001)
|
|
NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE = (0x00000002)
|
|
NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO = (0x00000000)
|
|
NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO = (0x00000001)
|
|
NV_MSENC_ALLOCATION_PARAMETERS = NV_NVENC_ALLOCATION_PARAMETERS
|
|
NV04_ADD_VBLANK_CALLBACK = (0x0000003D)
|
|
NV_VASPACE_ALLOCATION_FLAGS_NONE = (0x00000000)
|
|
NV_VASPACE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE = BIT(0)
|
|
NV_VASPACE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS = BIT(1)
|
|
NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT = BIT(2)
|
|
NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED = BIT(3)
|
|
NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS = BIT(4)
|
|
NV_VASPACE_ALLOCATION_FLAGS_ENABLE_PAGE_FAULTING = BIT(6)
|
|
NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT = BIT(7)
|
|
NV_VASPACE_ALLOCATION_FLAGS_ALLOW_ZERO_ADDRESS = BIT(8)
|
|
NV_VASPACE_ALLOCATION_FLAGS_IS_FLA = BIT(9)
|
|
NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL = BIT(10)
|
|
NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE = BIT(11)
|
|
NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET = BIT(12)
|
|
NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED = BIT(13)
|
|
NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS_TEST = BIT(14)
|
|
NV_VASPACE_ALLOCATION_INDEX_GPU_NEW = 0x00
|
|
NV_VASPACE_ALLOCATION_INDEX_GPU_HOST = 0x01
|
|
NV_VASPACE_ALLOCATION_INDEX_GPU_GLOBAL = 0x02
|
|
NV_VASPACE_ALLOCATION_INDEX_GPU_DEVICE = 0x03
|
|
NV_VASPACE_ALLOCATION_INDEX_GPU_FLA = 0x04
|
|
NV_VASPACE_ALLOCATION_INDEX_GPU_MAX = 0x05
|
|
NV_VASPACE_BIG_PAGE_SIZE_64K = (64 * 1024)
|
|
NV_VASPACE_BIG_PAGE_SIZE_128K = (128 * 1024)
|
|
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT = (1, 0)
|
|
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SYNC = (0x00000000)
|
|
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC = (0x00000001)
|
|
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SPECIFIED = (0x00000002)
|
|
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER = (0x00000003)
|
|
NV_CTXSHARE_ALLOCATION_SUBCTXID_SUBCTXID = (30, 0)
|
|
NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION = (31, 31)
|
|
NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_SUCCESS = (0x00000001)
|
|
NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_FAIL = (0x00000000)
|
|
NV_TIMEOUT_CONTROL_CMD_SET_DEVICE_TIMEOUT = (0x00000002)
|
|
NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT = (0x00000003)
|
|
NVC36F_CTRL_RESERVED = (0x00)
|
|
NVC36F_CTRL_GPFIFO = (0x01)
|
|
NVC36F_CTRL_INTERNAL = (0x03)
|
|
NVC36F_CTRL_CMD_NULL = (0xc36f0000)
|
|
NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = (0xc36f0108)
|
|
NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID = (0x8)
|
|
NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES = 0x2
|
|
NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER = (0xc36f0109)
|
|
NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID = (0x9)
|
|
NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX = (0xc36f010a)
|
|
NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID = (0xA)
|
|
NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN = (0xc36f0301)
|
|
NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID = (0x1)
|
|
NVCB33_CTRL_RESERVED = (0x00)
|
|
NVCB33_CTRL_CONF_COMPUTE = (0x01)
|
|
NV_CONF_COMPUTE_CTRL_CMD_NULL = (0xcb330000)
|
|
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = (0xcb330101)
|
|
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE = 0
|
|
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV = 1
|
|
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX = 2
|
|
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV_SNP = 3
|
|
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SNP_VTOM = 4
|
|
NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE = 0
|
|
NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM = 1
|
|
NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC = 2
|
|
NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE = 0
|
|
NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM = 1
|
|
NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD = 2
|
|
NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED = 0
|
|
NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED = 1
|
|
NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED = 2
|
|
NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED = 0
|
|
NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED = 1
|
|
NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE = 0
|
|
NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE = 1
|
|
NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NVLE = 2
|
|
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE = (0xcb330104)
|
|
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE = (0xcb330105)
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE = (0xcb330106)
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE = (0xcb330107)
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS = (0xcb330108)
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0x8)
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE = (0xcb330109)
|
|
NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE = 0x1000
|
|
NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE = 0x1400
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID = (0x9)
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT = (0xcb33010a)
|
|
NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE = 0x2000
|
|
NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE = 0x1000
|
|
NV_CONF_COMPUTE_NONCE_SIZE = 0x20
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID = (0xA)
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS = (0xcb33010b)
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0xB)
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE = (0xcb33010c)
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED = 0
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED = 1
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED = 2
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED = 3
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID = (0xC)
|
|
NVA06C_CTRL_RESERVED = (0x00)
|
|
NVA06C_CTRL_GPFIFO = (0x01)
|
|
NVA06C_CTRL_INTERNAL = (0x02)
|
|
NVA06C_CTRL_CMD_NULL = (0xa06c0000)
|
|
NVA06C_CTRL_CMD_GPFIFO_SCHEDULE = (0xa06c0101)
|
|
NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x1)
|
|
NVA06C_CTRL_CMD_BIND = (0xa06c0102)
|
|
NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID = (0x2)
|
|
NVA06C_CTRL_CMD_SET_TIMESLICE = (0xa06c0103)
|
|
NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID = (0x3)
|
|
NVA06C_CTRL_CMD_GET_TIMESLICE = (0xa06c0104)
|
|
NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID = (0x4)
|
|
NVA06C_CTRL_CMD_PREEMPT = (0xa06c0105)
|
|
NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID = (0x5)
|
|
NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US = (1000000)
|
|
NVA06C_CTRL_CMD_GET_INFO = (0xa06c0106)
|
|
NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID = (0x6)
|
|
NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL = (0xa06c0107)
|
|
NVA06C_CTRL_INTERLEAVE_LEVEL_LOW = (0x00000000)
|
|
NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM = (0x00000001)
|
|
NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH = (0x00000002)
|
|
NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x7)
|
|
NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL = (0xa06c0108)
|
|
NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x8)
|
|
NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE = (0xa06c0109)
|
|
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID = (0x9)
|
|
NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS = (0xa06c010a)
|
|
NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES = (NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES)
|
|
NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID = (0xa)
|
|
NVA06C_CTRL_CMD_MAKE_REALTIME = (0xa06c0110)
|
|
NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID = (0x10)
|
|
NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE = (0xa06c0201)
|
|
NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x1)
|
|
NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE = (0xa06c0202)
|
|
NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID = (0x2)
|
|
GMMU_FMT_MAX_LEVELS = 6
|
|
NV90F1_CTRL_RESERVED = (0x00)
|
|
NV90F1_CTRL_VASPACE = (0x01)
|
|
NV90F1_CTRL_CMD_NULL = (0x90f10000)
|
|
NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT = (0x90f10101)
|
|
NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID = (0x1)
|
|
NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO = (0x90f10102)
|
|
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID = (0x2)
|
|
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE = 0x0
|
|
NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES = (0x90f10103)
|
|
NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID = (0x3)
|
|
NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES = (0x90f10104)
|
|
NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID = (0x4)
|
|
NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF = (0x90f10105)
|
|
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID = (0x5)
|
|
NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES = (0x90f10106)
|
|
NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID = (0x6)
|
|
NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE = (0x90f10107)
|
|
NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID = (0x7)
|
|
NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO = (0x90f10108)
|
|
NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID = (0x8)
|
|
NVA06F_CTRL_CMD_GPFIFO_SCHEDULE = (0xa06f0103)
|
|
NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x3)
|
|
NVA06F_CTRL_CMD_BIND = (0xa06f0104)
|
|
NVA06F_CTRL_BIND_PARAMS_MESSAGE_ID = (0x4)
|
|
NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER = (0xa06f0108)
|
|
NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS_MESSAGE_ID = (0x8)
|
|
NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL = (0xa06f0109)
|
|
NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x9)
|
|
NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL = (0xa06f0110)
|
|
NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x10)
|
|
NVA06F_CTRL_CMD_RESTART_RUNLIST = (0xa06f0111)
|
|
NVA06F_CTRL_RESTART_RUNLIST_PARAMS_MESSAGE_ID = (0x11)
|
|
NVA06F_CTRL_CMD_STOP_CHANNEL = (0xa06f0112)
|
|
NVA06F_CTRL_STOP_CHANNEL_PARAMS_MESSAGE_ID = (0x12)
|
|
NVA06F_CTRL_CMD_GET_CONTEXT_ID = (0xa06f0113)
|
|
NVA06F_CTRL_GET_CONTEXT_ID_PARAMS_MESSAGE_ID = (0x13)
|
|
NV0000_CTRL_RESERVED = (0x00)
|
|
NV0000_CTRL_SYSTEM = (0x01)
|
|
NV0000_CTRL_GPU = (0x02)
|
|
NV0000_CTRL_GSYNC = (0x03)
|
|
NV0000_CTRL_DIAG = (0x04)
|
|
NV0000_CTRL_EVENT = (0x05)
|
|
NV0000_CTRL_NVD = (0x06)
|
|
NV0000_CTRL_SWINSTR = (0x07)
|
|
NV0000_CTRL_PROC = (0x09)
|
|
NV0000_CTRL_SYNC_GPU_BOOST = (0x0A)
|
|
NV0000_CTRL_GPUACCT = (0x0B)
|
|
NV0000_CTRL_VGPU = (0x0C)
|
|
NV0000_CTRL_CLIENT = (0x0D)
|
|
NV0000_CTRL_OS_WINDOWS = (0x3F)
|
|
NV0000_CTRL_OS_MACOS = (0x3E)
|
|
NV0000_CTRL_OS_UNIX = (0x3D)
|
|
NV0000_CTRL_CMD_NULL = (0x0)
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE = (0xd01)
|
|
NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID = 0x00000000
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM = 0x00000001
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM = 0x00000002
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM = 0x00000003
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC = 0x00000004
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC_MC = 0x00000005
|
|
NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO = (0xd02)
|
|
NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID = 0x00000000
|
|
NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT = 0x00000001
|
|
NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID = 0x00000002
|
|
NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS = (0xd03)
|
|
NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID = (0x3)
|
|
NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY = (0xd04)
|
|
NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID = (0x4)
|
|
NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE = (0xd05)
|
|
NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID = (0x5)
|
|
NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT = (0xd06)
|
|
NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID = (0x6)
|
|
NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES = (0xd07)
|
|
NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID = (0x7)
|
|
NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL = (0xd08)
|
|
NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID = (0x8)
|
|
NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE = (0x480)
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID = (0x80)
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED = (0x00000000)
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED = (0x00000001)
|
|
NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES = (0x20000)
|
|
NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE = (0x481)
|
|
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID = (0x81)
|
|
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE = (0x00000000)
|
|
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE = (0x00000001)
|
|
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET = (0x00000002)
|
|
NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH = (0xc)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA = (0x00000001)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED = (0x00000002)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND = (0x00000003)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA = (0x00000004)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API = (0x00000010)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API = (0x00000011)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS = (0x00000020)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS = (0x00000021)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA = (0x00000100)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL = (0x00001000)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX = (0x00002002)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX = (0x00002003)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP = (0x00003000)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM = (0x00003001)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM = (0x00003002)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA = (0x00003003)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA = (0x00003004)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC = (0x00004000)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM = (0x00004001)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT = (0x00004010)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT = (0x00005000)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE = (0x00005001)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE = (0x00005002)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG = (0x00005003)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP = (0x00005004)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN = (0x00005005)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL = (0x00005006)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG = (0x00005007)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP = (0x00005008)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY = (0x00005009)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM = (0x0000500A)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT = (0x0000500B)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT = (0x0000500C)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS = (0x00006000)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA = (0x00007000)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA = (0x00007001)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR = (0x0000F000)
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC = (0x0000F00F)
|
|
NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES = (0x485)
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX = (0x40)
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID = (0x85)
|
|
NV0000_CTRL_CMD_DIAG_PROFILE_RPC = (0x488)
|
|
NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID = (0x88)
|
|
NV0000_CTRL_PROFILE_RPC_CMD_DISABLE = (0x00000000)
|
|
NV0000_CTRL_PROFILE_RPC_CMD_ENABLE = (0x00000001)
|
|
NV0000_CTRL_PROFILE_RPC_CMD_RESET = (0x00000002)
|
|
NV0000_CTRL_CMD_DIAG_DUMP_RPC = (0x489)
|
|
NV0000_CTRL_DIAG_RPC_MAX_ENTRIES = (100)
|
|
NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID = (0x89)
|
|
NV0000_NOTIFIERS_DISPLAY_CHANGE = (0)
|
|
NV0000_NOTIFIERS_VGPU_UNBIND_EVENT = (1)
|
|
NV0000_NOTIFIERS_VGPU_BIND_EVENT = (2)
|
|
NV0000_NOTIFIERS_GPU_BIND_UNBIND_EVENT = (3)
|
|
NV0000_NOTIFIERS_MAXCOUNT = (4)
|
|
NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION = (0x501)
|
|
NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE = (0x00000000)
|
|
NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE = (0x00000001)
|
|
NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT = (0x00000002)
|
|
NV0000_CTRL_CMD_GET_SYSTEM_EVENT_DATA = (0x502)
|
|
NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS = (0x201)
|
|
NV0000_CTRL_GPU_MAX_ATTACHED_GPUS = 32
|
|
NV0000_CTRL_GPU_INVALID_ID = (0xffffffff)
|
|
NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0000_CTRL_CMD_GPU_GET_ID_INFO = (0x202)
|
|
NV0000_CTRL_GPU_MAX_SZNAME = 128
|
|
NV0000_CTRL_NO_NUMA_NODE = (-1)
|
|
NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0000_CTRL_SLI_STATUS_OK = (0x00000000)
|
|
NV0000_CTRL_SLI_STATUS_OS_NOT_SUPPORTED = (0x00000002)
|
|
NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED = (0x00000040)
|
|
NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT = (0x00000001)
|
|
NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 = (0x205)
|
|
NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID = (0x5)
|
|
NV0000_CTRL_GPU_ID_INFO_IN_USE = (0, 0)
|
|
NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE = (0x00000000)
|
|
NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE = (0x00000001)
|
|
NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE = (1, 1)
|
|
NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE = (0x00000000)
|
|
NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE = (0x00000001)
|
|
NV0000_CTRL_GPU_ID_INFO_MOBILE = (2, 2)
|
|
NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE = (0x00000000)
|
|
NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE = (0x00000001)
|
|
NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER = (3, 3)
|
|
NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE = (0x00000000)
|
|
NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE = (0x00000001)
|
|
NV0000_CTRL_GPU_ID_INFO_SOC = (5, 5)
|
|
NV0000_CTRL_GPU_ID_INFO_SOC_FALSE = (0x00000000)
|
|
NV0000_CTRL_GPU_ID_INFO_SOC_TRUE = (0x00000001)
|
|
NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED = (6, 6)
|
|
NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE = (0x00000000)
|
|
NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE = (0x00000001)
|
|
NV0000_CTRL_GPU_ID_INFO_SOC_TYPE = (8, 7)
|
|
NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_NONE = (0x00000000)
|
|
NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_DISPLAY = (0x00000001)
|
|
NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_IGPU = (0x00000002)
|
|
NV0000_CTRL_GPU_ID_INFO_SOC_TYPE_DISPLAY_AND_IGPU = (0x00000003)
|
|
NV0000_CTRL_CMD_GPU_GET_INIT_STATUS = (0x203)
|
|
NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID = (0x3)
|
|
NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS = (0x204)
|
|
NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID = (0x4)
|
|
NV0000_CTRL_CMD_GPU_GET_PROBED_IDS = (0x214)
|
|
NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID = (0x14)
|
|
NV0000_CTRL_GPU_PROBED_ID_FLAGS_SOC_DISPLAY = (0, 0)
|
|
NV0000_CTRL_GPU_PROBED_ID_FLAGS_SOC_DISPLAY_FALSE = (0x00000000)
|
|
NV0000_CTRL_GPU_PROBED_ID_FLAGS_SOC_DISPLAY_TRUE = (0x00000001)
|
|
NV0000_CTRL_CMD_GPU_GET_PCI_INFO = (0x21b)
|
|
NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID = (0x1B)
|
|
NV0000_CTRL_CMD_GPU_ATTACH_IDS = (0x215)
|
|
NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS = (0x0000ffff)
|
|
NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID = (0x15)
|
|
NV0000_CTRL_CMD_GPU_DETACH_IDS = (0x216)
|
|
NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS = (0x0000ffff)
|
|
NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID = (0x16)
|
|
NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS = (0x219)
|
|
NV0000_CTRL_GPU_MAX_VIDEO_LINKS = 8
|
|
NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID = (0x19)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO = (0x274)
|
|
NV0000_GPU_MAX_GID_LENGTH = (0x00000100)
|
|
NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID = (0x74)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT = (1, 0)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII = (0x00000000)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY = (0x00000002)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE = (2, 2)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 = (0x00000000)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 = (0x00000001)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID = (0x275)
|
|
NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID = (0x75)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT = (1, 0)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII = (0x00000000)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY = (0x00000002)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE = (2, 2)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 = (0x00000000)
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 = (0x00000001)
|
|
NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE = (0x278)
|
|
NV0000_CTRL_GPU_DRAIN_STATE_DISABLED = (0x00000000)
|
|
NV0000_CTRL_GPU_DRAIN_STATE_ENABLED = (0x00000001)
|
|
NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE = (0x00000001)
|
|
NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE = (0x00000002)
|
|
NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID = (0x78)
|
|
NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE = (0x279)
|
|
NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID = (0x79)
|
|
NV0000_CTRL_CMD_GPU_DISCOVER = (0x27a)
|
|
NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE = (0x27b)
|
|
NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID = (0x7B)
|
|
NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE = (0x00000001)
|
|
NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT = (0x281)
|
|
NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID = (0x81)
|
|
NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA = 0x00000175
|
|
NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN = 6
|
|
NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT = 5
|
|
NV0000_CTRL_CMD_IDLE_CHANNELS = (0x283)
|
|
NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID = (0x83)
|
|
NV0000_CTRL_GPU_IMAGE_TYPE_GSP = (0x00000001)
|
|
NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG = (0x00000002)
|
|
NV0000_CTRL_GPU_IMAGE_TYPE_BINDATA_IMAGE = (0x00000003)
|
|
NV0000_CTRL_CMD_PUSH_UCODE_IMAGE = (0x285)
|
|
NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS_MESSAGE_ID = (0x85)
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SETTING_LEGACY = (2, 0)
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SETTING_LINK_COUNT = (7, 3)
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL = (0x00)
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF = (0x01)
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN = (0x02)
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF = (0x03)
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER = (0x04)
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_LINK_COUNT = (0x05)
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_UNSET = (0x00)
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_NODE = (0x01)
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_GPU = (0x02)
|
|
NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE = (0x286)
|
|
NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID = (0x86)
|
|
NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE = (0x287)
|
|
NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID = (0x87)
|
|
NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS = (0x288)
|
|
NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES = 256
|
|
NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID = (0x88)
|
|
NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID = (0x289)
|
|
NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID = (0x89)
|
|
NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID = (0x290)
|
|
NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID = (0x90)
|
|
NV0000_CTRL_CMD_GPU_PCI_READ_WRITE_DATA_SIZE_08 = 0
|
|
NV0000_CTRL_CMD_GPU_PCI_READ_WRITE_DATA_SIZE_16 = 1
|
|
NV0000_CTRL_CMD_GPU_PCI_READ_WRITE_DATA_SIZE_32 = 2
|
|
NV0000_CTRL_CMD_GPU_PCI_READ_WRITE = (0x291)
|
|
NV0000_CTRL_GPU_PCI_READ_WRITE_PARAMS_MESSAGE_ID = (0x91)
|
|
NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE = (0xb01)
|
|
NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED = (0x00000000)
|
|
NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED = (0x00000001)
|
|
NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE = (0xb02)
|
|
NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO = (0xb03)
|
|
NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID = (0x3)
|
|
NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS = (0xb04)
|
|
NV0000_GPUACCT_PID_MAX_COUNT = 4000
|
|
NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID = (0x4)
|
|
NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA = (0xb05)
|
|
NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID = (0x5)
|
|
NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO_V2 = (0xb06)
|
|
NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_V2_PARAMS_MESSAGE_ID = (0x6)
|
|
NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS = (0x301)
|
|
NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0000_CTRL_GSYNC_INVALID_ID = (0xffffffff)
|
|
NV0000_CTRL_CMD_GSYNC_GET_ID_INFO = (0x302)
|
|
NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0000_CTRL_NVD_DUMP_COMPONENT_SYS = (0x400)
|
|
NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG = (0x800)
|
|
NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED = (0xB00)
|
|
NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE = (0x601)
|
|
NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0000_CTRL_NVD_MAX_DUMP_SIZE = (1000000)
|
|
NV0000_CTRL_CMD_NVD_GET_DUMP = (0x602)
|
|
NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT = (0x00000000)
|
|
NV0000_NVD_CPU_TIME_CLK_ID_OSTIME = (0x00000001)
|
|
NV0000_NVD_CPU_TIME_CLK_ID_TSC = (0x00000002)
|
|
NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API = (0x00000003)
|
|
NV0000_CTRL_CMD_NVD_GET_TIMESTAMP = (0x603)
|
|
NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID = (0x3)
|
|
NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO = (0x604)
|
|
NV0000_CTRL_NVD_MAX_RUNTIME_SIZES = (16)
|
|
NV0000_CTRL_NVD_SIGNATURE_SIZE = (4)
|
|
NV0000_CTRL_NVD_MAX_BUFFERS = (3840)
|
|
NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID = (0x4)
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED = (0)
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_INT = (1)
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG = (2)
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_STRING = (3)
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_PTR = (4)
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR = (5)
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT = (6)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_INFO = (7, 0)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE = (23, 8)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE = (0x00000000)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT = (0x00000004)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_RUNTIME_LEVEL = (28, 25)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP = (30, 29)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE = (0x00000000)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32 = (0x00000001)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64 = (0x00000002)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF = (0x00000003)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED = (31, 31)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO = (0x00000000)
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES = (0x00000001)
|
|
NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO = (0x605)
|
|
NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x5)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE = (0, 0)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO = (0x00000000)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES = (0x00000001)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED = (0, 0)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO = (0x00000000)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES = (0x00000001)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE = (1, 1)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING = (0x00000000)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP = (0x00000001)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE = (2, 2)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO = (0x00000000)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES = (0x00000001)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED = (3, 3)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO = (0x00000000)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES = (0x00000001)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING = (5, 4)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE = (0x00000000)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE = (0x00000001)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL = (0x00000002)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA = (6, 6)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO = (0x00000000)
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES = (0x00000001)
|
|
NV0000_CTRL_CMD_NVD_GET_NVLOG = (0x606)
|
|
NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE = (4000)
|
|
NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID = (0x6)
|
|
NV0000_CTRL_CMD_NVD_GET_RCERR_RPT = (0x607)
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES = 200
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST = 0
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS = 1
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS = 2
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS = 3
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_RC_ERROR = 4
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY = 0x00000000
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED = 0x00000001
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG = 0x0000000f
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST = 0x00000001
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST = 0x00000002
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID = 0x00000004
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID = 0x00000008
|
|
TPC_REG_ATTR = lambda gpcId,tpcId: ((gpcId << 8) | (tpcId)) # type: ignore
|
|
ROP_REG_ATTR = lambda gpcId,ropId: ((gpcId << 8) | (ropId)) # type: ignore
|
|
SM_REG_ATTR = lambda gpcId,tpcId,smId: ((((gpcId) << 16) | ((tpcId) << 8)) | (smId)) # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID = 0x00000000
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID = 0xFFFFFFFF
|
|
NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID = (0x7)
|
|
NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS = (0x608)
|
|
NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID = (0x8)
|
|
NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0000_CTRL_CMD_SET_SUB_PROCESS_ID = (0x901)
|
|
NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION = (0x902)
|
|
NV0000_SYNC_GPU_BOOST_MAX_GROUPS = (0x10)
|
|
NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID = 0xFFFFFFFF
|
|
NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO = (0xa01)
|
|
NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE = (0xa02)
|
|
NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY = (0xa03)
|
|
NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID = (0x3)
|
|
NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO = (0xa04)
|
|
NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID = (0x4)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_FEATURES = (0x1f0)
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID = (0xF0)
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_SLI = (0, 0)
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING = (3, 3)
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED = (4, 4)
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_TRUE = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION = (0x101)
|
|
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO = (0x102)
|
|
NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0000_CTRL_SYSTEM_CPU_FAMILY = (3, 0)
|
|
NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY = (11, 4)
|
|
NV0000_CTRL_SYSTEM_CPU_MODEL = (3, 0)
|
|
NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL = (7, 4)
|
|
NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY = 0xF
|
|
NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY = 0xA
|
|
NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL = 0x0
|
|
NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL = 0x4
|
|
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY = 0x6
|
|
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY = 0x0
|
|
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL = 0x7
|
|
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL = 0xA
|
|
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL = 0x9
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P5 = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P55 = (0x00000002)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P6 = (0x00000003)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P2 = (0x00000004)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC = (0x00000005)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_CELA = (0x00000006)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P3 = (0x00000007)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 = (0x00000008)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P4 = (0x00000009)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 = (0x00000010)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H = (0x00000011)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM = (0x00000012)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM = (0x00000013)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR = (0x00000014)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K5 = (0x00000030)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K6 = (0x00000031)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K62 = (0x00000032)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K63 = (0x00000033)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K7 = (0x00000034)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K8 = (0x00000035)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K10 = (0x00000036)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K11 = (0x00000037)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN = (0x00000038)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_C6 = (0x00000060)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_C62 = (0x00000061)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_GX = (0x00000070)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_M1 = (0x00000071)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_M2 = (0x00000072)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_MGX = (0x00000073)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE = (0x00000080)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 = (0x00000090)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 = (0x00000091)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 = (0x00000092)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN = (0x00000093)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN = (0xA0000000)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 = (0xA0000009)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 = (0xA000000F)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 = (0xA0001000)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 = (0xA0002000)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC = (0xA00FF000)
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC = (0xA00FF001)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_MMX = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_SSE = (0x00000002)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW = (0x00000004)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 = (0x00000008)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE = (0x00000010)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING = (0x00000020)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC = (0x00000040)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO = (0x00000080)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND = (0x00000100)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT = (0x00000200)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT = (0x00000400)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_CMOV = (0x00000800)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH = (0x00001000)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 = (0x00002000)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 = (0x00004000)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 = (0x00008000)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE = (0x00010000)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 = (0x00020000)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 = (0x00040000)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_AVX = (0x00080000)
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_ERMS = (0x00100000)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO = (0x104)
|
|
NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH = (0x0000020)
|
|
NV0000_SYSTEM_CHIPSET_INVALID_ID = (0xffff)
|
|
NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID = (0x4)
|
|
NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE = (0, 0)
|
|
NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_CHIPSET_FLAG_BAR1_UNALIGNED_ACCESS = (1, 1)
|
|
NV0000_CTRL_SYSTEM_CHIPSET_FLAG_BAR1_UNALIGNED_ACCESS_NO = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_CHIPSET_FLAG_BAR1_UNALIGNED_ACCESS_YES = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT = (0x107)
|
|
NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID = (0x7)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES = (0x109)
|
|
NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID = (0x9)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST = (0x108)
|
|
NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE = (32)
|
|
NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID = (0x8)
|
|
NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT = (0x110)
|
|
NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID = (0x10)
|
|
NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE = (0x00000002)
|
|
NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID = (0x00000003)
|
|
NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK = (0x00000004)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF = (0x00000002)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI = (0x00000003)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL = (0x00000004)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT = (0x5)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF = (0x00000002)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI = (0x00000003)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL = (0x00000004)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT = (0x5)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE = (0x111)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID = (0x11)
|
|
NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP = (0x000000)
|
|
NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC = (0x000001)
|
|
NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA = (0x000002)
|
|
NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC = (0x000003)
|
|
NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL = (0x121)
|
|
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE = 512
|
|
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID = (0x21)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL = (0x122)
|
|
NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID = (0x22)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_INVALID = (0xFFFF)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT = (0x0000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC = (0x0001)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC = (0x0002)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS = (0x0003)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS = (0x0004)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC = (0x0005)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC = (0x0006)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE = (0x0007)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE = (0x0008)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT = (0x0009)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT = (0x000A)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE = (0x000B)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE = (0x000C)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER = (0x0100)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER = (0x0101)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET = (0x0102)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET = (0x0103)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD = (0x0104)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD = (0x0105)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET = (0x0106)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET = (0x0107)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT = (0x0108)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST = (0x0109)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST = (0x010A)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE = (0x010B)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE = (0x010C)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO = (0x010D)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS = (0x010E)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER = (0x0200)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA = (0x0201)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE = (0x0202)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG = (0x0203)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL = (0x0204)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN = (0x0205)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE = (0x0206)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS = (0x0210)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP = (0x0220)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA = (0x0221)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE = (0x0222)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE = (0x0240)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP = (0x0241)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN = (0x0242)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX = (0x0243)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION = (0x0244)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT = (0x0245)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE = (0x0250)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE = (0x0251)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA = (0x0252)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA = (0x0253)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK = (0x0320)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT = (0x0321)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID = (0xFFFF)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM = (0x0000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU = lambda i: (0x0100+((i)%0x100)) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU = lambda i: (0x0200+((i)%0x100)) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID = (0x80000000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC = (0x00000002)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH = (0x00000002)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE = (0xFFFFFFFF)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT = (0x00000002)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS = (0x00000002)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS = (0x00000004)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC = (0x00000008)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC = (0x00000010)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB = (0x00000020)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS = (0x00000040)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING = (0x00000002)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT = (0x00000003)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 = (0x00000004)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 = (0x00000005)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM = (0x00000006)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM = (0x00000007)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL = (0x123)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX = (16)
|
|
NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID = (0x23)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS = (0x127)
|
|
NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS = 32
|
|
NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED = 1024
|
|
NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS = 8
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER = 0xffffffff
|
|
NV0000_CTRL_P2P_CAPS_INDEX_READ = 0
|
|
NV0000_CTRL_P2P_CAPS_INDEX_WRITE = 1
|
|
NV0000_CTRL_P2P_CAPS_INDEX_NVLINK = 2
|
|
NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS = 3
|
|
NV0000_CTRL_P2P_CAPS_INDEX_PROP = 4
|
|
NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK = 5
|
|
NV0000_CTRL_P2P_CAPS_INDEX_PCI = 6
|
|
NV0000_CTRL_P2P_CAPS_INDEX_C2C = 7
|
|
NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 = 8
|
|
NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE = 9
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID = (0x27)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED = (0, 0)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED = (1, 1)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED = (2, 2)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED = (3, 3)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED = (4, 4)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED = (5, 5)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED = (6, 6)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED = (7, 7)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED = (8, 8)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED = (9, 9)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED = (10, 10)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED = (12, 12)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED = (13, 13)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE = (0x00000001)
|
|
NV0000_P2P_CAPS_STATUS_OK = (0x00)
|
|
NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED = (0x01)
|
|
NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED = (0x02)
|
|
NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED = (0x03)
|
|
NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY = (0x04)
|
|
NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED = (0x05)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 = (0x12b)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID = (0x2B)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX = (0x13a)
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID = (0x3A)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CTRL = (0x12a)
|
|
NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID = (0x2A)
|
|
NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION = (0x00010000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT = (0x00000002)
|
|
NV0000_CTRL_GPS_INPUT_SENSOR_INDEX = (0x00000000)
|
|
NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT = (0x00000000)
|
|
NV0000_CTRL_GPS_RESULT_MIN_LIMIT = (0x00000001)
|
|
NV0000_CTRL_GPS_RESULT_MAX_LIMIT = (0x00000002)
|
|
NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE = (0x00000003)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT = (0x00000003)
|
|
NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA = (0x00000004)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA = (0x00000005)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA = (0x00000006)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA = (0x00000007)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA = (0x00000008)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA = (0x00000009)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000A)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000B)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000C)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000D)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS = (0x00000016)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS = (0x00000017)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM = (0x00000018)
|
|
NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM = (0x00000019)
|
|
NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR = (0x0000001A)
|
|
NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL = (0x00000001)
|
|
NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE = (0x00000000)
|
|
NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI = (0x0000001B)
|
|
NV0000_CTRL_GPS_INPUT_ACPI_CMD = (0x00000000)
|
|
NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN = (0x00000001)
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 = (0x00000000)
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 = (0x00000001)
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS = (0x00000000)
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION = (0x00000001)
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ = (0x00000002)
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ = (0x00000000)
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO = (0x0000001C)
|
|
NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD = (0x00000026)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_PERIOD = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD = (0x00000027)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_PERIOD = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR = (0x00000028)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP = (0x00000000)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR = (0x00000029)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP = (0x00000000)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES = (0x0000002A)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES = (0x0000002B)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS = (0x0000002C)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER = (0x00000000)
|
|
NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS = (0x0000002D)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER = (0x00000000)
|
|
NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE = (0x0000002E)
|
|
NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE = (0x0000002F)
|
|
NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS = (0x00000044)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 = (0x00000001)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS = (0x00000045)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT = (0x00000046)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ = (0)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT = (0x00000047)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ = (0)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_PPM = (0x00000048)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX = (0)
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK = (1)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_PPM = (0x00000049)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX = (0)
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX = (2)
|
|
NV0000_CTRL_GPS_PPM_INDEX = (7, 0)
|
|
NV0000_CTRL_GPS_PPM_INDEX_MAXPERF = (0)
|
|
NV0000_CTRL_GPS_PPM_INDEX_BALANCED = (1)
|
|
NV0000_CTRL_GPS_PPM_INDEX_QUIET = (2)
|
|
NV0000_CTRL_GPS_PPM_INDEX_INVALID = (0xFF)
|
|
NV0000_CTRL_GPS_PPM_MASK = (15, 8)
|
|
NV0000_CTRL_GPS_PPM_MASK_INVALID = (0)
|
|
NV0000_CTRL_GPS_CMD_PS_STATUS_OFF = (0)
|
|
NV0000_CTRL_GPS_CMD_PS_STATUS_ON = (1)
|
|
GPS_MAX_COUNTERS_PER_BLOCK = 32
|
|
NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID = (0x29)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS = (0x12c)
|
|
NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x2C)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS = (0x12e)
|
|
NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x2E)
|
|
GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE = 288
|
|
NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID = (0x2D)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI = (0x12d)
|
|
NV0000_CTRL_SYSTEM_PARAM_TGPU = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_PARAM_PDTS = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_PARAM_SFAN = (0x00000002)
|
|
NV0000_CTRL_SYSTEM_PARAM_SKNT = (0x00000003)
|
|
NV0000_CTRL_SYSTEM_PARAM_CPUE = (0x00000004)
|
|
NV0000_CTRL_SYSTEM_PARAM_TMP1 = (0x00000005)
|
|
NV0000_CTRL_SYSTEM_PARAM_TMP2 = (0x00000006)
|
|
NV0000_CTRL_SYSTEM_PARAM_CTGP = (0x00000007)
|
|
NV0000_CTRL_SYSTEM_PARAM_PPMD = (0x00000008)
|
|
NV0000_CTRL_SYSTEM_PARAM_COUNT = (0x00000009)
|
|
NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD = (0x130)
|
|
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID = (0x30)
|
|
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS = (0x00000002)
|
|
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY = (0x00000003)
|
|
NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS = (0x131)
|
|
NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID = (0x31)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ = (0x00000002)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH = (0x00000004)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF = (0x00000010)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG = (0x00000020)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS = (0x00000040)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER = (0x00000080)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP = (0x00000100)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI = (0x00000200)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR = (0x00000400)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK = (0x00000800)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL = (0x00001000)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC = (0x00002000)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM = (0x00004000)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS = (0x00008000)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE = (0x00010000)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY = (0x00020000)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA = (0x12f)
|
|
NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE = 64
|
|
NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID = (0x2F)
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA = (0x132)
|
|
NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID = (0x32)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE = 256
|
|
NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO = (0x133)
|
|
NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID = (0x33)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS = (0x134)
|
|
NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID = (0x34)
|
|
NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED = 0
|
|
NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED = 1
|
|
NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS = (0x135)
|
|
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID = (0x35)
|
|
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG = (0x00000002)
|
|
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG = (0x00000004)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS = (0x136)
|
|
NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID = (0x36)
|
|
NV0000_CTRL_VGPU_GET_VGPU_VERSION = (0x137)
|
|
NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID = (0x37)
|
|
NV0000_CTRL_VGPU_SET_VGPU_VERSION = (0x138)
|
|
NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID = (0x38)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID = (0x139)
|
|
NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID = (0x39)
|
|
NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO = (0x13b)
|
|
NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE = 1
|
|
NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE = 32
|
|
NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT_MESSAGE_ID = (0x48)
|
|
NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID = (0x3B)
|
|
CONTROLLER_FILTER_TYPE_EMWA = 0
|
|
CONTROLLER_FILTER_TYPE_MOVING_MAX = 1
|
|
NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED_CASE = 0
|
|
NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_CASE = 1
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE = 2
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE = 3
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE = 4
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_CASE = 5
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL_CASE = 6
|
|
NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED = (0x00000000)
|
|
NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS = (0x00000002)
|
|
NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED = (0, 0)
|
|
NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES = 1
|
|
NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO = 0
|
|
NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED = (8, 8)
|
|
NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED_YES = 1
|
|
NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED_NO = 0
|
|
NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED = (9, 9)
|
|
NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED_YES = 1
|
|
NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED_NO = 0
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION = (0x00000200)
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED = (0x00000000)
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES = (0x00000001)
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS = (0x00000002)
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE = (0x00000008)
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL = (0x00000009)
|
|
NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX = (255)
|
|
NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT = (0x13c)
|
|
NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID = (0x3C)
|
|
NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO = (0x13d)
|
|
NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID = (0x3D)
|
|
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE = 256
|
|
NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 = (0x13e)
|
|
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID = (0x3E)
|
|
NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL = (0x13f)
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID = (0x3F)
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE = (0x00000000)
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE = (0x00000001)
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY = (0x00000002)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL = (0x140)
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID = (0x40)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID = (0xFFFF)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT = (0x0000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC = (0x0001)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC = (0x0002)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS = (0x0003)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS = (0x0004)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC = (0x0005)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC = (0x0006)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE = (0x0007)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE = (0x0008)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT = (0x0009)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT = (0x000A)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE = (0x000B)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE = (0x000C)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER = (0x0100)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER = (0x0101)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET = (0x0102)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET = (0x0103)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD = (0x0104)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD = (0x0105)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET = (0x0106)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET = (0x0107)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT = (0x0108)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST = (0x0109)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST = (0x010A)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE = (0x010B)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE = (0x010C)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO = (0x010D)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS = (0x010E)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER = (0x0200)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA = (0x0201)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE = (0x0202)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG = (0x0203)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL = (0x0204)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN = (0x0205)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE = (0x0206)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS = (0x0210)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP = (0x0220)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA = (0x0221)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE = (0x0222)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE = (0x0240)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP = (0x0241)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN = (0x0242)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX = (0x0243)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION = (0x0244)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT = (0x0245)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE = (0x0250)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE = (0x0251)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA = (0x0252)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA = (0x0253)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK = (0x0320)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT = (0x0321)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID = (0xFFFF)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM = (0x0000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU = lambda i: (0x0100+((i)%0x100)) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU = lambda i: (0x0200+((i)%0x100)) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID = (0x80000000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC = (0x00000002)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH = (0x00000002)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE = (0xFFFFFFFF)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT = (0x00000002)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS = (0x00000002)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS = (0x00000004)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC = (0x00000008)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC = (0x00000010)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB = (0x00000020)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS = (0x00000040)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING = (0x00000002)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT = (0x00000003)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 = (0x00000004)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 = (0x00000005)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM = (0x00000006)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM = (0x00000007)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF = (0x00000000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON = (0x00000001)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL = (0x141)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX = (16)
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID = (0x41)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL = (0x142)
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID = (0x42)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION = (0x00010000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT = (0x00000002)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT = (0x00000002)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE = (0x00000003)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT = (0x00000003)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA = (0x00000004)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA = (0x00000005)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA = (0x00000006)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA = (0x00000007)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA = (0x00000008)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA = (0x00000009)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000A)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000B)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000C)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000D)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS = (0x00000016)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS = (0x00000017)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM = (0x00000018)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM = (0x00000019)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR = (0x0000001A)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI = (0x0000001B)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ = (0x00000002)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO = (0x0000001C)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD = (0x00000026)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD = (0x00000027)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR = (0x00000028)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR = (0x00000029)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES = (0x0000002A)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES = (0x0000002B)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS = (0x0000002C)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS = (0x0000002D)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE = (0x0000002E)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE = (0x0000002F)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS = (0x00000044)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 = (0x00000001)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS = (0x00000045)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT = (0x00000046)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ = (0)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT = (0x00000047)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ = (0)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM = (0x00000048)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX = (0)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK = (1)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM = (0x00000049)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX = (0)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX = (2)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX = (7, 0)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF = (0)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED = (1)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET = (2)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID = (0xFF)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK = (15, 8)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID = (0)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF = (0)
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON = (1)
|
|
PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK = 32
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS = (0x146)
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x46)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS = (0x147)
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x47)
|
|
PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE = 288
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID = (0x43)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI = (0x143)
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR = (0x00008000)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA = (0x144)
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE = 64
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID = (0x44)
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA = (0x145)
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID = (0x45)
|
|
NV0000_CTRL_CMD_SYSTEM_READ_CPER = (0x149)
|
|
NV0000_CTRL_SYSTEM_READ_CPER_ACCESS_TYPE_GPU = (1)
|
|
READ_CPER_BUFFER_SIZE = 1024
|
|
NV0000_CTRL_SYSTEM_READ_CPER_PARAMS_MESSAGE_ID = (0x49)
|
|
NV0000_CTRL_CMD_SYSTEM_SOC_SET_PERF_LIMITS = (0x150)
|
|
NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_TEST_PERF_LEVELS = (0)
|
|
NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_ISMODEPOSSIBLE = (1)
|
|
NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_MCLK_SWITCH = (2)
|
|
NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_ID_MODS = (3)
|
|
NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_PERF_LEVEL = (0)
|
|
NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_DISPCLK = (1)
|
|
NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMIT_BW_RESOURCE_HUBCLK = (2)
|
|
NV0000_CTRL_SYSTEM_SOC_PERF_MAX_LIMITS = (16)
|
|
NV0000_CTRL_SYSTEM_SOC_SET_PERF_LIMITS_PARAMS_MESSAGE_ID = (0x150)
|
|
NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE = (0x3d02)
|
|
NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH = (0x00000001)
|
|
NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE = (0x00000002)
|
|
NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE = (0x00000003)
|
|
NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR = (0x3d04)
|
|
NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD = (0x3d05)
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID = (0x5)
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD = (0, 0)
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE = (0x00000000)
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE = (0x00000001)
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD = (0x3d06)
|
|
NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID = (0x6)
|
|
NV0000_CTRL_CMD_OS_GET_GPU_INFO = (0x3d07)
|
|
NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO = (0x3d08)
|
|
NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE = 64
|
|
NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID = (0x8)
|
|
NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST = (0x3d09)
|
|
NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD = (0x3d0a)
|
|
NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE = NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE
|
|
NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID = (0xA)
|
|
NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD = (0x3d0b)
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS = 512
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID = (0xB)
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD = (0x3d0c)
|
|
NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS = 128
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE = 0
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM = 1
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM = 2
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC = 3
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC = 4
|
|
NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID = (0xC)
|
|
NV0000_CTRL_OS_UNIX_MEMACCT_SET_LIMITS_PARAMS_MESSAGE_ID = (0xD)
|
|
NV0000_CTRL_OS_UNIX_CMD_MEMACCT_SET_LIMITS = (0x3d0d)
|
|
NV0000_CTRL_OS_UNIX_MEMACCT_GET_LIMITS_PARAMS_MESSAGE_ID = (0xE)
|
|
NV0000_CTRL_OS_UNIX_CMD_MEMACCT_GET_LIMITS = (0x3d0e)
|
|
NV0000_BUSDEVICE_DOMAIN = (31, 16)
|
|
NV0000_BUSDEVICE_BUS = (15, 8)
|
|
NV0000_BUSDEVICE_DEVICE = (7, 0)
|
|
NV0000_CTRL_CMD_VGPU_CREATE_DEVICE = (0xc02)
|
|
NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0000_CTRL_CMD_VGPU_GET_INSTANCES = (0xc03)
|
|
NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS_MESSAGE_ID = (0x3)
|
|
NV0000_CTRL_CMD_VGPU_DELETE_DEVICE = (0xc04)
|
|
NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS_MESSAGE_ID = (0x4)
|
|
NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS = (0xc05)
|
|
NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID = (0x5)
|
|
NV0000_CTRL_CMD_GPU_UPDATE_SYSFS_NODE = (0x206)
|
|
NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS_MESSAGE_ID = (0x6)
|
|
NV0080_CTRL_RESERVED = (0x00)
|
|
NV0080_CTRL_BIF = (0x01)
|
|
NV0080_CTRL_GPU = (0x02)
|
|
NV0080_CTRL_CLK = (0x10)
|
|
NV0080_CTRL_GR = (0x11)
|
|
NV0080_CTRL_CIPHER = (0x12)
|
|
NV0080_CTRL_FB = (0x13)
|
|
NV0080_CTRL_HOST = (0x14)
|
|
NV0080_CTRL_VIDEO = (0x15)
|
|
NV0080_CTRL_FIFO = (0x17)
|
|
NV0080_CTRL_DMA = (0x18)
|
|
NV0080_CTRL_PERF = (0x19)
|
|
NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED = (0x99)
|
|
NV0080_CTRL_NVENC = (0x1B)
|
|
NV0080_CTRL_NVDEC = (0x1C)
|
|
NV0080_CTRL_RC = (0x1D)
|
|
NV0080_CTRL_OS_UNIX = (0x1E)
|
|
NV0080_CTRL_NVJPG = (0x1F)
|
|
NV0080_CTRL_INTERNAL = (0x20)
|
|
NV0080_CTRL_NVLINK = (0x21)
|
|
NV0080_CTRL_CMD_NULL = (0x800000)
|
|
NV0080_CTRL_CMD_BIF_RESET = (0x800102)
|
|
NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE = (4, 0)
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET = 0x1
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR = 0x2
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL = 0x3
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE = 0x4
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE = 0x5
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX = 0x6
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER = 0x7
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE = 0x8
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_CXL_RESET = 0x9
|
|
NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE = (0x800105)
|
|
NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID = (0x5)
|
|
NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK = (0x800106)
|
|
NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID = (0x6)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID = (0, 0)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE = (0x00000001)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED = (2, 1)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE = (0x00000001)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED = (0x00000002)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE = (6, 3)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY = (0x00000000)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY = (0x00000001)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY = (0x00000002)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY = (0x00000003)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS = (10, 7)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE = (0x00000000)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1 = (0x00000001)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2 = (0x00000002)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4 = (0x00000004)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED = (12, 11)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE = (0x00000001)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED = (0x00000002)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS = (14, 13)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE = (0x00000000)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY = (0x00000001)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY = (0x00000002)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED = (0x00000003)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY = (15, 15)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE = (0x00000001)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC = (16, 16)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE = (0x00000000)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE = (0x00000001)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING = (17, 17)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE = (0x00000000)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE = (0x00000001)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED = (18, 18)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE = (0x00000001)
|
|
NV0080_CTRL_CMD_DMA_GET_PTE_INFO = (0x801801)
|
|
NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS = 5
|
|
NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0080_CTRL_CMD_DMA_SET_PTE_INFO = (0x80180a)
|
|
NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS = 5
|
|
NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID = (0xA)
|
|
NV0080_CTRL_CMD_DMA_FILL_PTE_MEM = (0x801802)
|
|
NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0080_CTRL_CMD_DMA_FLUSH = (0x801805)
|
|
NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID = (0x5)
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2 = (0, 0)
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE = (0x00000000)
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE = (0x00000001)
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG = (1, 1)
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE = (0x00000000)
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE = (0x00000001)
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB = (2, 2)
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE = (0x00000000)
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE = (0x00000001)
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE = (4, 3)
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM = (0x00000001)
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM = (0x00000002)
|
|
NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS = (0x801806)
|
|
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS = (16)
|
|
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID = (0x6)
|
|
NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO = 0x1
|
|
NV0080_CTRL_CMD_DMA_GET_PDE_INFO = (0x801809)
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY = (0x00000000)
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY = (0x00000001)
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY = (0x00000002)
|
|
NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS = 5
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID = (0x9)
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY = (0x00000000)
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY = (0x00000001)
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY = (0x00000002)
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL = 1
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF = 2
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER = 3
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH = 4
|
|
NV0080_CTRL_CMD_DMA_INVALIDATE_TLB = (0x80180c)
|
|
NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID = (0xC)
|
|
NV0080_CTRL_DMA_INVALIDATE_TLB_ALL = (0, 0)
|
|
NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE = (0x00000001)
|
|
NV0080_CTRL_CMD_DMA_GET_CAPS = (0x80180d)
|
|
NV0080_CTRL_DMA_CAPS_TBL_SIZE = 8
|
|
NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID = (0xD)
|
|
NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE = (0x80180e)
|
|
NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID = (0xE)
|
|
NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX = (0xFFFFFFFFFFFFFFFF)
|
|
NV0080_CTRL_CMD_DMA_UPDATE_PDE_2 = (0x80180f)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID = (0x00000000)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY = (0x00000001)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY = (0x00000002)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY = (0x00000003)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL = 0
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG = 1
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE = 2
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID = (0xF)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE = (0, 0)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE = (0x00000001)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE = (1, 1)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE = (0x00000001)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE = (3, 2)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL = (0x00000000)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF = (0x00000001)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER = (0x00000002)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH = (0x00000003)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE = (4, 4)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE = (0x00000001)
|
|
NV0080_CTRL_DMA_SET_DEFAULT_VASPACE = (0x801812)
|
|
NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID = (0x12)
|
|
NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY = (0x801813)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID = (0x13)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE = (1, 0)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM = (0x00000000)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH = (0x00000001)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH = (0x00000002)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES = (2, 2)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE = (0x00000001)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS = (3, 3)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE = (0x00000001)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY = (4, 4)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE = (0x00000001)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE = (5, 5)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE = (0x00000000)
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE = (0x00000001)
|
|
NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY = (0x801814)
|
|
NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID = (0x14)
|
|
NV0080_CTRL_CMD_FB_GET_CAPS = (0x801301)
|
|
NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0080_CTRL_FB_CAPS_TBL_SIZE = 3
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO = (0x801306)
|
|
NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID = (0x6)
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN = 0
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM = 1
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM = 2
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY = 0
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1 = 1
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4 = 2
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE = 3
|
|
NV0080_CTRL_CMD_FB_GET_CAPS_V2 = (0x801307)
|
|
NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x7)
|
|
NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY = (0x801308)
|
|
NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID = (0x8)
|
|
NV0080_CTRL_CMD_FIFO_GET_CAPS = (0x801701)
|
|
NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0080_CTRL_FIFO_CAPS_TBL_SIZE = 2
|
|
NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES = (0x801707)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID = (4, 0)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS = (0x00000000)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD = (0x00000001)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO = (0x00000002)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG = (0x00000003)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE = (0x00000004)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY = (0x00000005)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION = (0x00000006)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS = (0x00000007)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL = (0x00000008)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM = (0x00000009)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT = (0x0000000a)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT = (0x0000000b)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL = (0x0000000c)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL = (0x0000000d)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB = (0x0000000e)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV = (0x0000000f)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH = (0x00000010)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB = (0x00000011)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL = (0x00000012)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB = (0x00000013)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL = (0x00000014)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL = (0x00000015)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK = (0x00000016)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT = (0x00000017)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP = (0x00000018)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SETUP = (0x00000019)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT = (0x0000001a)
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID = (0x7)
|
|
NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST = (0x80170d)
|
|
NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID = (0xD)
|
|
NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE = (0x80170e)
|
|
NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0xE)
|
|
NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL = (0xffffffff)
|
|
NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES = (0x80170f)
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID = (0xF)
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET = (0x00000004)
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT = (0x00000005)
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP = (0x00000007)
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT = (0x00000008)
|
|
NV0080_CTRL_CMD_FIFO_STOP_RUNLIST = (0x801711)
|
|
NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID = (0x11)
|
|
NV0080_CTRL_CMD_FIFO_START_RUNLIST = (0x801712)
|
|
NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID = (0x12)
|
|
NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 = (0x801713)
|
|
NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x13)
|
|
NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS = (0x801714)
|
|
NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS = 4096
|
|
NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID = (0x14)
|
|
NV0080_CTRL_CMD_GPU_GET_CLASSLIST = (0x800201)
|
|
NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES = (0x800280)
|
|
NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID = (0x80)
|
|
NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER = (0x800281)
|
|
NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID = (0x81)
|
|
NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER = (0x800282)
|
|
NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID = (0x82)
|
|
NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER = (0x800283)
|
|
NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID = (0x83)
|
|
NV0080_CTRL_CMD_GPU_SET_VIDLINK = (0x800285)
|
|
NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID = (0x85)
|
|
NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE = (0x00000000)
|
|
NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE = (0x00000001)
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS = 0
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN = 1
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP = 2
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON = 0
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN = 1
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED = 2
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP = 3
|
|
NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE = (0x800287)
|
|
NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED = (0x00000000)
|
|
NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED = (0x00000001)
|
|
NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID = (0x87)
|
|
NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE = (0x800288)
|
|
NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID = (0x88)
|
|
NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE = (0x800289)
|
|
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE = (0x00000000)
|
|
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS = (0x00000001)
|
|
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX = (0x00000002)
|
|
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST = (0x00000003)
|
|
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU = NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST
|
|
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA = (0x00000004)
|
|
NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID = (0x89)
|
|
NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE = (0x80028c)
|
|
NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID = (0x8C)
|
|
NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE = (0x80028d)
|
|
NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID = (0x8D)
|
|
NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT = 0
|
|
NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE = 1
|
|
NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE = 2
|
|
NV0080_CTRL_CMD_GPU_GET_VGX_CAPS = (0x80028e)
|
|
NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID = (0x8E)
|
|
NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS = (0x800291)
|
|
NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID = (0x91)
|
|
NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE = 200
|
|
NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 = (0x800292)
|
|
NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID = (0x92)
|
|
NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE = (0x800293)
|
|
NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID = (0x93)
|
|
NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO = NVBIT(0)
|
|
NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS = NVBIT(1)
|
|
NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN = NVBIT(2)
|
|
NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS = (0x800294)
|
|
NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID = (0x94)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M = (1 << 6)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M = (1 << 7)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M = (1 << 8)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M = (1 << 9)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G = (1 << 10)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G = (1 << 11)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G = (1 << 12)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G = (1 << 13)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G = (1 << 14)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G = (1 << 15)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G = (1 << 16)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G = (1 << 17)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G = (1 << 18)
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN = NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX = NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G
|
|
NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID = 0x0
|
|
NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE = (0x800296)
|
|
NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID = (0x96)
|
|
NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE = (0x800297)
|
|
NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0x97)
|
|
NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE = (0x800298)
|
|
NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0x98)
|
|
NV0080_CTRL_CMD_GR_GET_CAPS = (0x801102)
|
|
NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0080_CTRL_GR_CAPS_TBL_SIZE = 23
|
|
NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS = (0x00000000)
|
|
NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 = (0x00000001)
|
|
NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK = (0x00000002)
|
|
NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT = (0x00000003)
|
|
NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT = (0x00000004)
|
|
NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE = (0x00000005)
|
|
NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT = (0x00000006)
|
|
NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT = (0x00000007)
|
|
NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR = (0x00000008)
|
|
NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT = (0x00000009)
|
|
NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT = (0x0000000A)
|
|
NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT = (0x0000000B)
|
|
NV0080_CTRL_GR_INFO_INDEX_SM_VERSION = (0x0000000C)
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM = (0x0000000D)
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP = (0x0000000E)
|
|
NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES = (0x0000000F)
|
|
NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES = (0x00000010)
|
|
NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY = (0x00000011)
|
|
NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY = (0x00000012)
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM = (0x00000013)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS = (0x00000014)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS = (0x00000015)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS = (0x00000016)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC = (0x00000017)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS = (0x00000018)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS = (0x00000019)
|
|
NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED = (0x0000001A)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS = (0x0000001B)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC = (0x0000001C)
|
|
NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT = (0x0000001D)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES = (0x0000001E)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS = (0x0000001F)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC = (0x00000020)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS = (0x00000021)
|
|
NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT = (0x00000022)
|
|
NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT = (0x00000023)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS = (0x00000024)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS = (0x00000025)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES = (0x00000026)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC = (0x00000027)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP = (0x00000028)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC = (0x00000029)
|
|
NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC = (0x0000002A)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP = (0x0000002B)
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT = (0x0000002C)
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT = (0x0000002D)
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT = (0x0000002E)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC = (0x00000032)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES = (0x00000033)
|
|
NV0080_CTRL_GR_INFO_INDEX_RESERVED = (0x00000033)
|
|
NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES = (0x00000034)
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES = (0x00000035)
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS = (0x00000036)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG = (0x00000037)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET = (0x00000038)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET = (0x00000039)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_CPC_PER_GPC = (0x0000003A)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_NVLINK_MASK = (0x0000003B)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_C2C_MASK = (0x0000003C)
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_PCIE_MASK = (0x0000003D)
|
|
NV0080_CTRL_GR_INFO_INDEX_RESERVED1 = (0x0000003E)
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX = (0x0000003E)
|
|
NV0080_CTRL_GR_INFO_MAX_SIZE = (0x3f)
|
|
NV0080_CTRL_CMD_GR_GET_INFO = (0x801104)
|
|
NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x4)
|
|
NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE = (0x801107)
|
|
NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = (0x801108)
|
|
NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x7)
|
|
NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x8)
|
|
NV0080_CTRL_CMD_GR_GET_CAPS_V2 = (0x801109)
|
|
NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x9)
|
|
NV0080_CTRL_CMD_GR_GET_INFO_V2 = (0x801110)
|
|
NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x10)
|
|
NV0080_CTRL_CMD_HOST_GET_CAPS = (0x801401)
|
|
NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0080_CTRL_HOST_CAPS_TBL_SIZE = 3
|
|
NV0080_CTRL_CMD_HOST_GET_CAPS_V2 = (0x801402)
|
|
NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE = (0x802002)
|
|
NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE = (0x802003)
|
|
NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID = (0x3)
|
|
NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL = (0x802009)
|
|
NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE = (0x802004)
|
|
NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL = (0x802007)
|
|
NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS = (0x802008)
|
|
NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS = 200
|
|
NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID = (0x08)
|
|
NV0080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED = (0x80200a)
|
|
NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID = (0x0A)
|
|
NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID = (0x45)
|
|
NV0080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR = (0x802046)
|
|
NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID = (0x46)
|
|
NV0080_CTRL_CMD_NVDEC_GET_CAPS = (0x801c01)
|
|
NV0080_CTRL_CMD_BSP_GET_CAPS = NV0080_CTRL_CMD_NVDEC_GET_CAPS
|
|
NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0080_CTRL_BSP_GET_CAPS_PARAMS = NV0080_CTRL_NVDEC_GET_CAPS_PARAMS
|
|
NV0080_CTRL_NVDEC_CAPS_TBL_SIZE = 8
|
|
NV0080_CTRL_BSP_CAPS_TBL_SIZE = NV0080_CTRL_NVDEC_CAPS_TBL_SIZE
|
|
NV0080_CTRL_CMD_NVDEC_GET_CAPS_V2 = (0x801c02)
|
|
NV0080_CTRL_CMD_BSP_GET_CAPS_V2 = NV0080_CTRL_CMD_NVDEC_GET_CAPS_V2
|
|
NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_V2_MESSAGE_ID = (0x2)
|
|
NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 = NV0080_CTRL_NVDEC_GET_CAPS_PARAMS_V2
|
|
NV0080_CTRL_CMD_NVENC_GET_CAPS = (0x801b01)
|
|
NV0080_CTRL_CMD_MSENC_GET_CAPS = NV0080_CTRL_CMD_NVENC_GET_CAPS
|
|
NV0080_CTRL_NVENC_GET_CAPS_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0080_CTRL_MSENC_GET_CAPS_PARAMS = NV0080_CTRL_NVENC_GET_CAPS_PARAMS
|
|
NV0080_CTRL_NVENC_CAPS_TBL_SIZE = 6
|
|
NV0080_CTRL_MSENC_CAPS_TBL_SIZE = NV0080_CTRL_NVENC_CAPS_TBL_SIZE
|
|
NV0080_CTRL_CMD_NVENC_GET_CAPS_V2 = (0x801b02)
|
|
NV0080_CTRL_CMD_MSENC_GET_CAPS_V2 = NV0080_CTRL_CMD_NVENC_GET_CAPS_V2
|
|
NV0080_CTRL_NVENC_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS = NV0080_CTRL_NVENC_GET_CAPS_V2_PARAMS
|
|
NV0080_CTRL_NVJPG_CAPS_TBL_SIZE = 9
|
|
NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 = (0x801f02)
|
|
NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2)
|
|
NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID = (0x7)
|
|
NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID = (0x9)
|
|
NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL = (0x801909)
|
|
NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH = (0x801e01)
|
|
NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID = (0x1)
|
|
NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE = (0x00000001)
|
|
NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE = (0x00000002)
|
|
NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED = (0x00000003)
|
|
NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO = (0x801e02)
|
|
NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_RESERVED = (0x00)
|
|
NV2080_CTRL_GPU = (0x01)
|
|
NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED = (0x81)
|
|
NV2080_CTRL_FUSE = (0x02)
|
|
NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED = (0x82)
|
|
NV2080_CTRL_EVENT = (0x03)
|
|
NV2080_CTRL_TIMER = (0x04)
|
|
NV2080_CTRL_THERMAL = (0x05)
|
|
NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED = (0xc5)
|
|
NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED = (0x85)
|
|
NV2080_CTRL_I2C = (0x06)
|
|
NV2080_CTRL_EXTI2C = (0x07)
|
|
NV2080_CTRL_BIOS = (0x08)
|
|
NV2080_CTRL_CIPHER = (0x09)
|
|
NV2080_CTRL_INTERNAL = (0x0A)
|
|
NV2080_CTRL_CLK_LEGACY_PRIVILEGED = (0xd0)
|
|
NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED = (0x90)
|
|
NV2080_CTRL_CLK = (0x10)
|
|
NV2080_CTRL_FIFO = (0x11)
|
|
NV2080_CTRL_GR = (0x12)
|
|
NV2080_CTRL_FB = (0x13)
|
|
NV2080_CTRL_NOISE = (0x15)
|
|
NV2080_CTRL_MC = (0x17)
|
|
NV2080_CTRL_BUS = (0x18)
|
|
NV2080_CTRL_PERF_LEGACY_PRIVILEGED = (0xe0)
|
|
NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED = (0xa0)
|
|
NV2080_CTRL_PERF = (0x20)
|
|
NV2080_CTRL_NVIF = (0x21)
|
|
NV2080_CTRL_RC = (0x22)
|
|
NV2080_CTRL_GPIO = (0x23)
|
|
NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED = (0xa3)
|
|
NV2080_CTRL_NVD = (0x24)
|
|
NV2080_CTRL_DMA = (0x25)
|
|
NV2080_CTRL_PMGR = (0x26)
|
|
NV2080_CTRL_PMGR_LEGACY_PRIVILEGED = (0xe6)
|
|
NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED = (0xa6)
|
|
NV2080_CTRL_POWER = (0x27)
|
|
NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED = (0xa7)
|
|
NV2080_CTRL_LPWR = (0x28)
|
|
NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED = (0xa8)
|
|
NV2080_CTRL_LPWR_LEGACY_PRIVILEGED = (0xe8)
|
|
NV2080_CTRL_ACR = (0x29)
|
|
NV2080_CTRL_CE = (0x2A)
|
|
NV2080_CTRL_SPI = (0x2B)
|
|
NV2080_CTRL_NVLINK = (0x30)
|
|
NV2080_CTRL_FLCN = (0x31)
|
|
NV2080_CTRL_VOLT = (0x32)
|
|
NV2080_CTRL_VOLT_LEGACY_PRIVILEGED = (0xf2)
|
|
NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED = (0xb2)
|
|
NV2080_CTRL_RIST = (0x33)
|
|
NV2080_CTRL_RIST_LEGACY_PRIVILEGED = (0xf3)
|
|
NV2080_CTRL_RIST_LEGACY_NON_PRIVILEGED = (0xb3)
|
|
NV2080_CTRL_ECC = (0x34)
|
|
NV2080_CTRL_ECC_NON_PRIVILEGED = (0xb4)
|
|
NV2080_CTRL_FLA = (0x35)
|
|
NV2080_CTRL_GSP = (0x36)
|
|
NV2080_CTRL_NNE = (0x37)
|
|
NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED = (0xb7)
|
|
NV2080_CTRL_GRMGR = (0x38)
|
|
NV2080_CTRL_UCODE_FUZZER = (0x39)
|
|
NV2080_CTRL_DMABUF = (0x3A)
|
|
NV2080_CTRL_BIF = (0x3B)
|
|
NV2080_CTRL_OS_WINDOWS = (0x3F)
|
|
NV2080_CTRL_OS_MACOS = (0x3E)
|
|
NV2080_CTRL_OS_UNIX = (0x3D)
|
|
NV2080_CTRL_CMD_NULL = (0x20800000)
|
|
NV2080_CTRL_CMD_BIF_DATA_PARAMS_MAX = 32
|
|
NV2080_CTRL_CMD_BIF_GET_DATA = (0x20803b01)
|
|
NV2080_CTRL_BIF_GET_DATA_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_BIOS_INFO_MAX_SIZE = (0x0000000F)
|
|
NV2080_CTRL_BIOS_INFO_INDEX_REVISION = (0x00000000)
|
|
NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION = (0x00000001)
|
|
NV2080_CTRL_CMD_BIOS_GET_INFO = (0x20800802)
|
|
NV2080_CTRL_CMD_BIOS_GET_INFO_V2 = (0x20800810)
|
|
NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x10)
|
|
NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH = (0x00000100)
|
|
NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII = (0x00000000)
|
|
NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE = (0x00000001)
|
|
NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH = (0x00000002)
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_ROOT = (0x00000000)
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_RM = (0x00000001)
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER = (0x00000002)
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO = (0x00000003)
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_CPL = (0x00000004)
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_D3D = (0x00000005)
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_OGL = (0x00000006)
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_PMU = (0x00000007)
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_MODE = (0x00000008)
|
|
NV2080_CTRL_BIOS_NBSI_NUM_MODULES = (0x00000009)
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN = (0x80000000)
|
|
NV2080_CTRL_BIOS_GET_NBSI_SUCCESS = (0x00000000)
|
|
NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE = (0x00000001)
|
|
NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH = (0xFFFFFFFA)
|
|
NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS = (0xFFFFFFFB)
|
|
NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE = (0xFFFFFFFC)
|
|
NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE = (0xFFFFFFFD)
|
|
NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE = (0xFFFFFFFE)
|
|
NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND = (0xFFFFFFFF)
|
|
NV2080_CTRL_CMD_BIOS_GET_NBSI = (0x20800803)
|
|
NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_BIOS_GET_NBSI_V2 = (0x2080080e)
|
|
NV2080_BIOS_GET_NBSI_MAX_RET_SIZE = (0x100)
|
|
NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID = (0xE)
|
|
NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ = (0x20800806)
|
|
NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID = (0x6)
|
|
GLOB_TYPE_GET_NBSI_DIR = 0xfffe
|
|
GLOB_TYPE_APITEST = 0xffff
|
|
GLOB_TYPE_GET_NBSI_ACPI_RAW = 0xfffd
|
|
NV2080_CTRL_CMD_BIOS_GET_SKU_INFO = (0x20800808)
|
|
NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID = (0x8)
|
|
NV2080_CTRL_CMD_BIOS_GET_POST_TIME = (0x20800809)
|
|
NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID = (0x9)
|
|
NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT = (0x2080080b)
|
|
NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID = (0xB)
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE = (1, 0)
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO = (0x00000000)
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES = (0x00000001)
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER = (0x00000002)
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN = (0x00000003)
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING = (2, 2)
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE = (0x00000000)
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE = (0x00000001)
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT = (3, 3)
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE = (0x00000000)
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE = (0x00000001)
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE = 32
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX = lambda _bit: ((_bit) / NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) # type: ignore
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET = lambda _bit: ((_bit) % NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) # type: ignore
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_DATA_SIZE = lambda _bits: (NV2080_CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1) + 1) # type: ignore
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE = 1
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE = lambda _bits: (NV2080_CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) - (NV2080_CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE)) # type: ignore
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_E32_FOR_EACH_INDEX__DEPRECATED = lambda _index,_pMask: NV2080_CTRL_BOARDOBJGRP_MASK_FOR_EACH_INDEX__DEPRECATED_DO_NOT_USE( NV2080_CTRL_BOARDOBJGRP_E32_MAX_OBJECTS,_index,_pMask) # type: ignore
|
|
NV2080_CTRL_BOARDOBJGRP_MASK_E255_FOR_EACH_INDEX__DEPRECATED = lambda _index,_pMask: NV2080_CTRL_BOARDOBJGRP_MASK_FOR_EACH_INDEX__DEPRECATED_DO_NOT_USE( NV2080_CTRL_BOARDOBJGRP_E255_MAX_OBJECTS,_index,_pMask) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCI_INFO = (0x20801801)
|
|
NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_BUS_INFO_INDEX_TYPE = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_INDEX_INTLINE = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_INDEX_CAPS = (0x00000002)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS = (0x00000003)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS = (0x00000004)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS = (0x00000005)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS = (0x00000006)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS = (0x00000007)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS = (0x00000008)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS = (0x00000009)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS = (0x0000000A)
|
|
NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS = (0x0000000B)
|
|
NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS = (0x0000000C)
|
|
NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE = (0x0000000D)
|
|
NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS = (0x0000000E)
|
|
NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER = (0x0000000F)
|
|
NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER = (0x00000010)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS = (0x00000011)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS = (0x00000012)
|
|
NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE = (0x00000013)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO = (0x00000014)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER = (0x00000015)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS = (0x00000016)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS = (0x00000017)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS = (0x00000018)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT = (0x00000019)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT = (0x0000001A)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM = (0x0000001B)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS = (0x0000001C)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS = (0x0000001D)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED = (0x0000001E)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS = (0x0000001F)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR = (0x00000020)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR = (0x00000021)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR = (0x00000022)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR = (0x00000023)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS = (0x00000024)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS = (0x00000025)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS = (0x00000026)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS = (0x00000027)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR = (0x00000028)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR = (0x00000029)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR = (0x0000002A)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR = (0x0000002B)
|
|
NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER = (0x0000002C)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO = (0x0000002D)
|
|
NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE = (0x0000002E)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO = (0x0000002F)
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO = (0x00000030)
|
|
NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO = (0x00000031)
|
|
NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI = (0x00000032)
|
|
NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE = (0x00000033)
|
|
NV2080_CTRL_BUS_INFO_INDEX_MAX = NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE
|
|
NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE = (0x00000034)
|
|
NV2080_CTRL_BUS_INFO_TYPE_PCI = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS = (0x00000003)
|
|
NV2080_CTRL_BUS_INFO_TYPE_FPCI = (0x00000004)
|
|
NV2080_CTRL_BUS_INFO_TYPE_AXI = (0x00000008)
|
|
NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED = (0x00000002)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED = (3, 0)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS = (0x00000002)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS = (0x00000003)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS = (0x00000004)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS = (0x00000005)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS = (0x00000006)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_WIDTH = (9, 4)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM = (11, 10)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1 = (0x00000003)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN = (15, 12)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 = (0x00000002)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 = (0x00000003)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 = (0x00000004)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6 = (0x00000005)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL = (19, 16)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 = (0x00000002)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 = (0x00000003)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 = (0x00000004)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6 = (0x00000005)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN = (23, 20)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1 = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2 = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3 = (0x00000002)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4 = (0x00000003)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5 = (0x00000004)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6 = (0x00000005)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES = (24, 24)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM = (1, 0)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1 = (0x00000002)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1 = (0x00000003)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED = (19, 16)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS = (0x00000002)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS = (0x00000003)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS = (0x00000004)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS = (0x00000005)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS = (0x00000006)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH = (25, 20)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1 = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2 = (0x00000002)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4 = (0x00000004)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8 = (0x00000008)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12 = (0x0000000C)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16 = (0x00000010)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32 = (0x00000020)
|
|
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA = (0, 0)
|
|
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART = (2, 2)
|
|
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA = (0, 0)
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART = (2, 2)
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE = (3, 3)
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH = (0, 0)
|
|
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED = (1, 1)
|
|
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR = (0x00000002)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR = (0x00000004)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST = (0x00000008)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY = (0x00000010)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP = (0, 0)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL = (1, 1)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1 = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2 = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR = (0x00000002)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP = (0x00000004)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR = (0x00000008)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT = (0x00000010)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT = (0x00000020)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL = (0x00000040)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW = (0x00000080)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP = (0x00000100)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR = (0x00000200)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ = (0x00000400)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR = (0x00010000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP = (0x00020000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP = (0x00040000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER = (0x00080000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT = (0x00100000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL = (0x00200000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE = (0, 0)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED = (1, 1)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE = (2, 2)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED = (3, 3)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04 = (4, 4)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID = (0, 0)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM = (2, 1)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 = (0x00000002)
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 = (0x00000003)
|
|
NV2080_CTRL_BUS_INFO_MSI_STATUS = (0, 0)
|
|
NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED = (0, 0)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED = (1, 1)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED = (2, 2)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED = (3, 3)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED = (4, 4)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_RESERVED = (7, 5)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PORT_RESTORE_TIME = (15, 8)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_SCALE = (17, 16)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_VALUE = (23, 19)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED = (0, 0)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED = (1, 1)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED = (2, 2)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED = (3, 3)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_COMMON_MODE_RESTORE_TIME = (15, 8)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_VALUE = (25, 16)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_SCALE = (31, 29)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_SCALE = (1, 0)
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_VALUE = (7, 3)
|
|
NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE = (0x00000000)
|
|
NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK = (0x00000001)
|
|
NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C = (0x00000002)
|
|
NV2080_CTRL_CMD_BUS_GET_INFO = (0x20801802)
|
|
NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_BUS_GET_INFO_V2 = (0x20801823)
|
|
NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x23)
|
|
NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO = (0x20801803)
|
|
NV2080_CTRL_BUS_MAX_PCI_BARS = (8)
|
|
NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH = (0x20801804)
|
|
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID = (0x4)
|
|
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE = (0x00000001)
|
|
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS = (0x00000002)
|
|
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING = (0x00000004)
|
|
NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED = (0x20801805)
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID = (0x5)
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS = (0x00000001)
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS = (0x00000002)
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS = (0x00000003)
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS = (0x00000004)
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS = (0x00000005)
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS = (0x00000006)
|
|
NV2080_CTRL_CMD_BUS_MAP_BAR2 = (0x20801809)
|
|
NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID = (0x9)
|
|
NV2080_CTRL_CMD_BUS_UNMAP_BAR2 = (0x2080180a)
|
|
NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID = (0xA)
|
|
NV2080_CTRL_CMD_BUS_VERIFY_BAR2 = (0x2080180b)
|
|
NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID = (0xB)
|
|
NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE = (0x20801812)
|
|
NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID = (0x12)
|
|
NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE = (0x00000000)
|
|
NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE = (0x00000001)
|
|
NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE = (0x00000002)
|
|
NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS = (0x20801813)
|
|
NV2080_CTRL_PEX_MAX_COUNTER_TYPES = 31
|
|
NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x13)
|
|
NV2080_CTRL_BUS_PEX_COUNTER_TYPE = 0x00000000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS = 0x00000001
|
|
NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT = 0x00000002
|
|
NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT = 0x00000004
|
|
NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT = 0x00000008
|
|
NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT = 0x00000010
|
|
NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT = 0x00000020
|
|
NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT = 0x00000040
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT = 0x00000080
|
|
NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT = 0x00000100
|
|
NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT = 0x00000200
|
|
NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT = 0x00000400
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS = 0x00000800
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT = 0x00001000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT = 0x00002000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT = 0x00004000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT = 0x00008000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT = 0x00010000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT = 0x00020000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT = 0x00040000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT = 0x00080000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT = 0x00100000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT = 0x00200000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT = 0x00400000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT = 0x00800000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT = 0x01000000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT = 0x02000000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT = 0x04000000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT = 0x08000000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT = 0x10000000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT = 0x20000000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT = 0x40000000
|
|
NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS = (0x20801814)
|
|
NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x14)
|
|
NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS = (0x20801815)
|
|
NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x15)
|
|
NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS = (0x20801816)
|
|
NV2080_CTRL_PEX_MAX_LANES = 16
|
|
NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID = (0x16)
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE = 0x00000000
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR = 0x00000001
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR = 0x00000002
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR = 0x00000004
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR = 0x00000008
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR = 0x00000010
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW = 0x00000020
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW = 0x00000040
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR = 0x00000080
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR = 0x00000100
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY = (0x20801817)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID = (0x17)
|
|
NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY = (0x20801818)
|
|
NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID = (0x18)
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES = 0x00000001
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES = 0x00000002
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0 = 0x00000004
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0 = 0x00000008
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S = 0x00000010
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S = 0x00000020
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S = 0x00000040
|
|
NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES = 7
|
|
NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS = (0x20801819)
|
|
NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID = (0x19)
|
|
NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS = (0x20801820)
|
|
NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID = (0x20)
|
|
NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS = (0x20801824)
|
|
NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID = (0x24)
|
|
NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK = (0x20801825)
|
|
NV2080_CTRL_BUS_MAX_NUM_GPUS = 32
|
|
NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID = (0x25)
|
|
NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS = (0x20801826)
|
|
NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID = (0x26)
|
|
NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE = (0x20801827)
|
|
NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID = (0x27)
|
|
NV2080_CTRL_CMD_BUS_GET_EOM_STATUS = (0x20801828)
|
|
NV2080_CTRL_BUS_MAX_NUM_LANES = 32
|
|
NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID = (0x28)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS = (0x20801829)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID = (0x29)
|
|
NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM = 0x0
|
|
NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU = 0x1
|
|
NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P = 0x2
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32 = (0, 0)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64 = (1, 1)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32 = (2, 2)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64 = (3, 3)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32 = (4, 4)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64 = (5, 5)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128 = (6, 6)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS = (0x2080182a)
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD = 0
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN = 1
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX = 2
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC = 3
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC = 4
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND = 5
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR = 6
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR = 7
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH = 8
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS = 9
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD = 10
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN = 11
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX = 12
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT = 13
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID = (0x2A)
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR = (0, 0)
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES = 1
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO = 0
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR = (1, 1)
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES = 1
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO = 0
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION = (2, 2)
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES = 1
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO = 0
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32 = (3, 3)
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES = 1
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO = 0
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64 = (4, 4)
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES = 1
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO = 0
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128 = (5, 5)
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES = 1
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO = 0
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED = (6, 6)
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES = 1
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO = 0
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED = (7, 7)
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES = 1
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO = 0
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_INFO = (0x2080182b)
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_INSTANCES = 2
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS_PER_INSTANCE = 7
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_INFO_MAX_C2C_LINKS = (0xe)
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID = (0x2B)
|
|
NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU = 1
|
|
NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU = 2
|
|
NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS = (0x2080182c)
|
|
NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID = (0x2C)
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO = (0x2080182d)
|
|
NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID = (0x2D)
|
|
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING = (0x2080182e)
|
|
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID = 0
|
|
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK = 1
|
|
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE = 2
|
|
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 = 3
|
|
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C = 4
|
|
NV2080_SET_P2P_MAPPING_UUID_LEN = 16
|
|
NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID = (0x2E)
|
|
NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING = (0x2080182f)
|
|
NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID = (0x2F)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS = (0x20801830)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID = (0x30)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32 = (0, 0)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64 = (1, 1)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32 = (2, 2)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64 = (3, 3)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32 = (4, 4)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64 = (5, 5)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128 = (6, 6)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS = (0x20801831)
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS_MESSAGE_ID = (0x31)
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER = 0x0
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 = 0x1
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 = 0x2
|
|
NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE = (0x20801832)
|
|
NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS_MESSAGE_ID = (0x32)
|
|
NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD = (0x20801836)
|
|
NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_IDLE_THRESHOLD_PARAMS_MESSAGE_ID = (0x36)
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS = (0x20801837)
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_PACKET_COUNTERS_PARAMS_MESSAGE_ID = (0x37)
|
|
NV2080_CTRL_CMD_CE_GET_CAPS = (0x20802a01)
|
|
NV2080_CTRL_CE_CAPS_TBL_SIZE = 2
|
|
NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_CMD_CE_GET_CAPS_V2 = (0x20802a03)
|
|
NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK = (0x20802a02)
|
|
NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG = (0x20802a04)
|
|
NV2080_CTRL_MAX_PCES = 64
|
|
NV2080_CTRL_MAX_GRCES = 4
|
|
NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID = (0x4)
|
|
NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS = (0x20802a05)
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID = (0x5)
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE = 0xf
|
|
NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB = (0x20802a06)
|
|
NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID = (0x6)
|
|
NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS = (0x20802a07)
|
|
NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID = (0x7)
|
|
NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x8)
|
|
NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE = (0x20802a08)
|
|
NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK = (0x20802a09)
|
|
NV2080_CTRL_CE_MAX_HSHUBS = 32
|
|
NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID = (0x9)
|
|
NV2080_CTRL_CMD_CE_GET_ALL_CAPS = (0x20802a0a)
|
|
NV2080_CTRL_MAX_CES = 64
|
|
NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID = (0xa)
|
|
NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS = (0x20802a0b)
|
|
NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID = (0xb)
|
|
NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO = (0x20802a0c)
|
|
NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID = (0xc)
|
|
NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS_V2 = (0x20802a0d)
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID = (0xd)
|
|
NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_V2 = (0x20802a0e)
|
|
NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID = (0xe)
|
|
NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE = (0x20802a0f)
|
|
NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID = (0xf)
|
|
NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK = (0x20802a11)
|
|
NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID = (0x11)
|
|
NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED = (0x20802a12)
|
|
NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID = (0x12)
|
|
NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE = (0x20802a13)
|
|
NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_MIG_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0x13)
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS = (0x20802a14)
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MIG_MAPPINGS_PARAMS_MESSAGE_ID = (0x14)
|
|
NV2080_CTRL_CLK_DOMAIN_TEGRA_UNDEFINED = (0x00000000)
|
|
NV2080_CTRL_CLK_DOMAIN_TEGRA_GPCCLK = (0x00000001)
|
|
NV2080_CTRL_CLK_DOMAIN_TEGRA_NVDCLK = (0x00000002)
|
|
NV2080_CTRL_CMD_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES = (0x20801037)
|
|
NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_SAMPLE_COUNT = (250)
|
|
NV2080_CTRL_CLK_PMUMON_CLK_DOMAINS_GET_SAMPLES_PARAMS_MESSAGE_ID = (0x37)
|
|
NV2080_CTRL_CMD_DMA_INVALIDATE_TLB = (0x20802502)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS = (0, 0)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE = (0x00000000)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE = (0x00000001)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO = (1, 1)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE = (0x00000000)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE = (0x00000001)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY = (2, 2)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE = (0x00000000)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE = (0x00000001)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE = (3, 3)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE = (0x00000000)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE = (0x00000001)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB = (4, 4)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE = (0x00000000)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE = (0x00000001)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV = (5, 5)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE = (0x00000000)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE = (0x00000001)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG = (6, 6)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE = (0x00000000)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE = (0x00000001)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD = (7, 7)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE = (0x00000000)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE = (0x00000001)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION = (8, 8)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE = (0x00000000)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE = (0x00000001)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON = (9, 9)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE = (0x00000000)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE = (0x00000001)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS = (10, 10)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE = (0x00000000)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE = (0x00000001)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR = (11, 11)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE = (0x00000000)
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE = (0x00000001)
|
|
NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE = (0x000000000)
|
|
NV2080_CTRL_DMA_INFO_INDEX_MAX = NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
|
|
NV2080_CTRL_CMD_DMA_GET_INFO = (0x20802503)
|
|
NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES = (256)
|
|
NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD = (0x20803a01)
|
|
NV2080_CTRL_DMABUF_MAX_HANDLES = 128
|
|
NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT = (0x00000000)
|
|
NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE = (0x00000001)
|
|
NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS = (0x20803400)
|
|
NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID = (0x0)
|
|
NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS = (0x20803401)
|
|
NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_ECC_SRAM_UNIQUE_UNCORR_COUNTS_MAX_COUNT = 600
|
|
NV2080_CTRL_CMD_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS = (0x20803402)
|
|
NV2080_CTRL_ECC_GET_SRAM_UNIQUE_UNCORR_COUNTS_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_ECC_ERROR_TYPE_CORRECTED = 0
|
|
NV2080_CTRL_ECC_ERROR_TYPE_UNCORRECTED = 1
|
|
NV2080_CTRL_CMD_ECC_INJECT_ERROR = (0x20803403)
|
|
NV2080_CTRL_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_ECC_GET_REPAIR_STATUS = (0x20803404)
|
|
NV2080_CTRL_ECC_GET_REPAIR_STATUS_PARAMS_MESSAGE_ID = (0x4)
|
|
NV2080_CTRL_CMD_ECC_INJECTION_SUPPORTED = (0x20803405)
|
|
NV2080_CTRL_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID = (0x5)
|
|
NV2080_CTRL_CMD_ECC_GET_UNREPAIRABLE_MEMORY_FLAG = (0x20803406)
|
|
NV2080_CTRL_ECC_GET_UNREPAIRABLE_MEMORY_FLAG_PARAMS_MESSAGE_ID = (0x6)
|
|
NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION = (0x20800301)
|
|
NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE = (0x00000000)
|
|
NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE = (0x00000001)
|
|
NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT = (0x00000002)
|
|
NV2080_EVENT_DSTATE_XUSB_D0 = (0x00000000)
|
|
NV2080_EVENT_DSTATE_XUSB_D3 = (0x00000003)
|
|
NV2080_EVENT_DSTATE_XUSB_INVALID = (0xFFFFFFFF)
|
|
NV2080_EVENT_DSTATE_PPC_D0 = (0x00000000)
|
|
NV2080_EVENT_DSTATE_PPC_D3 = (0x00000003)
|
|
NV2080_EVENT_DSTATE_PPC_INVALID = (0xFFFFFFFF)
|
|
NV2080_CTRL_CMD_EVENT_SET_TRIGGER = (0x20800302)
|
|
NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES = (0x20800303)
|
|
NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED = 0
|
|
NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING = 1
|
|
NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR = 2
|
|
NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY = (0x20800304)
|
|
NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID = (0x4)
|
|
NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI = (0x20800305)
|
|
NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID = (0x5)
|
|
NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION = (0x20800306)
|
|
NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID = (0x6)
|
|
NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO = (0x20800308)
|
|
NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID = (0x8)
|
|
NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF = (0x20800309)
|
|
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0x9)
|
|
NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF = (0x2080030a)
|
|
NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0xA)
|
|
NV2080_CTRL_CMD_EVENT_NOCAT_BIND_EVTBUF = (0x2080030b)
|
|
NV2080_CTRL_EVENT_NOCAT_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0xB)
|
|
NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT = (0x00000000)
|
|
NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE = (0x00000001)
|
|
NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE = (0x00000002)
|
|
NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT = (0x00000003)
|
|
NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT = (0x00000004)
|
|
NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE = (0x00000005)
|
|
NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT = (0x00000006)
|
|
NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE = (0x00000007)
|
|
NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE = (0x00000008)
|
|
NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE = (0x00000009)
|
|
NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE = (0x0000000A)
|
|
NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH = (0x0000000B)
|
|
NV2080_CTRL_FB_INFO_INDEX_RAM_CFG = (0x0000000C)
|
|
NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE = (0x0000000D)
|
|
NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT = (0x0000000E)
|
|
NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT = (0x0000000F)
|
|
NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB = (0x0000000F)
|
|
NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB = (0x0000000F)
|
|
NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB = (0x0000000F)
|
|
NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW = (0x0000000F)
|
|
NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB = (0x00000010)
|
|
NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB = (0x00000011)
|
|
NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB = (0x00000012)
|
|
NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB = (0x00000013)
|
|
NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK = (0x00000014)
|
|
NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE = (0x00000015)
|
|
NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE = (0x00000016)
|
|
NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION = (0x00000017)
|
|
NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN = (0x00000018)
|
|
NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT = (0x00000019)
|
|
NV2080_CTRL_FB_INFO_INDEX_FBP_MASK = (0x0000001A)
|
|
NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE = (0x0000001B)
|
|
NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID = (0x0000001C)
|
|
NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE = (0x0000001D)
|
|
NV2080_CTRL_FB_INFO_INDEX_HEAP_START = (0x0000001E)
|
|
NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE = (0x0000001F)
|
|
NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE = (0x00000020)
|
|
NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T = (0x00000021)
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT = (0x00000022)
|
|
NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT = (0x00000023)
|
|
NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE = (0x00000024)
|
|
NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE = (0x00000025)
|
|
NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE = (0x00000026)
|
|
NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE = (0x00000027)
|
|
NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED = (0x00000028)
|
|
NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE = (0x00000029)
|
|
NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT = (0x0000002A)
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK = (0x0000002B)
|
|
NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED = (0x0000002C)
|
|
NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED = (0x0000002D)
|
|
NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED = (0x0000002E)
|
|
NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED = (0x0000002F)
|
|
NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE = (0x00000030)
|
|
NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT = (0x00000031)
|
|
NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB = (0x00000032)
|
|
NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB = (0x00000033)
|
|
NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB = (0x00000034)
|
|
NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE = (0x00000035)
|
|
NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB = (0x00000036)
|
|
NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0 = (NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK)
|
|
NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1 = (0x00000037)
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0 = (NV2080_CTRL_FB_INFO_INDEX_LTC_MASK)
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 = (0x00000038)
|
|
NV2080_CTRL_FB_INFO_INDEX_ACCESS_COUNTER_BUFFER_COUNT = (0x00000039)
|
|
NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO = (0x0000003A)
|
|
NV2080_CTRL_FB_INFO_INDEX_NUMA_NODE_ID = (0x0000003B)
|
|
NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_2 = (0x0000003C)
|
|
NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_3 = (0x0000003D)
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_2 = (0x0000003E)
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_3 = (0x0000003F)
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_4 = (0x00000040)
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_5 = (0x00000041)
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_6 = (0x00000042)
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_7 = (0x00000043)
|
|
NV2080_CTRL_FB_INFO_INDEX_MAX = NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_7
|
|
NV2080_CTRL_FB_INFO_MAX_LIST_SIZE = (0x00000080)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN = (0x00000000)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM = (0x00000001)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 = (0x00000002)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 = (0x00000003)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 = NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 = (0x00000004)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 = (0x00000005)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 = (0x00000006)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 = (0x00000007)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 = NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 = (0x00000008)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 = (0x00000009)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 = (0x0000000C)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 = (0x0000000D)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 = (0x0000000E)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 = (0x0000000F)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X = (0x00000010)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 = (0x00000011)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X = (0x00000012)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 = (0x00000013)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 = (0x00000014)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7 = (0x00000015)
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_HBM4 = (0x00000016)
|
|
NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED = (0x00000000)
|
|
NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED = (0x00000001)
|
|
NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED = (0x00000002)
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG = (0x00000001)
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA = (0x00000002)
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA = (0x00000003)
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON = (0x00000004)
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA = (0x00000005)
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX = (0x00000006)
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL = (0x00000007)
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND = (0x00000008)
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT = (0x00000009)
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON = (0x0000000F)
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN = (0xFFFFFFFF)
|
|
NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED = (0x00000000)
|
|
NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED = (0x00000001)
|
|
NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED = (0x00000002)
|
|
NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO_NON_FULLY_COHERENT = (0x00000000)
|
|
NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO_FULLY_COHERENT = (0x00000001)
|
|
NV2080_CTRL_CMD_FB_GET_INFO = (0x20801301)
|
|
NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_CMD_FB_GET_INFO_V2 = (0x20801303)
|
|
NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET = (0x20801310)
|
|
NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID = (0x10)
|
|
NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED = (0x2080130c)
|
|
NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID = (0xC)
|
|
NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE = (0x00000000)
|
|
NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET = (0x00000001)
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL = (0x2080130d)
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID = (0xD)
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK = (0, 0)
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE = (1, 1)
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH = (2, 2)
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO = (0x00000000)
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE = (0x2080130e)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES = 500
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID = (0xE)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE = (1, 0)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY = (0x00000000)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY = (0x00000001)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY = (0x00000002)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK = (2, 2)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO = (0x00000000)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES = (0x00000001)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE = (3, 3)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO = (0x00000000)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES = (0x00000001)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE = (4, 4)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY = (0x00000000)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE = (0x00000001)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH = (5, 5)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO = (0x00000000)
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_FB_IS_KIND = (0x20801313)
|
|
NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID = (0x13)
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED = (0x00000000)
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE = (0x00000001)
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 = (0x00000002)
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 = (0x00000003)
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 = (0x00000004)
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC = (0x00000005)
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 = (0x00000006)
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 = (0x00000007)
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 = (0x00000008)
|
|
NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO = (0x20801315)
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID = (0x15)
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED = (0x00000000)
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED = (0x00000001)
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH = (0x00000000)
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK = (0x00000001)
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED = (0x00000000)
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED = (0x00000001)
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL = (0x00000000)
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING = (0x00000001)
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED = (0x00000002)
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE = (0x00000003)
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO = (0x20801320)
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES = 18
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES = 16
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID = (0x20)
|
|
NV2080_CTRL_CMD_FB_OFFLINE_PAGES = (0x20801321)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES = (0x00000040)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS = (0xffffffffffffffff)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K = (0x00000000)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K = (0x00000001)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K = (0x00000002)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE = (0x00000002)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE = (0x00000004)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK = (0x00000000)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT = (0x00000001)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED = (0x00000002)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL = (0x00000003)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR = (0x00000004)
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE = NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE = NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE
|
|
NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID = (0x21)
|
|
NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES = (0x20801322)
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE = (0, 0)
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE = 0
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE = 1
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE = (1, 1)
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE = 0
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE = 1
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x22)
|
|
NV2080_CTRL_CMD_FB_QUERY_ACR_REGION = (0x20801325)
|
|
NV2080_CTRL_CMD_FB_ACR_CLIENT_ID = 2
|
|
NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID = (0x25)
|
|
NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES = (0x20801326)
|
|
NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x26)
|
|
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO = (0x20801327)
|
|
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID = (0x27)
|
|
NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP = (0x20801328)
|
|
NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID = (0x28)
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT = (0x20801329)
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS = (0x2080132a)
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS = (0x2080132b)
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB = (0x2080132c)
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB = (0x2080132d)
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 = (0x20801335)
|
|
NV2080_CTRL_CMD_FB_GET_AMAP_CONF = (0x20801336)
|
|
NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID = (0x36)
|
|
NV2080_CTRL_CMD_FB_CBC_OP = (0x20801337)
|
|
NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID = (0x37)
|
|
NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION = (0x20801338)
|
|
NV2080_MAX_CTAGS_FOR_CBC_EVICTION = 0x7F
|
|
NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID = (0x38)
|
|
NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE = (0x20801339)
|
|
NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID = (0x39)
|
|
NV2080_CTRL_CMD_FB_FREE_TILE = (0x2080133a)
|
|
NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID = (0x3A)
|
|
NV2080_CTRL_CMD_FB_SETUP_VPR_REGION = (0x2080133b)
|
|
NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID = (0x3B)
|
|
NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES = (0x2080133c)
|
|
NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x3C)
|
|
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO = (0x2080133d)
|
|
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID = (0x3D)
|
|
NV2080_CTRL_CMD_FB_SET_RRD = (0x2080133e)
|
|
NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID = (0x3E)
|
|
NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE = (0xff)
|
|
NV2080_CTRL_CMD_FB_SET_READ_LIMIT = (0x2080133f)
|
|
NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE = NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE
|
|
NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID = (0x3F)
|
|
NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT = (0x20801340)
|
|
NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE = NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE
|
|
NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID = (0x40)
|
|
NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING = (0x20801341)
|
|
NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID = (0x41)
|
|
NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT = (0x20801342)
|
|
NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID = (0x42)
|
|
NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR = (0x20801343)
|
|
NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x43)
|
|
NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING = (0, 0)
|
|
NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE = 0
|
|
NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE = 1
|
|
NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_ACTIVE = (1, 1)
|
|
NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_ACTIVE_FALSE = 0
|
|
NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_ACTIVE_TRUE = 1
|
|
NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD = (0x00000002)
|
|
NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD = (0x00000003)
|
|
NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS = (0x00000200)
|
|
NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS = (0x20801344)
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING = NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE = NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE = NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE = (1, 1)
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE = 0
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE = 1
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID = (0x44)
|
|
NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE = 24
|
|
NV2080_CTRL_FB_FS_INFO_INVALID_QUERY = 0x0
|
|
NV2080_CTRL_FB_FS_INFO_FBP_MASK = 0x1
|
|
NV2080_CTRL_FB_FS_INFO_LTC_MASK = 0x2
|
|
NV2080_CTRL_FB_FS_INFO_LTS_MASK = 0x3
|
|
NV2080_CTRL_FB_FS_INFO_FBPA_MASK = 0x4
|
|
NV2080_CTRL_FB_FS_INFO_ROP_MASK = 0x5
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK = 0x6
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK = 0x7
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK = 0x8
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK = 0x9
|
|
NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK = 0xA
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK = 0xB
|
|
NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP = 0xC
|
|
NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK = 0xD
|
|
NV2080_CTRL_FB_FS_INFO_PAC_MASK = 0xE
|
|
NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK = 0xF
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK = 0x10
|
|
NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK = 0x11
|
|
NV2080_CTRL_FB_FS_INFO_SYS_MASK = 0x12
|
|
NV2080_CTRL_FB_FS_INFO_MAX_QUERIES = 120
|
|
NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID = (0x46)
|
|
NV2080_CTRL_CMD_FB_GET_FS_INFO = (0x20801346)
|
|
NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS = (0x0)
|
|
NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW = (0x1)
|
|
NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS = (0x2)
|
|
NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW = (0x3)
|
|
NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS = (0x4)
|
|
NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID = (0x47)
|
|
NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM = (0x20801347)
|
|
NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES = (0x20801348)
|
|
NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES = 512
|
|
NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES = 64
|
|
NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x48)
|
|
NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID = (0x00000000)
|
|
NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE = (0x00000001)
|
|
NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO = (0x20801349)
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE = (4, 0)
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM = 0
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM = 1
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED = (5, 5)
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE = 0
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE = 1
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER = (6, 6)
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE = 0
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE = 1
|
|
NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID = (0x49)
|
|
NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS = (0x20801350)
|
|
NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID = (0x50)
|
|
NV2080_CTRL_CMD_FB_GET_NUMA_INFO = (0x20801351)
|
|
NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES = 64
|
|
NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID = (0x51)
|
|
NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT = (0x20801352)
|
|
NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED = (0x00000001)
|
|
NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED = (0x00000002)
|
|
NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID = (0x52)
|
|
NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE = (0x20801353)
|
|
NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID = (0x53)
|
|
NV2080_CTRL_CMD_FB_STATS_MAX_OWNER = 201
|
|
NV2080_CTRL_CMD_RM_FB_STATS_ENTRY_MESSAGE_ID = (0x2A)
|
|
NV2080_CTRL_CMD_FB_STATS_GET = (0x2080132f)
|
|
NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID = (0x2F)
|
|
NV2080_CTRL_CMD_GSP_FB_STATS_GET = (0x2080132a)
|
|
NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO = (0x20801354)
|
|
NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID = (0x54)
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION = (0x20801355)
|
|
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_DISABLED = (0x00000000)
|
|
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_ENABLED = (0x00000001)
|
|
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID = (0x55)
|
|
NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION = (0x20801356)
|
|
NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_DISABLE = (0x00000000)
|
|
NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_ENABLE = (0x00000001)
|
|
NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID = (0x56)
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT = (0x20801357)
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED = (0x00000000)
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED = (0x00000001)
|
|
NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID = (0x57)
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS = (0x20801358)
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED = (0x00000000)
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED = (0x00000001)
|
|
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID = (0x58)
|
|
NV2080_CTRL_CMD_FB_GET_MEMORY_BOOT_TRAINING_FLAGS = (0x20801359)
|
|
NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS_MESSAGE_ID = (0x59)
|
|
NV2080_CTRL_CMD_FB_GET_CARVEOUT_REGION_INFO = (0x20801360)
|
|
NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_MAX_ENTRIES = 8
|
|
NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS_MESSAGE_ID = (0x60)
|
|
NV2080_CTRL_FB_REMAPPED_BANK_SOURCE_FIELD = (0x00000002)
|
|
NV2080_CTRL_FB_REMAPPED_BANKS_MAX_BANKS = (0x00000200)
|
|
NV2080_CTRL_CMD_FB_GET_REMAPPED_BANKS = (0x20801361)
|
|
NV2080_CTRL_FB_GET_REMAPPED_BANKS_FLAGS_PENDING = (0, 0)
|
|
NV2080_CTRL_FB_GET_REMAPPED_BANKS_FLAGS_PENDING_FALSE = 0
|
|
NV2080_CTRL_FB_GET_REMAPPED_BANKS_FLAGS_PENDING_TRUE = 1
|
|
NV2080_CTRL_FB_GET_REMAPPED_BANKS_PARAMS_MESSAGE_ID = (0x61)
|
|
NV2080_CTRL_CMD_FB_GET_UGPU_MEMORY_INFO = (0x20801362)
|
|
NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_MAX_UGPUS = 2
|
|
NV2080_CTRL_FB_GET_UGPU_MEMORY_INFO_PARAMS_MESSAGE_ID = (0x62)
|
|
NV2080_CTRL_CMD_FB_GET_CPU_COHERENT_RANGE = (0x20801363)
|
|
NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS_MESSAGE_ID = (0x63)
|
|
NV2080_CTRL_CMD_FB_GET_WPR_REGION_INFO = (0x20801364)
|
|
NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS_MESSAGE_ID = (0x64)
|
|
NV2080_CTRL_CMD_SET_GPFIFO = (0x20801102)
|
|
NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT = (0x20801108)
|
|
NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID = (0x8)
|
|
NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL = (0x000000000)
|
|
NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS = (0x000000001)
|
|
NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP = (0x000000002)
|
|
NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP = (0x000000003)
|
|
NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET = (0x000000004)
|
|
NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE = (0x000000005)
|
|
NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE = (0x000000006)
|
|
NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED = (0x000000007)
|
|
NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE = (0x000000008)
|
|
NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE = (0x000000009)
|
|
NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT = (0x00000000a)
|
|
NV2080_CTRL_FIFO_INFO_INDEX_MAX = NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT
|
|
NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT = (12)
|
|
NV2080_CTRL_CMD_FIFO_GET_INFO = (0x20801109)
|
|
NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES = (256)
|
|
NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID = (0x9)
|
|
NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL = (0x2080110a)
|
|
NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID = (0xA)
|
|
NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS = (0x2080110b)
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES = (64)
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID = (0xB)
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE = (0x00000000)
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE = (0x00000001)
|
|
NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE = (0x00000000)
|
|
NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE = (0x00000001)
|
|
NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT = 0x2
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO = (0x2080110c)
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID = (0xC)
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID = 0x00000000
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM = 0x00000001
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH = 0x00000002
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH = 0x00000003
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION = (0x2080110d)
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID = (0xD)
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM = 0x00000000
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM = 0x00000001
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED = 0x00000000
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED = 0X00000001
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED = 0X00000002
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN = 0
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER = 1
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT = 2
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE = 3
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE = 4
|
|
NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT = 3
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT = 0
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE = 1
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE = 2
|
|
NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG = (0x2080110e)
|
|
NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT = 32
|
|
NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS = 8
|
|
NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES = 200
|
|
NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID = (0xE)
|
|
NV2080_CTRL_CMD_FIFO_CONFIG_CTXSW_TIMEOUT = (0x20801110)
|
|
NV2080_CTRL_FIFO_CONFIG_CTXSW_TIMEOUT_PARAMS_MESSAGE_ID = (0x10)
|
|
NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE = (0x20801112)
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES = 256
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES = 32
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES = 16
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA = 2
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN = 16
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID = (0x12)
|
|
NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT = (0x20801113)
|
|
NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE = 0x00000001
|
|
NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA = 0x00000002
|
|
NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID = (0x13)
|
|
NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY = (0x20801115)
|
|
NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT = 0x0
|
|
NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED = 0x1
|
|
NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM = 0x2
|
|
NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE = (0, 0)
|
|
NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE = (0x00000000)
|
|
NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE = (0x00000001)
|
|
NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID = (0x15)
|
|
NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO = (0x20801116)
|
|
NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID = (0x16)
|
|
NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS = (0x20801117)
|
|
NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID = (0x17)
|
|
NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB = (0x20801118)
|
|
NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID = (0x18)
|
|
NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS = (0x20801119)
|
|
NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS = 4096
|
|
NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID = (0x19)
|
|
NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION = (0x2080111a)
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES = (64)
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID = (0x1A)
|
|
NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 = (0x2080111b)
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID = (0x1B)
|
|
NV2080_CTRL_CMD_FIFO_ROTATE_KEYS = (0x2080111c)
|
|
NV2080_CTRL_CMD_FIFO_ROTATE_KEYS_PARAMS_MESSAGE_ID = (0x1C)
|
|
NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE = (0x20801120)
|
|
NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID = (0x20)
|
|
NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE = (0x20801121)
|
|
NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID = (0x21)
|
|
NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS = (0x20801122)
|
|
NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID = (0x22)
|
|
NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG = 128
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO = (0x20801123)
|
|
NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID = (0x23)
|
|
NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID = (0x20801124)
|
|
NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID = (0x24)
|
|
NV2080_CTRL_CMD_FLA_RANGE = (0x20803501)
|
|
NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE = 0x00000000
|
|
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE = NVBIT(0)
|
|
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY = NVBIT(1)
|
|
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE = NVBIT(2)
|
|
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY = NVBIT(3)
|
|
NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK = (0x20803502)
|
|
NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_FLA_GET_RANGE = (0x20803503)
|
|
NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS = (0x20803504)
|
|
NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID = (0x4)
|
|
FALCON_ID_PMU = (NV2080_ENGINE_TYPE_PMU)
|
|
FALCON_ID_DPU = (NV2080_ENGINE_TYPE_DPU)
|
|
FALCON_ID_SEC2 = (NV2080_ENGINE_TYPE_SEC2)
|
|
FALCON_ID_FBFLCN = (NV2080_ENGINE_TYPE_FBFLCN)
|
|
NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE = (0x20803101)
|
|
NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE = 0x00
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END = 0x01
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN = 0x02
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END = 0x03
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK = 0x04
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN = 0x05
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END = 0x06
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY = 0x07
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT = 0x08
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0 = 0x09
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END = 0x0A
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN = 0x0B
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END = 0x0C
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY = 0x0D
|
|
NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID = 0xFF
|
|
NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH = (0x20803118)
|
|
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID = (0x18)
|
|
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT = 0x0
|
|
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON = 0x1
|
|
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV = 0x2
|
|
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB = 0x3
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_FLAG = (31, 31)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_HEAD = (30, 30)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_VARIABLE = (29, 29)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EXTEND = (28, 28)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT = (27)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE = (20)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT = (28)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE = (24)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_LENGTH = (19, 8)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOAD = (7, 0)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT = (23, 0)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_HEAD_TIME = (29, 0)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_DATA_PAYLOAD = (30, 0)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_TASK_ID = (7, 0)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON = (10, 8)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD = 0x0
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0 = 0x1
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK = 0x2
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK = 0x3
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED = 0x4
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_ODP_MISS_COUNT = (23, 11)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TIMER_TICK_TIME_SLIP = (23, 0)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_TASK_ID = (7, 0)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_UNIT_ID = (15, 8)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE = (23, 16)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID = (7, 0)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CALLBACK_ID = (15, 8)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC = (15, 8)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE = 0xF0
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID = (23, 16)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT = 10
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_TASK_ID = (7, 0)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID = (23, 8)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED = 0x000000
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL = 0x000001
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT = 6
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID = (11, 0)
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID = 0x000
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL = 0x001
|
|
NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT = 0
|
|
NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT = 1
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH = (0, 0)
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED = 0
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED = 1
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH = (1, 1)
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED = 0
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED = 1
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH = (2, 2)
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED = 0
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED = 1
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_THRESHOLD = (31, 8)
|
|
NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT = (0x20)
|
|
NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES = (0x120)
|
|
NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES = (0x24)
|
|
NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO = (0x20803120)
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID = (0x20)
|
|
NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET = (0x20803122)
|
|
NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET = (0x20803123)
|
|
NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID = (0x22)
|
|
NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID = (0x23)
|
|
NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO = (0x20803124)
|
|
NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x24)
|
|
NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE = (0x20803125)
|
|
NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x25)
|
|
NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION = (0x20802300)
|
|
NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID = (0x00)
|
|
NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT = (0x20802301)
|
|
NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID = (0x01)
|
|
NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT = (0x20802302)
|
|
NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID = (0x02)
|
|
NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION = (0x20802303)
|
|
NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID = (0x03)
|
|
NV_GRID_LICENSE_INFO_MAX_LENGTH = (128)
|
|
NV_GRID_LICENSE_FEATURE_VPC_EDITION = "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0"
|
|
NV_GRID_LICENSE_FEATURE_VAPPS_EDITION = "GRID-Virtual-Apps,3.0"
|
|
NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION = "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0"
|
|
NV_GRID_LICENSE_FEATURE_GAMING_EDITION = "GRID-vGaming,8.0"
|
|
NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION = "NVIDIA-vComputeServer,9.0"
|
|
NV_GRID_LICENSED_PRODUCT_VWS = "NVIDIA RTX Virtual Workstation"
|
|
NV_GRID_LICENSED_PRODUCT_GAMING = "NVIDIA Cloud Gaming"
|
|
NV_GRID_LICENSED_PRODUCT_VPC = "NVIDIA Virtual PC"
|
|
NV_GRID_LICENSED_PRODUCT_VAPPS = "NVIDIA Virtual Applications"
|
|
NV_GRID_LICENSED_PRODUCT_COMPUTE = "NVIDIA Virtual Compute Server"
|
|
NV_GRID_LICENSED_PRODUCT_VGPU_FOR_COMPUTE = "NVIDIA vGPU for Compute"
|
|
NV2080_CTRL_GPU_INFO_INDEX_INDEX = (23, 0)
|
|
NV2080_CTRL_GPU_INFO_INDEX_ECID_LO32 = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_ECID_HI32 = (0x00000002)
|
|
NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT = (0x00000004)
|
|
NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 = (0x00000012)
|
|
NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 = (0x00000013)
|
|
NV2080_CTRL_GPU_INFO_INDEX_ECID_EXTENDED = (0x0000001b)
|
|
NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS = (0x0000001f)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD = (0x00000022)
|
|
NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE = (0x00000025)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED = (0x00000027)
|
|
NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED = (0x00000028)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT = (0x00000029)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE = (0x0000002a)
|
|
NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM = (0x0000002b)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION = (0x0000002c)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY = (0x0000002d)
|
|
NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM = (0x0000002f)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY = (0x00000030)
|
|
NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE = (0x00000031)
|
|
NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED = (0x00000034)
|
|
NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED = (0x00000035)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY = (0x00000036)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY = (0x00000037)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY = (0x0000003a)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY = (0x0000003b)
|
|
NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU = (0x0000003c)
|
|
NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY = (0x0000003d)
|
|
NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED = (0x0000003f)
|
|
NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED = (0x00000041)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_NON_PASID_ATS_CAPABILITY = (0x00000042)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_SYSMEM_CAPABILITY = (0x00000043)
|
|
NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE = (0x00000044)
|
|
NV2080_CTRL_GPU_INFO_INDEX_COMPR_BIT_BACKING_COPY_TYPE = (0x00000045)
|
|
NV2080_CTRL_GPU_INFO_INDEX_CPU_COHERENT_CACHING_GPU_MEMORY_CAPABILITY = (0x00000046)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_COHERENT_CACHING_CPU_MEMORY_CAPABILITY = (0x00000047)
|
|
NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE = (0x00000048)
|
|
NV2080_CTRL_GPU_INFO_INDEX_TYPE = (30, 28)
|
|
NV2080_CTRL_GPU_INFO_INDEX_TYPE_SPECIFIC_ID = (27, 24)
|
|
NV2080_CTRL_GPU_INFO_INDEX_RESERVED = (31, 31)
|
|
NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V = (0x00000002)
|
|
NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV = (0x00000003)
|
|
NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED = (0x00000002)
|
|
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING = (0x00000003)
|
|
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING = (0x00000004)
|
|
NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED = (0x00000002)
|
|
NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_PEERID = (31, 1)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_NON_PASID_ATS_CAPABILITY_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_NON_PASID_ATS_CAPABILITY_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_SYSMEM_CAPABILITY_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_SYSMEM_CAPABILITY_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_NONE = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_NUMA = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_COHERENT_GPU_MEMORY_MODE_DRIVER = (0x00000002)
|
|
NV2080_CTRL_GPU_INFO_INDEX_COMP_BIT_BACKING_COPY_TYPE_PHYSICAL = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_COMP_BIT_BACKING_COPY_TYPE_VIRTUAL = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_CPU_COHERENT_CACHING_GPU_MEMORY_CAPABILITY_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_CPU_COHERENT_CACHING_GPU_MEMORY_CAPABILITY_YES = (0x00000001)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_COHERENT_CACHING_CPU_MEMORY_CAPABILITY_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_COHERENT_CACHING_CPU_MEMORY_CAPABILITY_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_GPU_GET_INFO = (0x20800101)
|
|
NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_CMD_GPU_GET_INFO_V2 = (0x20800102)
|
|
NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_GPU_GET_NAME_STRING = (0x20800110)
|
|
NV2080_GPU_MAX_NAME_STRING_LENGTH = (0x0000040)
|
|
NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE = (31, 0)
|
|
NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII = (0x00000000)
|
|
NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID = (0x10)
|
|
NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING = (0x20800111)
|
|
NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID = (0x11)
|
|
NV2080_CTRL_CMD_GPU_SET_POWER = (0x20800112)
|
|
NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID = (0x12)
|
|
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 = (0x00000000)
|
|
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1 = (0x00000001)
|
|
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2 = (0x00000002)
|
|
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 = (0x00000003)
|
|
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 = (0x00000004)
|
|
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 = (0x00000007)
|
|
NV2080_CTRL_CMD_GPU_GET_SDM = (0x20800118)
|
|
NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID = (0x18)
|
|
NV2080_CTRL_CMD_GPU_SET_SDM = (0x20800120)
|
|
NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID = (0x20)
|
|
NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO = (0x20800119)
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID = (0x19)
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE = (0x00000000)
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL = (0x00000001)
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL = (0x00000002)
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL = (0x00000003)
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL = (0x00000004)
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU = (0x00000005)
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER = (0x00000006)
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA = (0x00000007)
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL = (0x00000008)
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL = (0x00000009)
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN = (0xFFFFFFFF)
|
|
NV2080_CTRL_GPU_REG_OP_READ_32 = (0x00000000)
|
|
NV2080_CTRL_GPU_REG_OP_WRITE_32 = (0x00000001)
|
|
NV2080_CTRL_GPU_REG_OP_READ_64 = (0x00000002)
|
|
NV2080_CTRL_GPU_REG_OP_WRITE_64 = (0x00000003)
|
|
NV2080_CTRL_GPU_REG_OP_READ_08 = (0x00000004)
|
|
NV2080_CTRL_GPU_REG_OP_WRITE_08 = (0x00000005)
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL = (0x00000000)
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX = (0x00000001)
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC = (0x00000002)
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM = (0x00000004)
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP = (0x00000008)
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP = (0x00000010)
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_FB = (0x00000020)
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD = (0x00000040)
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE = (0x00000080)
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS = (0x00)
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP = (0x01)
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE = (0x02)
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET = (0x04)
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP = (0x08)
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK = (0x10)
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS = (0x20)
|
|
NV2080_CTRL_CMD_GPU_EXEC_REG_OPS = (0x20800122)
|
|
NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0x22)
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINES = (0x20800123)
|
|
NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID = (0x23)
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 = (0x20800170)
|
|
NV2080_GPU_MAX_ENGINES_LIST_SIZE = 0x54
|
|
NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID = (0x70)
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST = (0x20800124)
|
|
NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID = (0x24)
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO = (0x20800125)
|
|
NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID = (0x25)
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN = 0
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM = 1
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH = 2
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB = 3
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL = 4
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB = 5
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL = 6
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL = 7
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK = 8
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT = 9
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP = 10
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP = 11
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP = 12
|
|
NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES = 16
|
|
NV2080_CTRL_CMD_GPU_PROMOTE_CTX = (0x2080012b)
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID = (0x2B)
|
|
NV2080_CTRL_CMD_GPU_EVICT_CTX = (0x2080012c)
|
|
NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID = (0x2C)
|
|
NV2080_CTRL_CMD_GPU_INITIALIZE_CTX = (0x2080012d)
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID = (0x2D)
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE = (1, 0)
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM = (0x00000000)
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS = (0x00000001)
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS = (0x00000002)
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE = (2, 2)
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES = (0x00000000)
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO = (0x00000001)
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX = (3, 3)
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO = (0x00000000)
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES = (0x00000001)
|
|
NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR = (0x2080012e)
|
|
NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS = (0x2080012f)
|
|
NV2080_CTRL_GPU_ECC_UNIT_GSP = (0x0000001D)
|
|
NV2080_CTRL_GPU_ECC_UNIT_COUNT = (0x00000029)
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE = (0, 0)
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED = (0x00000000)
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW = (0x00000001)
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE = 0
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE = 1
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE = 2
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID = (0x2F)
|
|
NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES = (0x20800130)
|
|
NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE = (0x00000000)
|
|
NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE = (0x00000001)
|
|
NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED = (0x00000002)
|
|
NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS = (0x00000003)
|
|
NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID = (0x30)
|
|
NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES = (0x20800131)
|
|
NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID = (0x31)
|
|
NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION = (0x20800133)
|
|
NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED = (0x00000000)
|
|
NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED = (0x00000001)
|
|
NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID = (0x33)
|
|
NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION = (0x20800134)
|
|
NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE = (0x00000000)
|
|
NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE = (0x00000001)
|
|
NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID = (0x34)
|
|
NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS = (0x20800136)
|
|
NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE = (0x00000000)
|
|
NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE = (0x00000001)
|
|
NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE = (0x00000002)
|
|
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE = (0, 0)
|
|
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE = 0
|
|
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE = 1
|
|
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID = (0x36)
|
|
NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO = (0x20800137)
|
|
NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID = (0x37)
|
|
NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO = (0x20800138)
|
|
NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID = (0x38)
|
|
NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO = (0x20800139)
|
|
NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x39)
|
|
NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO = (0x2080013f)
|
|
NV2080_GPU_MAX_MARKETING_NAME_LENGTH = (0x00000018)
|
|
NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH = (0x00000010)
|
|
NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH = (0x00000014)
|
|
NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH = (0x00000006)
|
|
NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH = (0x00000014)
|
|
NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID = (0x3F)
|
|
NV2080_CTRL_CMD_GPU_GET_ID = (0x20800142)
|
|
NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID = (0x42)
|
|
NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE = (0x20800143)
|
|
NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID = (0x43)
|
|
NV2080_CTRL_GPU_DEBUG_MODE_ENABLED = (0x00000001)
|
|
NV2080_CTRL_GPU_DEBUG_MODE_DISABLED = (0x00000002)
|
|
NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE = (0x20800144)
|
|
NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID = (0x44)
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST = (0x20800147)
|
|
NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS = (0x00000020)
|
|
NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID = (0x47)
|
|
NV2080_CTRL_CMD_GPU_GET_GID_INFO = (0x2080014a)
|
|
NV2080_GPU_MAX_GID_LENGTH = (0x000000100)
|
|
NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH = (0x000000010)
|
|
NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID = (0x4A)
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT = (1, 0)
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII = (0x00000000)
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY = (0x00000002)
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE = (2, 2)
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 = (0x00000000)
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_MODE = (5, 3)
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_MODE_GPU = (0x00000000)
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_MODE_UGPU = (0x00000001)
|
|
NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION = (0x2080014b)
|
|
NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN = 3
|
|
NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID = (0x4B)
|
|
NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO = (0x2080014c)
|
|
NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID = (0x4C)
|
|
NV2080_CTRL_CMD_GPU_GET_IP_VERSION = (0x2080014d)
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID = (0x4D)
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY = (0x00000001)
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC = (0x00000002)
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_PMGR = (0x00000003)
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU = (0x00000004)
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON = (0x00000005)
|
|
NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS = 0
|
|
NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS = 1
|
|
NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT = (0x20800153)
|
|
NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID = (0x53)
|
|
NV2080_CTRL_CMD_GPU_GET_ILLUM = (0x20800154)
|
|
NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID = (0x54)
|
|
NV2080_CTRL_CMD_GPU_SET_ILLUM = (0x20800155)
|
|
NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID = (0x55)
|
|
NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION = (0x20800156)
|
|
NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN = 16
|
|
NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID = (0x56)
|
|
NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT = (0x20800157)
|
|
NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO = (0x2080015a)
|
|
NV2080_CTRL_MAX_PHYSICAL_BRIDGE = (100)
|
|
NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID = (0x5A)
|
|
NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU = (0x2080015b)
|
|
NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID = (0x5B)
|
|
NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS = (0x2080015f)
|
|
NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID = (0x5F)
|
|
NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING = (0x00000000)
|
|
NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE = (0x00000001)
|
|
NV2080_CTRL_CMD_GPU_GET_VPR_CAPS = (0x20800160)
|
|
NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID = (0x60)
|
|
NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR = (0x20800167)
|
|
NV2080_CTRL_CMD_GPU_GET_PES_INFO = (0x20800168)
|
|
NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT = 10
|
|
NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID = (0x68)
|
|
NV2080_CTRL_CMD_GPU_GET_OEM_INFO = (0x20800169)
|
|
NV2080_GPU_MAX_OEM_INFO_LENGTH = (0x000001F8)
|
|
NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID = (0x69)
|
|
NV2080_CTRL_CMD_GPU_GET_VPR_INFO = (0x2080016b)
|
|
NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID = (0x6B)
|
|
NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY = (0x2080016c)
|
|
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID = (0x6C)
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS = (0x2080016d)
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID = (0x6D)
|
|
NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES = 0x200
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID = (0x6E)
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO = (0x2080016e)
|
|
NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x6F)
|
|
NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR = (0x2080016f)
|
|
NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID = (0x72)
|
|
NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT = (0x20800172)
|
|
NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID = (0x73)
|
|
NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS = (0x20800173)
|
|
NV_GI_UUID_LEN = 16
|
|
NV2080_CTRL_GPU_PARTITION_ID_INVALID = 0xFFFFFFFF
|
|
NV2080_CTRL_GPU_MAX_PARTITIONS = 0x00000008
|
|
NV2080_CTRL_GPU_MAX_PARTITION_IDS = 0x00000009
|
|
NV2080_CTRL_GPU_MAX_SMC_IDS = 0x00000008
|
|
NV2080_CTRL_GPU_MAX_GPC_PER_SMC = 0x00000040
|
|
NV2080_CTRL_GPU_MAX_CE_PER_SMC = 0x00000008
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE = (1, 0)
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL = 0x00000000
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF = 0x00000001
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER = 0x00000002
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH = 0x00000003
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE = 4
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE = (4, 2)
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL = 0x00000000
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF = 0x00000001
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF = 0x00000002
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER = 0x00000003
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER = 0x00000004
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH = 0x00000005
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_06 = 0x00000006
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07 = 0x00000007
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE = 8
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE = (7, 5)
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL = 0x00000001
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF = 0x00000002
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF = 0x00000003
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER = 0x00000004
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH = 0x00000005
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_06 = 0x00000006
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_07 = 0x00000007
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE = 0x00000000
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE = 8
|
|
NV2080_CTRL_GPU_PARTITION_MAX_TYPES = 90
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA = (29, 28)
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_DEFAULT = 0
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_DISABLE = 1
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_ENABLE = 2
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA = (30, 30)
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE = 0
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE = 1
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN = (31, 31)
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE = 0
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE = 1
|
|
NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID = (0x74)
|
|
NV2080_CTRL_CMD_GPU_SET_PARTITIONS = (0x20800174)
|
|
NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID = (0x75)
|
|
NV2080_CTRL_CMD_GPU_GET_PARTITIONS = (0x20800175)
|
|
NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION = (0x20800176)
|
|
NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID = (0x76)
|
|
NV2080_CTRL_GPU_FAULT_PACKET_SIZE = 32
|
|
NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT = (0x20800177)
|
|
NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID = (0x77)
|
|
NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU = (0x20800178)
|
|
NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID = (0x78)
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE = (0x20800179)
|
|
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID = (0x79)
|
|
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL = (0xFFFFFFFF)
|
|
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR = (0xFFFFFFFB)
|
|
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_INVALID = (0xFFFFFFFF)
|
|
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_ERROR = (0xFFFFFFFB)
|
|
NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID = (0x2080017a)
|
|
NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID = (0x7A)
|
|
NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL = (0xFFFFFFFF)
|
|
NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR = (0xFFFFFFFB)
|
|
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS = (0x2080017b)
|
|
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID = (0x7B)
|
|
NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED = 0x00000001
|
|
NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED = 0x00000002
|
|
NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT = 0x00000004
|
|
NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE = 0x00000008
|
|
NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT = 0x00000010
|
|
NV2080_GPU_NVFBC_MAX_SESSION_COUNT = 256
|
|
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID = (0x7C)
|
|
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO = (0x2080017c)
|
|
NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID = (0xe6)
|
|
NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX = (0x208001e6)
|
|
NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE = (0x2080017e)
|
|
NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID = (0x7E)
|
|
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB = 0x02000000
|
|
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB = 0x04000000
|
|
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB = 0x08000000
|
|
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB = 0x10000000
|
|
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB = 0x20000000
|
|
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_1024MB = 0x40000000
|
|
NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY = (0x20800181)
|
|
NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID = (0x81)
|
|
NV2080_CTRL_CMD_GPU_GET_CACHED_INFO = (0x20800182)
|
|
NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID = (0x82)
|
|
NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE = (0x20800183)
|
|
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING = (1, 0)
|
|
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY = 0
|
|
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF = 1
|
|
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG = 2
|
|
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID = (0x83)
|
|
NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID = (0x85)
|
|
NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS = (0x20800185)
|
|
NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE = (0x20800188)
|
|
NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID = (0x88)
|
|
NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID = (0x8A)
|
|
NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC = (0x2080018a)
|
|
NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID = (0x8B)
|
|
NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS = (0x2080018b)
|
|
NV2080_CTRL_CMD_GPU_GET_PIDS = (0x2080018d)
|
|
NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT = 950
|
|
NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID = (0x8D)
|
|
NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS = (0x00000000)
|
|
NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST = (0x00000001)
|
|
NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE = (0x00000000)
|
|
NV2080_CTRL_GPU_PID_INFO_INDEX_MAX = NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE
|
|
NV2080_CTRL_CMD_GPU_GET_PID_INFO = (0x2080018e)
|
|
NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT = 200
|
|
NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID = (0x8E)
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT = (0x20800192)
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID = 0
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1 = 1
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2 = 2
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL = 3
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE = 4
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID = (0x92)
|
|
NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE = 0
|
|
NV2080_CTRL_GPU_COMPUTE_POLICY_MAX = 1
|
|
NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID = (0x94)
|
|
NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG = (0x20800195)
|
|
NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX = 32
|
|
NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID = (0x95)
|
|
NV2080_CTRL_CMD_GPU_GET_GFID = (0x20800196)
|
|
NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID = (0x96)
|
|
NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY = (0x20800197)
|
|
NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID = (0x97)
|
|
NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST = (0x20800198)
|
|
NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID = (0x98)
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES = (0x2080019b)
|
|
NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS = 0xC8
|
|
NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID = (0x9B)
|
|
NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING = (0x2080019c)
|
|
NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID = (0x9C)
|
|
NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS = (0x2080019d)
|
|
NV2080_CTRL_REG_OPS_ARRAY_MAX = 100
|
|
NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID = (0x9D)
|
|
NV2080_CTRL_GPU_SKYLINE_INFO_MAX_SKYLINES = 9
|
|
NV2080_CTRL_GPU_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS = 64
|
|
NV2080_CTRL_GPU_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID = (0x9F)
|
|
NV2080_CTRL_CMD_GPU_GET_SKYLINE_INFO = (0x2080019f)
|
|
NV2080_GET_P2P_CAPS_UUID_LEN = 16
|
|
NV2080_CTRL_CMD_GET_P2P_CAPS = (0x208001a0)
|
|
NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID = (0xA0)
|
|
NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG_MULTIDIE = (0, 0)
|
|
NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG_MULTIDIE_FALSE = 0
|
|
NV2080_CTRL_GPU_COMPUTE_PROFILE_FLAG_MULTIDIE_TRUE = 1
|
|
NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xA2)
|
|
NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES = (0x208001a2)
|
|
NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED = 0
|
|
NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED = 1
|
|
NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS = 2
|
|
NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE = 3
|
|
NV2080_GPU_FABRIC_CLUSTER_UUID_LEN = 16
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW = (1, 0)
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED = 0
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE = 1
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE = 2
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE = (3, 2)
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED = 0
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE = 1
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE = 2
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY = (5, 4)
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED = 0
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE = 1
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE = 2
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY = (7, 6)
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED = 0
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE = 1
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE = 2
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION = (11, 8)
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NOT_SUPPORTED = 0
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NONE = 1
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_SYSGUID = 2
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_CHASSIS_SN = 3
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NO_PARTITION = 4
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INSUFFICIENT_NVLINKS = 5
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCOMPATIBLE_GPU_FW = 6
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INVALID_LOCATION = 7
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_GPU_STATE_INVALID = 8
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED = (13, 12)
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_NOT_SUPPORTED = 0
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_TRUE = 1
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_FALSE = 2
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_NOT_SUPPORTED = 0
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_HEALTHY = 1
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_UNHEALTHY = 2
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_LIMITED_CAPACITY = 3
|
|
NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xA3)
|
|
NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO = (0x208001a3)
|
|
NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS = (0x208001a4)
|
|
GPU_PART_NUMBER_FMT = "%4X-%s-%X%X"
|
|
NV2080_MAX_CHIP_SKU_LENGTH = 0x00000004
|
|
NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID = (0xA4)
|
|
NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP = (0x208001a5)
|
|
NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID = (0xA5)
|
|
NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS = (0x208001a6)
|
|
NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP = (0x208001a7)
|
|
NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU = (0x208001a8)
|
|
NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX = 50
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID = (0xA6)
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID = (0xA7)
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID = (0xA8)
|
|
NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET = (0x208001a9)
|
|
NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET = (0x208001aa)
|
|
NV2080_CTRL_CMD_GPU_GET_RESET_STATUS = (0x208001ab)
|
|
NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID = (0xAB)
|
|
NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET = (0x208001ac)
|
|
NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET = (0x208001ad)
|
|
NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS = (0x208001ae)
|
|
NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID = (0xAE)
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID = (0xAF)
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 = (0x208001af)
|
|
NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS = 0x40
|
|
NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO = (0x208001b0)
|
|
NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID = (0xB0)
|
|
NV2080_CTRL_CMD_GPU_GET_VF_CAPS = (0x208001b1)
|
|
NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID = (0xB1)
|
|
NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION = (0x208001b2)
|
|
NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET = NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_PF_FLR
|
|
NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT = NV2080_CTRL_GPU_RECOVERY_ACTION_OS_REBOOT
|
|
NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID = (0xB2)
|
|
NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID = (0xe4)
|
|
NV2080_CTRL_GPU_GET_FIPS_STATUS = (0x208001e4)
|
|
NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU = 0x2
|
|
NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU = 0xC
|
|
NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC = (0x18)
|
|
NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT = (0x1a)
|
|
NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID = (0xB3)
|
|
NV2080_CTRL_GPU_GET_RAFTS_FS_MASK = (0x208001b3)
|
|
NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILE_CAPACITY = (0x208001e5)
|
|
NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID = (0xe5)
|
|
NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK = (0x208001e7)
|
|
NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID = (0xe7)
|
|
NV2080_CTRL_CMD_GPU_RPC_GSP_TEST = (0x208001e8)
|
|
NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS_MESSAGE_ID = (0xe8)
|
|
NV2080_CTRL_GPU_RPC_GSP_TEST_SERIALIZED_INTEGRITY = 0x1
|
|
NV2080_CTRL_GPU_RPC_GSP_TEST_UNSERIALIZED = 0x2
|
|
NV2080_CTRL_GPU_RPC_GSP_TEST_SERIALIZED_NOP = 0x3
|
|
NV2080_CTRL_GPU_RPC_GSP_TEST_TIMEOUT = 0x4
|
|
NV2080_CTRL_CMD_GPU_RPC_GSP_QUERY_SIZES = (0x208001e9)
|
|
NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS_MESSAGE_ID = (0xe9)
|
|
RUSD_FEATURE_NON_POLLING = 0x1
|
|
RUSD_FEATURE_POLLING = 0x2
|
|
NV2080_CTRL_CMD_RUSD_GET_SUPPORTED_FEATURES = (0x208001ea)
|
|
NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS_MESSAGE_ID = (0xea)
|
|
NV2080_CTRL_CMD_GPU_RUSD_SET_FEATURES = (0x208001eb)
|
|
NV2080_CTRL_GPU_RUSD_SET_FEATURES_PARAMS_MESSAGE_ID = (0xeb)
|
|
NV2080_CTRL_CMD_GPU_FORCE_GSP_UNLOAD = (0x208001ec)
|
|
NV2080_CTRL_GPU_FORCE_GSP_UNLOAD_PARAMS_MESSAGE_ID = (0xec)
|
|
NV2080_CTRL_CMD_GPU_VGA_SR_READ_WRITE = (0x208001ed)
|
|
NV2080_CTRL_GPU_VGA_SR_READ_WRITE_PARAMS_MESSAGE_ID = (0xed)
|
|
NV2080_CTRL_CMD_GPU_ERROR_INJECTION_CONTROL = (0x208001ef)
|
|
NV2080_CTRL_GPU_ERROR_INJECTION_CONTROL_PARAMS_MESSAGE_ID = (0xef)
|
|
NV2080_CTRL_CMD_GPU_CHECK_MEM_SUBSYS_ERROR = (0x208001f0)
|
|
NV2080_CTRL_GPU_CHECK_MEM_SUBSYS_ERROR_PARAMS_MESSAGE_ID = (0xf0)
|
|
NV2080_CTRL_CMD_GPU_GET_DEFAULT_TIMEOUT = (0x208001f1)
|
|
NV2080_CTRL_GPU_GET_DEFAULT_TIMEOUT_PARAMS_MESSAGE_ID = (0xf1)
|
|
NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL = (0x208001f2)
|
|
NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_RSA_EXPONENT_SIZE = 4
|
|
NV2080_CTRL_CMD_GSP_CRYPTO_CONTROL_NONCE_SIZE = 48
|
|
NV2080_CTRL_GSP_CRYPTO_CONTROL_PARAMS_MESSAGE_ID = (0xf2)
|
|
NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED = (0x208081f3)
|
|
NV2080_CTRL_CMD_GPU_IS_RESET_COUPLED_PARAMS_MESSAGE_ID = (0xf3)
|
|
NV2080_CTRL_GPU_GET_DIELET_INFO_MAX_SIZE = (256)
|
|
NV2080_CTRL_CMD_GPU_GET_DIELET_INFO = (0x208081f4)
|
|
NV2080_CTRL_GPU_GET_DIELET_INFO_PARAMS_MESSAGE_ID = (0xf4)
|
|
NV2080_CTRL_CMD_GPU_GET_UNIT_FS_INFO_FROM_DIELET = (0x208081f5)
|
|
NV2080_CTRL_GPU_GET_UNIT_FS_INFO_FROM_DIELET_PARAMS_MESSAGE_ID = (0xf5)
|
|
NV2080_CTRL_CMD_GPU_SET_MIGRATION_BLOCK = (0x208001fa)
|
|
NV2080_CTRL_GPU_SET_MIGRATION_BLOCK_PARAMS_MESSAGE_ID = (0xfa)
|
|
NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS = 0x00000001
|
|
NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL = 0x00000002
|
|
NV2080_GPUMON_PID_INVALID = ((NvU32)(~0))
|
|
NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE = (1, 0)
|
|
NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE = 0x0
|
|
NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID = 0x1
|
|
NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL = 0x2
|
|
NV2080_CTRL_GR_ROUTE_INFO_DATA_CHANNEL_HANDLE = (31, 0)
|
|
NV2080_CTRL_GR_ROUTE_INFO_DATA_ENGID = (31, 0)
|
|
NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS = NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS
|
|
NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 = NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894
|
|
NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK = NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK
|
|
NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT = NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT
|
|
NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT = NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT
|
|
NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE = NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE
|
|
NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT = NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT
|
|
NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT = NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT
|
|
NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR = NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR
|
|
NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT = NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT
|
|
NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT = NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT
|
|
NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT = NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT
|
|
NV2080_CTRL_GR_INFO_INDEX_SM_VERSION = NV0080_CTRL_GR_INFO_INDEX_SM_VERSION
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM = NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP = NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP
|
|
NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES = NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES
|
|
NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES = NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES
|
|
NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY = NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY
|
|
NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY = NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM = NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS
|
|
NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED = NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC
|
|
NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT = NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS
|
|
NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT = NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT
|
|
NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT = NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC
|
|
NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT = NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT = NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT = NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES
|
|
NV2080_CTRL_GR_INFO_INDEX_RESERVED = NV0080_CTRL_GR_INFO_INDEX_RESERVED
|
|
NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES = NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES = NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS = NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG = NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET = NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_CPC_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_CPC_PER_GPC
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_NVLINK_MASK = NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_NVLINK_MASK
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_C2C_MASK = NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_C2C_MASK
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_PCIE_MASK = NV0080_CTRL_GR_INFO_INDEX_LITTER_HSHUB_PCIE_MASK
|
|
NV2080_CTRL_GR_INFO_INDEX_RESERVED1 = NV0080_CTRL_GR_INFO_INDEX_RESERVED1
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX = NV0080_CTRL_GR_INFO_INDEX_MAX
|
|
NV2080_CTRL_GR_INFO_MAX_SIZE = NV0080_CTRL_GR_INFO_MAX_SIZE
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_NONE = (0x00000000)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_1_05 = (0x00000105)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_1_1 = (0x00000110)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_1_2 = (0x00000120)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_1_3 = (0x00000130)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_1_4 = (0x00000140)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_1_5 = (0x00000150)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_2_0 = (0x00000200)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_2_1 = (0x00000210)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_2_2 = (0x00000220)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_0 = (0x00000300)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_1 = (0x00000310)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_2 = (0x00000320)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_3 = (0x00000330)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_5 = (0x00000350)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_6 = (0x00000360)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_8 = (0x00000380)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_9 = (0x00000390)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_4_0 = (0x00000400)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_5_0 = (0x00000500)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_5_02 = (0x00000502)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_5_03 = (0x00000503)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_6_0 = (0x00000600)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_6_01 = (0x00000601)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_6_02 = (0x00000602)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_0 = (0x00000700)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_01 = (0x00000701)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_02 = (0x00000702)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_03 = (0x00000703)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_05 = (0x00000705)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_02 = (0x00000802)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_06 = (0x00000806)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_07 = (0x00000807)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_08 = (0x00000808)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_09 = (0x00000809)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_9_00 = (0x00000900)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_00 = (0x00000A00)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_01 = (0x00000A01)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_03 = (0x00000A03)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_04 = (0x00000A04)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_12_00 = (0x00000C00)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_12_01 = (0x00000C01)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_05 = (0x00000A05)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_13_00 = (0x00000D00)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_5_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_5_02)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_5_3 = (NV2080_CTRL_GR_INFO_SM_VERSION_5_03)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_6_1 = (NV2080_CTRL_GR_INFO_SM_VERSION_6_01)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_6_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_6_02)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_1 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_01)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_02)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_3 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_03)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_5 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_05)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_02)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_6 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_06)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_7 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_07)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_8 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_08)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_9 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_09)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_9_0 = (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_0 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_00)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_1 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_3 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_03)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_4 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_04)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_5 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_05)
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_13_0 = (NV2080_CTRL_GR_INFO_SM_VERSION_13_00)
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D = (0, 0)
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE = 0x0
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE = 0x1
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D = (1, 1)
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE = 0x0
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE = 0x1
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE = (2, 2)
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE = 0x0
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE = 0x1
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M = (3, 3)
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE = 0x0
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE = 0x1
|
|
NV2080_CTRL_CMD_GR_GET_INFO = (0x20801201)
|
|
NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE = (0x20801205)
|
|
NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID = (0x5)
|
|
NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL = (0x00000000)
|
|
NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW = (0x00000001)
|
|
NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER = (0x00000002)
|
|
NV2080_CTRL_CMD_GR_GET_ZCULL_INFO = (0x20801206)
|
|
NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x6)
|
|
NV2080_CTRL_CMD_GR_CTXSW_PM_MODE = (0x20801207)
|
|
NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID = (0x7)
|
|
NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW = (0x00000000)
|
|
NV2080_CTRL_CTXSW_PM_MODE_CTXSW = (0x00000001)
|
|
NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW = (0x00000002)
|
|
NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND = (0x20801208)
|
|
NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID = (0x8)
|
|
NV2080_CTRL_CMD_GR_CTXSW_PM_BIND = (0x20801209)
|
|
NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID = (0x9)
|
|
NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND = (0x2080123a)
|
|
NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID = (0x3A)
|
|
NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES = 128
|
|
NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP = (0x2080120a)
|
|
NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID = (0xA)
|
|
NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE = (0x2080120e)
|
|
NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID = (0xE)
|
|
NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW = (0x00000000)
|
|
NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW = (0x00000001)
|
|
NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS = (0x2080120f)
|
|
NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT = 512
|
|
NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID = (0xF)
|
|
NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE = (0x20801210)
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID = (0x10)
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP = (0, 0)
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE = (0x00000000)
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET = (0x00000001)
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP = (1, 1)
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE = (0x00000000)
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET = (0x00000001)
|
|
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI = (0x00000000)
|
|
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP = (0x00000001)
|
|
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL = (0x00000002)
|
|
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI = (0x00000000)
|
|
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA = (0x00000001)
|
|
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP = (0x00000002)
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND = (0x20801211)
|
|
NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID = (0x11)
|
|
NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE = (0x20801212)
|
|
NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID = (0x12)
|
|
NV2080_CTRL_PC_SAMPLING_MODE_DISABLED = (0x00000000)
|
|
NV2080_CTRL_PC_SAMPLING_MODE_ENABLED = (0x00000001)
|
|
NV2080_CTRL_CMD_GR_GET_ROP_INFO = (0x20801213)
|
|
NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x13)
|
|
NV2080_CTRL_CMD_GR_GET_CTXSW_STATS = (0x20801215)
|
|
NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID = (0x15)
|
|
NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET = (0, 0)
|
|
NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE = (0x00000000)
|
|
NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE = (0x00000001)
|
|
NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE = (0x20801218)
|
|
NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x18)
|
|
NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT = 64
|
|
NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO = (0x20801219)
|
|
NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x19)
|
|
NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN = 0
|
|
NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM = 1
|
|
NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM = 2
|
|
NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER = (0x2080121b)
|
|
NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT = 512
|
|
NV2080_CTRL_GR_DISABLED_SM_VGPC_ID = 0xFF
|
|
NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x1B)
|
|
NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL = (0x2080121c)
|
|
NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID = (0x1C)
|
|
NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE = (0x2080121e)
|
|
NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x1E)
|
|
NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE = (0x2080121f)
|
|
NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID = (0x1F)
|
|
NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE = (0x20801220)
|
|
NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID = (0x20)
|
|
NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS = 64
|
|
NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS = (0x20801221)
|
|
NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID = (0x21)
|
|
NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS = (0x20801222)
|
|
NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID = (0x22)
|
|
NV2080_CTRL_CMD_GR_GET_CAPS_V2 = (0x20801227)
|
|
NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x27)
|
|
NV2080_CTRL_CMD_GR_GET_INFO_V2 = (0x20801228)
|
|
NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x28)
|
|
NV2080_CTRL_CMD_GR_GET_GPC_MASK = (0x2080122a)
|
|
NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID = (0x2A)
|
|
NV2080_CTRL_CMD_GR_GET_TPC_MASK = (0x2080122b)
|
|
NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID = (0x2B)
|
|
NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = (0x2080122c)
|
|
NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x2C)
|
|
NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES = (0x2080122d)
|
|
NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID = (0x2D)
|
|
NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER = (0x20801230)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED = (0x0)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2 = (0x1)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4 = (0x2)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8 = (0x3)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16 = (0x4)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32 = (0x5)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64 = (0x6)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED = (0x0)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2 = (0x1)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4 = (0x2)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8 = (0x3)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16 = (0x4)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32 = (0x5)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED = (0x0)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED = (0x1)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED = (0x0)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2 = (0x1)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4 = (0x2)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8 = (0x3)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16 = (0x4)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32 = (0x5)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED = (0x0)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2 = (0x1)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4 = (0x2)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8 = (0x3)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16 = (0x4)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32 = (0x5)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED = (0x0)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2 = (0x1)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4 = (0x2)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8 = (0x3)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16 = (0x4)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32 = (0x5)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64 = (0x6)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED = (0x0)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2 = (0x1)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4 = (0x2)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8 = (0x3)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16 = (0x4)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32 = (0x5)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64 = (0x6)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED = (0x0)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2 = (0x1)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4 = (0x2)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8 = (0x3)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16 = (0x4)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32 = (0x5)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64 = (0x6)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED = (0x0)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2 = (0x1)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4 = (0x2)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8 = (0x3)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16 = (0x4)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32 = (0x5)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64 = (0x6)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x30)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE = (0xFF)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FMLA16 = (0x0)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DP = (0x1)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FMLA32 = (0x2)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FFMA = (0x3)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA0 = (0x4)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA1 = (0x5)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA2 = (0x6)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA3 = (0x7)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA4 = (0x8)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FP16 = (0x9)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FP32 = (0xA)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DFMA = (0xB)
|
|
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DMLA = (0xC)
|
|
NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2 = (0x2080123c)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID = (0x3C)
|
|
NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MAX_LIST_SIZE = (0xFF)
|
|
NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_MASK = (0x0)
|
|
NV2080_CTRL_GR_SM_ISSUE_THROTTLE_CTRL_CREDIT = (0x1)
|
|
NV2080_CTRL_CMD_GR_GET_SM_ISSUE_THROTTLE_CTRL = (0x2080123d)
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID = (0x3D)
|
|
NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID = (0x20801231)
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID = (0x31)
|
|
NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK = (0x20801232)
|
|
NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID = (0x32)
|
|
NV2080_CTRL_CMD_GR_GET_PPC_MASK = (0x20801233)
|
|
NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID = (0x33)
|
|
NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC = (0x20801234)
|
|
NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID = (0x34)
|
|
NV2080_CTRL_CMD_GR_GET_CTXSW_MODES = (0x20801235)
|
|
NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID = (0x35)
|
|
NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP = (0x20801236)
|
|
NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID = (0x36)
|
|
NV2080_CTRL_CMD_GR_GET_ZCULL_MASK = (0x20801237)
|
|
NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID = (0x37)
|
|
NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 = (0x20801238)
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID = (0x38)
|
|
NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO = (0x20801239)
|
|
NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID = (0x39)
|
|
NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK = (0x2080123b)
|
|
NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID = (0x3b)
|
|
NV2080_CTRL_CMD_GR_TEST_CTXSW_ERROR_LOGS = (0x2080123e)
|
|
NV2080_CTRL_GR_TEST_CTXSW_ERROR_LOGS_PARAMS_MESSAGE_ID = (0x3E)
|
|
NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO = (0x20803801)
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES = 96
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE = 32
|
|
NV2080_CTRL_GRMGR_MAX_SMC_IDS = 8
|
|
NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID = 0
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT = 1
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP = 2
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK = 3
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK = 4
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP = 5
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK = 6
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS = 7
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK = 8
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID = 9
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK = 10
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GRAPHICS_SYSPIPE_MASK = 11
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GFX_CAPABLE_GPC_MASK = 12
|
|
NV2080_CTRL_CMD_GSP_GET_FEATURES = (0x20803601)
|
|
NV2080_GSP_MAX_BUILD_VERSION_LENGTH = (0x0000040)
|
|
NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED = (0, 0)
|
|
NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE = (0x00000000)
|
|
NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE = (0x00000001)
|
|
NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED = (1, 1)
|
|
NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE = (0x00000000)
|
|
NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE = (0x00000001)
|
|
NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS = (0x20803602)
|
|
NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS = (0x20803603)
|
|
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS = (0x20803604)
|
|
NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX = 64
|
|
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID = (0x4)
|
|
NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST = (0x20803605)
|
|
NV2080_CTRL_CMD_GSP_GDMA_FUZZ_TEST_PARAMS_MESSAGE_ID = (0x5)
|
|
NV2080_CTRL_CMD_GSP_CORE_TEST = (0x20803606)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L1_LIBOS = (0, 0)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L1_LIBOS_YES = (0x00000001)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L1_LIBOS_NO = (0x00000000)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_EVICT_L2 = (1, 1)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_EVICT_L2_YES = (0x00000001)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_EVICT_L2_NO = (0x00000000)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L2 = (2, 2)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L2_YES = (0x00000001)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_INVAL_L2_NO = (0x00000000)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_UNCACHED = (3, 3)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_UNCACHED_YES = (0x00000001)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_UNCACHED_NO = (0x00000000)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_FENCE = (4, 4)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_FENCE_YES = (0x00000001)
|
|
NV2080_CTRL_GSP_CORE_TEST_FLAGS_FENCE_NO = (0x00000000)
|
|
NV2080_CTRL_GSP_CORE_TEST_SIZE_MAX = (0x400000)
|
|
NV2080_CTRL_GSP_CORE_TEST_ITERS_MAX = (10000)
|
|
NV2080_CTRL_CMD_GSP_CORE_TEST_PARAMS_MESSAGE_ID = (0x6)
|
|
NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK = (0x20804101)
|
|
NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE = (0x20804102)
|
|
NV2080_CTRL_I2C_VERSION_0 = 0x00
|
|
NV2080_CTRL_I2C_MAX_ENTRIES = 256
|
|
NV2080_CTRL_I2C_MAX_REG_LEN = 8
|
|
NV2080_CTRL_I2C_MAX_ADDR_ENTRIES = 20
|
|
NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC = (0x00000001)
|
|
NV2080_CTRL_I2C_FLAGS_PRIVILEGE = (0x00000002)
|
|
NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED = (0x00000004)
|
|
NV2080_CTRL_I2C_FLAGS_PX3540 = (0x00000010)
|
|
NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED = (0x00000008)
|
|
NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_CMD_I2C_READ_BUFFER = (0x20800601)
|
|
NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_I2C_WRITE_BUFFER = (0x20800602)
|
|
NV2080_CTRL_CMD_I2C_READ_REG = (0x20800603)
|
|
NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_I2C_WRITE_REG = (0x20800604)
|
|
NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID = (0x4)
|
|
NV2080_CTRL_CMD_I2C_ACCESS = (0x20800610)
|
|
NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID = (0x10)
|
|
NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE = 0x1
|
|
NV2080_CTRL_I2C_ACCESS_CMD_RELEASE = 0x2
|
|
NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE = 0x3
|
|
NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE = 0x4
|
|
NV2080_CTRL_I2C_ACCESS_CMD_NULL = 0x5
|
|
NV2080_CTRL_I2C_ACCESS_CMD_RESET = 0x6
|
|
NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT = 0x11
|
|
NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE = 0x12
|
|
NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE = 0x13
|
|
NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER = 0x14
|
|
NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER = 0x15
|
|
NV2080_CTRL_I2C_ACCESS_CMD_START = 0x17
|
|
NV2080_CTRL_I2C_ACCESS_CMD_STOP = 0x18
|
|
NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE = 0x20
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_START = 0x1
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_STOP = 0x2
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_ACK = 0x4
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_RAB = 0x8
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS = 0x10
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE = 0x20
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED = 0x40
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_RESTART = 0x80
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT = 0x100
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT = 0x200
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT = 0x400
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT = 0x800
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT = 0x1000
|
|
NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC = 0x0
|
|
NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY = 0x1
|
|
NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY = 0x2
|
|
NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY = 0x3
|
|
NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY = 0x4
|
|
NV2080_CTRL_I2C_ACCESS_PORT_1 = 0x1
|
|
NV2080_CTRL_I2C_ACCESS_PORT_2 = 0x2
|
|
NV2080_CTRL_I2C_ACCESS_PORT_3 = 0x3
|
|
NV2080_CTRL_I2C_ACCESS_PORT_4 = 0x4
|
|
NV2080_CTRL_I2C_ACCESS_PORT_5 = 0x5
|
|
NV2080_CTRL_I2C_ACCESS_PORT_6 = 0x6
|
|
NV2080_CTRL_I2C_ACCESS_PORT_7 = 0x7
|
|
NV2080_CTRL_I2C_ACCESS_PORT_8 = 0x8
|
|
NV2080_CTRL_I2C_ACCESS_PORT_9 = 0x9
|
|
NV2080_CTRL_I2C_ACCESS_PORT_10 = 0x10
|
|
NV2080_CTRL_I2C_ACCESS_NUM_PORTS = NV2080_CTRL_I2C_ACCESS_PORT_10
|
|
NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS = 0x0
|
|
NV2080_CTRL_I2C_ACCESS_STATUS_ERROR = 0x1
|
|
NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR = 0x2
|
|
NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY = 0x3
|
|
NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND = 0x4
|
|
NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING = 0x5
|
|
NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE = (0x20800620)
|
|
NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID = (0x20)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO = (0x20800a01)
|
|
NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID = (0x1C)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG = (0x20800a1c)
|
|
NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER = (0x20800a1d)
|
|
NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES = 64
|
|
NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID = (0x1D)
|
|
NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER = (0x20800a1e)
|
|
NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID = (0x1E)
|
|
NV2080_CTRL_INTERNAL_GR_MAX_ENGINES = 8
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID = (0x20)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS = (0x20800a1f)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID = (0x1F)
|
|
NV2080_CTRL_INTERNAL_GR_MAX_SM = 512
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x23)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER = (0x20800a22)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x22)
|
|
NV2080_CTRL_CMD_INTERNAL_MAX_NVDECS = 8
|
|
NV2080_CTRL_CMD_INTERNAL_MAX_BSPS = NV2080_CTRL_CMD_INTERNAL_MAX_NVDECS
|
|
NV2080_CTRL_INTERNAL_BSP_CAPS = NV2080_CTRL_INTERNAL_NVDEC_CAPS
|
|
NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS = NV2080_CTRL_INTERNAL_NVDEC_GET_CAPS_PARAMS
|
|
NV2080_CTRL_CMD_INTERNAL_MAX_NVENCS = 8
|
|
NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS = NV2080_CTRL_CMD_INTERNAL_MAX_NVENCS
|
|
NV2080_CTRL_INTERNAL_MSENC_CAPS = NV2080_CTRL_INTERNAL_NVENC_CAPS
|
|
NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS = NV2080_CTRL_INTERNAL_NVENC_GET_CAPS_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_MAX_GPC = 64
|
|
NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT = 10
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID = (0x27)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS = (0x20800a26)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID = (0x26)
|
|
NV2080_CTRL_KGR_MAX_BUFFER_PTES = 128
|
|
NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES = (0x20800a28)
|
|
NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID = (0x28)
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x2B)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO = (0x20800a2a)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID = (0x2A)
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x2D)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO = (0x20800a2c)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x2C)
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x2F)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO = (0x20800a2e)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x2E)
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID = (0x31)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS = (0x20800a30)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID = (0x30)
|
|
NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT = 0x1a
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID = (0x33)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO = (0x20800a32)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID = (0x32)
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x35)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER = (0x20800a34)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x34)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO = (0x20800a36)
|
|
NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX = 16
|
|
NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID = (0x36)
|
|
NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE = (0x20800a37)
|
|
NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE = (0x20800a38)
|
|
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID = (0x37)
|
|
NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID = (0x38)
|
|
NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET = (0x20800a39)
|
|
NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET = (0x20800a3a)
|
|
NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET = (0x20800a3b)
|
|
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID = (0x39)
|
|
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID = (0x3A)
|
|
NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID = (0x3B)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE = (0x20800a3d)
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID = (0x3C)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID = (0x3D)
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID = (0x3E)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES = (0x20800a3f)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID = (0x3F)
|
|
NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES = 512
|
|
NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE = (0x20800a40)
|
|
NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID = (0x40)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP = (0x20800a41)
|
|
NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE = 16384
|
|
NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES = 4096
|
|
NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID = (0x41)
|
|
NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID = (0x43)
|
|
NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE = (0x20800a44)
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID = (0x44)
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE = (0x20800a43)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_CHECK_CTS_ID_VALID = (0x20800a46)
|
|
NV2080_CTRL_INTERNAL_GPU_CHECK_CTS_ID_VALID_PARAMS_MESSAGE_ID = (0x46)
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID = (0x47)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES = (0x20800a48)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID = (0x48)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM = (0x20800a49)
|
|
NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID = (0x49)
|
|
NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS = (0x20800a4a)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION = (0x20800a4b)
|
|
NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID = (0x4B)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE = (0x20800a4c)
|
|
NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID = (0x4C)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR = (0x20800a4d)
|
|
NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID = (0x4D)
|
|
NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES = 90
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID = (0x4F)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM = (0x20800a51)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID = (0x51)
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE = 4
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID = (0x52)
|
|
NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS = 2
|
|
NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID = 64
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS = (0x20800a53)
|
|
NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID = (0x53)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO = (0x20800a54)
|
|
NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID = (0x54)
|
|
NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO = (0x20800a55)
|
|
NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID = (0x55)
|
|
NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE = (0x00000000)
|
|
NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM = (0x00000001)
|
|
NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 = (0x00000002)
|
|
NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 = (0x00000003)
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR = (0x20800a70)
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL = (0x20800a71)
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID = (0x71)
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE = (0x20800a72)
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID = (0x72)
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX = (0x20800a73)
|
|
NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID = (0x73)
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING = (0x20800a74)
|
|
NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID = (0x74)
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING = (0x20800a75)
|
|
NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID = (0x75)
|
|
NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES = (0x20800a57)
|
|
NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES = 128
|
|
NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID = (0x57)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER = (0x20800a58)
|
|
NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID = (0x58)
|
|
NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO = (0x20800a59)
|
|
NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x59)
|
|
NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES = (0x20800a5a)
|
|
NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID = (0x5A)
|
|
NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE = (0x20800a5b)
|
|
NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID = (0x5B)
|
|
NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE = (0x20800a5c)
|
|
NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE = 128
|
|
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID = (0x5C)
|
|
NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR = (0x00000000)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK = (0x20800a98)
|
|
NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID = (0x98)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET = (0x20800a99)
|
|
NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID = (0x99)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES = (0x20800a5d)
|
|
NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID = (0x5D)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES = (0x20800a60)
|
|
NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID = 15
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID = (0x60)
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS = (0x20800a61)
|
|
NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID = (0x61)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES = (0x20800a63)
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID = (0x63)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES = (0x20800a65)
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID = (0x65)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES = (0x20800a66)
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID = (0x66)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG = (0x20800a68)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID = (0x68)
|
|
NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG = (0x20800a67)
|
|
NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID = (0x67)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE = (0x20800a6b)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE = 8
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID = (0x6B)
|
|
NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT = (0x20800a6a)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE = (0x20800a81)
|
|
NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID = (0x81)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X = (0x20800a9a)
|
|
NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID = (0x9A)
|
|
NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE = 0
|
|
NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK = 1
|
|
NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST = NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK
|
|
NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM = (0x2)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL = (0x20800a7e)
|
|
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID = (0x7E)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS = (0x20800a7f)
|
|
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID = (0x7F)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO = (0x20800a80)
|
|
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID = (0x80)
|
|
NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER = (0x20800a9b)
|
|
NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES = 256
|
|
NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9B)
|
|
NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER = (0x20800a9c)
|
|
NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE = (0x00000000)
|
|
NV2080_CTRL_FAULT_BUFFER_REPLAYABLE = (0x00000001)
|
|
NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER = (0x20800a9d)
|
|
NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES = 3000
|
|
NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9D)
|
|
NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER = (0x20800a9e)
|
|
NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9E)
|
|
NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER = (0x20800a9f)
|
|
NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID = (0x9F)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X = (0x20800aa0)
|
|
NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID = (0xA0)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X = (0x20800aa1)
|
|
NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID = (0xA1)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO = (0x20800aa2)
|
|
NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES = 9
|
|
NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS = 64
|
|
NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID = (0xA2)
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE = (0x20800aa3)
|
|
NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID = (0xA3)
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE = (0x20800aa4)
|
|
NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA4)
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES = (0x20800aa5)
|
|
NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID = (0xA5)
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES = (0x20800aa6)
|
|
NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID = (0xA6)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED = (0x20800a69)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID = (0x69)
|
|
NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE = (0x20800aa7)
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE = (0x20800aa8)
|
|
NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE = (0x20800aa9)
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE = (0x20800aaa)
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE = 4
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA7)
|
|
NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA8)
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA9)
|
|
NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xAA)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT = (0x20800a6c)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID = (0x6c)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL = (0x00000001)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST = (0x00000002)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST = (0x00000004)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL = (0x00000008)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN = (0x00000010)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL = (0x00000020)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES = (0x20800a6d)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_CLEAN_LTC_PROBE_FILTER = (0x20800ab0)
|
|
NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO = (0x20800aac)
|
|
NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0xac)
|
|
NV2080_CTRL_CMD_INTERNAL_BIF_GET_DATA = (0x20800a00)
|
|
NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG = (0x20800a88)
|
|
NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID = (0x88)
|
|
NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS = (0x20800a8a)
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE = 32
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID = (0x8a)
|
|
NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS = (0x20800a8b)
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID = (0x8b)
|
|
NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID = (0x20800a8c)
|
|
NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID = (0x8c)
|
|
NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG = (0x20800a8d)
|
|
NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID = (0x8d)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR = (0x20800aad)
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID = (0xae)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR = (0x20800aae)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT = (0x20800ab1)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE = 32
|
|
NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID = (0xB1)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS = (0x20800a6e)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE = (0x20800a6f)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID = (0x6f)
|
|
NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO = (0x20800ab2)
|
|
NV2080_CTRL_CMD_INTERNAL_CCU_MAP = (0x20800ab3)
|
|
NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX = 1
|
|
NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID = (0xB3)
|
|
NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP = (0x20800ab4)
|
|
NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID = (0xB4)
|
|
NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS = (0x20800ab5)
|
|
NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB5)
|
|
NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS = (0x20800ab6)
|
|
NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB6)
|
|
NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS = (0x20800ab8)
|
|
NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB8)
|
|
NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO = (0x20800ab9)
|
|
NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID = (0xB9)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE = (0x20800a76)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID = (0x76)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE = (0x20800a77)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID = (0x77)
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xBB)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES = (0x20800aba)
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xBA)
|
|
NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE = (0x20800abd)
|
|
NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID = (0xBD)
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT = (0x20800abe)
|
|
NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID = (0xBE)
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS = (0x20800abf)
|
|
NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID = (0xBF)
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS = (0x20800ac0)
|
|
NV2080_MAX_NUM_HEADS = 4
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID = (0xC0)
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC = (0x20800ac1)
|
|
NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID = (0xC1)
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES = (0x20800ac4)
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID = (0xC4)
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID = (0x20800ac9)
|
|
NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID = (0xC9)
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC = (0x20800aca)
|
|
NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID = (0xCA)
|
|
NV2080_CTRL_CMD_INTERNAL_FBSR_INIT = (0x20800ac2)
|
|
NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID = (0xC2)
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING = (0x20800ac3)
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID = (0xC3)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB = (0x20800ac5)
|
|
NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID = (0xC5)
|
|
NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD = (0x20800ac6)
|
|
NV2080_CTRL_ACPI_DSM_READ_SIZE = (0x1000)
|
|
NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID = (0xC6)
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID = (0xC7)
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL = (0x20800ac7)
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID = (0xC8)
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL = (0x20800ac8)
|
|
NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE = (0x20800acb)
|
|
NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID = (0xCB)
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR = 0x00
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM = 0x01
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI = 0x02
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD = 0x00
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT = 0x01
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR = 0x02
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET = 0x03
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC = (0x20800acc)
|
|
NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID = (0xCC)
|
|
NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC = (0x20800acd)
|
|
NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID = (0xCD)
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS = 0x00
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS = 0x01
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE = (0x20800ace)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID = (0xCE)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE = (0x20800acf)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID = (0xCF)
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT = (0x20800ad0)
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID = (0xD0)
|
|
NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT = (0x20800ad1)
|
|
NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID = (0xD1)
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE = (0x20800ad2)
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID = (0xD2)
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 = (0x20800ad3)
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID = (0xD3)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO = (0x20800ad4)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID = (0xD4)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING = (0x20800ad5)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID = (0xD5)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE = (0x20800ad6)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID = (0xD6)
|
|
NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE = (0x2080a7d7)
|
|
NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID = (0xD7)
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT = (0x20800a7b)
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS = (0x20800ad8)
|
|
NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0xD8)
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK = (0x20800a45)
|
|
NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS = (0x20800adb)
|
|
NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID = (0xDB)
|
|
NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS = (0x20800adc)
|
|
NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID = (0xDC)
|
|
NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE = (0x20800add)
|
|
NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL = (0x20800ade)
|
|
NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID = (0xDE)
|
|
NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA = (0x20800adf)
|
|
MAX_EDID_SIZE_FROM_SBIOS = 512
|
|
NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID = (0xDF)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED = (0x20800af0)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET = (0x20800af1)
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET = (0x20800af2)
|
|
NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF4)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO = (0x208001f4)
|
|
NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF5)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE = (0x208001f5)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE = (0x208001f6)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE = (0x208001f7)
|
|
NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF8)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE = (0x208001f8)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE = (0x208001f9)
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO = (0x20800af3)
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0xF3)
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS = (0x20800ae1)
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE = 3
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL = 0
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER = 1
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER = 2
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT = 3
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT = 6
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID = (0xE1)
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS = (0x20800ae2)
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID = (0xE2)
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS = (0x20800ae5)
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID = (0xE5)
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION = (0x20800ae6)
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID = (0xE6)
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE = (0x20800ae7)
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID = (0xE7)
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY = (0x20800ae8)
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID = (0xE8)
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID = (0x20800aef)
|
|
NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID = (0xEF)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP = (0x20800afa)
|
|
CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES = (0x10)
|
|
NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID = (0xFA)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG = (0x20800afb)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID = (0xFB)
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG = (0x20800afc)
|
|
NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID = (0xFC)
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO = (0x20800afd)
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID = (0xFD)
|
|
NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID = (0xFE)
|
|
NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA = (0x20800afe)
|
|
NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID = (0xFF)
|
|
NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL = (0x20800aff)
|
|
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID = (0xE3)
|
|
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_OLDEST = 0x00
|
|
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_NEWEST = 0x01
|
|
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_STOP = 0x02
|
|
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE = (0x208001e3)
|
|
NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID = (0xAF)
|
|
NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES = (0x20800aaf)
|
|
NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND = (0x20800ae4)
|
|
NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID = (0xE4)
|
|
NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID = (0xE9)
|
|
NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER = (0x20800ae9)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY = (0x20800aea)
|
|
NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID = (0xEA)
|
|
NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID = (0xEB)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP = (0x20800aeb)
|
|
NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID = (0xEC)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM = (0x20800aec)
|
|
NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID = (0xED)
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR = (0x20800aed)
|
|
NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM = (0x20800a79)
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID = (0x79)
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID = (0x14)
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE = (0x20800a14)
|
|
NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID = (0xEE)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_PF_BAR1_SPA = (0x20800aee)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER = (0x20800a21)
|
|
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x21)
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_OFF = 0x00
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_HS = 0x01
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAFE = 0x02
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAULT = 0x03
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RECOVERY = 0x04
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAIL = 0x05
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DETECT = 0x06
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESET = 0x07
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ENABLE_PM = 0x08
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_PM = 0x09
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SLEEP = 0x0A
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAVE_STATE = 0x0B
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESTORE_STATE = 0x0C
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_PRE_HS = 0x0E
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT = 0x0F
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_DISABLE = 0x10
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN = 0x11
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP = 0x12
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE1 = 0x13
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITNEGOTIATE = 0x14
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE = 0x15
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITOPTIMIZE = 0x16
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE = 0x17
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT = 0x18
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_CONTAIN = 0x19
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITTL = 0x1A
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE5 = 0x1B
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ALI = 0x1C
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING = 0x1D
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INVALID = 0xFF
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS = 0x00
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE = 0x04
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER = 0x04
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN = 0x05
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE = 0x06
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF = 0x07
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE = 0x08
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE = 0x09
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY = 0x0A
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ = 0x0B
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN = 0x0C
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS = 0x0D
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS = 0x00
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE = 0x04
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER = 0x04
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN = 0x05
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE = 0x06
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF = 0x07
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL = 0x08
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM = 0x09
|
|
NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM = 6
|
|
NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE = (0x7)
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE = 0x00
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE = 0x01
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE = 0x02
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE = 0x03
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE = 0x04
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE = 0x05
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE = 0x06
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE = 0x07
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT = 0x08
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT = 0x09
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN = 0x0A
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN = 0x0B
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE = 0x0C
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD = 0x0D
|
|
NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID = (0x24)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK = (0x20800a24)
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID = (0x25)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID = (0x20800a25)
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID = (0x29)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED = (0x20800a29)
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM = 0x0
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET = 0x1
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID = (0x42)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX = (0x20800a42)
|
|
NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x4E)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER = (0x20800a4e)
|
|
NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x50)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER = (0x20800a50)
|
|
NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID = (0x20800a56)
|
|
NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE = (81)
|
|
NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID = (0x56)
|
|
NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM = 0x1
|
|
NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER = 0x2
|
|
NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID = (0x5F)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING = (0x20800a5f)
|
|
NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID = (0x62)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE = (0x20800a62)
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET = (0x00000000)
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE = (0x00000001)
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE = (0x00000002)
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID = (0x64)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY = (0x20800a64)
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID = (0x78)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG = (0x20800a78)
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID = (0x7D)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK = (0x20800a7d)
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID = (0x82)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION = (0x20800a82)
|
|
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID = (0x83)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY = (0x20800a83)
|
|
NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID = (0x84)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI = (0x20800a84)
|
|
NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE = 64
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID = (0x85)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET = (0x20800a85)
|
|
NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID = (0x86)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI = (0x20800a86)
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_INVALID_TIME_MS = 0
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x87)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO = (0x20800a87)
|
|
NV2080_CTRL_INTERNAL_NVLINK_MAX_LINKS_PER_IOCTRL_SW = 6
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x8E)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO = (0x20800a8e)
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID = (0x8F)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED = (0x20800a8f)
|
|
NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID = (0x90)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED = (0x20800a90)
|
|
NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_ASSERT = (0x00000000)
|
|
NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_DEASSERT = (0x00000001)
|
|
NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_TOGGLE = (0x00000002)
|
|
NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID = (0x91)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS = (0x20800a91)
|
|
NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID = (0x92)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS = (0x20800a92)
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID = (0x93)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO = (0x20800a93)
|
|
NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID = (0x94)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM = (0x20800a94)
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID = (0x95)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS = (0x20800a95)
|
|
NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID = (0x96)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS = (0x20800a96)
|
|
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID = (0x97)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS = (0x20800a97)
|
|
NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID = (0xAB)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK = (0x20800aab)
|
|
NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x89)
|
|
NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO = (0x20800a89)
|
|
NV2080_CTRL_INTERNAL_HFRP_INSTANCE_SIZE = 5
|
|
NV2080_CTRL_INTERNAL_GPU_GET_HFRP_INFO_PARAMS_MESSAGE_ID = (0x7A)
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_HFRP_INFO = (0x20800a7a)
|
|
NV2080_CTRL_INTERNAL_SEND_CMC_UMD_API_OP_PARAMS_MESSAGE_ID = (0x7C)
|
|
NV2080_INTERNAL_CMC_UMD_API_TASK_CONSTRUCT = 0x0
|
|
NV2080_INTERNAL_CMC_UMD_API_TASK_DESTROY = 0x1
|
|
NV2080_INTERNAL_CMC_UMD_API_TASK_ADD_QUEUE = 0x2
|
|
NV2080_CTRL_CMD_INTERNAL_SEND_CMC_UMD_API_OP = (0x20800a7c)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS = (0x20800b01)
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID = (0x02)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2 = (0x20800b03)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID = (0x03)
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID = (0x04)
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL = (0x20800b05)
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_THROTTLE_CTRL_PARAMS_MESSAGE_ID = (0x05)
|
|
NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY = (0x20800b11)
|
|
NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS_MESSAGE_ID = (0x11)
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEYS = (0x20800b07)
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_PER_CHANNEL_KEYS_PARAMS_MESSAGE_ID = (0x07)
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_RC_USER_MODE_CHANNELS = (0x20800b08)
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES = (0x20800b06)
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_POSSIBLE_REFRESH_RATES_PARAMS_MESSAGE_ID = (0x06)
|
|
NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE = (0x20800b12)
|
|
NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_STATE_PARAMS_MESSAGE_ID = (0x12)
|
|
NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE = (0x20800b13)
|
|
NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_SET_STATE_PARAMS_MESSAGE_ID = (0x13)
|
|
NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_MAX_DATA_SIZE = 65536
|
|
NV2080_CTRL_CMD_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA = (0x20800b14)
|
|
NV2080_CTRL_INTERNAL_UCODE_INSTRUMENTATION_GET_DATA_PARAMS_MESSAGE_ID = (0x14)
|
|
NV2080_CTRL_CMD_LPWR_DIFR_CTRL = (0x20802801)
|
|
NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE = (0x00000001)
|
|
NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE = (0x00000002)
|
|
NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS = (0x00000003)
|
|
NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_LPWR_DIFR_SUPPORTED = (0x00000001)
|
|
NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED = (0x00000002)
|
|
NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE = (0x20802802)
|
|
NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS = (0x00000001)
|
|
NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED = (0x00000002)
|
|
NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE = (0x00000003)
|
|
NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR = (0x00000004)
|
|
NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_MC_GET_ARCH_INFO = (0x20801701)
|
|
NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X = (0xE0000023)
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 = (0x00000160)
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 = (0x00000170)
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100 = (0x00000180)
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 = (0x00000190)
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100 = (0x000001A0)
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200 = (0x000001B0)
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GR100 = (0x000001C0)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 = (0x00000004)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D = (0x00000005)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100 = (0x00000000)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102 = (0x00000002)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104 = (0x00000004)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106 = (0x00000006)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116 = (0x00000008)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117 = (0x00000007)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100 = (0x00000000)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102 = (0x00000002)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103 = (0x00000003)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104 = (0x00000004)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106 = (0x00000006)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107 = (0x00000007)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B = (0x0000000B)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100 = (0x00000000)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC = (0x00000001)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100 = (0x00000000)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000 = (0x00000001)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101 = (0x00000001)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102 = (0x00000002)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103 = (0x00000003)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104 = (0x00000004)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106 = (0x00000006)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107 = (0x00000007)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 = (0x00000000)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 = (0x00000002)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB110 = (0x00000003)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB112 = (0x00000004)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 = (0x00000000)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 = (0x00000002)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 = (0x00000003)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 = (0x00000005)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 = (0x00000006)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 = (0x00000007)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20B = (0x0000000B)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20C = (0x0000000C)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GR100 = (0x00000000)
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GR102 = (0x00000002)
|
|
NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION = (0x00000000)
|
|
NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P = (0x00000001)
|
|
NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q = (0x00000002)
|
|
NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R = (0x00000003)
|
|
NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS = (0x20801702)
|
|
NV2080_CTRL_MC_ENGINE_ID_GRAPHICS = 0x00000001
|
|
NV2080_CTRL_MC_ENGINE_ID_ALL = 0xFFFFFFFF
|
|
NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_MC_GET_MANUFACTURER = (0x20801703)
|
|
NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP = (0x2080170c)
|
|
NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID = (0xC)
|
|
NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS = (0x2080170d)
|
|
NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES = 256
|
|
NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID = (0xD)
|
|
NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE = (0x2080170e)
|
|
NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX = 32
|
|
NV2080_INTR_TYPE_NULL = (0x00000000)
|
|
NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT = (0x00000001)
|
|
NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR = (0x00000002)
|
|
NV2080_INTR_TYPE_INFO_FAULT = (0x00000003)
|
|
NV2080_INTR_TYPE_REPLAYABLE_FAULT = (0x00000004)
|
|
NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR = (0x00000005)
|
|
NV2080_INTR_TYPE_ACCESS_CNTR = (0x00000006)
|
|
NV2080_INTR_TYPE_TMR = (0x00000007)
|
|
NV2080_INTR_TYPE_CPU_DOORBELL = (0x00000008)
|
|
NV2080_INTR_TYPE_GR0_FECS_LOG = (0x00000009)
|
|
NV2080_INTR_TYPE_GR1_FECS_LOG = (0x0000000A)
|
|
NV2080_INTR_TYPE_GR2_FECS_LOG = (0x0000000B)
|
|
NV2080_INTR_TYPE_GR3_FECS_LOG = (0x0000000C)
|
|
NV2080_INTR_TYPE_GR4_FECS_LOG = (0x0000000D)
|
|
NV2080_INTR_TYPE_GR5_FECS_LOG = (0x0000000E)
|
|
NV2080_INTR_TYPE_GR6_FECS_LOG = (0x0000000F)
|
|
NV2080_INTR_TYPE_GR7_FECS_LOG = (0x00000010)
|
|
NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID = (0xE)
|
|
NV2080_CTRL_CMD_MC_GET_INTR_CATEGORY_SUBTREE_MAP = (0x2080170f)
|
|
NV2080_CTRL_MC_GET_INTR_CATEGORY_SUBTREE_MAP_PARAMS_MESSAGE_ID = (0xF)
|
|
NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE = (0x20802401)
|
|
NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_CMD_NVD_GET_DUMP = (0x20802402)
|
|
NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL = (0x20802409)
|
|
NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER = 1024
|
|
NV2080_NOCAT_JOURNAL_MAX_STR_LEN = 65
|
|
NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS = 10
|
|
NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS = 32
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN = 0
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK = 1
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE = 2
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_TDR = 3
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_RC = 4
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT = 5
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_ANY = 6
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT = (0x7)
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX = 0
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX = 1
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX = 2
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX = 3
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX = 4
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATION_FAIL_IDX = 5
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX = 6
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX = 7
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX = 8
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX = 9
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX = 10
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX = 11
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX = 12
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX = 13
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX = 14
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX = 15
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX = 16
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX = 17
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX = 18
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX = 19
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX = 20
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX = 21
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX = 22
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX = 23
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX = 24
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX = 25
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX = 26
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX = 27
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX = 28
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX = 29
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX = 30
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX = 31
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT = (0x20)
|
|
NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY = (0, 0)
|
|
NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES = 1
|
|
NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO = 0
|
|
NV2080_CTRL_NOCAT_GET_RESET_COUNTERS = (1, 1)
|
|
NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES = 1
|
|
NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO = 0
|
|
NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID = (0x9)
|
|
NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA = (0x2080240b)
|
|
NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY = 0
|
|
NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON = 1
|
|
NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG = 2
|
|
NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG = 3
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_NONE = 0
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY = 1
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP = 2
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET = 3
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET = 4
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL = 5
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET = 6
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_GPU_RC_RESET = 7
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_TEST = 8
|
|
NV2080_CTRL_NOCAT_TAG_CLEAR = (0, 0)
|
|
NV2080_CTRL_NOCAT_TAG_CLEAR_YES = 1
|
|
NV2080_CTRL_NOCAT_TAG_CLEAR_NO = 0
|
|
NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID = (0xB)
|
|
NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD = (0x2080240c)
|
|
NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR = (0, 0)
|
|
NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES = 1
|
|
NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO = 0
|
|
NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER = (1, 1)
|
|
NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES = 1
|
|
NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO = 0
|
|
NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID = (0xC)
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_NVLINK_CAPS_TBL_SIZE = 2
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID = (0x00000000)
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 = (0x00000001)
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0 = (0x00000002)
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 = (0x00000004)
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 = (0x00000005)
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 = (0x00000006)
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 = (0x00000007)
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0 = (0x00000008)
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_6_0 = (0x00000009)
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID = (0x00000000)
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 = (0x00000001)
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 = (0x00000002)
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 = (0x00000004)
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 = (0x00000005)
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 = (0x00000006)
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 = (0x00000007)
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0 = (0x00000008)
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_6_0 = (0x00000009)
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS = (0x20803001)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS = (31, 0)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE = (0x00000000)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI = (0x00000001)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID = (0x00000002)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE = (0x00000000)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU = (0x00000001)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU = (0x00000002)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH = (0x00000003)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA = (0x00000004)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE = (0x000000FF)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID = (0xFFFFFFFF)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED = (0, 0)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_FALSE = (0x00000000)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_TRUE = (0x00000001)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY = (1, 1)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_INACTIVE = (0x00000000)
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_ACTIVE = (0x00000001)
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT = (0x00000000)
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG = (0x00000001)
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG = (0x00000002)
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE = (0x00000003)
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT = (0x00000004)
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP = (0x00000005)
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY = (0x00000006)
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC = (0x00000008)
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX = (0x0000000a)
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID = (0xFFFFFFFF)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 = (0x00000000)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE = (0x00000004)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER = (0x00000004)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING = (0x00000005)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE = (0x00000006)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF = (0x00000007)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST = (0x00000008)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT = (0x0000000e)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID = (0x000000FF)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 = (0x00000000)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE = (0x00000004)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER = (0x00000004)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING = (0x00000005)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE = (0x00000006)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF = (0x00000007)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST = (0x00000008)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT = (0x0000000e)
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID = (0x000000FF)
|
|
NV2080_CTRL_NVLINK_STATUS_PHY_NVHS = (0x00000001)
|
|
NV2080_CTRL_NVLINK_STATUS_PHY_GRS = (0x00000002)
|
|
NV2080_CTRL_NVLINK_STATUS_PHY_INVALID = (0x000000FF)
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0 = (0x00000001)
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0 = (0x00000002)
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2 = (0x00000004)
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 = (0x00000005)
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 = (0x00000006)
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 = (0x00000007)
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0 = (0x00000008)
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_6_0 = (0x00000009)
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID = (0x000000FF)
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 = (0x00000001)
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0 = (0x00000002)
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2 = (0x00000004)
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0 = (0x00000005)
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 = (0x00000006)
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 = (0x00000007)
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0 = (0x00000008)
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_6_0 = (0x00000009)
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID = (0x000000FF)
|
|
NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 = (0x00000001)
|
|
NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID = (0x000000FF)
|
|
NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0 = (0x00000001)
|
|
NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID = (0x000000FF)
|
|
NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE = (0x00000001)
|
|
NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE = (0x00000000)
|
|
NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK = (0x00000001)
|
|
NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT = (0x00000002)
|
|
NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE = (0x00000000)
|
|
NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID = (0x000000FF)
|
|
NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID = (0x00)
|
|
NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS = (0x01)
|
|
NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX = (0x02)
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS = (0x20803002)
|
|
NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT = lambda intr,i: (((1 << i) & (intr)) >> i) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_TL_INTEN_BIT = lambda intr,i: NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i) # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE = (0x00000001)
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE = (0x00000000)
|
|
NV2080_CTRL_NVLINK_TL_INTEN_TRUE = (0x00000001)
|
|
NV2080_CTRL_NVLINK_TL_INTEN_FALSE = (0x00000000)
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN = 0
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN = 1
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN = 2
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN = 3
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN = 4
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN = 5
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN = 6
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN = 7
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN = 8
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN = 9
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN = 10
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN = 12
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN = 13
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX = 14
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR = 0
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR = 1
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR = 2
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR = 3
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR = 4
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR = 5
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR = 6
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR = 7
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR = 8
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR = 9
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR = 10
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR = 12
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR = 13
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX = 14
|
|
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS = (0x00000000)
|
|
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE = (0x00000004)
|
|
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN = (0x00000005)
|
|
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE = (0x00000006)
|
|
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF = (0x00000007)
|
|
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS = (0x00000000)
|
|
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE = (0x00000004)
|
|
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN = (0x00000005)
|
|
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE = (0x00000006)
|
|
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF = (0x00000007)
|
|
NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT = (0x0)
|
|
NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS = (0x1)
|
|
NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS = (0x2)
|
|
NV2080_CTRL_NVLINK_MAX_IOCTRLS = 3
|
|
NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO = (0x20803003)
|
|
NV2080_CTRL_NVLINK_COUNTER_INVALID = 0x00000000
|
|
NV2080_CTRL_NVLINK_COUNTER_TL_TX0 = 0x00000001
|
|
NV2080_CTRL_NVLINK_COUNTER_TL_TX1 = 0x00000002
|
|
NV2080_CTRL_NVLINK_COUNTER_TL_RX0 = 0x00000004
|
|
NV2080_CTRL_NVLINK_COUNTER_TL_RX1 = 0x00000008
|
|
NV2080_CTRL_NVLINK_LP_COUNTERS_DL = 0x00000010
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L = lambda i: (1 << (i + 8)) # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE = 4
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0 = 0x00000100
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1 = 0x00000200
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2 = 0x00000400
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3 = 0x00000800
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT = 0x00010000
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L = lambda i: (1 << (i + 17)) # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE = 8
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 = 0x00020000
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 = 0x00040000
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 = 0x00080000
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 = 0x00100000
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 = 0x00200000
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 = 0x00400000
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 = 0x00800000
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 = 0x01000000
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY = 0x02000000
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY = 0x04000000
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY = 0x08000000
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED = 0x10000000
|
|
NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES = 32
|
|
NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID = (0x4)
|
|
NV2080_CTRL_CMD_NVLINK_GET_COUNTERS = (0x20803004)
|
|
NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS = (0x20803005)
|
|
NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID = (0x5)
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX0 = 0
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX1 = 1
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX0 = 2
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX1 = 3
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_SIZE = 4
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L0 = 4
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L1 = 5
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L2 = 6
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L3 = 7
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_SIZE = 8
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L0 = 8
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L1 = 9
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L2 = 10
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L3 = 11
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L4 = 12
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L5 = 13
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L6 = 14
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L7 = 15
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_RECOVERY = 16
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_REPLAY = 17
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_REPLAY = 18
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_MASKED = 19
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_FLIT = 20
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_DL = 21
|
|
NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER = NV2080_CTRL_NVLINK_COUNTER_LP_DL
|
|
NV2080_CTRL_NVLINK_COUNTER_XMIT_PACKETS = 22
|
|
NV2080_CTRL_NVLINK_COUNTER_XMIT_BYTES = 23
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_PACKETS = 24
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_BYTES = 25
|
|
NV2080_CTRL_NVLINK_COUNTER_LINK_ERROR_RECOVERY_COUNTER = 26
|
|
NV2080_CTRL_NVLINK_COUNTER_LINK_DOWNED_COUNTER = 27
|
|
NV2080_CTRL_NVLINK_COUNTER_LINK_RECOVERY_SUCCESSFUL_COUNTER = 28
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_ERRORS = 29
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_REMOTE_ERRORS = 30
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_GENERAL_ERRORS = 31
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_MALFORMED_PKT_ERROR = 32
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_BUFFER_OVERRUN_ERROR = 33
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_VL15DROPPED_ERROR = 34
|
|
NV2080_CTRL_NVLINK_COUNTER_LINK_INTEGRITY_ERRORS = 35
|
|
NV2080_CTRL_NVLINK_COUNTER_BUFFER_OVERRUN_ERRORS = 36
|
|
NV2080_CTRL_NVLINK_COUNTER_XMIT_WAIT_TIME = 37
|
|
NV2080_CTRL_NVLINK_COUNTER_XMIT_ERRORS = 38
|
|
NV2080_CTRL_NVLINK_COUNTER_SINGLE_ERROR_BLOCKS = 39
|
|
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BLOCKS = 40
|
|
NV2080_CTRL_NVLINK_COUNTER_UNCORRECTED_BLOCKS = 41
|
|
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_0 = 42
|
|
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_1 = 43
|
|
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_TOTAL = 44
|
|
NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_0 = 45
|
|
NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_1 = 46
|
|
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BITS = 47
|
|
NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_0 = 48
|
|
NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_1 = 49
|
|
NV2080_CTRL_NVLINK_COUNTER_RAW_BER_TOTAL = 50
|
|
NV2080_CTRL_NVLINK_COUNTER_NO_ERROR_BLOCKS = 51
|
|
NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_ERRORS = 52
|
|
NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_BER = 53
|
|
NV2080_CTRL_NVLINK_COUNTER_SYMBOL_ERRORS = 54
|
|
NV2080_CTRL_NVLINK_COUNTER_SYMBOL_BER = 55
|
|
NV2080_CTRL_NVLINK_COUNTER_RECEIVED_BITS = 56
|
|
NV2080_CTRL_NVLINK_COUNTER_SYNC_HEADER_ERRORS = 57
|
|
NV2080_CTRL_NVLINK_COUNTER_TIME_SINCE_LAST_CLEAR = 58
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS = 59
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_UNCORRECTABLE_ERRORS = 60
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_ERRORS = 61
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_BLOCKS = 62
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_BLOCKS = 63
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS = 64
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_BW_LOSS = 65
|
|
NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_GOOD = 66
|
|
NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_ERROR = 67
|
|
NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_AUTH = 68
|
|
NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_GOOD = 69
|
|
NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_ERROR = 70
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_0 = 71
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_1 = 72
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_2 = 73
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_3 = 74
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_4 = 75
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_5 = 76
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_6 = 77
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_7 = 78
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_8 = 79
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_9 = 80
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_10 = 81
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_11 = 82
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_12 = 83
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_13 = 84
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_14 = 85
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_15 = 86
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_RX_DATA = 87
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_TX_DATA = 88
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_RX_RAW = 89
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_TX_RAW = 90
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY = 91
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY_FORCE = 92
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_EXIT = 93
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_RECAL = 94
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_REMOTE = 95
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_LP_STEADY_STATE_TIME = 96
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_HIGH_SPEED_STEADY_STATE_TIME = 97
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_OTHER_STATE_TIME = 98
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_ENTRY_TIME = 99
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_EXIT_TIME = 100
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_ENTRY_TIME = 101
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_EXIT_TIME = 102
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_ENTRY_TIME = 103
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_EXIT_TIME = 104
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_ENTRY_TIME = 105
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_EXIT_TIME = 106
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_LAST_RAW_BER = 107
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS_WITHIN_T_SEC_MAX_LOW = 108
|
|
NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_ENTRY = 109
|
|
NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_ENTRY_DUE_TO_L1 = 110
|
|
NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_REQ_NOT_YET_ACTIVE = 111
|
|
NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_ACTIVE_DUE_TO_L1_REQ = 112
|
|
NV2080_CTRL_NVLINK_COUNTER_L0_TX_IDLE_ACTIVE = 113
|
|
NV2080_CTRL_NVLINK_COUNTERS_MAX = 114
|
|
NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS = 2
|
|
NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ = 28
|
|
NV2080_CTRL_NVLINK_COUNTER_V2_GROUP = lambda i: ((i) / 64) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID = (0x50)
|
|
NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2 = (0x20803050)
|
|
NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID = (0x51)
|
|
NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2 = (0x20803051)
|
|
NV2080_CTRL_CMD_NVLINK_INJECT_ERROR = (0x20803006)
|
|
NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID = (0x6)
|
|
NV2080_CTRL_NVLINK_UNIT_DL = 0x01
|
|
NV2080_CTRL_NVLINK_UNIT_TL = 0x02
|
|
NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 = 0x03
|
|
NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 = 0x04
|
|
NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 = 0x05
|
|
NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 = 0x06
|
|
NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 = 0x07
|
|
NV2080_CTRL_NVLINK_UNIT_MINION = 0x08
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE = (31, 28)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_NO_ERROR = 0x00000000
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_RAW_BER = 0x00000001
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_EFFECTIVE_BER = 0x00000002
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_ERR_INJECT_DURATION = (27, 12)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_MANTISSA = (11, 8)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_EXPONENT = (7, 0)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_INJECT_COUNT = (15, 0)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP = (16, 16)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_DIS = 0x00000000
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_EN = 0x00000001
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON = (17, 17)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_DIS = 0x00000000
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_EN = 0x00000001
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_CLEAR_COUNTERS = (18, 18)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_PIPE_INDEX = (3, 0)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR = (4, 4)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_DIS = 0x00000000
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_EN = 0x00000001
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN = (0, 0)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_DIS = 0x00000000
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_EN = 0x00000001
|
|
NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID = (0x81)
|
|
NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT = (0x20803081)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE = (1, 0)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_UP = 0x00000000
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_REQUEST = 0x00000001
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_HW_ERR = 0x00000002
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS = (0, 0)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_NO_ERR_INJECT = 0x00000000
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_PERFORMING_ERR_INJECT = 0x00000001
|
|
NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID = (0x82)
|
|
NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT = (0x20803082)
|
|
NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES = (0x20803007)
|
|
NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID = (0x7)
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE = (0x20803008)
|
|
NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID = (0x8)
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS = (0x20803009)
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY = 0
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY = 1
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL = 2
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW = 3
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY = 4
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY = 5
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP = 6
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON = 7
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY = 8
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY = 9
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT = 10
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY = 11
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY = 12
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG = 13
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM = 14
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE = 15
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE = 16
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE = 17
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL = 18
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT = 19
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY = 0
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY = 1
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY = 4
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY = 5
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD = 7
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY = 8
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY = 9
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY = 11
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY = 20
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD = 21
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD = 22
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN = 23
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN = 24
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC = 25
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC = 26
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE = 27
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS = 28
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS = 29
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ = 30
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP = 31
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE = 32
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE = 33
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE = 34
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR = 35
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP = 36
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET = 37
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST = 38
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW = 39
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW = 40
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD = 41
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL = 42
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW = 43
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE = 44
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE = 45
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW = 46
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW = 47
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW = 48
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW = 49
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT = 50
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT = 51
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET = 52
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST = 53
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY = 54
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY = 55
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY = 56
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY = 57
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE = 58
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE = 59
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY = 60
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP = 61
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN = 62
|
|
NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES = 63
|
|
NV2080_CTRL_NVLINK_IS_FATAL_ERROR_COUNT_VALID = lambda count,supportedCounts: ( not not ((supportedCounts) & NVBIT64(count))) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID = (0x9)
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES = (0x2080300a)
|
|
NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES = 5
|
|
NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID = (0xA)
|
|
NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE = (0x2080300b)
|
|
NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID = (0xB)
|
|
NV2080_CTRL_CMD_NVLINK_SETUP_EOM = (0x2080300c)
|
|
NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID = (0xC)
|
|
NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE = (0x2080300d)
|
|
NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID = (0xD)
|
|
NV2080_CTRL_NVLINK_POWER_STATE_L0 = (0x00)
|
|
NV2080_CTRL_NVLINK_POWER_STATE_L1 = (0x01)
|
|
NV2080_CTRL_NVLINK_POWER_STATE_L2 = (0x02)
|
|
NV2080_CTRL_NVLINK_POWER_STATE_L3 = (0x03)
|
|
NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE = (0x2080300e)
|
|
NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID = (0xE)
|
|
NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR = (0x2080300f)
|
|
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID = (0xF)
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES = (0x20803011)
|
|
NV2080_CTRL_NVLINK_MAX_LANES = 4
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID = (0x11)
|
|
NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER = (0x20803012)
|
|
NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x12)
|
|
NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG = (0x20803013)
|
|
NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID = (0x13)
|
|
NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID = (0x14)
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS = (0x20803014)
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX = 0
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX = 1
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX = 2
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX = 3
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX = 4
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID = (0x15)
|
|
NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS = (0x20803015)
|
|
NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE = (0x20803016)
|
|
NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID = (0x16)
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS = 0
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH = 1
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER = 2
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER = 3
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT = 4
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP = 5
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME = 6
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME = 7
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME = 8
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME = 9
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME = 10
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME = 11
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME = 12
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME = 13
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME = 14
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME = 15
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS = 16
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID = (0x18)
|
|
NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS = (0x20803018)
|
|
NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS = (0x20803052)
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT = (0x00000000)
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA = (0x00000001)
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR = (0x00000002)
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW = (0x00000003)
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_REMOTE = (0x00000004)
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_LOCAL = (0x00000005)
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_EXT_LOCAL = (0x00000006)
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID = (0x23)
|
|
NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE = (0x20803023)
|
|
NV2080_CTRL_NVLINK_MAX_LINK_COUNT = 32
|
|
NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID = (0x28)
|
|
NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS = (0x20803028)
|
|
NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID = (0x29)
|
|
NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS = (0x20803029)
|
|
NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID = (0x38)
|
|
NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR = (0x20803038)
|
|
NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID = (0x39)
|
|
NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO = (0x20803039)
|
|
NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS = (0x2080303a)
|
|
NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID = (0x3b)
|
|
NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS = (0x2080303b)
|
|
NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID = (0x3c)
|
|
NV2080_CTRL_CMD_NVLINK_EOM_CONTROL = (0x2080303c)
|
|
NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE = 5120
|
|
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID = (0x3d)
|
|
NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE = (0x2080303d)
|
|
NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT = (0xFFFFFFFF)
|
|
NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID = (0x3e)
|
|
NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD = (0x2080303e)
|
|
NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID = (0x3f)
|
|
NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD = (0x2080303f)
|
|
NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID = (0x40)
|
|
NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA = (0x20803040)
|
|
NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID = (0x41)
|
|
NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED = (0x20803041)
|
|
NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID = (0x42)
|
|
NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK = (0x20803042)
|
|
NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID = (0x43)
|
|
NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP = (0x20803043)
|
|
NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE = 64
|
|
NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID = (0x44)
|
|
NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS = (0x20803044)
|
|
NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID = (0x45)
|
|
NV2080_CTRL_CMD_NVLINK_CYCLE_LINK = (0x20803045)
|
|
NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID = (0x46)
|
|
NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG = (0x20803046)
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH = 496
|
|
NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS = (0x20803074)
|
|
NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID = (0x74)
|
|
NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO = (0x20803083)
|
|
NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID = (0x83)
|
|
NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN = (0x20803084)
|
|
NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID = (0x84)
|
|
NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT = 23
|
|
NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE = (0x20803085)
|
|
NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID = (0x85)
|
|
NV2080_CTRL_CMD_NVLINK_SET_BW_MODE_POLL_TIMEOUT_MS_INVALID = 0
|
|
NV2080_CTRL_CMD_NVLINK_SET_BW_MODE = (0x20803086)
|
|
NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID = (0x86)
|
|
NV2080_CTRL_CMD_NVLINK_GET_BW_MODE = (0x20803087)
|
|
NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID = (0x87)
|
|
NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO = (0x20803088)
|
|
NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x88)
|
|
NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR = (0x20803089)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID = (0x89)
|
|
NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY = (0x2080308c)
|
|
NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS_MESSAGE_ID = (0x8c)
|
|
NV2080_CTRL_NVLINK_MAX_REMAP_TABLE_ENTRIES = 32
|
|
NV2080_CTRL_NVLINK_MAX_REMAP_TABLE_ENTRIES_V2 = 4096
|
|
NV2080_CTRL_NVLINK_REMAP_TABLE_ENTRIES_CHUNK = 128
|
|
NV2080_CTRL_NVLINK_MAX_ALID_CLID_TABLE_ENTRIES = 128
|
|
NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS = (0x2080308d)
|
|
NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_PARAMS_MESSAGE_ID = (0x8d)
|
|
NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY = (0x2080308a)
|
|
NV2080_CTRL_CMD_NVLINK_CONFIGURE_L1_TOGGLE = (0x2080308e)
|
|
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID = (0x8E)
|
|
NV2080_CTRL_CMD_NVLINK_GET_L1_TOGGLE = (0x2080308f)
|
|
NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID = (0x8F)
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLE_ENCRYPT_EN_INFO = (0x2080308b)
|
|
NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS_MESSAGE_ID = (0x8b)
|
|
NV2080_CTRL_NVLINK_FIRMWARE_VERSION_LENGTH = (0x10)
|
|
NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_MSE = (0x01)
|
|
NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR = (0x02)
|
|
NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR_UPHY = (0x03)
|
|
NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR_CLN = (0x04)
|
|
NV2080_CTRL_NVLINK_SEMANTIC_VERSION_UCODE_TYPE_NETIR_DLN = (0x05)
|
|
NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO = (0x20803091)
|
|
NV2080_CTRL_NVLINK_GET_FIRMWARE_VERSION_INFO_PARAMS_MESSAGE_ID = (0x91)
|
|
NV2080_CTRL_CMD_NVLINK_SET_NVLE_ENABLED_STATE = (0x20803092)
|
|
NV2080_CTRL_NVLINK_SET_NVLE_ENABLED_STATE_PARAMS_MESSAGE_ID = (0x92)
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS = (0x20803095)
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS_MESSAGE_ID = (0x95)
|
|
NV2080_CTRL_NVLINK_FIXED_POINT_HISTOGRAM_MAX_SIZE = 32
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA = (0x20803097)
|
|
NV2080_CTRL_NVLINK_GET_LINK_ACCUMULATIVE_METRIC_DATA_PARAMS_MESSAGE_ID = (0x97)
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_RECORD_METRIC_DATA = (0x20803098)
|
|
NV2080_CTRL_NVLINK_GET_LINK_RECORD_METRIC_DATA_PARAMS_MESSAGE_ID = (0x98)
|
|
NV2080_CTRL_CMD_NVLINK_GET_DEVICE_RECORD_METRIC_DATA = (0x20803099)
|
|
NV2080_CTRL_NVLINK_GET_DEVICE_RECORD_METRIC_DATA_PARAMS_MESSAGE_ID = (0x99)
|
|
NV2080_CTRL_NVLINK_SAVE_NODE_HOSTNAME_PARAMS_MESSAGE_ID = (0x9A)
|
|
NV2080_CTRL_CMD_NVLINK_SAVE_NODE_HOSTNAME = (0x2080309a)
|
|
NV2080_CTRL_NVLINK_GET_SAVED_NODE_HOSTNAME_PARAMS_MESSAGE_ID = (0x9B)
|
|
NV2080_CTRL_CMD_NVLINK_GET_SAVED_NODE_HOSTNAME = (0x2080309b)
|
|
NV2080_CTRL_NVLINK_UPDATE_CLID_PARAMS_MESSAGE_ID = (0x9C)
|
|
NV2080_CTRL_CMD_NVLINK_UPDATE_CLID = (0x2080309c)
|
|
NV2080_CTRL_NVLINK_LOCK_REMAP_TABLE_AND_MSE_PARAMS_MESSAGE_ID = (0x9D)
|
|
NV2080_CTRL_CMD_NVLINK_LOCK_REMAP_TABLE_AND_MSE = (0x2080309d)
|
|
NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_PARAMS_MESSAGE_ID = (0x9E)
|
|
NV2080_CTRL_CMD_NVLINK_GET_REMAP_TABLE_INFO = (0x2080309e)
|
|
NV2080_CTRL_NVLINK_GET_NVLE_PKT_COUNTERS_PARAMS_MESSAGE_ID = (0x9F)
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLE_PKT_COUNTERS = (0x2080309f)
|
|
NV2080_CTRL_NVLINK_NVLE_AES_256_GCM_KEY_SIZE_BYTES = 32
|
|
NV2080_CTRL_NVLINK_SETUP_NVLE_ENCRYPTION_KEY_PARAMS_MESSAGE_ID = (0xA0)
|
|
NV2080_CTRL_CMD_NVLINK_SETUP_NVLE_ENCRYPTION_KEY = (0x208030a0)
|
|
NV2080_CTRL_NVLINK_GET_REMAP_TABLE_INFO_V2_PARAMS_MESSAGE_ID = (0xA1)
|
|
NV2080_CTRL_CMD_NVLINK_GET_REMAP_TABLE_INFO_V2 = (0x208030a1)
|
|
NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2_PARAMS_MESSAGE_ID = (0xA2)
|
|
NV2080_CTRL_NVLINK_GET_UPDATE_NVLE_LIDS_V2 = (0x208030a2)
|
|
NV2080_CTRL_NVLINK_MAX_LINKS = 64
|
|
NV2080_CTRL_NVLINK_MAX_ARR_SIZE = 64
|
|
NV2080_CTRL_LINKS_PER_MASK_INDEX = 64
|
|
NV2080_CTRL_NVLINK_MAX_MASK_SIZE = (0x1)
|
|
NV_SUBPROC_NAME_MAX_LENGTH = 100
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CMD = (1, 0)
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR = (0x00000000)
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL = (0x00000001)
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX = (0x00000002)
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA = (4, 4)
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO = (0x00000000)
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES = (0x00000001)
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC = (5, 5)
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO = (0x00000000)
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES = (0x00000001)
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY = (6, 6)
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT = (0x00000000)
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH = (0x00000001)
|
|
NV2080_CTRL_PERF_BOOST_DURATION_MAX = 3600
|
|
NV2080_CTRL_PERF_BOOST_DURATION_INFINITE = 0xffffffff
|
|
NV2080_CTRL_CMD_PERF_BOOST = (0x2080200a)
|
|
NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID = (0xA)
|
|
NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW = (0x20802093)
|
|
NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID = (0x93)
|
|
NV2080_CTRL_PERF_POWER_SOURCE_AC = (0x00000000)
|
|
NV2080_CTRL_PERF_POWER_SOURCE_BATTERY = (0x00000001)
|
|
NV2080_CTRL_CMD_PERF_SET_POWERSTATE = (0x2080205b)
|
|
NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID = (0x5B)
|
|
NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE = (0x20802092)
|
|
NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID = (0x92)
|
|
NV2080_CTRL_PERF_AUX_POWER_STATE_P0 = (0x00000000)
|
|
NV2080_CTRL_PERF_AUX_POWER_STATE_P1 = (0x00000001)
|
|
NV2080_CTRL_PERF_AUX_POWER_STATE_P2 = (0x00000002)
|
|
NV2080_CTRL_PERF_AUX_POWER_STATE_P3 = (0x00000003)
|
|
NV2080_CTRL_PERF_AUX_POWER_STATE_P4 = (0x00000004)
|
|
NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT = (0x00000005)
|
|
NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID = (0x6D)
|
|
NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL = (0x2080206e)
|
|
NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID = (0x6E)
|
|
NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL = (0x2080206f)
|
|
NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID = (0x6F)
|
|
NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID = (0x83)
|
|
NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL = 72
|
|
NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 = (0x20802096)
|
|
NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID = (0x96)
|
|
NV2080_CTRL_CMD_PERF_GPU_IS_IDLE = (0x20802089)
|
|
NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID = (0x89)
|
|
NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE = (0x00000001)
|
|
NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE = (0x00000002)
|
|
NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY = (0x2080208f)
|
|
NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID = (0x8F)
|
|
NV2080_CTRL_PERF_CLK_MAX_DOMAINS = 32
|
|
NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO = (0x20802002)
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2 = (0x2080200b)
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID = (0xB)
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_LEVEL_STANDARD = 0
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_LEVEL_CONSERVATIVE = 1
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_LEVEL_AGGRESSIVE = 2
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE = (0, 0)
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT = (0x00000000)
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK = (0x00000001)
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE = (2, 1)
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE = (0x00000000)
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP = (0x00000001)
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF = (0x00000002)
|
|
NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE = (0x20802087)
|
|
NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID = (0x87)
|
|
NV2080_CTRL_CMD_PERF_GET_POWERSTATE = (0x2080205a)
|
|
NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID = (0x5A)
|
|
NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT = (0x2080205d)
|
|
NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID = (0x5D)
|
|
NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK = (0x0000ffff)
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START = (0x00000001)
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP = (0x00000002)
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START = NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP = NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START = (0x00000003)
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP = (0x00000004)
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START = (0x00000005)
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP = (0x00000006)
|
|
NV2080_CTRL_PERF_VIDEOEVENT_OFA_START = (0x00000007)
|
|
NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP = (0x00000008)
|
|
NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE = (0x00010000)
|
|
NV2080_CTRL_PERF_PSTATES_UNDEFINED = (0x00000000)
|
|
NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED = (0x00000000)
|
|
NV2080_CTRL_PERF_PSTATES_MIN = (0x00000001)
|
|
NV2080_CTRL_PERF_PSTATES_P0 = (0x00000001)
|
|
NV2080_CTRL_PERF_PSTATES_P1 = (0x00000002)
|
|
NV2080_CTRL_PERF_PSTATES_P2 = (0x00000004)
|
|
NV2080_CTRL_PERF_PSTATES_P3 = (0x00000008)
|
|
NV2080_CTRL_PERF_PSTATES_P4 = (0x00000010)
|
|
NV2080_CTRL_PERF_PSTATES_P5 = (0x00000020)
|
|
NV2080_CTRL_PERF_PSTATES_P6 = (0x00000040)
|
|
NV2080_CTRL_PERF_PSTATES_P7 = (0x00000080)
|
|
NV2080_CTRL_PERF_PSTATES_P8 = (0x00000100)
|
|
NV2080_CTRL_PERF_PSTATES_P9 = (0x00000200)
|
|
NV2080_CTRL_PERF_PSTATES_P10 = (0x00000400)
|
|
NV2080_CTRL_PERF_PSTATES_P11 = (0x00000800)
|
|
NV2080_CTRL_PERF_PSTATES_P12 = (0x00001000)
|
|
NV2080_CTRL_PERF_PSTATES_P13 = (0x00002000)
|
|
NV2080_CTRL_PERF_PSTATES_P14 = (0x00004000)
|
|
NV2080_CTRL_PERF_PSTATES_P15 = (0x00008000)
|
|
NV2080_CTRL_PERF_PSTATES_MAX = NV2080_CTRL_PERF_PSTATES_P15
|
|
NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY = (0x10000)
|
|
NV2080_CTRL_PERF_PSTATES_ALL = (0xffff)
|
|
NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE = (0x20802068)
|
|
NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID = (0x68)
|
|
NV2080_CTRL_CMD_PERF_GET_TEGRA_PERFMON_SAMPLE = (0x20802069)
|
|
NV2080_CTRL_PERF_GET_TEGRA_PERFMON_SAMPLE_PARAMS_MESSAGE_ID = (0x69)
|
|
NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED = 0
|
|
NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED = 1
|
|
NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE = 2
|
|
NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID = (0x9)
|
|
NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO = (0x20802609)
|
|
NV2080_CTRL_CMD_GC6_ENTRY = (0x2080270d)
|
|
NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID = (0xD)
|
|
NV2080_CTRL_CMD_GC6_EXIT = (0x2080270e)
|
|
NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID = (0xE)
|
|
NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID = (0x4)
|
|
NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM = (0x20802204)
|
|
NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID = (0x5)
|
|
NV2080_CTRL_CMD_RC_GET_ERROR_COUNT = (0x20802205)
|
|
NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE = (0x2000)
|
|
NV2080_CTRL_CMD_RC_GET_ERROR = (0x20802206)
|
|
NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID = (0x13)
|
|
NV2080_CTRL_CMD_RC_GET_ERROR_V2 = (0x20802213)
|
|
NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY = (0x20802207)
|
|
NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID = (0x9)
|
|
NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO = (0x20802209)
|
|
NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE = (0x00000000)
|
|
NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED = (0x00000001)
|
|
NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING = (0x00000002)
|
|
NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED = (0x00000004)
|
|
NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG = (0x2080220a)
|
|
NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG = (0x2080220b)
|
|
NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS = (0x2080220c)
|
|
NV2080_CTRL_CMD_SET_RC_RECOVERY = (0x2080220d)
|
|
NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID = (0xD)
|
|
NV2080_CTRL_CMD_GET_RC_RECOVERY = (0x2080220e)
|
|
NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID = (0xE)
|
|
NV2080_CTRL_CMD_RC_RECOVERY_DISABLED = (0x00000000)
|
|
NV2080_CTRL_CMD_RC_RECOVERY_ENABLED = (0x00000001)
|
|
NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE = (0x2080220f)
|
|
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID = (0xF)
|
|
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN = (0x00000000)
|
|
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END = (0x00000001)
|
|
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS = (0x00000000)
|
|
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL = (0x00000001)
|
|
NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG = (0x20802210)
|
|
NV2080_CTRL_CMD_SET_RC_INFO = (0x20802211)
|
|
NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID = (0x11)
|
|
NV2080_CTRL_CMD_GET_RC_INFO = (0x20802212)
|
|
NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID = (0x12)
|
|
NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE = (0x00000000)
|
|
NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE = (0x00000001)
|
|
NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE = (0x00000000)
|
|
NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE = (0x00000001)
|
|
NV2080_CTRL_CMD_SET_RC_WATCHDOG_INFO = (0x20802214)
|
|
NV2080_CTRL_SET_RC_WATCHDOG_INFO_PARAMS_MESSAGE_ID = (0x14)
|
|
NV2080_CTRL_CMD_GET_RC_WATCHDOG_INFO = (0x20802215)
|
|
NV2080_CTRL_GET_RC_WATCHDOG_INFO_PARAMS_MESSAGE_ID = (0x15)
|
|
RM_GSP_SPDM_CMD_ID_CC_INIT = (0x1)
|
|
RM_GSP_SPDM_CMD_ID_CC_DEINIT = (0x2)
|
|
RM_GSP_SPDM_CMD_ID_CC_CTRL = (0x3)
|
|
RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA = (0x4)
|
|
RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL = (0x5)
|
|
RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST = (0x6)
|
|
RM_GSP_SPDM_CMD_ID_INVALID_COMMAND = (0xFF)
|
|
SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE = 0x2400
|
|
RSVD7_SIZE = 16
|
|
RSVD8_SIZE = 2
|
|
CE_FIPS_SELF_TEST_DATA_SIZE = 16
|
|
CE_FIPS_SELF_TEST_AUTH_TAG_SIZE = 16
|
|
CE_FIPS_SELF_TEST_IV_SIZE = 12
|
|
RM_GSP_SPDM_MSG_ID_CC_INIT = (0x1)
|
|
RM_GSP_SPDM_MSG_ID_CC_DEINIT = (0x2)
|
|
RM_GSP_SPDM_MSG_ID_CC_CTRL = (0x3)
|
|
RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA = (0x4)
|
|
RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL = (0x5)
|
|
RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST = (0x6)
|
|
RM_GSP_SPDM_MSG_ID_INVALID_COMMAND = (0xFF)
|
|
NV2080_CTRL_INTERNAL_SPDM_PARTITION = (0x20800ad9)
|
|
NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID = (0xD9)
|
|
NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT = (0x20800ada)
|
|
NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID = (0xDA)
|
|
THERMAL_SYSTEM_API_VER = 1
|
|
THERMAL_SYSTEM_API_REV = 0
|
|
NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE = (0x00000000)
|
|
NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU = (0x00000001)
|
|
NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY = (0x00000002)
|
|
NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY = (0x00000004)
|
|
NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD = (0x00000008)
|
|
NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN = (0xFFFFFFFF)
|
|
NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_DEFAULT = (0x00000000)
|
|
NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_IGNORE_FAIL = (0x00000001)
|
|
NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2 = (0x20800513)
|
|
NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2_PHYSICAL = (0x20808513)
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPCODE = (0x00000100)
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPCODE = (0x00000101)
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPCODE = (0x00000301)
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPCODE = (0x00000500)
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPCODE = (0x00000510)
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPCODE = (0x00001500)
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPCODE = (0x00000520)
|
|
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPCODE = (0x00000540)
|
|
NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_MAX_COUNT = 0x20
|
|
NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID = (0x13)
|
|
NV2080_CTRL_CMD_TIMER_SCHEDULE = (0x20800401)
|
|
NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME = (0, 0)
|
|
NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS = (0x00000000)
|
|
NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL = (0x00000001)
|
|
NV2080_CTRL_CMD_TIMER_CANCEL = (0x20800402)
|
|
NV2080_CTRL_CMD_TIMER_GET_TIME = (0x20800403)
|
|
NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET = (0x20800404)
|
|
NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID = (0x4)
|
|
NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO = (0x20800406)
|
|
NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES = 16
|
|
NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID = (0x6)
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE = (3, 0)
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME = (0x00000001)
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC = (0x00000002)
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API = (0x00000003)
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS = (0x00000004)
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR = (7, 4)
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU = (0x00000000)
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP = (0x00000001)
|
|
NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ = (0x20800407)
|
|
NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID = (0x7)
|
|
NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT = (0x20803d01)
|
|
NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC = (0x00000001)
|
|
NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC = (0x00000002)
|
|
NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF = (0x20803d02)
|
|
NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW = (0x00000001)
|
|
NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW = (0x00000002)
|
|
NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER = (0x20803d03)
|
|
NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS = (0x20803d04)
|
|
NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID = (0x4)
|
|
NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER = (0x20803d05)
|
|
NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER = (0x20803d06)
|
|
NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS = (0x20803d07)
|
|
NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID = (0x7)
|
|
NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS = (0x20803d08)
|
|
NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID = (0x8)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK = (0x20804001)
|
|
NV2080_CTRL_MAX_VMMU_SEGMENTS = 384
|
|
NV2080_GPU_MAX_ENGINES = 0x54
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID = (0x1)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK = (0x20804002)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID = (0x2)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE = (0x20804003)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID = (0x3)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU = (0x20804004)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID = (0x4)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO = (0x20804005)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID = (0x5)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE = (0x20804006)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID = (0x6)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY = (0x20804007)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID = (0x7)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP = (0x20804008)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID = (0x8)
|
|
NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN = 8
|
|
NV2080_CTRL_MAX_GPC_COUNT = 32
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING = (0x20804009)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID = (0x9)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT = (0x2080400a)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID = (0xA)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG = (0x2080400b)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID = (0xB)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES = (0x2080400c)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID = (0xC)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS = (0x2080400d)
|
|
NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID = (0xD)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE = (0x2080400e)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0xE)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE = (0x2080400f)
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS_MESSAGE_ID = (0xF)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE = (0x20804010)
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_POWER_STATE_PARAMS_MESSAGE_ID = (0x10)
|
|
NV83DE_CTRL_RESERVED = (0x00)
|
|
NV83DE_CTRL_GR = (0x01)
|
|
NV83DE_CTRL_FIFO = (0x02)
|
|
NV83DE_CTRL_DEBUG = (0x03)
|
|
NV83DE_CTRL_INTERNAL = (0x04)
|
|
NV83DE_CTRL_CMD_NULL = (0x83de0000)
|
|
NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE = (0x83de0301)
|
|
NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE = (0x83de0302)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG = (0x83de0307)
|
|
NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID = (0x7)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE = (0x00000001)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE = (0x00000002)
|
|
NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS = (0x00000003)
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG = (0x83de0308)
|
|
NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID = (0x8)
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_ENABLED = (0x00000001)
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_DISABLED = (0x00000002)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK = (0x83de0309)
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID = (0x9)
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL = (0x00000001)
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP = (0x00000002)
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP = (0x00000004)
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT = (0x00000008)
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP = (0x00000010)
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED = (0x00000020)
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE = (0x00000000)
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL = (0x0000FFFF)
|
|
NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE = (0x83de030b)
|
|
NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID = (0xB)
|
|
NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES = (0x83de030c)
|
|
NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL = 100
|
|
NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID = (0xC)
|
|
NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE = (0x83de030f)
|
|
NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID = (0xF)
|
|
NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES = (0x83de0310)
|
|
NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID = (0x10)
|
|
NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS_DEFINED = 1
|
|
NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_HAS_RESIDENT_CHANNEL = 1
|
|
NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE = (0x83de0313)
|
|
NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID = (0x13)
|
|
NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM = (0x00000001)
|
|
NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCSAT = (0x00000002)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING = (0x83de0314)
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID = (0x14)
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING = (0x00000001)
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING = (0x00000002)
|
|
NV83DE_CTRL_CMD_DEBUG_READ_MEMORY = (0x83de0315)
|
|
NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID = (0x15)
|
|
NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY = (0x83de0316)
|
|
NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID = (0x16)
|
|
NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT = (0x83de0317)
|
|
NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID = (0x17)
|
|
NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT = (0x83de0318)
|
|
NV83DE_CTRL_CMD_DEBUG_GET_HANDLES = (0x83de0319)
|
|
NV83DE_CTRL_CMD_READ_SURFACE = (0x83de031a)
|
|
NV83DE_CTRL_CMD_WRITE_SURFACE = (0x83de031b)
|
|
MAX_ACCESS_OPS = 64
|
|
NV83DE_CTRL_CMD_GET_MAPPINGS = (0x83de031c)
|
|
MAX_GET_MAPPINGS_OPS = 64
|
|
NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS = (0x83de031d)
|
|
NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS = 100
|
|
NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0x1D)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG = (0x83de031f)
|
|
NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID = (0x1F)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_DISABLE = (0x00000000)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_ENABLE = (0x00000001)
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG = (0x83de0320)
|
|
NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID = (0x20)
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_DISABLED = (0x00000000)
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_ENABLED = (0x00000001)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP = (0x83de0321)
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID = (0x21)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER = (0x83de0322)
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID = (0x22)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER = (0x83de0323)
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID = (0x23)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT = (0x83de0324)
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID = (0x24)
|
|
NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS = (0x83de0325)
|
|
NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID = (0x25)
|
|
NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY = (0x83de0326)
|
|
NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY = (0x83de0327)
|
|
MAX_ACCESS_MEMORY_OPS = 150
|
|
NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES = 4
|
|
NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO = (0x83de0328)
|
|
NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID = (0x28)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_DROP_DEFERRED_RC = (0x83de0329)
|
|
NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS_MESSAGE_ID = (0x29)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG = (0x83de032a)
|
|
NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID = (0x2A)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_ENABLE = (0x00000001)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_DISABLE = (0x00000002)
|
|
NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_GCC_DEBUG_REQUESTS = (0x00000003)
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG = (0x83de032b)
|
|
NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID = (0x2B)
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_ENABLED = (0x00000001)
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_DISABLED = (0x00000002)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT = (0x83de022d)
|
|
NV83DE_CTRL_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_PARAMS_MESSAGE_ID = (0x2D)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_ACTIVE = (0x00000001)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_NON_PREEMPTABLE_DEBUGGER_CONTEXT_INACTIVE = (0x00000000)
|
|
NV83DE_CTRL_CMD_DEBUG_SET_RECOVERY_SUPPRESSION_TIMEOUT = (0x83de022e)
|
|
NV83DE_CTRL_DEBUG_SET_RECOVERY_SUPPRESSION_TIMEOUT_PARAMS_MESSAGE_ID = (0x2E)
|
|
NVB0CC_CTRL_RESERVED = (0x00)
|
|
NVB0CC_CTRL_PROFILER = (0x01)
|
|
NVB0CC_CTRL_INTERNAL = (0x02)
|
|
NVB0CC_CTRL_CMD_NULL = (0xb0cc0000)
|
|
NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM = (0xb0cc0204)
|
|
NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID = (0x0)
|
|
NVB0CC_CTRL_CMD_INTERNAL_QUIESCE_PMA_CHANNEL = (0xb0cc0201)
|
|
NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_MESSAGE_ID = (0x1)
|
|
NVB0CC_CTRL_CMD_INTERNAL_SRIOV_PROMOTE_PMA_STREAM = (0xb0cc0202)
|
|
NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_MESSAGE_ID = (0x2)
|
|
NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT = (0xb0cc0203)
|
|
NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS_MESSAGE_ID = (0x3)
|
|
NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID = (0x4)
|
|
NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM = (0xb0cc0206)
|
|
NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID = (0x6)
|
|
NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS = (0xb0cc0207)
|
|
NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID = (0x7)
|
|
NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES = (0xb0cc0208)
|
|
NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES = (0xb0cc0209)
|
|
NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY = (0xb0cc020a)
|
|
NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID = (0xa)
|
|
NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES = (0xb0cc0301)
|
|
NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID = (0x1)
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG = (1, 0)
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG = (3, 2)
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG = (5, 4)
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG = (7, 6)
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN = (9, 8)
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT = (11, 10)
|
|
NVB0CC_CTRL_POWER_FEATURE_IGNORE = (0x00000000)
|
|
NVB0CC_CTRL_POWER_FEATURE_DISABLE = (0x00000001)
|
|
NVB0CC_CTRL_POWER_FEATURE_ENABLE = (0x00000002)
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE = NVB0CC_CTRL_POWER_FEATURE_IGNORE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE = NVB0CC_CTRL_POWER_FEATURE_DISABLE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE = NVB0CC_CTRL_POWER_FEATURE_ENABLE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE = NVB0CC_CTRL_POWER_FEATURE_IGNORE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE = NVB0CC_CTRL_POWER_FEATURE_DISABLE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE = NVB0CC_CTRL_POWER_FEATURE_ENABLE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE = NVB0CC_CTRL_POWER_FEATURE_IGNORE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE = NVB0CC_CTRL_POWER_FEATURE_DISABLE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE = NVB0CC_CTRL_POWER_FEATURE_ENABLE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE = NVB0CC_CTRL_POWER_FEATURE_IGNORE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE = NVB0CC_CTRL_POWER_FEATURE_DISABLE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE = NVB0CC_CTRL_POWER_FEATURE_ENABLE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE = NVB0CC_CTRL_POWER_FEATURE_IGNORE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE = NVB0CC_CTRL_POWER_FEATURE_DISABLE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE = NVB0CC_CTRL_POWER_FEATURE_ENABLE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE = NVB0CC_CTRL_POWER_FEATURE_IGNORE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE = NVB0CC_CTRL_POWER_FEATURE_DISABLE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE = NVB0CC_CTRL_POWER_FEATURE_ENABLE
|
|
NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED = (0x00000000)
|
|
NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED = (0x00000001)
|
|
NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED = (0x00000002)
|
|
NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED = (0x00000003)
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FULFILLED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_REJECTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_NOT_SUPPORTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FAILED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FULFILLED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_REJECTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_NOT_SUPPORTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FAILED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FULFILLED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_REJECTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_NOT_SUPPORTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FAILED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FULFILLED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_REJECTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_NOT_SUPPORTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FAILED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FAILED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FULFILLED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_REJECTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_NOT_SUPPORTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FAILED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED
|
|
NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES = (0xb0cc0302)
|
|
NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID = (0x2)
|
|
NVB0CC_CTRL_POWER_FEATURE_RELEASE = (0x00000003)
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE = NVB0CC_CTRL_POWER_FEATURE_RELEASE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE = NVB0CC_CTRL_POWER_FEATURE_RELEASE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE = NVB0CC_CTRL_POWER_FEATURE_RELEASE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE = NVB0CC_CTRL_POWER_FEATURE_RELEASE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE = NVB0CC_CTRL_POWER_FEATURE_RELEASE
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE = NVB0CC_CTRL_POWER_FEATURE_RELEASE
|
|
NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY = (0xb0cc0101)
|
|
NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID = (0x1)
|
|
NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY = (0xb0cc0102)
|
|
NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC = (0xb0cc0103)
|
|
NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID = (0x3)
|
|
NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC = (0xb0cc0104)
|
|
NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM = (0xb0cc0105)
|
|
NVB0CC_PMA_BUFFER_SIZE_MAX = (0xffe00000)
|
|
NVB0CC_PMA_BYTES_AVAILABLE_SIZE = (0x1000)
|
|
NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID = (0x5)
|
|
NVB0CC_CTRL_CMD_FREE_PMA_STREAM = (0xb0cc0106)
|
|
NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID = (0x6)
|
|
NVB0CC_CTRL_CMD_BIND_PM_RESOURCES = (0xb0cc0107)
|
|
NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES = (0xb0cc0108)
|
|
NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT = (0xb0cc0109)
|
|
NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE = 0xFFFFFFFF
|
|
NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID = (0x9)
|
|
NVB0CC_REGOPS_MAX_COUNT = (124)
|
|
NVB0CC_CTRL_CMD_EXEC_REG_OPS = (0xb0cc010a)
|
|
NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0xA)
|
|
NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER = (0xb0cc010b)
|
|
NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER = (0xb0cc010c)
|
|
NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS = (0xb0cc010d)
|
|
NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID = (0xD)
|
|
NVB0CC_CTRL_CMD_SET_HS_CREDITS = (0xb0cc010e)
|
|
NVB0CC_MAX_CREDIT_INFO_ENTRIES = (63)
|
|
NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID = (0xE)
|
|
NVB0CC_CTRL_CMD_GET_HS_CREDITS = (0xb0cc010f)
|
|
NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID = (0xF)
|
|
NVB0CC_CTRL_HES_INVALID = (0x00000000)
|
|
NVB0CC_CTRL_HES_CWD = (0x00000001)
|
|
NVB0CC_CTRL_HES_TPC = (0x00000002)
|
|
NVB0CC_CTRL_CMD_RESERVE_HES = (0xb0cc0113)
|
|
NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID = (0x13)
|
|
NVB0CC_CTRL_CMD_RELEASE_HES = (0xb0cc0114)
|
|
NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID = (0x14)
|
|
NVB0CC_CREDIT_POOL_MAX_COUNT = 30
|
|
NVB0CC_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL = (0xb0cc0115)
|
|
NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL_MESSAGE_ID = (0x15)
|
|
NVB0CC_CTRL_CMD_GET_HS_CREDITS_MAPPING = (0xb0cc0116)
|
|
NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS_MESSAGE_ID = (0x16)
|
|
NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST = (0xb0cc0117)
|
|
NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID = (0x17)
|
|
NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS = (0xb0cc0118)
|
|
NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID = (0x18)
|
|
NVB0CC_CTRL_CMD_RESERVE_CCU_PROF = (0xb0cc0119)
|
|
NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_MESSAGE_ID = (0x19)
|
|
NVB0CC_CTRL_CMD_RELEASE_CCU_PROF = (0xb0cc011a)
|
|
NV_STATUS_LEVEL_OK = 0
|
|
NV_STATUS_LEVEL_WARN = 1
|
|
NV_STATUS_LEVEL_ERR = 3
|
|
NV01_ROOT = (0x00000000)
|
|
NV1_ROOT = (0x00000000)
|
|
NV01_NULL_OBJECT = (0x00000000)
|
|
NV1_NULL_OBJECT = (0x00000000)
|
|
NV01_ROOT_NON_PRIV = (0x00000001)
|
|
NV1_ROOT_NON_PRIV = (0x00000001)
|
|
NV01_ROOT_CLIENT = (0x00000041)
|
|
FABRIC_MANAGER_SESSION = (0x0000000f)
|
|
NV0020_GPU_MANAGEMENT = (0x00000020)
|
|
NV01_DEVICE_0 = (0x00000080)
|
|
NV20_SUBDEVICE_0 = (0x00002080)
|
|
NV2081_BINAPI = (0x00002081)
|
|
NV2082_BINAPI_PRIVILEGED = (0x00002082)
|
|
NV20_SUBDEVICE_DIAG = (0x0000208f)
|
|
NV01_CONTEXT_DMA = (0x00000002)
|
|
NV01_MEMORY_SYSTEM = (0x0000003e)
|
|
NV1_MEMORY_SYSTEM = (0x0000003e)
|
|
NV01_MEMORY_LOCAL_PRIVILEGED = (0x0000003f)
|
|
NV1_MEMORY_LOCAL_PRIVILEGED = (0x0000003f)
|
|
NV01_MEMORY_PRIVILEGED = (0x0000003f)
|
|
NV1_MEMORY_PRIVILEGED = (0x0000003f)
|
|
NV01_MEMORY_LOCAL_USER = (0x00000040)
|
|
NV1_MEMORY_LOCAL_USER = (0x00000040)
|
|
NV01_MEMORY_USER = (0x00000040)
|
|
NV1_MEMORY_USER = (0x00000040)
|
|
NV01_MEMORY_VIRTUAL = (0x00000070)
|
|
NV01_MEMORY_SYSTEM_DYNAMIC = (0x00000070)
|
|
NV1_MEMORY_SYSTEM_DYNAMIC = (0x00000070)
|
|
NV_MEMORY_MAPPER = (0x000000fe)
|
|
NV01_MEMORY_LOCAL_PHYSICAL = (0x000000c2)
|
|
NV01_MEMORY_SYNCPOINT = (0x000000c3)
|
|
NV01_MEMORY_SYSTEM_OS_DESCRIPTOR = (0x00000071)
|
|
NV01_MEMORY_DEVICELESS = (0x000090ce)
|
|
NV01_MEMORY_FRAMEBUFFER_CONSOLE = (0x00000076)
|
|
NV01_MEMORY_HW_RESOURCES = (0x000000b1)
|
|
NV01_MEMORY_LIST_SYSTEM = (0x00000081)
|
|
NV01_MEMORY_LIST_FBMEM = (0x00000082)
|
|
NV01_MEMORY_LIST_OBJECT = (0x00000083)
|
|
NV_IMEX_SESSION = (0x000000f1)
|
|
PROFILER_DEVICE_EVENT = (0x0000b0cd)
|
|
PROFILER_CONTEXT_EVENT = (0x0000b0ce)
|
|
TRACE_DEVICE_EVENT = (0x0000cdcd)
|
|
NV_MEMORY_EXPORT = (0x000000e0)
|
|
NV_CE_UTILS = (0x00000050)
|
|
NV_MEMORY_FABRIC = (0x000000f8)
|
|
NV_MEMORY_FABRIC_IMPORT_V2 = (0x000000f9)
|
|
NV_MEMORY_FABRIC_IMPORTED_REF = (0x000000fb)
|
|
FABRIC_VASPACE_A = (0x000000fc)
|
|
NV_MEMORY_MULTICAST_FABRIC = (0x000000fd)
|
|
IO_VASPACE_A = (0x000000f2)
|
|
NV01_NULL = (0x00000030)
|
|
NV1_NULL = (0x00000030)
|
|
NV01_EVENT = (0x00000005)
|
|
NV1_EVENT = (0x00000005)
|
|
NV01_EVENT_KERNEL_CALLBACK = (0x00000078)
|
|
NV1_EVENT_KERNEL_CALLBACK = (0x00000078)
|
|
NV01_EVENT_OS_EVENT = (0x00000079)
|
|
NV1_EVENT_OS_EVENT = (0x00000079)
|
|
NV01_EVENT_WIN32_EVENT = (0x00000079)
|
|
NV1_EVENT_WIN32_EVENT = (0x00000079)
|
|
NV01_EVENT_KERNEL_CALLBACK_EX = (0x0000007e)
|
|
NV1_EVENT_KERNEL_CALLBACK_EX = (0x0000007e)
|
|
NV01_TIMER = (0x00000004)
|
|
NV1_TIMER = (0x00000004)
|
|
KERNEL_GRAPHICS_CONTEXT = (0x00000090)
|
|
KERNEL_WATCHDOG = (0x0000008f)
|
|
LOCK_STRESS_OBJECT = (0x00000100)
|
|
LOCK_TEST_RELAXED_DUP_OBJECT = (0x00000101)
|
|
NV50_CHANNEL_GPFIFO = (0x0000506f)
|
|
GF100_CHANNEL_GPFIFO = (0x0000906f)
|
|
KEPLER_CHANNEL_GPFIFO_A = (0x0000a06f)
|
|
UVM_CHANNEL_RETAINER = (0x0000c574)
|
|
KEPLER_CHANNEL_GPFIFO_B = (0x0000a16f)
|
|
MAXWELL_CHANNEL_GPFIFO_A = (0x0000b06f)
|
|
PASCAL_CHANNEL_GPFIFO_A = (0x0000c06f)
|
|
VOLTA_CHANNEL_GPFIFO_A = (0x0000c36f)
|
|
TURING_CHANNEL_GPFIFO_A = (0x0000c46f)
|
|
AMPERE_CHANNEL_GPFIFO_A = (0x0000c56f)
|
|
HOPPER_CHANNEL_GPFIFO_A = (0x0000c86f)
|
|
BLACKWELL_CHANNEL_GPFIFO_A = (0x0000c96f)
|
|
BLACKWELL_CHANNEL_GPFIFO_B = (0x0000ca6f)
|
|
NV04_SOFTWARE_TEST = (0x0000007d)
|
|
NV4_SOFTWARE_TEST = (0x0000007d)
|
|
NV30_GSYNC = (0x000030f1)
|
|
VOLTA_USERMODE_A = (0x0000c361)
|
|
TURING_USERMODE_A = (0x0000c461)
|
|
AMPERE_USERMODE_A = (0x0000c561)
|
|
HOPPER_USERMODE_A = (0x0000c661)
|
|
BLACKWELL_USERMODE_A = (0x0000c761)
|
|
NVC371_DISP_SF_USER = (0x0000c371)
|
|
NVC372_DISPLAY_SW = (0x0000c372)
|
|
NVC573_DISP_CAPABILITIES = (0x0000c573)
|
|
NVC673_DISP_CAPABILITIES = (0x0000c673)
|
|
NVC773_DISP_CAPABILITIES = (0x0000c773)
|
|
NVC873_DISP_CAPABILITIES = (0x0000c873)
|
|
NVC973_DISP_CAPABILITIES = (0x0000c973)
|
|
NVCA73_DISP_CAPABILITIES = (0x0000ca73)
|
|
NVCB73_DISP_CAPABILITIES = (0x0000cb73)
|
|
NVCC73_DISP_CAPABILITIES = (0x0000cc73)
|
|
NV04_DISPLAY_COMMON = (0x00000073)
|
|
NV50_DEFERRED_API_CLASS = (0x00005080)
|
|
MPS_COMPUTE = (0x0000900e)
|
|
NVC570_DISPLAY = (0x0000c570)
|
|
NVC57A_CURSOR_IMM_CHANNEL_PIO = (0x0000c57a)
|
|
NVC57B_WINDOW_IMM_CHANNEL_DMA = (0x0000c57b)
|
|
NVC57D_CORE_CHANNEL_DMA = (0x0000c57d)
|
|
NVC57E_WINDOW_CHANNEL_DMA = (0x0000c57e)
|
|
NVC670_DISPLAY = (0x0000c670)
|
|
NVC671_DISP_SF_USER = (0x0000c671)
|
|
NVC67A_CURSOR_IMM_CHANNEL_PIO = (0x0000c67a)
|
|
NVC67B_WINDOW_IMM_CHANNEL_DMA = (0x0000c67b)
|
|
NVC67D_CORE_CHANNEL_DMA = (0x0000c67d)
|
|
NVC67E_WINDOW_CHANNEL_DMA = (0x0000c67e)
|
|
NVC77F_ANY_CHANNEL_DMA = (0x0000c77f)
|
|
NVC770_DISPLAY = (0x0000c770)
|
|
NVC771_DISP_SF_USER = (0x0000c771)
|
|
NVC77D_CORE_CHANNEL_DMA = (0x0000c77d)
|
|
NVC870_DISPLAY = (0x0000c870)
|
|
NVC871_DISP_SF_USER = (0x0000c871)
|
|
NVC87A_CURSOR_IMM_CHANNEL_PIO = (0x0000c87a)
|
|
NVC87B_WINDOW_IMM_CHANNEL_DMA = (0x0000c87b)
|
|
NVC87D_CORE_CHANNEL_DMA = (0x0000c87d)
|
|
NVC87E_WINDOW_CHANNEL_DMA = (0x0000c87e)
|
|
NVC970_DISPLAY = (0x0000c970)
|
|
NVC971_DISP_SF_USER = (0x0000c971)
|
|
NVC97A_CURSOR_IMM_CHANNEL_PIO = (0x0000c97a)
|
|
NVC97B_WINDOW_IMM_CHANNEL_DMA = (0x0000c97b)
|
|
NVC97D_CORE_CHANNEL_DMA = (0x0000c97d)
|
|
NVC97E_WINDOW_CHANNEL_DMA = (0x0000c97e)
|
|
NVCA70_DISPLAY = (0x0000ca70)
|
|
NVCA71_DISP_SF_USER = (0x0000ca71)
|
|
NVCA7A_CURSOR_IMM_CHANNEL_PIO = (0x0000ca7a)
|
|
NVCA7B_WINDOW_IMM_CHANNEL_DMA = (0x0000ca7b)
|
|
NVCA7D_CORE_CHANNEL_DMA = (0x0000ca7d)
|
|
NVCA7E_WINDOW_CHANNEL_DMA = (0x0000ca7e)
|
|
NVCB70_DISPLAY = (0x0000cb70)
|
|
NVCB71_DISP_SF_USER = (0x0000cb71)
|
|
NVCB7A_CURSOR_IMM_CHANNEL_PIO = (0x0000cb7a)
|
|
NVCB7B_WINDOW_IMM_CHANNEL_DMA = (0x0000cb7b)
|
|
NVCB7D_CORE_CHANNEL_DMA = (0x0000cb7d)
|
|
NVCB7E_WINDOW_CHANNEL_DMA = (0x0000cb7e)
|
|
NVCC70_DISPLAY = (0x0000cc70)
|
|
NVCC71_DISP_SF_USER = (0x0000cc71)
|
|
NVCC7A_CURSOR_IMM_CHANNEL_PIO = (0x0000cc7a)
|
|
NVCC7B_WINDOW_IMM_CHANNEL_DMA = (0x0000cc7b)
|
|
NVCC7D_CORE_CHANNEL_DMA = (0x0000cc7d)
|
|
NVCC7E_WINDOW_CHANNEL_DMA = (0x0000cc7e)
|
|
NV9010_VBLANK_CALLBACK = (0x00009010)
|
|
GF100_PROFILER = (0x000090cc)
|
|
MAXWELL_PROFILER = (0x0000b0cc)
|
|
MAXWELL_PROFILER_CONTEXT = (0x0000b1cc)
|
|
MAXWELL_PROFILER_DEVICE = (0x0000b2cc)
|
|
GF100_SUBDEVICE_MASTER = (0x000090e6)
|
|
GF100_SUBDEVICE_INFOROM = (0x000090e7)
|
|
GF100_ZBC_CLEAR = (0x00009096)
|
|
GF100_DISP_SW = (0x00009072)
|
|
GF100_TIMED_SEMAPHORE_SW = (0x00009074)
|
|
G84_PERFBUFFER = (0x0000844c)
|
|
NV50_MEMORY_VIRTUAL = (0x000050a0)
|
|
NV50_P2P = (0x0000503b)
|
|
NV50_THIRD_PARTY_P2P = (0x0000503c)
|
|
FERMI_TWOD_A = (0x0000902d)
|
|
FERMI_VASPACE_A = (0x000090f1)
|
|
HOPPER_SEC2_WORK_LAUNCH_A = (0x0000cba2)
|
|
GF100_HDACODEC = (0x000090ec)
|
|
NVB8B0_VIDEO_DECODER = (0x0000b8b0)
|
|
NVC4B0_VIDEO_DECODER = (0x0000c4b0)
|
|
NVC6B0_VIDEO_DECODER = (0x0000c6b0)
|
|
NVC7B0_VIDEO_DECODER = (0x0000c7b0)
|
|
NVC9B0_VIDEO_DECODER = (0x0000c9b0)
|
|
NVCDB0_VIDEO_DECODER = (0x0000cdb0)
|
|
NVCEB0_VIDEO_DECODER = (0x0000ceb0)
|
|
NVCFB0_VIDEO_DECODER = (0x0000cfb0)
|
|
NVD1B0_VIDEO_DECODER = (0x0000d1b0)
|
|
NVD2B0_VIDEO_DECODER = (0x0000d2b0)
|
|
NVC4B7_VIDEO_ENCODER = (0x0000c4b7)
|
|
NVB4B7_VIDEO_ENCODER = (0x0000b4b7)
|
|
NVC7B7_VIDEO_ENCODER = (0x0000c7b7)
|
|
NVC9B7_VIDEO_ENCODER = (0x0000c9b7)
|
|
NVCEB7_VIDEO_ENCODER = (0x0000ceb7)
|
|
NVCFB7_VIDEO_ENCODER = (0x0000cfb7)
|
|
NVD1B7_VIDEO_ENCODER = (0x0000d1b7)
|
|
NVB8D1_VIDEO_NVJPG = (0x0000b8d1)
|
|
NVC4D1_VIDEO_NVJPG = (0x0000c4d1)
|
|
NVC9D1_VIDEO_NVJPG = (0x0000c9d1)
|
|
NVCED0_VIDEO_NVJPG = (0x0000ced0)
|
|
NVCDD1_VIDEO_NVJPG = (0x0000cdd1)
|
|
NVCFD1_VIDEO_NVJPG = (0x0000cfd1)
|
|
NVD2D1_VIDEO_NVJPG = (0x0000d2d1)
|
|
NVB8FA_VIDEO_OFA = (0x0000b8fa)
|
|
NVC6FA_VIDEO_OFA = (0x0000c6fa)
|
|
NVC7FA_VIDEO_OFA = (0x0000c7fa)
|
|
NVC9FA_VIDEO_OFA = (0x0000c9fa)
|
|
NVCDFA_VIDEO_OFA = (0x0000cdfa)
|
|
NVCEFA_VIDEO_OFA = (0x0000cefa)
|
|
NVCFFA_VIDEO_OFA = (0x0000cffa)
|
|
NVD1FA_VIDEO_OFA = (0x0000d1fa)
|
|
NVD2FA_VIDEO_OFA = (0x0000d2fa)
|
|
KEPLER_INLINE_TO_MEMORY_B = (0x0000a140)
|
|
FERMI_CONTEXT_SHARE_A = (0x00009067)
|
|
KEPLER_CHANNEL_GROUP_A = (0x0000a06c)
|
|
PASCAL_DMA_COPY_A = (0x0000c0b5)
|
|
TURING_DMA_COPY_A = (0x0000c5b5)
|
|
AMPERE_DMA_COPY_A = (0x0000c6b5)
|
|
AMPERE_DMA_COPY_B = (0x0000c7b5)
|
|
HOPPER_DMA_COPY_A = (0x0000c8b5)
|
|
BLACKWELL_DMA_COPY_A = (0x0000c9b5)
|
|
BLACKWELL_DMA_COPY_B = (0x0000cab5)
|
|
MAXWELL_DMA_COPY_A = (0x0000b0b5)
|
|
ACCESS_COUNTER_NOTIFY_BUFFER = (0x0000c365)
|
|
MMU_FAULT_BUFFER = (0x0000c369)
|
|
MMU_VIDMEM_ACCESS_BIT_BUFFER = (0x0000c763)
|
|
HOPPER_MMU_VIDMEM_ACCESS_BIT_BUFFER = (0x0000c863)
|
|
TURING_A = (0x0000c597)
|
|
TURING_COMPUTE_A = (0x0000c5c0)
|
|
AMPERE_A = (0x0000c697)
|
|
AMPERE_COMPUTE_A = (0x0000c6c0)
|
|
AMPERE_B = (0x0000c797)
|
|
AMPERE_COMPUTE_B = (0x0000c7c0)
|
|
ADA_A = (0x0000c997)
|
|
ADA_COMPUTE_A = (0x0000c9c0)
|
|
AMPERE_SMC_PARTITION_REF = (0x0000c637)
|
|
AMPERE_SMC_EXEC_PARTITION_REF = (0x0000c638)
|
|
AMPERE_SMC_CONFIG_SESSION = (0x0000c639)
|
|
NV0092_RG_LINE_CALLBACK = (0x00000092)
|
|
AMPERE_SMC_MONITOR_SESSION = (0x0000c640)
|
|
HOPPER_A = (0x0000cb97)
|
|
HOPPER_COMPUTE_A = (0x0000cbc0)
|
|
BLACKWELL_A = (0x0000cd97)
|
|
BLACKWELL_COMPUTE_A = (0x0000cdc0)
|
|
BLACKWELL_B = (0x0000ce97)
|
|
BLACKWELL_COMPUTE_B = (0x0000cec0)
|
|
BLACKWELL_INLINE_TO_MEMORY_A = (0x0000cd40)
|
|
NV40_DEBUG_BUFFER = (0x000000db)
|
|
RM_USER_SHARED_DATA = (0x000000de)
|
|
GT200_DEBUGGER = (0x000083de)
|
|
NV40_I2C = (0x0000402c)
|
|
KEPLER_DEVICE_VGPU = (0x0000a080)
|
|
NVA081_VGPU_CONFIG = (0x0000a081)
|
|
NVA084_KERNEL_HOST_VGPU_DEVICE = (0x0000a084)
|
|
NVA083_GRID_DISPLAYLESS = (0x0000a083)
|
|
NV0060_SYNC_GPU_BOOST = (0x00000060)
|
|
GP100_UVM_SW = (0x0000c076)
|
|
NVENC_SW_SESSION = (0x0000a0bc)
|
|
NV_EVENT_BUFFER = (0x000090cd)
|
|
NVFBC_SW_SESSION = (0x0000a0bd)
|
|
NV_CONFIDENTIAL_COMPUTE = (0x0000cb33)
|
|
NV_COUNTER_COLLECTION_UNIT = (0x0000cbca)
|
|
NV_SEMAPHORE_SURFACE = (0x000000da) |