mirror of
https://github.com/firestar5683/StarPilot.git
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firestar5683
22a8575199
Keep official openpilot ancestry and dependency licenses. Store resources directly in Git, remove LFS setup requirements, and leave the downloadable big model outside the source tree.
201 lines
6.8 KiB
Python
201 lines
6.8 KiB
Python
# do not change these tests. we need to fix bugs to make them pass
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# the Inst constructor should be looking at the types of the fields to correctly set the value
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import unittest, struct
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from tinygrad.runtime.autogen.amd.rdna3.ins import *
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from tinygrad.renderer.amd.dsl import Inst
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from test.amd.test_roundtrip import compile_asm
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from test.amd.disasm import disasm
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class IntegrationTestBase(unittest.TestCase):
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inst: Inst
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arch: str
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def tearDown(self):
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if not hasattr(self, 'inst'): return
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b = self.inst.to_bytes()
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st = disasm(self.inst)
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# Test that the instruction can be compiled by LLVM and produces the same bytes
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desc = f"{st:25s} {self.inst} {b!r}"
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self.assertEqual(b, compile_asm(st, arch=self.arch), desc)
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print(desc)
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class TestIntegration(IntegrationTestBase):
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arch: str = "rdna3"
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def test_wmma(self):
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self.inst = v_wmma_f32_16x16x16_f16(v[0:7], v[184:191], v[136:143], v[0:7])
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def test_load_b128(self):
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self.inst = s_load_b128(s[4:7], s[0:1], NULL, 0)
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def test_load_b128_wrong_size(self):
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# this should have to be 4 regs on the loaded to
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with self.assertRaises(TypeError):
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self.inst = s_load_b128(s[4:6], s[0:1], NULL, 0)
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def test_mov_b32(self):
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self.inst = s_mov_b32(s[80], s[0])
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def test_mov_b64(self):
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self.inst = s_mov_b64(s[80:81], s[0:1])
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def test_mov_b32_wrong(self):
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with self.assertRaises(Exception):
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self.inst = s_mov_b32(s[80:81], s[0:1])
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with self.assertRaises(Exception):
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self.inst = s_mov_b32(s[80:81], s[0])
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with self.assertRaises(Exception):
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self.inst = s_mov_b32(s[80], s[0:1])
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def test_mov_b64_wrong(self):
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with self.assertRaises(Exception):
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self.inst = s_mov_b64(s[80], s[0])
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with self.assertRaises(Exception):
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self.inst = s_mov_b64(s[80], s[0:1])
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with self.assertRaises(Exception):
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self.inst = s_mov_b64(s[80:81], s[0])
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def test_load_b128_no_0(self):
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self.inst = s_load_b128(s[4:7], s[0:1], NULL)
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def test_load_b128_s(self):
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self.inst = s_load_b128(s[4:7], s[0:1], s[8], 0)
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def test_load_b128_v(self):
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with self.assertRaises(TypeError):
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self.inst = s_load_b128(s[4:7], s[0:1], v[8], 0)
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def test_load_b128_off(self):
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self.inst = s_load_b128(s[4:7], s[0:1], NULL, 3)
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def test_simple_stos(self):
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self.inst = s_mov_b32(s[0], s[1])
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def test_simple_wrong(self):
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with self.assertRaises(TypeError):
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self.inst = s_mov_b32(v[0], s[1])
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def test_simple_vtov(self):
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self.inst = v_mov_b32_e32(v[0], v[1])
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def test_simple_stov(self):
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self.inst = v_mov_b32_e32(v[0], s[2])
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def test_simple_float_to_v(self):
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self.inst = v_mov_b32_e32(v[0], 1.0)
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def test_simple_v_to_float(self):
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with self.assertRaises(TypeError):
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self.inst = v_mov_b32_e32(1, v[0])
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def test_invalid_field(self):
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with self.assertRaises(TypeError):
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self.inst = s_load_b128(s[4:7], s[0:1], NULL, ioffset=0x8)
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def test_simple_int_to_v(self):
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self.inst = v_mov_b32_e32(v[0], 1)
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def test_three_add(self):
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self.inst = v_add_co_ci_u32_e32(v[3], s[7], v[3])
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def test_three_add_v(self):
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self.inst = v_add_co_ci_u32_e32(v[3], v[7], v[3])
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def test_three_add_const(self):
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self.inst = v_add_co_ci_u32_e32(v[3], 2.0, v[3])
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def test_swaitcnt_lgkm(self): self.inst = s_waitcnt(0xfc07)
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def test_swaitcnt_vm(self): self.inst = s_waitcnt(0x03f7)
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def test_vmad(self):
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self.inst = v_mad_u64_u32(v[1:2], NULL, s[2], 3, v[1:2])
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def test_large_imm(self):
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self.inst = v_mov_b32_e32(v[0], 0x1234)
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def test_dual_mov(self):
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self.inst = VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_MOV_B32, vdstx=v[0], vdsty=v[1], srcx0=v[2], srcy0=v[4])
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def test_dual_mul(self):
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self.inst = v_dual_mul_f32(VOPDOp.V_DUAL_MUL_F32, vdstx=v[0], vdsty=v[1], srcx0=v[2], vsrcx1=v[3], srcy0=v[4], vsrcy1=v[5])
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def test_simple_int_to_s(self):
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self.inst = s_mov_b32(s[0], 3)
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def test_complex_int_to_s(self):
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self.inst = s_mov_b32(s[0], 0x235646)
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def test_simple_float_to_s(self):
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self.inst = s_mov_b32(s[0], 1.0)
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def test_complex_float_to_s(self):
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self.inst = s_mov_b32(s[0], 1337.0)
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int_inst = s_mov_b32(s[0], struct.unpack("I", struct.pack("f", 1337.0))[0])
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self.assertEqual(self.inst, int_inst)
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class TestIntegrationCDNA(IntegrationTestBase):
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arch = "cdna"
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def test_mfma(self):
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from tinygrad.runtime.autogen.amd.cdna.ins import v_mfma_f32_16x16x16_f16
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self.inst = v_mfma_f32_16x16x16_f16(v[0:3], v[0:1], v[0:1], 0)
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def test_mfma_fp8(self):
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from tinygrad.runtime.autogen.amd.cdna.ins import v_mfma_f32_16x16x128_f8f6f4
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self.inst = v_mfma_f32_16x16x128_f8f6f4(v[0:3], v[0:5], v[0:5], 1, cbsz=2, blgp=2)
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def test_mfma_scale_fp8(self):
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from tinygrad.runtime.autogen.amd.cdna.ins import v_mfma_scale_f32_16x16x128_f8f6f4
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self.inst = v_mfma_scale_f32_16x16x128_f8f6f4(v[0:3], v[4:11], v[12:19], v[0:3], scale_src0=v[20].offset, scale_src1=v[21].offset)
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class TestRegisterSliceSyntax(unittest.TestCase):
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"""
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Issue: Register slice syntax should use AMD assembly convention (inclusive end).
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In AMD assembly, s[4:7] means registers s4, s5, s6, s7 (4 registers, inclusive).
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The DSL should match this convention so that:
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- s[4:7] gives 4 registers
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- Disassembler output can be copied directly back into DSL code
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Fix: Change _RegFactory.__getitem__ to use inclusive end:
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key.stop - key.start + 1 (instead of key.stop - key.start)
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"""
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def test_register_slice_count(self):
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# s[4:7] should give 4 registers: s4, s5, s6, s7 (AMD convention, inclusive)
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reg = s[4:7]
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self.assertEqual(reg.sz, 4, "s[4:7] should give 4 registers (s4, s5, s6, s7)")
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def test_register_slice_roundtrip(self):
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# Round-trip: DSL -> disasm -> DSL should preserve register count
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reg = s[4:7] # 4 registers in AMD convention
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inst = s_load_b128(reg, s[0:1], NULL, 0)
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d = disasm(inst)
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# Disasm shows s[4:7] - user should be able to copy this back
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self.assertIn("s[4:7]", d)
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# And s[4:7] in DSL should give the same 4 registers
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reg_from_disasm = s[4:7]
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self.assertEqual(reg_from_disasm.sz, 4, "s[4:7] from disasm should give 4 registers")
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class TestInstructionEquality(unittest.TestCase):
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"""
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Issue: No __eq__ method - instruction comparison requires repr() workaround.
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Two identical instructions should compare equal with ==, but currently:
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inst1 == inst2 returns False
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The test_handwritten.py works around this with:
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self.assertEqual(repr(self.inst), repr(reasm))
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"""
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def test_identical_instructions_equal(self):
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inst1 = v_mov_b32_e32(v[0], v[1])
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inst2 = v_mov_b32_e32(v[0], v[1])
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self.assertEqual(inst1, inst2, "identical instructions should be equal")
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def test_different_instructions_not_equal(self):
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inst1 = v_mov_b32_e32(v[0], v[1])
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inst2 = v_mov_b32_e32(v[0], v[2])
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self.assertNotEqual(inst1, inst2, "different instructions should not be equal")
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if __name__ == "__main__":
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unittest.main()
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