From f0950133f616d761f9bc1eea48132985120afa64 Mon Sep 17 00:00:00 2001
From: firestar5683 <168790843+firestar5683@users.noreply.github.com>
Date: Sun, 20 Sep 2026 11:31:09 -0700
Subject: [PATCH] Accept advancing DAC batches with repeated CoreAudio current
 timestamps

---
 roadscore/prototype/stream_clock_bridge.py      | 2 +-
 roadscore/prototype/test_stream_clock_bridge.py | 6 ++++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/roadscore/prototype/stream_clock_bridge.py b/roadscore/prototype/stream_clock_bridge.py
index 19af31c7a6..c32a75ef18 100644
--- a/roadscore/prototype/stream_clock_bridge.py
+++ b/roadscore/prototype/stream_clock_bridge.py
@@ -25,7 +25,7 @@ class StreamClockBridge:
       if (not all(type(value) in (int,float) and math.isfinite(value) for value in (wall,current,dac))
           or current<=0 or dac<=0 or not -.02<=dac-current<=5):
         raise ValueError('Invalid callback clock sample')
-      if previous is not None and (wall<previous[0] or current<=previous[1] or dac<=previous[2]):
+      if previous is not None and (wall<previous[0] or current<previous[1] or dac<=previous[2]):
         raise ValueError('Output callback clock did not advance')
       previous=(wall,current,dac)
       offsets.append(wall-current)
diff --git a/roadscore/prototype/test_stream_clock_bridge.py b/roadscore/prototype/test_stream_clock_bridge.py
index 51cd1e6a83..53832f56e7 100644
--- a/roadscore/prototype/test_stream_clock_bridge.py
+++ b/roadscore/prototype/test_stream_clock_bridge.py
@@ -47,5 +47,11 @@ class StreamClockBridgeTests(unittest.TestCase):
     for samples in ([(1.,0.,0.)]*8,[(1.+i*.02,500.,500.04) for i in range(8)],[]):
       with self.assertRaises(ValueError):StreamClockBridge.from_callbacks(samples)
 
+  def test_coreaudio_batch_may_repeat_current_time_while_dac_advances(self):
+    samples=[(100.+i*.02,500.+(i//2)*.04,500.1+i*.02) for i in range(8)]
+    bridge=StreamClockBridge.from_callbacks(samples)
+    self.assertAlmostEqual(bridge.offset,-400.)
+    self.assertAlmostEqual(bridge.dac_wall(501.),101.)
+
 
 if __name__=='__main__':unittest.main()