mirror of
https://github.com/MoreTore/openpilot.git
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firestar5683
23908 lines
1.3 MiB
Plaintext
23908 lines
1.3 MiB
Plaintext
# mypy: disable-error-code="empty-body"
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from __future__ import annotations
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import ctypes
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from typing import Annotated, Literal, TypeAlias
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from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR
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from tinygrad.runtime.support import c
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class _anonenum0(Annotated[int, ctypes.c_uint32], c.Enum): pass
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AES128_NONE = _anonenum0.define('AES128_NONE', 0)
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AES128_CTR = _anonenum0.define('AES128_CTR', 1)
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AES128_CBC = _anonenum0.define('AES128_CBC', 2)
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AES128_ECB = _anonenum0.define('AES128_ECB', 3)
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AES128_OFB = _anonenum0.define('AES128_OFB', 4)
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AES128_CTR_LSB16B = _anonenum0.define('AES128_CTR_LSB16B', 5)
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AES128_CLR_AS_ENCRYPT = _anonenum0.define('AES128_CLR_AS_ENCRYPT', 6)
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AES128_RESERVED = _anonenum0.define('AES128_RESERVED', 7)
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class _anonenum1(Annotated[int, ctypes.c_uint32], c.Enum): pass
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AES128_CTS_DISABLE = _anonenum1.define('AES128_CTS_DISABLE', 0)
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AES128_CTS_ENABLE = _anonenum1.define('AES128_CTS_ENABLE', 1)
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class _anonenum2(Annotated[int, ctypes.c_uint32], c.Enum): pass
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AES128_PADDING_NONE = _anonenum2.define('AES128_PADDING_NONE', 0)
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AES128_PADDING_CARRY_OVER = _anonenum2.define('AES128_PADDING_CARRY_OVER', 1)
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AES128_PADDING_RFC2630 = _anonenum2.define('AES128_PADDING_RFC2630', 2)
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AES128_PADDING_RESERVED = _anonenum2.define('AES128_PADDING_RESERVED', 7)
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class ENCR_MODE(Annotated[int, ctypes.c_uint32], c.Enum): pass
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ENCR_MODE_CTR64 = ENCR_MODE.define('ENCR_MODE_CTR64', 0)
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ENCR_MODE_CBC = ENCR_MODE.define('ENCR_MODE_CBC', 1)
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ENCR_MODE_ECB = ENCR_MODE.define('ENCR_MODE_ECB', 2)
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ENCR_MODE_ECB_PARTIAL = ENCR_MODE.define('ENCR_MODE_ECB_PARTIAL', 3)
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ENCR_MODE_CBC_PARTIAL = ENCR_MODE.define('ENCR_MODE_CBC_PARTIAL', 4)
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ENCR_MODE_CLEAR_INTO_VPR = ENCR_MODE.define('ENCR_MODE_CLEAR_INTO_VPR', 5)
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ENCR_MODE_FORCE_INTO_VPR = ENCR_MODE.define('ENCR_MODE_FORCE_INTO_VPR', 6)
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class _anonenum3(Annotated[int, ctypes.c_uint32], c.Enum): pass
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DRM_MS_PIFF_CTR = _anonenum3.define('DRM_MS_PIFF_CTR', 17)
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class _anonenum4(Annotated[int, ctypes.c_uint32], c.Enum): pass
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DRM_MS_PIFF_CBC = _anonenum4.define('DRM_MS_PIFF_CBC', 2)
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class _anonenum5(Annotated[int, ctypes.c_uint32], c.Enum): pass
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DRM_MARLIN_CTR = _anonenum5.define('DRM_MARLIN_CTR', 1)
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class _anonenum6(Annotated[int, ctypes.c_uint32], c.Enum): pass
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DRM_MARLIN_CBC = _anonenum6.define('DRM_MARLIN_CBC', 34)
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class _anonenum7(Annotated[int, ctypes.c_uint32], c.Enum): pass
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DRM_WIDEVINE = _anonenum7.define('DRM_WIDEVINE', 10)
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class _anonenum8(Annotated[int, ctypes.c_uint32], c.Enum): pass
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DRM_WIDEVINE_CTR = _anonenum8.define('DRM_WIDEVINE_CTR', 17)
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class _anonenum9(Annotated[int, ctypes.c_uint32], c.Enum): pass
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DRM_ULTRA_VIOLET = _anonenum9.define('DRM_ULTRA_VIOLET', 5)
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class _anonenum10(Annotated[int, ctypes.c_uint32], c.Enum): pass
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DRM_NONE = _anonenum10.define('DRM_NONE', 0)
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class _anonenum11(Annotated[int, ctypes.c_uint32], c.Enum): pass
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DRM_CLR_AS_ENCRYPT = _anonenum11.define('DRM_CLR_AS_ENCRYPT', 6)
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@c.record
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class struct__nvdec_ssm_s(c.Struct):
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SIZE = 8
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bytes_of_protected_data: Annotated[Annotated[int, ctypes.c_uint32], 0]
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bytes_of_clear_data: Annotated[Annotated[int, ctypes.c_uint32], 4, 16, 0]
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skip_byte_blk: Annotated[Annotated[int, ctypes.c_uint32], 6, 4, 0]
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crypt_byte_blk: Annotated[Annotated[int, ctypes.c_uint32], 6, 4, 4]
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skip: Annotated[Annotated[int, ctypes.c_uint32], 7, 1, 0]
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last: Annotated[Annotated[int, ctypes.c_uint32], 7, 1, 1]
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pad: Annotated[Annotated[int, ctypes.c_uint32], 7, 1, 2]
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mode: Annotated[Annotated[int, ctypes.c_uint32], 7, 1, 3]
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entry_type: Annotated[Annotated[int, ctypes.c_uint32], 7, 1, 4]
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reserved: Annotated[Annotated[int, ctypes.c_uint32], 7, 3, 5]
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nvdec_ssm_s: TypeAlias = struct__nvdec_ssm_s
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@c.record
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class struct__nvdec_pass2_otf_ext_s(c.Struct):
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SIZE = 12
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ssm_entry_num: Annotated[Annotated[int, ctypes.c_uint32], 0, 16, 0]
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ssm_iv_num: Annotated[Annotated[int, ctypes.c_uint32], 2, 16, 0]
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real_stream_length: Annotated[Annotated[int, ctypes.c_uint32], 4]
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non_slice_data: Annotated[Annotated[int, ctypes.c_uint32], 8, 16, 0]
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drm_mode: Annotated[Annotated[int, ctypes.c_uint32], 10, 7, 0]
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reserved: Annotated[Annotated[int, ctypes.c_uint32], 10, 9, 7]
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nvdec_pass2_otf_ext_s: TypeAlias = struct__nvdec_pass2_otf_ext_s
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@c.record
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class struct__nvdec_substream_entry_s(c.Struct):
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SIZE = 12
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substream_start_offset: Annotated[Annotated[int, ctypes.c_uint32], 0]
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substream_length: Annotated[Annotated[int, ctypes.c_uint32], 4]
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substream_first_tile_idx: Annotated[Annotated[int, ctypes.c_uint32], 8, 8, 0]
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substream_last_tile_idx: Annotated[Annotated[int, ctypes.c_uint32], 9, 8, 0]
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last_substream_entry_in_frame: Annotated[Annotated[int, ctypes.c_uint32], 10, 1, 0]
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reserved: Annotated[Annotated[int, ctypes.c_uint32], 10, 15, 1]
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nvdec_substream_entry_s: TypeAlias = struct__nvdec_substream_entry_s
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@c.record
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class struct__nvdec_ecdma_config_s(c.Struct):
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SIZE = 24
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ecdma_enable: Annotated[Annotated[int, ctypes.c_uint32], 0]
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ecdma_blk_x_src: Annotated[Annotated[int, ctypes.c_uint16], 4]
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ecdma_blk_y_src: Annotated[Annotated[int, ctypes.c_uint16], 6]
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ecdma_blk_x_dst: Annotated[Annotated[int, ctypes.c_uint16], 8]
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ecdma_blk_y_dst: Annotated[Annotated[int, ctypes.c_uint16], 10]
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ref_pic_idx: Annotated[Annotated[int, ctypes.c_uint16], 12]
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boundary0_top: Annotated[Annotated[int, ctypes.c_uint16], 14]
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boundary0_bottom: Annotated[Annotated[int, ctypes.c_uint16], 16]
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boundary1_left: Annotated[Annotated[int, ctypes.c_uint16], 18]
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boundary1_right: Annotated[Annotated[int, ctypes.c_uint16], 20]
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blk_copy_flag: Annotated[Annotated[int, ctypes.c_ubyte], 22]
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ctb_size: Annotated[Annotated[int, ctypes.c_ubyte], 23]
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nvdec_ecdma_config_s: TypeAlias = struct__nvdec_ecdma_config_s
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@c.record
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class struct__nvdec_status_hevc_s(c.Struct):
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SIZE = 36
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frame_status_intra_cnt: Annotated[Annotated[int, ctypes.c_uint32], 0]
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frame_status_inter_cnt: Annotated[Annotated[int, ctypes.c_uint32], 4]
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frame_status_skip_cnt: Annotated[Annotated[int, ctypes.c_uint32], 8]
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frame_status_fwd_mvx_cnt: Annotated[Annotated[int, ctypes.c_uint32], 12]
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frame_status_fwd_mvy_cnt: Annotated[Annotated[int, ctypes.c_uint32], 16]
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frame_status_bwd_mvx_cnt: Annotated[Annotated[int, ctypes.c_uint32], 20]
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frame_status_bwd_mvy_cnt: Annotated[Annotated[int, ctypes.c_uint32], 24]
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error_ctb_pos: Annotated[Annotated[int, ctypes.c_uint32], 28]
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error_slice_pos: Annotated[Annotated[int, ctypes.c_uint32], 32]
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nvdec_status_hevc_s: TypeAlias = struct__nvdec_status_hevc_s
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@c.record
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class struct__nvdec_status_vp9_s(c.Struct):
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SIZE = 36
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frame_status_intra_cnt: Annotated[Annotated[int, ctypes.c_uint32], 0]
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frame_status_inter_cnt: Annotated[Annotated[int, ctypes.c_uint32], 4]
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frame_status_skip_cnt: Annotated[Annotated[int, ctypes.c_uint32], 8]
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frame_status_fwd_mvx_cnt: Annotated[Annotated[int, ctypes.c_uint32], 12]
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frame_status_fwd_mvy_cnt: Annotated[Annotated[int, ctypes.c_uint32], 16]
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frame_status_bwd_mvx_cnt: Annotated[Annotated[int, ctypes.c_uint32], 20]
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frame_status_bwd_mvy_cnt: Annotated[Annotated[int, ctypes.c_uint32], 24]
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error_ctb_pos: Annotated[Annotated[int, ctypes.c_uint32], 28]
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error_slice_pos: Annotated[Annotated[int, ctypes.c_uint32], 32]
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nvdec_status_vp9_s: TypeAlias = struct__nvdec_status_vp9_s
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@c.record
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class struct__nvdec_status_s(c.Struct):
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SIZE = 56
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mbs_correctly_decoded: Annotated[Annotated[int, ctypes.c_uint32], 0]
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mbs_in_error: Annotated[Annotated[int, ctypes.c_uint32], 4]
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cycle_count: Annotated[Annotated[int, ctypes.c_uint32], 8]
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error_status: Annotated[Annotated[int, ctypes.c_uint32], 12]
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hevc: Annotated[nvdec_status_hevc_s, 16]
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vp9: Annotated[nvdec_status_vp9_s, 16]
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slice_header_error_code: Annotated[Annotated[int, ctypes.c_uint32], 52]
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nvdec_status_s: TypeAlias = struct__nvdec_status_s
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@c.record
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class struct__external_mv_s(c.Struct):
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SIZE = 4
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mvx: Annotated[Annotated[int, ctypes.c_int32], 0, 14, 0]
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mvy: Annotated[Annotated[int, ctypes.c_int32], 1, 14, 6]
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refidx: Annotated[Annotated[int, ctypes.c_uint32], 3, 4, 4]
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external_mv_s: TypeAlias = struct__external_mv_s
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@c.record
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class struct__nvdec_hevc_main10_444_ext_s(c.Struct):
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SIZE = 28
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transformSkipRotationEnableFlag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 0]
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transformSkipContextEnableFlag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 1]
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intraBlockCopyEnableFlag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 2]
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implicitRdpcmEnableFlag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 3]
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explicitRdpcmEnableFlag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 4]
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extendedPrecisionProcessingFlag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 5]
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intraSmoothingDisabledFlag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 6]
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highPrecisionOffsetsEnableFlag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 7]
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fastRiceAdaptationEnableFlag: Annotated[Annotated[int, ctypes.c_uint32], 1, 1, 0]
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cabacBypassAlignmentEnableFlag: Annotated[Annotated[int, ctypes.c_uint32], 1, 1, 1]
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sps_444_extension_reserved: Annotated[Annotated[int, ctypes.c_uint32], 1, 22, 2]
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log2MaxTransformSkipSize: Annotated[Annotated[int, ctypes.c_uint32], 4, 4, 0]
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crossComponentPredictionEnableFlag: Annotated[Annotated[int, ctypes.c_uint32], 4, 1, 4]
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chromaQpAdjustmentEnableFlag: Annotated[Annotated[int, ctypes.c_uint32], 4, 1, 5]
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diffCuChromaQpAdjustmentDepth: Annotated[Annotated[int, ctypes.c_uint32], 4, 2, 6]
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chromaQpAdjustmentTableSize: Annotated[Annotated[int, ctypes.c_uint32], 5, 3, 0]
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log2SaoOffsetScaleLuma: Annotated[Annotated[int, ctypes.c_uint32], 5, 3, 3]
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log2SaoOffsetScaleChroma: Annotated[Annotated[int, ctypes.c_uint32], 5, 3, 6]
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pps_444_extension_reserved: Annotated[Annotated[int, ctypes.c_uint32], 6, 15, 1]
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cb_qp_adjustment: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[6]], 8]
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cr_qp_adjustment: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[6]], 14]
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HevcFltAboveOffset: Annotated[Annotated[int, ctypes.c_uint32], 20]
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HevcSaoAboveOffset: Annotated[Annotated[int, ctypes.c_uint32], 24]
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nvdec_hevc_main10_444_ext_s: TypeAlias = struct__nvdec_hevc_main10_444_ext_s
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@c.record
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class struct__nvdec_hevc_pic_v1_s(c.Struct):
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SIZE = 32
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hevc_main10_444_ext: Annotated[nvdec_hevc_main10_444_ext_s, 0]
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sw_skip_start_length: Annotated[Annotated[int, ctypes.c_uint32], 28, 14, 0]
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external_ref_mem_dis: Annotated[Annotated[int, ctypes.c_uint32], 29, 1, 6]
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error_recovery_start_pos: Annotated[Annotated[int, ctypes.c_uint32], 29, 2, 7]
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error_external_mv_en: Annotated[Annotated[int, ctypes.c_uint32], 30, 1, 1]
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reserved0: Annotated[Annotated[int, ctypes.c_uint32], 30, 14, 2]
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nvdec_hevc_pic_v1_s: TypeAlias = struct__nvdec_hevc_pic_v1_s
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@c.record
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class struct__nvdec_hevc_pic_v2_s(c.Struct):
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SIZE = 4
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mv_hevc_enable: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 0]
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nuh_layer_id: Annotated[Annotated[int, ctypes.c_uint32], 0, 6, 1]
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default_ref_layers_active_flag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 7]
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NumDirectRefLayers: Annotated[Annotated[int, ctypes.c_uint32], 1, 6, 0]
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max_one_active_ref_layer_flag: Annotated[Annotated[int, ctypes.c_uint32], 1, 1, 6]
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NumActiveRefLayerPics: Annotated[Annotated[int, ctypes.c_uint32], 1, 6, 7]
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poc_lsb_not_present_flag: Annotated[Annotated[int, ctypes.c_uint32], 2, 1, 5]
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reserved0: Annotated[Annotated[int, ctypes.c_uint32], 2, 10, 6]
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nvdec_hevc_pic_v2_s: TypeAlias = struct__nvdec_hevc_pic_v2_s
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@c.record
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class struct__nvdec_hevc_pic_v3_s(c.Struct):
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SIZE = 8
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slice_decoding_enable: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 0]
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slice_ec_enable: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 1]
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slice_ec_mv_type: Annotated[Annotated[int, ctypes.c_uint32], 0, 2, 2]
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err_detected_sw: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 4]
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slice_ec_slice_type: Annotated[Annotated[int, ctypes.c_uint32], 0, 2, 5]
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slice_strm_recfg_en: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 7]
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reserved: Annotated[Annotated[int, ctypes.c_uint32], 1, 24, 0]
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HevcSliceEdgeOffset: Annotated[Annotated[int, ctypes.c_uint32], 4]
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nvdec_hevc_pic_v3_s: TypeAlias = struct__nvdec_hevc_pic_v3_s
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@c.record
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class struct__nvdec_hevc_pic_s(c.Struct):
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SIZE = 276
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wrapped_session_key: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 0]
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wrapped_content_key: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 16]
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initialization_vector: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 32]
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stream_len: Annotated[Annotated[int, ctypes.c_uint32], 48]
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enable_encryption: Annotated[Annotated[int, ctypes.c_uint32], 52]
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key_increment: Annotated[Annotated[int, ctypes.c_uint32], 56, 6, 0]
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encryption_mode: Annotated[Annotated[int, ctypes.c_uint32], 56, 4, 6]
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key_slot_index: Annotated[Annotated[int, ctypes.c_uint32], 57, 4, 2]
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ssm_en: Annotated[Annotated[int, ctypes.c_uint32], 57, 1, 6]
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enable_histogram: Annotated[Annotated[int, ctypes.c_uint32], 57, 1, 7]
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enable_substream_decoding: Annotated[Annotated[int, ctypes.c_uint32], 58, 1, 0]
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reserved0: Annotated[Annotated[int, ctypes.c_uint32], 58, 15, 1]
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gptimer_timeout_value: Annotated[Annotated[int, ctypes.c_uint32], 60]
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tileformat: Annotated[Annotated[int, ctypes.c_ubyte], 64, 2, 0]
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gob_height: Annotated[Annotated[int, ctypes.c_ubyte], 64, 3, 2]
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reserverd_surface_format: Annotated[Annotated[int, ctypes.c_ubyte], 64, 3, 5]
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sw_start_code_e: Annotated[Annotated[int, ctypes.c_ubyte], 65]
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disp_output_mode: Annotated[Annotated[int, ctypes.c_ubyte], 66]
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reserved1: Annotated[Annotated[int, ctypes.c_ubyte], 67]
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framestride: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], 68]
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colMvBuffersize: Annotated[Annotated[int, ctypes.c_uint32], 76]
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HevcSaoBufferOffset: Annotated[Annotated[int, ctypes.c_uint32], 80]
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HevcBsdCtrlOffset: Annotated[Annotated[int, ctypes.c_uint32], 84]
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pic_width_in_luma_samples: Annotated[Annotated[int, ctypes.c_uint16], 88]
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pic_height_in_luma_samples: Annotated[Annotated[int, ctypes.c_uint16], 90]
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chroma_format_idc: Annotated[Annotated[int, ctypes.c_uint32], 92, 4, 0]
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bit_depth_luma: Annotated[Annotated[int, ctypes.c_uint32], 92, 4, 4]
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bit_depth_chroma: Annotated[Annotated[int, ctypes.c_uint32], 93, 4, 0]
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log2_min_luma_coding_block_size: Annotated[Annotated[int, ctypes.c_uint32], 93, 4, 4]
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log2_max_luma_coding_block_size: Annotated[Annotated[int, ctypes.c_uint32], 94, 4, 0]
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log2_min_transform_block_size: Annotated[Annotated[int, ctypes.c_uint32], 94, 4, 4]
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log2_max_transform_block_size: Annotated[Annotated[int, ctypes.c_uint32], 95, 4, 0]
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reserved2: Annotated[Annotated[int, ctypes.c_uint32], 95, 4, 4]
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max_transform_hierarchy_depth_inter: Annotated[Annotated[int, ctypes.c_uint32], 96, 3, 0]
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max_transform_hierarchy_depth_intra: Annotated[Annotated[int, ctypes.c_uint32], 96, 3, 3]
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|
scalingListEnable: Annotated[Annotated[int, ctypes.c_uint32], 96, 1, 6]
|
|
amp_enable_flag: Annotated[Annotated[int, ctypes.c_uint32], 96, 1, 7]
|
|
sample_adaptive_offset_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 97, 1, 0]
|
|
pcm_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 97, 1, 1]
|
|
pcm_sample_bit_depth_luma: Annotated[Annotated[int, ctypes.c_uint32], 97, 4, 2]
|
|
pcm_sample_bit_depth_chroma: Annotated[Annotated[int, ctypes.c_uint32], 97, 4, 6]
|
|
log2_min_pcm_luma_coding_block_size: Annotated[Annotated[int, ctypes.c_uint32], 98, 4, 2]
|
|
log2_max_pcm_luma_coding_block_size: Annotated[Annotated[int, ctypes.c_uint32], 98, 4, 6]
|
|
pcm_loop_filter_disabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 99, 1, 2]
|
|
sps_temporal_mvp_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 99, 1, 3]
|
|
strong_intra_smoothing_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 99, 1, 4]
|
|
reserved3: Annotated[Annotated[int, ctypes.c_uint32], 99, 3, 5]
|
|
dependent_slice_segments_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 100, 1, 0]
|
|
output_flag_present_flag: Annotated[Annotated[int, ctypes.c_uint32], 100, 1, 1]
|
|
num_extra_slice_header_bits: Annotated[Annotated[int, ctypes.c_uint32], 100, 3, 2]
|
|
sign_data_hiding_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 100, 1, 5]
|
|
cabac_init_present_flag: Annotated[Annotated[int, ctypes.c_uint32], 100, 1, 6]
|
|
num_ref_idx_l0_default_active: Annotated[Annotated[int, ctypes.c_uint32], 100, 4, 7]
|
|
num_ref_idx_l1_default_active: Annotated[Annotated[int, ctypes.c_uint32], 101, 4, 3]
|
|
init_qp: Annotated[Annotated[int, ctypes.c_uint32], 101, 7, 7]
|
|
constrained_intra_pred_flag: Annotated[Annotated[int, ctypes.c_uint32], 102, 1, 6]
|
|
transform_skip_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 102, 1, 7]
|
|
cu_qp_delta_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 103, 1, 0]
|
|
diff_cu_qp_delta_depth: Annotated[Annotated[int, ctypes.c_uint32], 103, 2, 1]
|
|
reserved4: Annotated[Annotated[int, ctypes.c_uint32], 103, 5, 3]
|
|
pps_cb_qp_offset: Annotated[Annotated[bytes, ctypes.c_char], 104]
|
|
pps_cr_qp_offset: Annotated[Annotated[bytes, ctypes.c_char], 105]
|
|
pps_beta_offset: Annotated[Annotated[bytes, ctypes.c_char], 106]
|
|
pps_tc_offset: Annotated[Annotated[bytes, ctypes.c_char], 107]
|
|
pps_slice_chroma_qp_offsets_present_flag: Annotated[Annotated[int, ctypes.c_uint32], 108, 1, 0]
|
|
weighted_pred_flag: Annotated[Annotated[int, ctypes.c_uint32], 108, 1, 1]
|
|
weighted_bipred_flag: Annotated[Annotated[int, ctypes.c_uint32], 108, 1, 2]
|
|
transquant_bypass_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 108, 1, 3]
|
|
tiles_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 108, 1, 4]
|
|
entropy_coding_sync_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 108, 1, 5]
|
|
num_tile_columns: Annotated[Annotated[int, ctypes.c_uint32], 108, 5, 6]
|
|
num_tile_rows: Annotated[Annotated[int, ctypes.c_uint32], 109, 5, 3]
|
|
loop_filter_across_tiles_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 110, 1, 0]
|
|
loop_filter_across_slices_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 110, 1, 1]
|
|
deblocking_filter_control_present_flag: Annotated[Annotated[int, ctypes.c_uint32], 110, 1, 2]
|
|
deblocking_filter_override_enabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 110, 1, 3]
|
|
pps_deblocking_filter_disabled_flag: Annotated[Annotated[int, ctypes.c_uint32], 110, 1, 4]
|
|
lists_modification_present_flag: Annotated[Annotated[int, ctypes.c_uint32], 110, 1, 5]
|
|
log2_parallel_merge_level: Annotated[Annotated[int, ctypes.c_uint32], 110, 3, 6]
|
|
slice_segment_header_extension_present_flag: Annotated[Annotated[int, ctypes.c_uint32], 111, 1, 1]
|
|
reserved5: Annotated[Annotated[int, ctypes.c_uint32], 111, 6, 2]
|
|
num_ref_frames: Annotated[Annotated[int, ctypes.c_ubyte], 112]
|
|
reserved6: Annotated[Annotated[int, ctypes.c_ubyte], 113]
|
|
longtermflag: Annotated[Annotated[int, ctypes.c_uint16], 114]
|
|
initreflistidxl0: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[16]], 116]
|
|
initreflistidxl1: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[16]], 132]
|
|
RefDiffPicOrderCnts: Annotated[c.Array[Annotated[int, ctypes.c_int16], Literal[16]], 148]
|
|
IDR_picture_flag: Annotated[Annotated[int, ctypes.c_ubyte], 180]
|
|
RAP_picture_flag: Annotated[Annotated[int, ctypes.c_ubyte], 181]
|
|
curr_pic_idx: Annotated[Annotated[int, ctypes.c_ubyte], 182]
|
|
pattern_id: Annotated[Annotated[int, ctypes.c_ubyte], 183]
|
|
sw_hdr_skip_length: Annotated[Annotated[int, ctypes.c_uint16], 184]
|
|
reserved7: Annotated[Annotated[int, ctypes.c_uint16], 186]
|
|
ecdma_cfg: Annotated[nvdec_ecdma_config_s, 188]
|
|
separate_colour_plane_flag: Annotated[Annotated[int, ctypes.c_uint32], 212, 1, 0]
|
|
log2_max_pic_order_cnt_lsb_minus4: Annotated[Annotated[int, ctypes.c_uint32], 212, 4, 1]
|
|
num_short_term_ref_pic_sets: Annotated[Annotated[int, ctypes.c_uint32], 212, 7, 5]
|
|
num_long_term_ref_pics_sps: Annotated[Annotated[int, ctypes.c_uint32], 213, 6, 4]
|
|
bBitParsingDisable: Annotated[Annotated[int, ctypes.c_uint32], 214, 1, 2]
|
|
num_delta_pocs_of_rps_idx: Annotated[Annotated[int, ctypes.c_uint32], 214, 8, 3]
|
|
long_term_ref_pics_present_flag: Annotated[Annotated[int, ctypes.c_uint32], 215, 1, 3]
|
|
reserved_dxva: Annotated[Annotated[int, ctypes.c_uint32], 215, 4, 4]
|
|
num_bits_short_term_ref_pics_in_slice: Annotated[Annotated[int, ctypes.c_uint32], 216]
|
|
v1: Annotated[nvdec_hevc_pic_v1_s, 220]
|
|
v2: Annotated[nvdec_hevc_pic_v2_s, 252]
|
|
v3: Annotated[nvdec_hevc_pic_v3_s, 256]
|
|
ssm: Annotated[nvdec_pass2_otf_ext_s, 264]
|
|
nvdec_hevc_pic_s: TypeAlias = struct__nvdec_hevc_pic_s
|
|
@c.record
|
|
class struct__hevc_slice_info_s(c.Struct):
|
|
SIZE = 16
|
|
first_flag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 0]
|
|
err_flag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 1]
|
|
last_flag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 2]
|
|
conceal_partial_slice: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 3]
|
|
available: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 4]
|
|
reserved0: Annotated[Annotated[int, ctypes.c_uint32], 0, 7, 5]
|
|
ctb_count: Annotated[Annotated[int, ctypes.c_uint32], 1, 20, 4]
|
|
bs_offset: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
|
bs_length: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
|
start_ctbx: Annotated[Annotated[int, ctypes.c_uint16], 12]
|
|
start_ctby: Annotated[Annotated[int, ctypes.c_uint16], 14]
|
|
hevc_slice_info_s: TypeAlias = struct__hevc_slice_info_s
|
|
@c.record
|
|
class struct__slice_edge_ctb_pos_ctx_s(c.Struct):
|
|
SIZE = 8
|
|
next_slice_pos_ctbxy: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
|
next_slice_segment_addr: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
|
slice_edge_ctb_pos_ctx_s: TypeAlias = struct__slice_edge_ctb_pos_ctx_s
|
|
@c.record
|
|
class struct__slice_edge_tile_ctx_s(c.Struct):
|
|
SIZE = 12
|
|
tileInfo1: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
|
tileInfo2: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
|
tileInfo3: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
|
slice_edge_tile_ctx_s: TypeAlias = struct__slice_edge_tile_ctx_s
|
|
@c.record
|
|
class struct__slice_edge_stats_ctx_s(c.Struct):
|
|
SIZE = 32
|
|
frame_status_intra_cnt: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
|
frame_status_inter_cnt: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
|
frame_status_skip_cnt: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
|
frame_status_fwd_mvx_cnt: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
|
frame_status_fwd_mvy_cnt: Annotated[Annotated[int, ctypes.c_uint32], 16]
|
|
frame_status_bwd_mvx_cnt: Annotated[Annotated[int, ctypes.c_uint32], 20]
|
|
frame_status_bwd_mvy_cnt: Annotated[Annotated[int, ctypes.c_uint32], 24]
|
|
frame_status_mv_cnt_ext: Annotated[Annotated[int, ctypes.c_uint32], 28]
|
|
slice_edge_stats_ctx_s: TypeAlias = struct__slice_edge_stats_ctx_s
|
|
@c.record
|
|
class struct__slice_vpc_edge_ctx_s(c.Struct):
|
|
SIZE = 4
|
|
reserved: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
|
slice_vpc_edge_ctx_s: TypeAlias = struct__slice_vpc_edge_ctx_s
|
|
@c.record
|
|
class struct__slice_vpc_main_ctx_s(c.Struct):
|
|
SIZE = 4
|
|
reserved: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
|
slice_vpc_main_ctx_s: TypeAlias = struct__slice_vpc_main_ctx_s
|
|
@c.record
|
|
class struct__slice_edge_ctx_s(c.Struct):
|
|
SIZE = 60
|
|
slice_ctb_pos_ctx: Annotated[slice_edge_ctb_pos_ctx_s, 0]
|
|
slice_stats_ctx: Annotated[slice_edge_stats_ctx_s, 8]
|
|
slice_tile_ctx: Annotated[slice_edge_tile_ctx_s, 40]
|
|
slice_vpc_edge_ctx: Annotated[slice_vpc_edge_ctx_s, 52]
|
|
slice_vpc_main_ctx: Annotated[slice_vpc_main_ctx_s, 56]
|
|
slice_edge_ctx_s: TypeAlias = struct__slice_edge_ctx_s
|
|
@c.record
|
|
class struct__nvdec_vp9_pic_v1_s(c.Struct):
|
|
SIZE = 8
|
|
Vp9FltAboveOffset: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
|
external_ref_mem_dis: Annotated[Annotated[int, ctypes.c_uint32], 4, 1, 0]
|
|
bit_depth: Annotated[Annotated[int, ctypes.c_uint32], 4, 4, 1]
|
|
error_recovery_start_pos: Annotated[Annotated[int, ctypes.c_uint32], 4, 2, 5]
|
|
error_external_mv_en: Annotated[Annotated[int, ctypes.c_uint32], 4, 1, 7]
|
|
Reserved0: Annotated[Annotated[int, ctypes.c_uint32], 5, 24, 0]
|
|
nvdec_vp9_pic_v1_s: TypeAlias = struct__nvdec_vp9_pic_v1_s
|
|
class enum_VP9_FRAME_SFC_ID(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
VP9_LAST_FRAME_SFC = enum_VP9_FRAME_SFC_ID.define('VP9_LAST_FRAME_SFC', 0)
|
|
VP9_GOLDEN_FRAME_SFC = enum_VP9_FRAME_SFC_ID.define('VP9_GOLDEN_FRAME_SFC', 1)
|
|
VP9_ALTREF_FRAME_SFC = enum_VP9_FRAME_SFC_ID.define('VP9_ALTREF_FRAME_SFC', 2)
|
|
VP9_CURR_FRAME_SFC = enum_VP9_FRAME_SFC_ID.define('VP9_CURR_FRAME_SFC', 3)
|
|
|
|
@c.record
|
|
class struct__nvdec_vp9_pic_s(c.Struct):
|
|
SIZE = 256
|
|
wrapped_session_key: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 0]
|
|
wrapped_content_key: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 16]
|
|
initialization_vector: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 32]
|
|
stream_len: Annotated[Annotated[int, ctypes.c_uint32], 48]
|
|
enable_encryption: Annotated[Annotated[int, ctypes.c_uint32], 52]
|
|
key_increment: Annotated[Annotated[int, ctypes.c_uint32], 56, 6, 0]
|
|
encryption_mode: Annotated[Annotated[int, ctypes.c_uint32], 56, 4, 6]
|
|
sw_hdr_skip_length: Annotated[Annotated[int, ctypes.c_uint32], 57, 14, 2]
|
|
key_slot_index: Annotated[Annotated[int, ctypes.c_uint32], 59, 4, 0]
|
|
ssm_en: Annotated[Annotated[int, ctypes.c_uint32], 59, 1, 4]
|
|
enable_histogram: Annotated[Annotated[int, ctypes.c_uint32], 59, 1, 5]
|
|
reserved0: Annotated[Annotated[int, ctypes.c_uint32], 59, 2, 6]
|
|
gptimer_timeout_value: Annotated[Annotated[int, ctypes.c_uint32], 60]
|
|
tileformat: Annotated[Annotated[int, ctypes.c_ubyte], 64, 2, 0]
|
|
gob_height: Annotated[Annotated[int, ctypes.c_ubyte], 64, 3, 2]
|
|
reserverd_surface_format: Annotated[Annotated[int, ctypes.c_ubyte], 64, 3, 5]
|
|
reserved1: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 65]
|
|
Vp9BsdCtrlOffset: Annotated[Annotated[int, ctypes.c_uint32], 68]
|
|
ref0_width: Annotated[Annotated[int, ctypes.c_uint16], 72]
|
|
ref0_height: Annotated[Annotated[int, ctypes.c_uint16], 74]
|
|
ref0_stride: Annotated[c.Array[Annotated[int, ctypes.c_uint16], Literal[2]], 76]
|
|
ref1_width: Annotated[Annotated[int, ctypes.c_uint16], 80]
|
|
ref1_height: Annotated[Annotated[int, ctypes.c_uint16], 82]
|
|
ref1_stride: Annotated[c.Array[Annotated[int, ctypes.c_uint16], Literal[2]], 84]
|
|
ref2_width: Annotated[Annotated[int, ctypes.c_uint16], 88]
|
|
ref2_height: Annotated[Annotated[int, ctypes.c_uint16], 90]
|
|
ref2_stride: Annotated[c.Array[Annotated[int, ctypes.c_uint16], Literal[2]], 92]
|
|
width: Annotated[Annotated[int, ctypes.c_uint16], 96]
|
|
height: Annotated[Annotated[int, ctypes.c_uint16], 98]
|
|
framestride: Annotated[c.Array[Annotated[int, ctypes.c_uint16], Literal[2]], 100]
|
|
keyFrame: Annotated[Annotated[int, ctypes.c_ubyte], 104, 1, 0]
|
|
prevIsKeyFrame: Annotated[Annotated[int, ctypes.c_ubyte], 104, 1, 1]
|
|
resolutionChange: Annotated[Annotated[int, ctypes.c_ubyte], 104, 1, 2]
|
|
errorResilient: Annotated[Annotated[int, ctypes.c_ubyte], 104, 1, 3]
|
|
prevShowFrame: Annotated[Annotated[int, ctypes.c_ubyte], 104, 1, 4]
|
|
intraOnly: Annotated[Annotated[int, ctypes.c_ubyte], 104, 1, 5]
|
|
reserved2: Annotated[Annotated[int, ctypes.c_ubyte], 104, 2, 6]
|
|
reserved3: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 105]
|
|
refFrameSignBias: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], 108]
|
|
loopFilterLevel: Annotated[Annotated[bytes, ctypes.c_char], 112]
|
|
loopFilterSharpness: Annotated[Annotated[bytes, ctypes.c_char], 113]
|
|
qpYAc: Annotated[Annotated[int, ctypes.c_ubyte], 114]
|
|
qpYDc: Annotated[Annotated[bytes, ctypes.c_char], 115]
|
|
qpChAc: Annotated[Annotated[bytes, ctypes.c_char], 116]
|
|
qpChDc: Annotated[Annotated[bytes, ctypes.c_char], 117]
|
|
lossless: Annotated[Annotated[bytes, ctypes.c_char], 118]
|
|
transform_mode: Annotated[Annotated[bytes, ctypes.c_char], 119]
|
|
allow_high_precision_mv: Annotated[Annotated[bytes, ctypes.c_char], 120]
|
|
mcomp_filter_type: Annotated[Annotated[bytes, ctypes.c_char], 121]
|
|
comp_pred_mode: Annotated[Annotated[bytes, ctypes.c_char], 122]
|
|
comp_fixed_ref: Annotated[Annotated[bytes, ctypes.c_char], 123]
|
|
comp_var_ref: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[2]], 124]
|
|
log2_tile_columns: Annotated[Annotated[bytes, ctypes.c_char], 126]
|
|
log2_tile_rows: Annotated[Annotated[bytes, ctypes.c_char], 127]
|
|
segmentEnabled: Annotated[Annotated[int, ctypes.c_ubyte], 128]
|
|
segmentMapUpdate: Annotated[Annotated[int, ctypes.c_ubyte], 129]
|
|
segmentMapTemporalUpdate: Annotated[Annotated[int, ctypes.c_ubyte], 130]
|
|
segmentFeatureMode: Annotated[Annotated[int, ctypes.c_ubyte], 131]
|
|
segmentFeatureEnable: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], Literal[8]], 132]
|
|
segmentFeatureData: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_int16], Literal[4]], Literal[8]], 164]
|
|
modeRefLfEnabled: Annotated[Annotated[bytes, ctypes.c_char], 228]
|
|
mbRefLfDelta: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[4]], 229]
|
|
mbModeLfDelta: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[2]], 233]
|
|
reserved5: Annotated[Annotated[bytes, ctypes.c_char], 235]
|
|
v1: Annotated[nvdec_vp9_pic_v1_s, 236]
|
|
ssm: Annotated[nvdec_pass2_otf_ext_s, 244]
|
|
nvdec_vp9_pic_s: TypeAlias = struct__nvdec_vp9_pic_s
|
|
@c.record
|
|
class nvdec_nmv_context(c.Struct):
|
|
SIZE = 69
|
|
joints: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 0]
|
|
sign: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], 3]
|
|
class0: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[1]], Literal[2]], 5]
|
|
fp: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], Literal[2]], 7]
|
|
class0_hp: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], 13]
|
|
hp: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], 15]
|
|
classes: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[10]], Literal[2]], 17]
|
|
class0_fp: Annotated[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], Literal[2]], Literal[2]], 37]
|
|
bits: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[10]], Literal[2]], 49]
|
|
@c.record
|
|
class nvdec_nmv_context_counts(c.Struct):
|
|
SIZE = 424
|
|
joints: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 0]
|
|
sign: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], Literal[2]], 16]
|
|
classes: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[11]], Literal[2]], 32]
|
|
class0: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], Literal[2]], 120]
|
|
bits: Annotated[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], Literal[10]], Literal[2]], 136]
|
|
class0_fp: Annotated[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], Literal[2]], Literal[2]], 296]
|
|
fp: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], Literal[2]], 360]
|
|
class0_hp: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], Literal[2]], 392]
|
|
hp: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], Literal[2]], 408]
|
|
@c.record
|
|
class struct_nvdec_vp9AdaptiveEntropyProbs_s(c.Struct):
|
|
SIZE = 2720
|
|
inter_mode_prob: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], Literal[7]], 0]
|
|
intra_inter_prob: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], 28]
|
|
uv_mode_prob: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[8]], Literal[10]], 32]
|
|
tx8x8_prob: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[1]], Literal[2]], 112]
|
|
tx16x16_prob: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], Literal[2]], 114]
|
|
tx32x32_prob: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], Literal[2]], 118]
|
|
sb_ymode_probB: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[1]], Literal[4]], 124]
|
|
sb_ymode_prob: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[8]], Literal[4]], 128]
|
|
partition_prob: Annotated[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], Literal[16]], Literal[2]], 160]
|
|
uv_mode_probB: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[1]], Literal[10]], 288]
|
|
switchable_interp_prob: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], Literal[4]], 298]
|
|
comp_inter_prob: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[5]], 306]
|
|
mbskip_probs: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 311]
|
|
pad1: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[1]], 314]
|
|
nmvc: Annotated[nvdec_nmv_context, 315]
|
|
single_ref_prob: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], Literal[5]], 384]
|
|
comp_ref_prob: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[5]], 394]
|
|
pad2: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[17]], 399]
|
|
probCoeffs: Annotated[c.Array[c.Array[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 416]
|
|
probCoeffs8x8: Annotated[c.Array[c.Array[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 992]
|
|
probCoeffs16x16: Annotated[c.Array[c.Array[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 1568]
|
|
probCoeffs32x32: Annotated[c.Array[c.Array[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 2144]
|
|
nvdec_vp9AdaptiveEntropyProbs_t: TypeAlias = struct_nvdec_vp9AdaptiveEntropyProbs_s
|
|
@c.record
|
|
class struct_nvdec_vp9EntropyProbs_s(c.Struct):
|
|
SIZE = 3744
|
|
kf_bmode_prob: Annotated[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[8]], Literal[10]], Literal[10]], 0]
|
|
kf_bmode_probB: Annotated[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[1]], Literal[10]], Literal[10]], 800]
|
|
ref_pred_probs: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 900]
|
|
mb_segment_tree_probs: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[7]], 903]
|
|
segment_pred_probs: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 910]
|
|
ref_scores: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], 913]
|
|
prob_comppred: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], 917]
|
|
pad1: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[9]], 919]
|
|
kf_uv_mode_prob: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[8]], Literal[10]], 928]
|
|
kf_uv_mode_probB: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[1]], Literal[10]], 1008]
|
|
pad2: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[6]], 1018]
|
|
a: Annotated[nvdec_vp9AdaptiveEntropyProbs_t, 1024]
|
|
nvdec_vp9EntropyProbs_t: TypeAlias = struct_nvdec_vp9EntropyProbs_s
|
|
@c.record
|
|
class struct_nvdec_vp9EntropyCounts_s(c.Struct):
|
|
SIZE = 13264
|
|
inter_mode_counts: Annotated[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], Literal[3]], Literal[7]], 0]
|
|
sb_ymode_counts: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[10]], Literal[4]], 168]
|
|
uv_mode_counts: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[10]], Literal[10]], 328]
|
|
partition_counts: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], Literal[16]], 728]
|
|
switchable_interp_counts: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[3]], Literal[4]], 984]
|
|
intra_inter_count: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], Literal[4]], 1032]
|
|
comp_inter_count: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], Literal[5]], 1064]
|
|
single_ref_count: Annotated[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], Literal[2]], Literal[5]], 1104]
|
|
comp_ref_count: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], Literal[5]], 1184]
|
|
tx32x32_count: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], Literal[2]], 1224]
|
|
tx16x16_count: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[3]], Literal[2]], 1256]
|
|
tx8x8_count: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], Literal[2]], 1280]
|
|
mbskip_count: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], Literal[3]], 1296]
|
|
nmvcount: Annotated[nvdec_nmv_context_counts, 1320]
|
|
countCoeffs: Annotated[c.Array[c.Array[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 1744]
|
|
countCoeffs8x8: Annotated[c.Array[c.Array[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 4048]
|
|
countCoeffs16x16: Annotated[c.Array[c.Array[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 6352]
|
|
countCoeffs32x32: Annotated[c.Array[c.Array[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], Literal[6]], Literal[6]], Literal[2]], Literal[2]], 8656]
|
|
countEobs: Annotated[c.Array[c.Array[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[6]], Literal[6]], Literal[2]], Literal[2]], Literal[4]], 10960]
|
|
nvdec_vp9EntropyCounts_t: TypeAlias = struct_nvdec_vp9EntropyCounts_s
|
|
@c.record
|
|
class struct__nvdec_pass2_otf_s(c.Struct):
|
|
SIZE = 52
|
|
wrapped_session_key: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 0]
|
|
wrapped_content_key: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 16]
|
|
initialization_vector: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 32]
|
|
enable_encryption: Annotated[Annotated[int, ctypes.c_uint32], 48, 1, 0]
|
|
key_increment: Annotated[Annotated[int, ctypes.c_uint32], 48, 6, 1]
|
|
encryption_mode: Annotated[Annotated[int, ctypes.c_uint32], 48, 4, 7]
|
|
key_slot_index: Annotated[Annotated[int, ctypes.c_uint32], 49, 4, 3]
|
|
ssm_en: Annotated[Annotated[int, ctypes.c_uint32], 49, 1, 7]
|
|
reserved1: Annotated[Annotated[int, ctypes.c_uint32], 50, 16, 0]
|
|
nvdec_pass2_otf_s: TypeAlias = struct__nvdec_pass2_otf_s
|
|
@c.record
|
|
class struct__nvdec_display_param_s(c.Struct):
|
|
SIZE = 28
|
|
enableTFOutput: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 0]
|
|
VC1MapYFlag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 1]
|
|
MapYValue: Annotated[Annotated[int, ctypes.c_uint32], 0, 3, 2]
|
|
VC1MapUVFlag: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 5]
|
|
MapUVValue: Annotated[Annotated[int, ctypes.c_uint32], 0, 3, 6]
|
|
OutStride: Annotated[Annotated[int, ctypes.c_uint32], 1, 8, 1]
|
|
TilingFormat: Annotated[Annotated[int, ctypes.c_uint32], 2, 3, 1]
|
|
OutputStructure: Annotated[Annotated[int, ctypes.c_uint32], 2, 1, 4]
|
|
reserved0: Annotated[Annotated[int, ctypes.c_uint32], 2, 11, 5]
|
|
OutputTop: Annotated[c.Array[Annotated[int, ctypes.c_int32], Literal[2]], 4]
|
|
OutputBottom: Annotated[c.Array[Annotated[int, ctypes.c_int32], Literal[2]], 12]
|
|
enableHistogram: Annotated[Annotated[int, ctypes.c_uint32], 20, 1, 0]
|
|
HistogramStartX: Annotated[Annotated[int, ctypes.c_uint32], 20, 12, 1]
|
|
HistogramStartY: Annotated[Annotated[int, ctypes.c_uint32], 21, 12, 5]
|
|
reserved1: Annotated[Annotated[int, ctypes.c_uint32], 23, 7, 1]
|
|
HistogramEndX: Annotated[Annotated[int, ctypes.c_uint32], 24, 12, 0]
|
|
HistogramEndY: Annotated[Annotated[int, ctypes.c_uint32], 25, 12, 4]
|
|
reserved2: Annotated[Annotated[int, ctypes.c_uint32], 27, 8, 0]
|
|
nvdec_display_param_s: TypeAlias = struct__nvdec_display_param_s
|
|
@c.record
|
|
class struct__nvdec_dpb_entry_s(c.Struct):
|
|
SIZE = 16
|
|
index: Annotated[Annotated[int, ctypes.c_uint32], 0, 7, 0]
|
|
col_idx: Annotated[Annotated[int, ctypes.c_uint32], 0, 5, 7]
|
|
state: Annotated[Annotated[int, ctypes.c_uint32], 1, 2, 4]
|
|
is_long_term: Annotated[Annotated[int, ctypes.c_uint32], 1, 1, 6]
|
|
not_existing: Annotated[Annotated[int, ctypes.c_uint32], 1, 1, 7]
|
|
is_field: Annotated[Annotated[int, ctypes.c_uint32], 2, 1, 0]
|
|
top_field_marking: Annotated[Annotated[int, ctypes.c_uint32], 2, 4, 1]
|
|
bottom_field_marking: Annotated[Annotated[int, ctypes.c_uint32], 2, 4, 5]
|
|
output_memory_layout: Annotated[Annotated[int, ctypes.c_uint32], 3, 1, 1]
|
|
reserved: Annotated[Annotated[int, ctypes.c_uint32], 3, 6, 2]
|
|
FieldOrderCnt: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], 4]
|
|
FrameIdx: Annotated[Annotated[int, ctypes.c_int32], 12]
|
|
nvdec_dpb_entry_s: TypeAlias = struct__nvdec_dpb_entry_s
|
|
@c.record
|
|
class struct__nvdec_h264_pic_s(c.Struct):
|
|
SIZE = 764
|
|
encryption_params: Annotated[nvdec_pass2_otf_s, 0]
|
|
eos: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[16]], 52]
|
|
explicitEOSPresentFlag: Annotated[Annotated[int, ctypes.c_ubyte], 68]
|
|
hint_dump_en: Annotated[Annotated[int, ctypes.c_ubyte], 69]
|
|
reserved0: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], 70]
|
|
stream_len: Annotated[Annotated[int, ctypes.c_uint32], 72]
|
|
slice_count: Annotated[Annotated[int, ctypes.c_uint32], 76]
|
|
mbhist_buffer_size: Annotated[Annotated[int, ctypes.c_uint32], 80]
|
|
gptimer_timeout_value: Annotated[Annotated[int, ctypes.c_uint32], 84]
|
|
log2_max_pic_order_cnt_lsb_minus4: Annotated[Annotated[int, ctypes.c_int32], 88]
|
|
delta_pic_order_always_zero_flag: Annotated[Annotated[int, ctypes.c_int32], 92]
|
|
frame_mbs_only_flag: Annotated[Annotated[int, ctypes.c_int32], 96]
|
|
PicWidthInMbs: Annotated[Annotated[int, ctypes.c_int32], 100]
|
|
FrameHeightInMbs: Annotated[Annotated[int, ctypes.c_int32], 104]
|
|
tileFormat: Annotated[Annotated[int, ctypes.c_uint32], 108, 2, 0]
|
|
gob_height: Annotated[Annotated[int, ctypes.c_uint32], 108, 3, 2]
|
|
reserverd_surface_format: Annotated[Annotated[int, ctypes.c_uint32], 108, 27, 5]
|
|
entropy_coding_mode_flag: Annotated[Annotated[int, ctypes.c_int32], 112]
|
|
pic_order_present_flag: Annotated[Annotated[int, ctypes.c_int32], 116]
|
|
num_ref_idx_l0_active_minus1: Annotated[Annotated[int, ctypes.c_int32], 120]
|
|
num_ref_idx_l1_active_minus1: Annotated[Annotated[int, ctypes.c_int32], 124]
|
|
deblocking_filter_control_present_flag: Annotated[Annotated[int, ctypes.c_int32], 128]
|
|
redundant_pic_cnt_present_flag: Annotated[Annotated[int, ctypes.c_int32], 132]
|
|
transform_8x8_mode_flag: Annotated[Annotated[int, ctypes.c_int32], 136]
|
|
pitch_luma: Annotated[Annotated[int, ctypes.c_uint32], 140]
|
|
pitch_chroma: Annotated[Annotated[int, ctypes.c_uint32], 144]
|
|
luma_top_offset: Annotated[Annotated[int, ctypes.c_uint32], 148]
|
|
luma_bot_offset: Annotated[Annotated[int, ctypes.c_uint32], 152]
|
|
luma_frame_offset: Annotated[Annotated[int, ctypes.c_uint32], 156]
|
|
chroma_top_offset: Annotated[Annotated[int, ctypes.c_uint32], 160]
|
|
chroma_bot_offset: Annotated[Annotated[int, ctypes.c_uint32], 164]
|
|
chroma_frame_offset: Annotated[Annotated[int, ctypes.c_uint32], 168]
|
|
HistBufferSize: Annotated[Annotated[int, ctypes.c_uint32], 172]
|
|
MbaffFrameFlag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 0]
|
|
direct_8x8_inference_flag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 1]
|
|
weighted_pred_flag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 2]
|
|
constrained_intra_pred_flag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 3]
|
|
ref_pic_flag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 4]
|
|
field_pic_flag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 5]
|
|
bottom_field_flag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 6]
|
|
second_field: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 7]
|
|
log2_max_frame_num_minus4: Annotated[Annotated[int, ctypes.c_uint32], 177, 4, 0]
|
|
chroma_format_idc: Annotated[Annotated[int, ctypes.c_uint32], 177, 2, 4]
|
|
pic_order_cnt_type: Annotated[Annotated[int, ctypes.c_uint32], 177, 2, 6]
|
|
pic_init_qp_minus26: Annotated[Annotated[int, ctypes.c_int32], 178, 6, 0]
|
|
chroma_qp_index_offset: Annotated[Annotated[int, ctypes.c_int32], 178, 5, 6]
|
|
second_chroma_qp_index_offset: Annotated[Annotated[int, ctypes.c_int32], 179, 5, 3]
|
|
weighted_bipred_idc: Annotated[Annotated[int, ctypes.c_uint32], 180, 2, 0]
|
|
CurrPicIdx: Annotated[Annotated[int, ctypes.c_uint32], 180, 7, 2]
|
|
CurrColIdx: Annotated[Annotated[int, ctypes.c_uint32], 181, 5, 1]
|
|
frame_num: Annotated[Annotated[int, ctypes.c_uint32], 181, 16, 6]
|
|
frame_surfaces: Annotated[Annotated[int, ctypes.c_uint32], 183, 1, 6]
|
|
output_memory_layout: Annotated[Annotated[int, ctypes.c_uint32], 183, 1, 7]
|
|
CurrFieldOrderCnt: Annotated[c.Array[Annotated[int, ctypes.c_int32], Literal[2]], 184]
|
|
dpb: Annotated[c.Array[nvdec_dpb_entry_s, Literal[16]], 192]
|
|
WeightScale: Annotated[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], Literal[4]], Literal[6]], 448]
|
|
WeightScale8x8: Annotated[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[8]], Literal[8]], Literal[2]], 544]
|
|
num_inter_view_refs_lX: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], 672]
|
|
reserved1: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[14]], 674]
|
|
inter_view_refidx_lX: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_byte], Literal[16]], Literal[2]], 688]
|
|
lossless_ipred8x8_filter_enable: Annotated[Annotated[int, ctypes.c_uint32], 720, 1, 0]
|
|
qpprime_y_zero_transform_bypass_flag: Annotated[Annotated[int, ctypes.c_uint32], 720, 1, 1]
|
|
reserved2: Annotated[Annotated[int, ctypes.c_uint32], 720, 30, 2]
|
|
displayPara: Annotated[nvdec_display_param_s, 724]
|
|
ssm: Annotated[nvdec_pass2_otf_ext_s, 752]
|
|
nvdec_h264_pic_s: TypeAlias = struct__nvdec_h264_pic_s
|
|
class enum__vc1_fcm_e(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
FCM_PROGRESSIVE = enum__vc1_fcm_e.define('FCM_PROGRESSIVE', 0)
|
|
FCM_FRAME_INTERLACE = enum__vc1_fcm_e.define('FCM_FRAME_INTERLACE', 2)
|
|
FCM_FIELD_INTERLACE = enum__vc1_fcm_e.define('FCM_FIELD_INTERLACE', 3)
|
|
|
|
vc1_fcm_e: TypeAlias = enum__vc1_fcm_e
|
|
class enum__syntax_vc1_ptype_e(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
PTYPE_I = enum__syntax_vc1_ptype_e.define('PTYPE_I', 0)
|
|
PTYPE_P = enum__syntax_vc1_ptype_e.define('PTYPE_P', 1)
|
|
PTYPE_B = enum__syntax_vc1_ptype_e.define('PTYPE_B', 2)
|
|
PTYPE_BI = enum__syntax_vc1_ptype_e.define('PTYPE_BI', 3)
|
|
PTYPE_SKIPPED = enum__syntax_vc1_ptype_e.define('PTYPE_SKIPPED', 4)
|
|
|
|
syntax_vc1_ptype_e: TypeAlias = enum__syntax_vc1_ptype_e
|
|
class enum_vc1_mvmode_e(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
MVMODE_MIXEDMV = enum_vc1_mvmode_e.define('MVMODE_MIXEDMV', 0)
|
|
MVMODE_1MV = enum_vc1_mvmode_e.define('MVMODE_1MV', 1)
|
|
MVMODE_1MV_HALFPEL = enum_vc1_mvmode_e.define('MVMODE_1MV_HALFPEL', 2)
|
|
MVMODE_1MV_HALFPEL_BILINEAR = enum_vc1_mvmode_e.define('MVMODE_1MV_HALFPEL_BILINEAR', 3)
|
|
MVMODE_INTENSITY_COMPENSATION = enum_vc1_mvmode_e.define('MVMODE_INTENSITY_COMPENSATION', 4)
|
|
|
|
class enum__vc1_fptype_e(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
FPTYPE_I_I = enum__vc1_fptype_e.define('FPTYPE_I_I', 0)
|
|
FPTYPE_I_P = enum__vc1_fptype_e.define('FPTYPE_I_P', 1)
|
|
FPTYPE_P_I = enum__vc1_fptype_e.define('FPTYPE_P_I', 2)
|
|
FPTYPE_P_P = enum__vc1_fptype_e.define('FPTYPE_P_P', 3)
|
|
FPTYPE_B_B = enum__vc1_fptype_e.define('FPTYPE_B_B', 4)
|
|
FPTYPE_B_BI = enum__vc1_fptype_e.define('FPTYPE_B_BI', 5)
|
|
FPTYPE_BI_B = enum__vc1_fptype_e.define('FPTYPE_BI_B', 6)
|
|
FPTYPE_BI_BI = enum__vc1_fptype_e.define('FPTYPE_BI_BI', 7)
|
|
|
|
vc1_fptype_e: TypeAlias = enum__vc1_fptype_e
|
|
class enum__vc1_dqprofile_e(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
DQPROFILE_ALL_FOUR_EDGES = enum__vc1_dqprofile_e.define('DQPROFILE_ALL_FOUR_EDGES', 0)
|
|
DQPROFILE_DOUBLE_EDGE = enum__vc1_dqprofile_e.define('DQPROFILE_DOUBLE_EDGE', 1)
|
|
DQPROFILE_SINGLE_EDGE = enum__vc1_dqprofile_e.define('DQPROFILE_SINGLE_EDGE', 2)
|
|
DQPROFILE_ALL_MACROBLOCKS = enum__vc1_dqprofile_e.define('DQPROFILE_ALL_MACROBLOCKS', 3)
|
|
|
|
vc1_dqprofile_e: TypeAlias = enum__vc1_dqprofile_e
|
|
@c.record
|
|
class struct__nvdec_vc1_pic_s(c.Struct):
|
|
SIZE = 404
|
|
encryption_params: Annotated[nvdec_pass2_otf_s, 0]
|
|
eos: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[16]], 52]
|
|
prefixStartCode: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], 68]
|
|
bitstream_offset: Annotated[Annotated[int, ctypes.c_uint32], 72]
|
|
explicitEOSPresentFlag: Annotated[Annotated[int, ctypes.c_ubyte], 76]
|
|
reserved0: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 77]
|
|
stream_len: Annotated[Annotated[int, ctypes.c_uint32], 80]
|
|
slice_count: Annotated[Annotated[int, ctypes.c_uint32], 84]
|
|
scratch_pic_buffer_size: Annotated[Annotated[int, ctypes.c_uint32], 88]
|
|
gptimer_timeout_value: Annotated[Annotated[int, ctypes.c_uint32], 92]
|
|
FrameWidth: Annotated[Annotated[int, ctypes.c_uint16], 96]
|
|
FrameHeight: Annotated[Annotated[int, ctypes.c_uint16], 98]
|
|
profile: Annotated[Annotated[int, ctypes.c_ubyte], 100]
|
|
postprocflag: Annotated[Annotated[int, ctypes.c_ubyte], 101]
|
|
pulldown: Annotated[Annotated[int, ctypes.c_ubyte], 102]
|
|
interlace: Annotated[Annotated[int, ctypes.c_ubyte], 103]
|
|
tfcntrflag: Annotated[Annotated[int, ctypes.c_ubyte], 104]
|
|
finterpflag: Annotated[Annotated[int, ctypes.c_ubyte], 105]
|
|
psf: Annotated[Annotated[int, ctypes.c_ubyte], 106]
|
|
tileFormat: Annotated[Annotated[int, ctypes.c_ubyte], 107, 2, 0]
|
|
gob_height: Annotated[Annotated[int, ctypes.c_ubyte], 107, 3, 2]
|
|
reserverd_surface_format: Annotated[Annotated[int, ctypes.c_ubyte], 107, 3, 5]
|
|
multires: Annotated[Annotated[int, ctypes.c_ubyte], 108]
|
|
syncmarker: Annotated[Annotated[int, ctypes.c_ubyte], 109]
|
|
rangered: Annotated[Annotated[int, ctypes.c_ubyte], 110]
|
|
maxbframes: Annotated[Annotated[int, ctypes.c_ubyte], 111]
|
|
dquant: Annotated[Annotated[int, ctypes.c_ubyte], 112]
|
|
panscan_flag: Annotated[Annotated[int, ctypes.c_ubyte], 113]
|
|
refdist_flag: Annotated[Annotated[int, ctypes.c_ubyte], 114]
|
|
quantizer: Annotated[Annotated[int, ctypes.c_ubyte], 115]
|
|
extended_mv: Annotated[Annotated[int, ctypes.c_ubyte], 116]
|
|
extended_dmv: Annotated[Annotated[int, ctypes.c_ubyte], 117]
|
|
overlap: Annotated[Annotated[int, ctypes.c_ubyte], 118]
|
|
vstransform: Annotated[Annotated[int, ctypes.c_ubyte], 119]
|
|
refdist: Annotated[Annotated[bytes, ctypes.c_char], 120]
|
|
reserved1: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[3]], 121]
|
|
fcm: Annotated[vc1_fcm_e, 124]
|
|
ptype: Annotated[syntax_vc1_ptype_e, 128]
|
|
tfcntr: Annotated[Annotated[int, ctypes.c_int32], 132]
|
|
rptfrm: Annotated[Annotated[int, ctypes.c_int32], 136]
|
|
tff: Annotated[Annotated[int, ctypes.c_int32], 140]
|
|
rndctrl: Annotated[Annotated[int, ctypes.c_int32], 144]
|
|
pqindex: Annotated[Annotated[int, ctypes.c_int32], 148]
|
|
halfqp: Annotated[Annotated[int, ctypes.c_int32], 152]
|
|
pquantizer: Annotated[Annotated[int, ctypes.c_int32], 156]
|
|
postproc: Annotated[Annotated[int, ctypes.c_int32], 160]
|
|
condover: Annotated[Annotated[int, ctypes.c_int32], 164]
|
|
transacfrm: Annotated[Annotated[int, ctypes.c_int32], 168]
|
|
transacfrm2: Annotated[Annotated[int, ctypes.c_int32], 172]
|
|
transdctab: Annotated[Annotated[int, ctypes.c_int32], 176]
|
|
pqdiff: Annotated[Annotated[int, ctypes.c_int32], 180]
|
|
abspq: Annotated[Annotated[int, ctypes.c_int32], 184]
|
|
dquantfrm: Annotated[Annotated[int, ctypes.c_int32], 188]
|
|
dqprofile: Annotated[vc1_dqprofile_e, 192]
|
|
dqsbedge: Annotated[Annotated[int, ctypes.c_int32], 196]
|
|
dqdbedge: Annotated[Annotated[int, ctypes.c_int32], 200]
|
|
dqbilevel: Annotated[Annotated[int, ctypes.c_int32], 204]
|
|
mvrange: Annotated[Annotated[int, ctypes.c_int32], 208]
|
|
mvmode: Annotated[enum_vc1_mvmode_e, 212]
|
|
mvmode2: Annotated[enum_vc1_mvmode_e, 216]
|
|
lumscale: Annotated[Annotated[int, ctypes.c_int32], 220]
|
|
lumshift: Annotated[Annotated[int, ctypes.c_int32], 224]
|
|
mvtab: Annotated[Annotated[int, ctypes.c_int32], 228]
|
|
cbptab: Annotated[Annotated[int, ctypes.c_int32], 232]
|
|
ttmbf: Annotated[Annotated[int, ctypes.c_int32], 236]
|
|
ttfrm: Annotated[Annotated[int, ctypes.c_int32], 240]
|
|
bfraction: Annotated[Annotated[int, ctypes.c_int32], 244]
|
|
fptype: Annotated[vc1_fptype_e, 248]
|
|
numref: Annotated[Annotated[int, ctypes.c_int32], 252]
|
|
reffield: Annotated[Annotated[int, ctypes.c_int32], 256]
|
|
dmvrange: Annotated[Annotated[int, ctypes.c_int32], 260]
|
|
intcompfield: Annotated[Annotated[int, ctypes.c_int32], 264]
|
|
lumscale1: Annotated[Annotated[int, ctypes.c_int32], 268]
|
|
lumshift1: Annotated[Annotated[int, ctypes.c_int32], 272]
|
|
lumscale2: Annotated[Annotated[int, ctypes.c_int32], 276]
|
|
lumshift2: Annotated[Annotated[int, ctypes.c_int32], 280]
|
|
mbmodetab: Annotated[Annotated[int, ctypes.c_int32], 284]
|
|
imvtab: Annotated[Annotated[int, ctypes.c_int32], 288]
|
|
icbptab: Annotated[Annotated[int, ctypes.c_int32], 292]
|
|
fourmvbptab: Annotated[Annotated[int, ctypes.c_int32], 296]
|
|
fourmvswitch: Annotated[Annotated[int, ctypes.c_int32], 300]
|
|
intcomp: Annotated[Annotated[int, ctypes.c_int32], 304]
|
|
twomvbptab: Annotated[Annotated[int, ctypes.c_int32], 308]
|
|
rangeredfrm: Annotated[Annotated[int, ctypes.c_int32], 312]
|
|
HistBufferSize: Annotated[Annotated[int, ctypes.c_uint32], 316]
|
|
FrameStride: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], 320]
|
|
luma_top_offset: Annotated[Annotated[int, ctypes.c_uint32], 328]
|
|
luma_bot_offset: Annotated[Annotated[int, ctypes.c_uint32], 332]
|
|
luma_frame_offset: Annotated[Annotated[int, ctypes.c_uint32], 336]
|
|
chroma_top_offset: Annotated[Annotated[int, ctypes.c_uint32], 340]
|
|
chroma_bot_offset: Annotated[Annotated[int, ctypes.c_uint32], 344]
|
|
chroma_frame_offset: Annotated[Annotated[int, ctypes.c_uint32], 348]
|
|
CodedWidth: Annotated[Annotated[int, ctypes.c_uint16], 352]
|
|
CodedHeight: Annotated[Annotated[int, ctypes.c_uint16], 354]
|
|
loopfilter: Annotated[Annotated[int, ctypes.c_ubyte], 356]
|
|
fastuvmc: Annotated[Annotated[int, ctypes.c_ubyte], 357]
|
|
output_memory_layout: Annotated[Annotated[int, ctypes.c_ubyte], 358]
|
|
ref_memory_layout: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], 359]
|
|
reserved3: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 361]
|
|
displayPara: Annotated[nvdec_display_param_s, 364]
|
|
ssm: Annotated[nvdec_pass2_otf_ext_s, 392]
|
|
nvdec_vc1_pic_s: TypeAlias = struct__nvdec_vc1_pic_s
|
|
@c.record
|
|
class struct__nvdec_mpeg2_pic_s(c.Struct):
|
|
SIZE = 344
|
|
encryption_params: Annotated[nvdec_pass2_otf_s, 0]
|
|
eos: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[16]], 52]
|
|
explicitEOSPresentFlag: Annotated[Annotated[int, ctypes.c_ubyte], 68]
|
|
reserved0: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 69]
|
|
stream_len: Annotated[Annotated[int, ctypes.c_uint32], 72]
|
|
slice_count: Annotated[Annotated[int, ctypes.c_uint32], 76]
|
|
gptimer_timeout_value: Annotated[Annotated[int, ctypes.c_uint32], 80]
|
|
FrameWidth: Annotated[Annotated[int, ctypes.c_int16], 84]
|
|
FrameHeight: Annotated[Annotated[int, ctypes.c_int16], 86]
|
|
picture_structure: Annotated[Annotated[int, ctypes.c_ubyte], 88]
|
|
picture_coding_type: Annotated[Annotated[int, ctypes.c_ubyte], 89]
|
|
intra_dc_precision: Annotated[Annotated[int, ctypes.c_ubyte], 90]
|
|
frame_pred_frame_dct: Annotated[Annotated[bytes, ctypes.c_char], 91]
|
|
concealment_motion_vectors: Annotated[Annotated[bytes, ctypes.c_char], 92]
|
|
intra_vlc_format: Annotated[Annotated[bytes, ctypes.c_char], 93]
|
|
tileFormat: Annotated[Annotated[int, ctypes.c_ubyte], 94, 2, 0]
|
|
gob_height: Annotated[Annotated[int, ctypes.c_ubyte], 94, 3, 2]
|
|
reserverd_surface_format: Annotated[Annotated[int, ctypes.c_ubyte], 94, 3, 5]
|
|
reserved1: Annotated[Annotated[bytes, ctypes.c_char], 95]
|
|
f_code: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[4]], 96]
|
|
PicWidthInMbs: Annotated[Annotated[int, ctypes.c_uint16], 100]
|
|
FrameHeightInMbs: Annotated[Annotated[int, ctypes.c_uint16], 102]
|
|
pitch_luma: Annotated[Annotated[int, ctypes.c_uint32], 104]
|
|
pitch_chroma: Annotated[Annotated[int, ctypes.c_uint32], 108]
|
|
luma_top_offset: Annotated[Annotated[int, ctypes.c_uint32], 112]
|
|
luma_bot_offset: Annotated[Annotated[int, ctypes.c_uint32], 116]
|
|
luma_frame_offset: Annotated[Annotated[int, ctypes.c_uint32], 120]
|
|
chroma_top_offset: Annotated[Annotated[int, ctypes.c_uint32], 124]
|
|
chroma_bot_offset: Annotated[Annotated[int, ctypes.c_uint32], 128]
|
|
chroma_frame_offset: Annotated[Annotated[int, ctypes.c_uint32], 132]
|
|
HistBufferSize: Annotated[Annotated[int, ctypes.c_uint32], 136]
|
|
output_memory_layout: Annotated[Annotated[int, ctypes.c_uint16], 140]
|
|
alternate_scan: Annotated[Annotated[int, ctypes.c_uint16], 142]
|
|
secondfield: Annotated[Annotated[int, ctypes.c_uint16], 144]
|
|
rounding_type: Annotated[Annotated[int, ctypes.c_uint16], 146]
|
|
MbInfoSizeInBytes: Annotated[Annotated[int, ctypes.c_uint32], 148]
|
|
q_scale_type: Annotated[Annotated[int, ctypes.c_uint32], 152]
|
|
top_field_first: Annotated[Annotated[int, ctypes.c_uint32], 156]
|
|
full_pel_fwd_vector: Annotated[Annotated[int, ctypes.c_uint32], 160]
|
|
full_pel_bwd_vector: Annotated[Annotated[int, ctypes.c_uint32], 164]
|
|
quant_mat_8x8intra: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[64]], 168]
|
|
quant_mat_8x8nonintra: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[64]], 232]
|
|
ref_memory_layout: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], 296]
|
|
displayPara: Annotated[nvdec_display_param_s, 304]
|
|
ssm: Annotated[nvdec_pass2_otf_ext_s, 332]
|
|
nvdec_mpeg2_pic_s: TypeAlias = struct__nvdec_mpeg2_pic_s
|
|
@c.record
|
|
class struct__nvdec_mpeg4_pic_s(c.Struct):
|
|
SIZE = 368
|
|
encryption_params: Annotated[nvdec_pass2_otf_s, 0]
|
|
eos: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[16]], 52]
|
|
explicitEOSPresentFlag: Annotated[Annotated[int, ctypes.c_ubyte], 68]
|
|
reserved2: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 69]
|
|
stream_len: Annotated[Annotated[int, ctypes.c_uint32], 72]
|
|
slice_count: Annotated[Annotated[int, ctypes.c_uint32], 76]
|
|
scratch_pic_buffer_size: Annotated[Annotated[int, ctypes.c_uint32], 80]
|
|
gptimer_timeout_value: Annotated[Annotated[int, ctypes.c_uint32], 84]
|
|
FrameWidth: Annotated[Annotated[int, ctypes.c_int16], 88]
|
|
FrameHeight: Annotated[Annotated[int, ctypes.c_int16], 90]
|
|
vop_time_increment_bitcount: Annotated[Annotated[bytes, ctypes.c_char], 92]
|
|
resync_marker_disable: Annotated[Annotated[bytes, ctypes.c_char], 93]
|
|
tileFormat: Annotated[Annotated[int, ctypes.c_ubyte], 94, 2, 0]
|
|
gob_height: Annotated[Annotated[int, ctypes.c_ubyte], 94, 3, 2]
|
|
reserverd_surface_format: Annotated[Annotated[int, ctypes.c_ubyte], 94, 3, 5]
|
|
reserved3: Annotated[Annotated[bytes, ctypes.c_char], 95]
|
|
width: Annotated[Annotated[int, ctypes.c_int32], 96]
|
|
height: Annotated[Annotated[int, ctypes.c_int32], 100]
|
|
FrameStride: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], 104]
|
|
luma_top_offset: Annotated[Annotated[int, ctypes.c_uint32], 112]
|
|
luma_bot_offset: Annotated[Annotated[int, ctypes.c_uint32], 116]
|
|
luma_frame_offset: Annotated[Annotated[int, ctypes.c_uint32], 120]
|
|
chroma_top_offset: Annotated[Annotated[int, ctypes.c_uint32], 124]
|
|
chroma_bot_offset: Annotated[Annotated[int, ctypes.c_uint32], 128]
|
|
chroma_frame_offset: Annotated[Annotated[int, ctypes.c_uint32], 132]
|
|
HistBufferSize: Annotated[Annotated[int, ctypes.c_uint32], 136]
|
|
trd: Annotated[c.Array[Annotated[int, ctypes.c_int32], Literal[2]], 140]
|
|
trb: Annotated[c.Array[Annotated[int, ctypes.c_int32], Literal[2]], 148]
|
|
divx_flags: Annotated[Annotated[int, ctypes.c_int32], 156]
|
|
vop_fcode_forward: Annotated[Annotated[int, ctypes.c_int16], 160]
|
|
vop_fcode_backward: Annotated[Annotated[int, ctypes.c_int16], 162]
|
|
interlaced: Annotated[Annotated[int, ctypes.c_ubyte], 164]
|
|
quant_type: Annotated[Annotated[int, ctypes.c_ubyte], 165]
|
|
quarter_sample: Annotated[Annotated[int, ctypes.c_ubyte], 166]
|
|
short_video_header: Annotated[Annotated[int, ctypes.c_ubyte], 167]
|
|
curr_output_memory_layout: Annotated[Annotated[int, ctypes.c_ubyte], 168]
|
|
ptype: Annotated[Annotated[int, ctypes.c_ubyte], 169]
|
|
rnd: Annotated[Annotated[int, ctypes.c_ubyte], 170]
|
|
alternate_vertical_scan_flag: Annotated[Annotated[int, ctypes.c_ubyte], 171]
|
|
top_field_flag: Annotated[Annotated[int, ctypes.c_ubyte], 172]
|
|
reserved0: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 173]
|
|
intra_quant_mat: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[64]], 176]
|
|
nonintra_quant_mat: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[64]], 240]
|
|
ref_memory_layout: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], 304]
|
|
reserved1: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[34]], 306]
|
|
displayPara: Annotated[nvdec_display_param_s, 340]
|
|
nvdec_mpeg4_pic_s: TypeAlias = struct__nvdec_mpeg4_pic_s
|
|
class enum_VP8_FRAME_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
VP8_KEYFRAME = enum_VP8_FRAME_TYPE.define('VP8_KEYFRAME', 0)
|
|
VP8_INTERFRAME = enum_VP8_FRAME_TYPE.define('VP8_INTERFRAME', 1)
|
|
|
|
class enum_VP8_FRAME_SFC_ID(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
VP8_GOLDEN_FRAME_SFC = enum_VP8_FRAME_SFC_ID.define('VP8_GOLDEN_FRAME_SFC', 0)
|
|
VP8_ALTREF_FRAME_SFC = enum_VP8_FRAME_SFC_ID.define('VP8_ALTREF_FRAME_SFC', 1)
|
|
VP8_LAST_FRAME_SFC = enum_VP8_FRAME_SFC_ID.define('VP8_LAST_FRAME_SFC', 2)
|
|
VP8_CURR_FRAME_SFC = enum_VP8_FRAME_SFC_ID.define('VP8_CURR_FRAME_SFC', 3)
|
|
|
|
@c.record
|
|
class struct__nvdec_vp8_pic_s(c.Struct):
|
|
SIZE = 192
|
|
encryption_params: Annotated[nvdec_pass2_otf_s, 0]
|
|
gptimer_timeout_value: Annotated[Annotated[int, ctypes.c_uint32], 52]
|
|
FrameWidth: Annotated[Annotated[int, ctypes.c_uint16], 56]
|
|
FrameHeight: Annotated[Annotated[int, ctypes.c_uint16], 58]
|
|
keyFrame: Annotated[Annotated[int, ctypes.c_ubyte], 60]
|
|
version: Annotated[Annotated[int, ctypes.c_ubyte], 61]
|
|
tileFormat: Annotated[Annotated[int, ctypes.c_ubyte], 62, 2, 0]
|
|
gob_height: Annotated[Annotated[int, ctypes.c_ubyte], 62, 3, 2]
|
|
reserverd_surface_format: Annotated[Annotated[int, ctypes.c_ubyte], 62, 3, 5]
|
|
errorConcealOn: Annotated[Annotated[int, ctypes.c_ubyte], 63]
|
|
firstPartSize: Annotated[Annotated[int, ctypes.c_uint32], 64]
|
|
HistBufferSize: Annotated[Annotated[int, ctypes.c_uint32], 68]
|
|
VLDBufferSize: Annotated[Annotated[int, ctypes.c_uint32], 72]
|
|
FrameStride: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], 76]
|
|
luma_top_offset: Annotated[Annotated[int, ctypes.c_uint32], 84]
|
|
luma_bot_offset: Annotated[Annotated[int, ctypes.c_uint32], 88]
|
|
luma_frame_offset: Annotated[Annotated[int, ctypes.c_uint32], 92]
|
|
chroma_top_offset: Annotated[Annotated[int, ctypes.c_uint32], 96]
|
|
chroma_bot_offset: Annotated[Annotated[int, ctypes.c_uint32], 100]
|
|
chroma_frame_offset: Annotated[Annotated[int, ctypes.c_uint32], 104]
|
|
displayPara: Annotated[nvdec_display_param_s, 108]
|
|
current_output_memory_layout: Annotated[Annotated[bytes, ctypes.c_char], 136]
|
|
output_memory_layout: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[3]], 137]
|
|
segmentation_feature_data_update: Annotated[Annotated[int, ctypes.c_ubyte], 140]
|
|
reserved1: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 141]
|
|
resultValue: Annotated[Annotated[int, ctypes.c_uint32], 144]
|
|
partition_offset: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[8]], 148]
|
|
ssm: Annotated[nvdec_pass2_otf_ext_s, 180]
|
|
nvdec_vp8_pic_s: TypeAlias = struct__nvdec_vp8_pic_s
|
|
@c.record
|
|
class struct__bytes_of_data_s(c.Struct):
|
|
SIZE = 8
|
|
clear_bytes: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
|
encypted_bytes: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
|
bytes_of_data_s: TypeAlias = struct__bytes_of_data_s
|
|
@c.record
|
|
class struct__nvdec_pass1_input_data_s(c.Struct):
|
|
SIZE = 836
|
|
sample_size: Annotated[c.Array[bytes_of_data_s, Literal[32]], 0]
|
|
initialization_vector: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], Literal[32]], 256]
|
|
IvValid: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[32]], 768]
|
|
stream_len: Annotated[Annotated[int, ctypes.c_uint32], 800]
|
|
clearBufferSize: Annotated[Annotated[int, ctypes.c_uint32], 804]
|
|
reencryptBufferSize: Annotated[Annotated[int, ctypes.c_uint32], 808]
|
|
vp8coeffPartitonBufferSize: Annotated[Annotated[int, ctypes.c_uint32], 812]
|
|
PrevWidth: Annotated[Annotated[int, ctypes.c_uint32], 816]
|
|
num_nals: Annotated[Annotated[int, ctypes.c_uint32], 820, 16, 0]
|
|
drm_mode: Annotated[Annotated[int, ctypes.c_uint32], 822, 8, 0]
|
|
key_sel: Annotated[Annotated[int, ctypes.c_uint32], 823, 4, 0]
|
|
codec: Annotated[Annotated[int, ctypes.c_uint32], 823, 4, 4]
|
|
TotalSizeOfClearData: Annotated[Annotated[int, ctypes.c_uint32], 824]
|
|
SliceHdrOffset: Annotated[Annotated[int, ctypes.c_uint32], 828]
|
|
EncryptBlkCnt: Annotated[Annotated[int, ctypes.c_uint32], 832, 16, 0]
|
|
SkipBlkCnt: Annotated[Annotated[int, ctypes.c_uint32], 834, 16, 0]
|
|
nvdec_pass1_input_data_s: TypeAlias = struct__nvdec_pass1_input_data_s
|
|
@c.record
|
|
class struct__nvdec_pass1_output_data_s(c.Struct):
|
|
SIZE = 128
|
|
clear_header_size: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
|
reencrypt_data_size: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
|
clear_token_data_size: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
|
key_increment: Annotated[Annotated[int, ctypes.c_uint32], 12, 6, 0]
|
|
encryption_mode: Annotated[Annotated[int, ctypes.c_uint32], 12, 4, 6]
|
|
bReEncrypted: Annotated[Annotated[int, ctypes.c_uint32], 13, 1, 2]
|
|
bvp9SuperFrame: Annotated[Annotated[int, ctypes.c_uint32], 13, 1, 3]
|
|
vp9NumFramesMinus1: Annotated[Annotated[int, ctypes.c_uint32], 13, 3, 4]
|
|
reserved1: Annotated[Annotated[int, ctypes.c_uint32], 13, 17, 7]
|
|
wrapped_session_key: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 16]
|
|
wrapped_content_key: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 32]
|
|
initialization_vector: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 48]
|
|
partition_size: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[8]], 64]
|
|
vp9_frame_sizes: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[8]], 64]
|
|
vp9_clear_hdr_size: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[8]], 96]
|
|
nvdec_pass1_output_data_s: TypeAlias = struct__nvdec_pass1_output_data_s
|
|
@c.record
|
|
class struct__scale_factors_reference_s(c.Struct):
|
|
SIZE = 4
|
|
x_scale_fp: Annotated[Annotated[int, ctypes.c_int16], 0]
|
|
y_scale_fp: Annotated[Annotated[int, ctypes.c_int16], 2]
|
|
scale_factors_reference_s: TypeAlias = struct__scale_factors_reference_s
|
|
@c.record
|
|
class struct__frame_info_t(c.Struct):
|
|
SIZE = 12
|
|
width: Annotated[Annotated[int, ctypes.c_uint16], 0]
|
|
height: Annotated[Annotated[int, ctypes.c_uint16], 2]
|
|
stride: Annotated[c.Array[Annotated[int, ctypes.c_uint16], Literal[2]], 4]
|
|
frame_buffer_idx: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
|
frame_info_t: TypeAlias = struct__frame_info_t
|
|
@c.record
|
|
class struct__ref_frame_struct_s(c.Struct):
|
|
SIZE = 24
|
|
info: Annotated[frame_info_t, 0]
|
|
sf: Annotated[scale_factors_reference_s, 12]
|
|
sign_bias: Annotated[Annotated[int, ctypes.c_ubyte], 16, 1, 0]
|
|
wmtype: Annotated[Annotated[int, ctypes.c_ubyte], 16, 2, 1]
|
|
reserved_rf: Annotated[Annotated[int, ctypes.c_ubyte], 16, 5, 3]
|
|
frame_off: Annotated[Annotated[int, ctypes.c_int16], 18]
|
|
roffset: Annotated[Annotated[int, ctypes.c_int16], 20]
|
|
ref_frame_struct_s: TypeAlias = struct__ref_frame_struct_s
|
|
@c.record
|
|
class struct__av1_fgs_cfg_t(c.Struct):
|
|
SIZE = 12
|
|
apply_grain: Annotated[Annotated[int, ctypes.c_uint16], 0, 1, 0]
|
|
overlap_flag: Annotated[Annotated[int, ctypes.c_uint16], 0, 1, 1]
|
|
clip_to_restricted_range: Annotated[Annotated[int, ctypes.c_uint16], 0, 1, 2]
|
|
chroma_scaling_from_luma: Annotated[Annotated[int, ctypes.c_uint16], 0, 1, 3]
|
|
num_y_points_b: Annotated[Annotated[int, ctypes.c_uint16], 0, 1, 4]
|
|
num_cb_points_b: Annotated[Annotated[int, ctypes.c_uint16], 0, 1, 5]
|
|
num_cr_points_b: Annotated[Annotated[int, ctypes.c_uint16], 0, 1, 6]
|
|
scaling_shift: Annotated[Annotated[int, ctypes.c_uint16], 0, 4, 7]
|
|
reserved_fgs: Annotated[Annotated[int, ctypes.c_uint16], 1, 5, 3]
|
|
sw_random_seed: Annotated[Annotated[int, ctypes.c_uint16], 2]
|
|
cb_offset: Annotated[Annotated[int, ctypes.c_int16], 4]
|
|
cr_offset: Annotated[Annotated[int, ctypes.c_int16], 6]
|
|
cb_mult: Annotated[Annotated[bytes, ctypes.c_char], 8]
|
|
cb_luma_mult: Annotated[Annotated[bytes, ctypes.c_char], 9]
|
|
cr_mult: Annotated[Annotated[bytes, ctypes.c_char], 10]
|
|
cr_luma_mult: Annotated[Annotated[bytes, ctypes.c_char], 11]
|
|
av1_fgs_cfg_t: TypeAlias = struct__av1_fgs_cfg_t
|
|
@c.record
|
|
class struct__nvdec_av1_pic_s(c.Struct):
|
|
SIZE = 572
|
|
encryption_params: Annotated[nvdec_pass2_otf_s, 0]
|
|
ssm: Annotated[nvdec_pass2_otf_ext_s, 52]
|
|
fgs_cfg: Annotated[av1_fgs_cfg_t, 64]
|
|
gptimer_timeout_value: Annotated[Annotated[int, ctypes.c_uint32], 76]
|
|
stream_len: Annotated[Annotated[int, ctypes.c_uint32], 80]
|
|
reserved12: Annotated[Annotated[int, ctypes.c_uint32], 84]
|
|
use_128x128_superblock: Annotated[Annotated[int, ctypes.c_uint32], 88, 1, 0]
|
|
chroma_format: Annotated[Annotated[int, ctypes.c_uint32], 88, 2, 1]
|
|
bit_depth: Annotated[Annotated[int, ctypes.c_uint32], 88, 4, 3]
|
|
enable_filter_intra: Annotated[Annotated[int, ctypes.c_uint32], 88, 1, 7]
|
|
enable_intra_edge_filter: Annotated[Annotated[int, ctypes.c_uint32], 89, 1, 0]
|
|
enable_interintra_compound: Annotated[Annotated[int, ctypes.c_uint32], 89, 1, 1]
|
|
enable_masked_compound: Annotated[Annotated[int, ctypes.c_uint32], 89, 1, 2]
|
|
enable_dual_filter: Annotated[Annotated[int, ctypes.c_uint32], 89, 1, 3]
|
|
reserved10: Annotated[Annotated[int, ctypes.c_uint32], 89, 1, 4]
|
|
reserved0: Annotated[Annotated[int, ctypes.c_uint32], 89, 3, 5]
|
|
enable_jnt_comp: Annotated[Annotated[int, ctypes.c_uint32], 90, 1, 0]
|
|
reserved1: Annotated[Annotated[int, ctypes.c_uint32], 90, 1, 1]
|
|
enable_cdef: Annotated[Annotated[int, ctypes.c_uint32], 90, 1, 2]
|
|
reserved11: Annotated[Annotated[int, ctypes.c_uint32], 90, 1, 3]
|
|
enable_fgs: Annotated[Annotated[int, ctypes.c_uint32], 90, 1, 4]
|
|
enable_substream_decoding: Annotated[Annotated[int, ctypes.c_uint32], 90, 1, 5]
|
|
reserved2: Annotated[Annotated[int, ctypes.c_uint32], 90, 10, 6]
|
|
frame_type: Annotated[Annotated[int, ctypes.c_uint32], 92, 2, 0]
|
|
show_frame: Annotated[Annotated[int, ctypes.c_uint32], 92, 1, 2]
|
|
reserved13: Annotated[Annotated[int, ctypes.c_uint32], 92, 1, 3]
|
|
disable_cdf_update: Annotated[Annotated[int, ctypes.c_uint32], 92, 1, 4]
|
|
allow_screen_content_tools: Annotated[Annotated[int, ctypes.c_uint32], 92, 1, 5]
|
|
cur_frame_force_integer_mv: Annotated[Annotated[int, ctypes.c_uint32], 92, 1, 6]
|
|
scale_denom_minus9: Annotated[Annotated[int, ctypes.c_uint32], 92, 3, 7]
|
|
allow_intrabc: Annotated[Annotated[int, ctypes.c_uint32], 93, 1, 2]
|
|
allow_high_precision_mv: Annotated[Annotated[int, ctypes.c_uint32], 93, 1, 3]
|
|
interp_filter: Annotated[Annotated[int, ctypes.c_uint32], 93, 3, 4]
|
|
switchable_motion_mode: Annotated[Annotated[int, ctypes.c_uint32], 93, 1, 7]
|
|
use_ref_frame_mvs: Annotated[Annotated[int, ctypes.c_uint32], 94, 1, 0]
|
|
refresh_frame_context: Annotated[Annotated[int, ctypes.c_uint32], 94, 1, 1]
|
|
delta_q_present_flag: Annotated[Annotated[int, ctypes.c_uint32], 94, 1, 2]
|
|
delta_q_res: Annotated[Annotated[int, ctypes.c_uint32], 94, 2, 3]
|
|
delta_lf_present_flag: Annotated[Annotated[int, ctypes.c_uint32], 94, 1, 5]
|
|
delta_lf_res: Annotated[Annotated[int, ctypes.c_uint32], 94, 2, 6]
|
|
delta_lf_multi: Annotated[Annotated[int, ctypes.c_uint32], 95, 1, 0]
|
|
reserved3: Annotated[Annotated[int, ctypes.c_uint32], 95, 1, 1]
|
|
coded_lossless: Annotated[Annotated[int, ctypes.c_uint32], 95, 1, 2]
|
|
tile_enabled: Annotated[Annotated[int, ctypes.c_uint32], 95, 1, 3]
|
|
reserved4: Annotated[Annotated[int, ctypes.c_uint32], 95, 2, 4]
|
|
superres_is_scaled: Annotated[Annotated[int, ctypes.c_uint32], 95, 1, 6]
|
|
reserved_fh: Annotated[Annotated[int, ctypes.c_uint32], 95, 1, 7]
|
|
tile_cols: Annotated[Annotated[int, ctypes.c_uint32], 96, 8, 0]
|
|
tile_rows: Annotated[Annotated[int, ctypes.c_uint32], 97, 8, 0]
|
|
context_update_tile_id: Annotated[Annotated[int, ctypes.c_uint32], 98, 16, 0]
|
|
cdef_damping_minus_3: Annotated[Annotated[int, ctypes.c_uint32], 100, 2, 0]
|
|
cdef_bits: Annotated[Annotated[int, ctypes.c_uint32], 100, 2, 2]
|
|
frame_tx_mode: Annotated[Annotated[int, ctypes.c_uint32], 100, 3, 4]
|
|
frame_reference_mode: Annotated[Annotated[int, ctypes.c_uint32], 100, 2, 7]
|
|
skip_mode_flag: Annotated[Annotated[int, ctypes.c_uint32], 101, 1, 1]
|
|
skip_ref0: Annotated[Annotated[int, ctypes.c_uint32], 101, 4, 2]
|
|
skip_ref1: Annotated[Annotated[int, ctypes.c_uint32], 101, 4, 6]
|
|
allow_warp: Annotated[Annotated[int, ctypes.c_uint32], 102, 1, 2]
|
|
reduced_tx_set_used: Annotated[Annotated[int, ctypes.c_uint32], 102, 1, 3]
|
|
ref_scaling_enable: Annotated[Annotated[int, ctypes.c_uint32], 102, 1, 4]
|
|
reserved5: Annotated[Annotated[int, ctypes.c_uint32], 102, 1, 5]
|
|
reserved6: Annotated[Annotated[int, ctypes.c_uint32], 102, 10, 6]
|
|
superres_upscaled_width: Annotated[Annotated[int, ctypes.c_uint16], 104]
|
|
superres_luma_step: Annotated[Annotated[int, ctypes.c_uint16], 106]
|
|
superres_chroma_step: Annotated[Annotated[int, ctypes.c_uint16], 108]
|
|
superres_init_luma_subpel_x: Annotated[Annotated[int, ctypes.c_uint16], 110]
|
|
superres_init_chroma_subpel_x: Annotated[Annotated[int, ctypes.c_uint16], 112]
|
|
base_qindex: Annotated[Annotated[int, ctypes.c_ubyte], 114]
|
|
y_dc_delta_q: Annotated[Annotated[bytes, ctypes.c_char], 115]
|
|
u_dc_delta_q: Annotated[Annotated[bytes, ctypes.c_char], 116]
|
|
v_dc_delta_q: Annotated[Annotated[bytes, ctypes.c_char], 117]
|
|
u_ac_delta_q: Annotated[Annotated[bytes, ctypes.c_char], 118]
|
|
v_ac_delta_q: Annotated[Annotated[bytes, ctypes.c_char], 119]
|
|
qm_y: Annotated[Annotated[int, ctypes.c_ubyte], 120]
|
|
qm_u: Annotated[Annotated[int, ctypes.c_ubyte], 121]
|
|
qm_v: Annotated[Annotated[int, ctypes.c_ubyte], 122]
|
|
cdef_y_pri_strength: Annotated[Annotated[int, ctypes.c_uint32], 124]
|
|
cdef_uv_pri_strength: Annotated[Annotated[int, ctypes.c_uint32], 128]
|
|
cdef_y_sec_strength: Annotated[Annotated[int, ctypes.c_uint32], 132, 16, 0]
|
|
cdef_uv_sec_strength: Annotated[Annotated[int, ctypes.c_uint32], 134, 16, 0]
|
|
segment_enabled: Annotated[Annotated[int, ctypes.c_ubyte], 136]
|
|
segment_update_map: Annotated[Annotated[int, ctypes.c_ubyte], 137]
|
|
reserved7: Annotated[Annotated[int, ctypes.c_ubyte], 138]
|
|
segment_temporal_update: Annotated[Annotated[int, ctypes.c_ubyte], 139]
|
|
segment_feature_data: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_int16], Literal[8]], Literal[8]], 140]
|
|
last_active_segid: Annotated[Annotated[int, ctypes.c_ubyte], 268]
|
|
segid_preskip: Annotated[Annotated[int, ctypes.c_ubyte], 269]
|
|
prevsegid_flag: Annotated[Annotated[int, ctypes.c_ubyte], 270]
|
|
segment_quant_sign: Annotated[Annotated[int, ctypes.c_ubyte], 271, 8, 0]
|
|
filter_level: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], 272]
|
|
filter_level_u: Annotated[Annotated[int, ctypes.c_ubyte], 274]
|
|
filter_level_v: Annotated[Annotated[int, ctypes.c_ubyte], 275]
|
|
lf_sharpness_level: Annotated[Annotated[int, ctypes.c_ubyte], 276]
|
|
lf_ref_deltas: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[8]], 277]
|
|
lf_mode_deltas: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[2]], 285]
|
|
lr_type: Annotated[Annotated[int, ctypes.c_ubyte], 287]
|
|
lr_unit_size: Annotated[Annotated[int, ctypes.c_ubyte], 288]
|
|
current_frame: Annotated[frame_info_t, 292]
|
|
ref_frame: Annotated[c.Array[ref_frame_struct_s, Literal[7]], 304]
|
|
use_temporal0_mvs: Annotated[Annotated[int, ctypes.c_uint32], 472, 1, 0]
|
|
use_temporal1_mvs: Annotated[Annotated[int, ctypes.c_uint32], 472, 1, 1]
|
|
use_temporal2_mvs: Annotated[Annotated[int, ctypes.c_uint32], 472, 1, 2]
|
|
mf1_type: Annotated[Annotated[int, ctypes.c_uint32], 472, 3, 3]
|
|
mf2_type: Annotated[Annotated[int, ctypes.c_uint32], 472, 3, 6]
|
|
mf3_type: Annotated[Annotated[int, ctypes.c_uint32], 473, 3, 1]
|
|
reserved_mfmv: Annotated[Annotated[int, ctypes.c_uint32], 473, 20, 4]
|
|
mfmv_offset: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_int16], Literal[7]], Literal[3]], 476]
|
|
mfmv_side: Annotated[c.Array[c.Array[Annotated[bytes, ctypes.c_char], Literal[7]], Literal[3]], 518]
|
|
tileformat: Annotated[Annotated[int, ctypes.c_ubyte], 539, 2, 0]
|
|
gob_height: Annotated[Annotated[int, ctypes.c_ubyte], 539, 3, 2]
|
|
errorConcealOn: Annotated[Annotated[int, ctypes.c_ubyte], 539, 1, 5]
|
|
reserver8: Annotated[Annotated[int, ctypes.c_ubyte], 539, 2, 6]
|
|
stream_error_detection: Annotated[Annotated[int, ctypes.c_ubyte], 540, 1, 0]
|
|
mv_error_detection: Annotated[Annotated[int, ctypes.c_ubyte], 540, 1, 1]
|
|
coeff_error_detection: Annotated[Annotated[int, ctypes.c_ubyte], 540, 1, 2]
|
|
reserved_eh: Annotated[Annotated[int, ctypes.c_ubyte], 540, 5, 3]
|
|
Av1FltTopOffset: Annotated[Annotated[int, ctypes.c_uint32], 544]
|
|
Av1FltVertOffset: Annotated[Annotated[int, ctypes.c_uint32], 548]
|
|
Av1CdefVertOffset: Annotated[Annotated[int, ctypes.c_uint32], 552]
|
|
Av1LrVertOffset: Annotated[Annotated[int, ctypes.c_uint32], 556]
|
|
Av1HusVertOffset: Annotated[Annotated[int, ctypes.c_uint32], 560]
|
|
Av1FgsVertOffset: Annotated[Annotated[int, ctypes.c_uint32], 564]
|
|
enable_histogram: Annotated[Annotated[int, ctypes.c_uint32], 568, 1, 0]
|
|
sw_skip_start_length: Annotated[Annotated[int, ctypes.c_uint32], 568, 14, 1]
|
|
reserved_stat: Annotated[Annotated[int, ctypes.c_uint32], 569, 17, 7]
|
|
nvdec_av1_pic_s: TypeAlias = struct__nvdec_av1_pic_s
|
|
@c.record
|
|
class struct__AV1FilmGrainMemory(c.Struct):
|
|
SIZE = 13056
|
|
scaling_lut_y: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[256]], 0]
|
|
scaling_lut_cb: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[256]], 256]
|
|
scaling_lut_cr: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[256]], 512]
|
|
cropped_luma_grain_block: Annotated[c.Array[Annotated[int, ctypes.c_int16], Literal[4096]], 768]
|
|
cropped_cb_grain_block: Annotated[c.Array[Annotated[int, ctypes.c_int16], Literal[1024]], 8960]
|
|
cropped_cr_grain_block: Annotated[c.Array[Annotated[int, ctypes.c_int16], Literal[1024]], 11008]
|
|
AV1FilmGrainMemory: TypeAlias = struct__AV1FilmGrainMemory
|
|
@c.record
|
|
class struct__AV1TileInfo_OLD(c.Struct):
|
|
SIZE = 16
|
|
width_in_sb: Annotated[Annotated[int, ctypes.c_ubyte], 0]
|
|
height_in_sb: Annotated[Annotated[int, ctypes.c_ubyte], 1]
|
|
tile_start_b0: Annotated[Annotated[int, ctypes.c_ubyte], 2]
|
|
tile_start_b1: Annotated[Annotated[int, ctypes.c_ubyte], 3]
|
|
tile_start_b2: Annotated[Annotated[int, ctypes.c_ubyte], 4]
|
|
tile_start_b3: Annotated[Annotated[int, ctypes.c_ubyte], 5]
|
|
tile_end_b0: Annotated[Annotated[int, ctypes.c_ubyte], 6]
|
|
tile_end_b1: Annotated[Annotated[int, ctypes.c_ubyte], 7]
|
|
tile_end_b2: Annotated[Annotated[int, ctypes.c_ubyte], 8]
|
|
tile_end_b3: Annotated[Annotated[int, ctypes.c_ubyte], 9]
|
|
padding: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[6]], 10]
|
|
AV1TileInfo_OLD: TypeAlias = struct__AV1TileInfo_OLD
|
|
@c.record
|
|
class struct__AV1TileInfo(c.Struct):
|
|
SIZE = 4
|
|
width_in_sb: Annotated[Annotated[int, ctypes.c_ubyte], 0]
|
|
padding_w: Annotated[Annotated[int, ctypes.c_ubyte], 1]
|
|
height_in_sb: Annotated[Annotated[int, ctypes.c_ubyte], 2]
|
|
padding_h: Annotated[Annotated[int, ctypes.c_ubyte], 3]
|
|
AV1TileInfo: TypeAlias = struct__AV1TileInfo
|
|
@c.record
|
|
class struct__AV1TileStreamInfo(c.Struct):
|
|
SIZE = 16
|
|
tile_start: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
|
tile_end: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
|
padding: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[8]], 8]
|
|
AV1TileStreamInfo: TypeAlias = struct__AV1TileStreamInfo
|
|
@c.record
|
|
class struct__nvdec_new_h264_pic_s(c.Struct):
|
|
SIZE = 764
|
|
encryption_params: Annotated[nvdec_pass2_otf_s, 0]
|
|
eos: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[16]], 52]
|
|
explicitEOSPresentFlag: Annotated[Annotated[int, ctypes.c_ubyte], 68]
|
|
hint_dump_en: Annotated[Annotated[int, ctypes.c_ubyte], 69]
|
|
reserved0: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], 70]
|
|
stream_len: Annotated[Annotated[int, ctypes.c_uint32], 72]
|
|
slice_count: Annotated[Annotated[int, ctypes.c_uint32], 76]
|
|
mbhist_buffer_size: Annotated[Annotated[int, ctypes.c_uint32], 80]
|
|
gptimer_timeout_value: Annotated[Annotated[int, ctypes.c_uint32], 84]
|
|
log2_max_pic_order_cnt_lsb_minus4: Annotated[Annotated[int, ctypes.c_int32], 88]
|
|
delta_pic_order_always_zero_flag: Annotated[Annotated[int, ctypes.c_int32], 92]
|
|
frame_mbs_only_flag: Annotated[Annotated[int, ctypes.c_int32], 96]
|
|
PicWidthInMbs: Annotated[Annotated[int, ctypes.c_int32], 100]
|
|
FrameHeightInMbs: Annotated[Annotated[int, ctypes.c_int32], 104]
|
|
tileFormat: Annotated[Annotated[int, ctypes.c_uint32], 108, 2, 0]
|
|
gob_height: Annotated[Annotated[int, ctypes.c_uint32], 108, 3, 2]
|
|
reserverd_surface_format: Annotated[Annotated[int, ctypes.c_uint32], 108, 27, 5]
|
|
entropy_coding_mode_flag: Annotated[Annotated[int, ctypes.c_int32], 112]
|
|
pic_order_present_flag: Annotated[Annotated[int, ctypes.c_int32], 116]
|
|
num_ref_idx_l0_active_minus1: Annotated[Annotated[int, ctypes.c_int32], 120]
|
|
num_ref_idx_l1_active_minus1: Annotated[Annotated[int, ctypes.c_int32], 124]
|
|
deblocking_filter_control_present_flag: Annotated[Annotated[int, ctypes.c_int32], 128]
|
|
redundant_pic_cnt_present_flag: Annotated[Annotated[int, ctypes.c_int32], 132]
|
|
transform_8x8_mode_flag: Annotated[Annotated[int, ctypes.c_int32], 136]
|
|
pitch_luma: Annotated[Annotated[int, ctypes.c_uint32], 140]
|
|
pitch_chroma: Annotated[Annotated[int, ctypes.c_uint32], 144]
|
|
luma_top_offset: Annotated[Annotated[int, ctypes.c_uint32], 148]
|
|
luma_bot_offset: Annotated[Annotated[int, ctypes.c_uint32], 152]
|
|
luma_frame_offset: Annotated[Annotated[int, ctypes.c_uint32], 156]
|
|
chroma_top_offset: Annotated[Annotated[int, ctypes.c_uint32], 160]
|
|
chroma_bot_offset: Annotated[Annotated[int, ctypes.c_uint32], 164]
|
|
chroma_frame_offset: Annotated[Annotated[int, ctypes.c_uint32], 168]
|
|
HistBufferSize: Annotated[Annotated[int, ctypes.c_uint32], 172]
|
|
MbaffFrameFlag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 0]
|
|
direct_8x8_inference_flag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 1]
|
|
weighted_pred_flag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 2]
|
|
constrained_intra_pred_flag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 3]
|
|
ref_pic_flag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 4]
|
|
field_pic_flag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 5]
|
|
bottom_field_flag: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 6]
|
|
second_field: Annotated[Annotated[int, ctypes.c_uint32], 176, 1, 7]
|
|
log2_max_frame_num_minus4: Annotated[Annotated[int, ctypes.c_uint32], 177, 4, 0]
|
|
chroma_format_idc: Annotated[Annotated[int, ctypes.c_uint32], 177, 2, 4]
|
|
pic_order_cnt_type: Annotated[Annotated[int, ctypes.c_uint32], 177, 2, 6]
|
|
pic_init_qp_minus26: Annotated[Annotated[int, ctypes.c_int32], 178, 6, 0]
|
|
chroma_qp_index_offset: Annotated[Annotated[int, ctypes.c_int32], 178, 5, 6]
|
|
second_chroma_qp_index_offset: Annotated[Annotated[int, ctypes.c_int32], 179, 5, 3]
|
|
weighted_bipred_idc: Annotated[Annotated[int, ctypes.c_uint32], 180, 2, 0]
|
|
CurrPicIdx: Annotated[Annotated[int, ctypes.c_uint32], 180, 7, 2]
|
|
CurrColIdx: Annotated[Annotated[int, ctypes.c_uint32], 181, 5, 1]
|
|
frame_num: Annotated[Annotated[int, ctypes.c_uint32], 181, 16, 6]
|
|
frame_surfaces: Annotated[Annotated[int, ctypes.c_uint32], 183, 1, 6]
|
|
output_memory_layout: Annotated[Annotated[int, ctypes.c_uint32], 183, 1, 7]
|
|
CurrFieldOrderCnt: Annotated[c.Array[Annotated[int, ctypes.c_int32], Literal[2]], 184]
|
|
dpb: Annotated[c.Array[nvdec_dpb_entry_s, Literal[16]], 192]
|
|
WeightScale: Annotated[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[4]], Literal[4]], Literal[6]], 448]
|
|
WeightScale8x8: Annotated[c.Array[c.Array[c.Array[Annotated[int, ctypes.c_ubyte], Literal[8]], Literal[8]], Literal[2]], 544]
|
|
num_inter_view_refs_lX: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], 672]
|
|
reserved1: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[14]], 674]
|
|
inter_view_refidx_lX: Annotated[c.Array[c.Array[Annotated[int, ctypes.c_byte], Literal[16]], Literal[2]], 688]
|
|
lossless_ipred8x8_filter_enable: Annotated[Annotated[int, ctypes.c_uint32], 720, 1, 0]
|
|
qpprime_y_zero_transform_bypass_flag: Annotated[Annotated[int, ctypes.c_uint32], 720, 1, 1]
|
|
reserved2: Annotated[Annotated[int, ctypes.c_uint32], 720, 30, 2]
|
|
displayPara: Annotated[nvdec_display_param_s, 724]
|
|
ssm: Annotated[nvdec_pass2_otf_ext_s, 752]
|
|
nvdec_new_h264_pic_s: TypeAlias = struct__nvdec_new_h264_pic_s
|
|
@c.record
|
|
class nvdec_crc_s(c.Struct):
|
|
SIZE = 128
|
|
dbg_crc_enable_partb: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 0]
|
|
dbg_crc_enable_partc: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 1]
|
|
dbg_crc_enable_partd: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 2]
|
|
dbg_crc_enable_parte: Annotated[Annotated[int, ctypes.c_uint32], 0, 1, 3]
|
|
dbg_crc_intf_partb: Annotated[Annotated[int, ctypes.c_uint32], 0, 6, 4]
|
|
dbg_crc_intf_partc: Annotated[Annotated[int, ctypes.c_uint32], 1, 6, 2]
|
|
dbg_crc_intf_partd: Annotated[Annotated[int, ctypes.c_uint32], 2, 6, 0]
|
|
dbg_crc_intf_parte: Annotated[Annotated[int, ctypes.c_uint32], 2, 6, 6]
|
|
reserved0: Annotated[Annotated[int, ctypes.c_uint32], 3, 4, 4]
|
|
dbg_crc_partb_golden: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 4]
|
|
dbg_crc_partc_golden: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 20]
|
|
dbg_crc_partd_golden: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 36]
|
|
dbg_crc_parte_golden: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[4]], 52]
|
|
dbg_crc_comp_partb: Annotated[Annotated[int, ctypes.c_uint32], 68, 4, 0]
|
|
dbg_crc_comp_partc: Annotated[Annotated[int, ctypes.c_uint32], 68, 4, 4]
|
|
dbg_crc_comp_partd: Annotated[Annotated[int, ctypes.c_uint32], 69, 4, 0]
|
|
dbg_crc_comp_parte: Annotated[Annotated[int, ctypes.c_uint32], 69, 4, 4]
|
|
reserved1: Annotated[Annotated[int, ctypes.c_uint32], 70, 16, 0]
|
|
reserved2: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[56]], 72]
|
|
@c.record
|
|
class struct_NV0000_ALLOC_PARAMETERS(c.Struct):
|
|
SIZE = 120
|
|
hClient: Annotated[NvHandle, 0]
|
|
processID: Annotated[NvU32, 4]
|
|
processName: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[100]], 8]
|
|
pOsPidInfo: Annotated[NvP64, 112]
|
|
NvHandle: TypeAlias = Annotated[int, ctypes.c_uint32]
|
|
NvU32: TypeAlias = Annotated[int, ctypes.c_uint32]
|
|
NvP64: TypeAlias = ctypes.c_void_p
|
|
NV0000_ALLOC_PARAMETERS: TypeAlias = struct_NV0000_ALLOC_PARAMETERS
|
|
@c.record
|
|
class struct_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
offset: Annotated[NvU64, 0]
|
|
limit: Annotated[NvU64, 8]
|
|
hVASpace: Annotated[NvHandle, 16]
|
|
NvU64: TypeAlias = Annotated[int, ctypes.c_uint64]
|
|
NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS: TypeAlias = struct_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS
|
|
@c.record
|
|
class struct_NV0080_ALLOC_PARAMETERS(c.Struct):
|
|
SIZE = 56
|
|
deviceId: Annotated[NvU32, 0]
|
|
hClientShare: Annotated[NvHandle, 4]
|
|
hTargetClient: Annotated[NvHandle, 8]
|
|
hTargetDevice: Annotated[NvHandle, 12]
|
|
flags: Annotated[NvV32, 16]
|
|
vaSpaceSize: Annotated[NvU64, 24]
|
|
vaStartInternal: Annotated[NvU64, 32]
|
|
vaLimitInternal: Annotated[NvU64, 40]
|
|
vaMode: Annotated[NvV32, 48]
|
|
NvV32: TypeAlias = Annotated[int, ctypes.c_uint32]
|
|
NV0080_ALLOC_PARAMETERS: TypeAlias = struct_NV0080_ALLOC_PARAMETERS
|
|
@c.record
|
|
class struct_NV2080_ALLOC_PARAMETERS(c.Struct):
|
|
SIZE = 4
|
|
subDeviceId: Annotated[NvU32, 0]
|
|
NV2080_ALLOC_PARAMETERS: TypeAlias = struct_NV2080_ALLOC_PARAMETERS
|
|
@c.record
|
|
class struct__cl2080_tag0(c.Struct):
|
|
SIZE = 7936
|
|
Reserved00: Annotated[c.Array[NvV32, Literal[1984]], 0]
|
|
@c.record
|
|
class volatile_struct__cl2080_tag0(c.Struct):
|
|
SIZE = 7936
|
|
Reserved00: Annotated[c.Array[NvV32, Literal[1984]], 0]
|
|
Nv2080Typedef: TypeAlias = volatile_struct__cl2080_tag0
|
|
Nv20Subdevice0: TypeAlias = volatile_struct__cl2080_tag0
|
|
@c.record
|
|
class struct_Nv2080HdcpStatusChangeNotificationRec(c.Struct):
|
|
SIZE = 8
|
|
displayId: Annotated[NvU32, 0]
|
|
hdcpStatusChangeNotif: Annotated[NvU32, 4]
|
|
Nv2080HdcpStatusChangeNotification: TypeAlias = struct_Nv2080HdcpStatusChangeNotificationRec
|
|
@c.record
|
|
class struct_Nv2080PStateChangeNotificationRec(c.Struct):
|
|
SIZE = 12
|
|
timeStamp: Annotated[struct_Nv2080PStateChangeNotificationRec_timeStamp, 0]
|
|
NewPstate: Annotated[NvU32, 8]
|
|
@c.record
|
|
class struct_Nv2080PStateChangeNotificationRec_timeStamp(c.Struct):
|
|
SIZE = 8
|
|
nanoseconds: Annotated[c.Array[NvU32, Literal[2]], 0]
|
|
Nv2080PStateChangeNotification: TypeAlias = struct_Nv2080PStateChangeNotificationRec
|
|
@c.record
|
|
class struct_Nv2080ClocksChangeNotificationRec(c.Struct):
|
|
SIZE = 8
|
|
timeStamp: Annotated[struct_Nv2080ClocksChangeNotificationRec_timeStamp, 0]
|
|
@c.record
|
|
class struct_Nv2080ClocksChangeNotificationRec_timeStamp(c.Struct):
|
|
SIZE = 8
|
|
nanoseconds: Annotated[c.Array[NvU32, Literal[2]], 0]
|
|
Nv2080ClocksChangeNotification: TypeAlias = struct_Nv2080ClocksChangeNotificationRec
|
|
@c.record
|
|
class struct_Nv2080WorkloadModulationChangeNotificationRec(c.Struct):
|
|
SIZE = 12
|
|
timeStamp: Annotated[struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp, 0]
|
|
WorkloadModulationEnabled: Annotated[NvBool, 8]
|
|
@c.record
|
|
class struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp(c.Struct):
|
|
SIZE = 8
|
|
nanoseconds: Annotated[c.Array[NvU32, Literal[2]], 0]
|
|
NvBool: TypeAlias = Annotated[int, ctypes.c_ubyte]
|
|
Nv2080WorkloadModulationChangeNotification: TypeAlias = struct_Nv2080WorkloadModulationChangeNotificationRec
|
|
@c.record
|
|
class Nv2080HotplugNotification(c.Struct):
|
|
SIZE = 8
|
|
plugDisplayMask: Annotated[NvU32, 0]
|
|
unplugDisplayMask: Annotated[NvU32, 4]
|
|
@c.record
|
|
class Nv2080PowerEventNotification(c.Struct):
|
|
SIZE = 8
|
|
bSwitchToAC: Annotated[NvBool, 0]
|
|
bGPUCapabilityChanged: Annotated[NvBool, 1]
|
|
displayMaskAffected: Annotated[NvU32, 4]
|
|
@c.record
|
|
class struct_Nv2080DpIrqNotificationRec(c.Struct):
|
|
SIZE = 4
|
|
displayId: Annotated[NvU32, 0]
|
|
Nv2080DpIrqNotification: TypeAlias = struct_Nv2080DpIrqNotificationRec
|
|
@c.record
|
|
class struct_Nv2080DstateXusbPpcNotificationRec(c.Struct):
|
|
SIZE = 8
|
|
dstateXusb: Annotated[NvU32, 0]
|
|
dstatePpc: Annotated[NvU32, 4]
|
|
Nv2080DstateXusbPpcNotification: TypeAlias = struct_Nv2080DstateXusbPpcNotificationRec
|
|
@c.record
|
|
class struct_Nv2080XusbPpcConnectStateNotificationRec(c.Struct):
|
|
SIZE = 1
|
|
bConnected: Annotated[NvBool, 0]
|
|
Nv2080XusbPpcConnectStateNotification: TypeAlias = struct_Nv2080XusbPpcConnectStateNotificationRec
|
|
@c.record
|
|
class struct_Nv2080ACPIEvent(c.Struct):
|
|
SIZE = 4
|
|
event: Annotated[NvU32, 0]
|
|
Nv2080ACPIEvent: TypeAlias = struct_Nv2080ACPIEvent
|
|
@c.record
|
|
class struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC(c.Struct):
|
|
SIZE = 4
|
|
currentZone: Annotated[NvU32, 0]
|
|
NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC: TypeAlias = struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC
|
|
@c.record
|
|
class struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC(c.Struct):
|
|
SIZE = 4
|
|
currentZone: Annotated[NvU32, 0]
|
|
NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC: TypeAlias = struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC
|
|
@c.record
|
|
class struct_Nv2080AudioHdcpRequestRec(c.Struct):
|
|
SIZE = 8
|
|
displayId: Annotated[NvU32, 0]
|
|
requestedState: Annotated[NvU32, 4]
|
|
Nv2080AudioHdcpRequest: TypeAlias = struct_Nv2080AudioHdcpRequestRec
|
|
@c.record
|
|
class struct_Nv2080GC5GpuReadyParams(c.Struct):
|
|
SIZE = 12
|
|
event: Annotated[NvU32, 0]
|
|
sciIntr0: Annotated[NvU32, 4]
|
|
sciIntr1: Annotated[NvU32, 8]
|
|
Nv2080GC5GpuReadyParams: TypeAlias = struct_Nv2080GC5GpuReadyParams
|
|
@c.record
|
|
class Nv2080PrivRegAccessFaultNotification(c.Struct):
|
|
SIZE = 4
|
|
errAddr: Annotated[NvU32, 0]
|
|
@c.record
|
|
class struct_Nv2080DstateHdaCodecNotificationRec(c.Struct):
|
|
SIZE = 4
|
|
dstateHdaCodec: Annotated[NvU32, 0]
|
|
Nv2080DstateHdaCodecNotification: TypeAlias = struct_Nv2080DstateHdaCodecNotificationRec
|
|
@c.record
|
|
class struct_Nv2080HdmiFrlRequestNotificationRec(c.Struct):
|
|
SIZE = 4
|
|
displayId: Annotated[NvU32, 0]
|
|
Nv2080HdmiFrlRequestNotification: TypeAlias = struct_Nv2080HdmiFrlRequestNotificationRec
|
|
@c.record
|
|
class struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS(c.Struct):
|
|
SIZE = 3
|
|
platformPowerModeIndex: Annotated[NvU8, 0]
|
|
platformPowerModeMask: Annotated[NvU8, 1]
|
|
eventReason: Annotated[NvU8, 2]
|
|
NvU8: TypeAlias = Annotated[int, ctypes.c_ubyte]
|
|
NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS: TypeAlias = struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS
|
|
@c.record
|
|
class struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE(c.Struct):
|
|
SIZE = 1
|
|
workloadType: Annotated[NvU8, 0]
|
|
NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE: TypeAlias = struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE
|
|
@c.record
|
|
class Nv2080QosIntrNotification(c.Struct):
|
|
SIZE = 4
|
|
engineType: Annotated[NvU32, 0]
|
|
@c.record
|
|
class Nv2080EccDbeNotification(c.Struct):
|
|
SIZE = 8
|
|
physAddress: Annotated[NvU64, 0]
|
|
@c.record
|
|
class Nv2080LpwrDifrPrefetchNotification(c.Struct):
|
|
SIZE = 4
|
|
l2CacheSize: Annotated[NvU32, 0]
|
|
@c.record
|
|
class Nv2080NvlinkLnkChangeNotification(c.Struct):
|
|
SIZE = 8
|
|
GpuId: Annotated[NvU32, 0]
|
|
linkId: Annotated[NvU32, 4]
|
|
@c.record
|
|
class Nv2080VrrSetTimeoutNotification(c.Struct):
|
|
SIZE = 4
|
|
head: Annotated[NvU32, 0]
|
|
@c.record
|
|
class struct_Nvc56fControl_struct(c.Struct):
|
|
SIZE = 512
|
|
Ignored00: Annotated[c.Array[NvU32, Literal[16]], 0]
|
|
Put: Annotated[NvU32, 64]
|
|
Get: Annotated[NvU32, 68]
|
|
Reference: Annotated[NvU32, 72]
|
|
PutHi: Annotated[NvU32, 76]
|
|
Ignored01: Annotated[c.Array[NvU32, Literal[2]], 80]
|
|
TopLevelGet: Annotated[NvU32, 88]
|
|
TopLevelGetHi: Annotated[NvU32, 92]
|
|
GetHi: Annotated[NvU32, 96]
|
|
Ignored02: Annotated[c.Array[NvU32, Literal[7]], 100]
|
|
Ignored03: Annotated[NvU32, 128]
|
|
Ignored04: Annotated[c.Array[NvU32, Literal[1]], 132]
|
|
GPGet: Annotated[NvU32, 136]
|
|
GPPut: Annotated[NvU32, 140]
|
|
Ignored05: Annotated[c.Array[NvU32, Literal[92]], 144]
|
|
@c.record
|
|
class volatile_struct_Nvc56fControl_struct(c.Struct):
|
|
SIZE = 512
|
|
Ignored00: Annotated[c.Array[NvU32, Literal[16]], 0]
|
|
Put: Annotated[NvU32, 64]
|
|
Get: Annotated[NvU32, 68]
|
|
Reference: Annotated[NvU32, 72]
|
|
PutHi: Annotated[NvU32, 76]
|
|
Ignored01: Annotated[c.Array[NvU32, Literal[2]], 80]
|
|
TopLevelGet: Annotated[NvU32, 88]
|
|
TopLevelGetHi: Annotated[NvU32, 92]
|
|
GetHi: Annotated[NvU32, 96]
|
|
Ignored02: Annotated[c.Array[NvU32, Literal[7]], 100]
|
|
Ignored03: Annotated[NvU32, 128]
|
|
Ignored04: Annotated[c.Array[NvU32, Literal[1]], 132]
|
|
GPGet: Annotated[NvU32, 136]
|
|
GPPut: Annotated[NvU32, 140]
|
|
Ignored05: Annotated[c.Array[NvU32, Literal[92]], 144]
|
|
Nvc56fControl: TypeAlias = volatile_struct_Nvc56fControl_struct
|
|
AmpereAControlGPFifo: TypeAlias = volatile_struct_Nvc56fControl_struct
|
|
@c.record
|
|
class struct_Nvc86fControl_struct(c.Struct):
|
|
SIZE = 512
|
|
Ignored00: Annotated[c.Array[NvU32, Literal[16]], 0]
|
|
Put: Annotated[NvU32, 64]
|
|
Get: Annotated[NvU32, 68]
|
|
Reference: Annotated[NvU32, 72]
|
|
PutHi: Annotated[NvU32, 76]
|
|
Ignored01: Annotated[c.Array[NvU32, Literal[2]], 80]
|
|
TopLevelGet: Annotated[NvU32, 88]
|
|
TopLevelGetHi: Annotated[NvU32, 92]
|
|
GetHi: Annotated[NvU32, 96]
|
|
Ignored02: Annotated[c.Array[NvU32, Literal[7]], 100]
|
|
Ignored03: Annotated[NvU32, 128]
|
|
Ignored04: Annotated[c.Array[NvU32, Literal[1]], 132]
|
|
GPGet: Annotated[NvU32, 136]
|
|
GPPut: Annotated[NvU32, 140]
|
|
Ignored05: Annotated[c.Array[NvU32, Literal[92]], 144]
|
|
@c.record
|
|
class volatile_struct_Nvc86fControl_struct(c.Struct):
|
|
SIZE = 512
|
|
Ignored00: Annotated[c.Array[NvU32, Literal[16]], 0]
|
|
Put: Annotated[NvU32, 64]
|
|
Get: Annotated[NvU32, 68]
|
|
Reference: Annotated[NvU32, 72]
|
|
PutHi: Annotated[NvU32, 76]
|
|
Ignored01: Annotated[c.Array[NvU32, Literal[2]], 80]
|
|
TopLevelGet: Annotated[NvU32, 88]
|
|
TopLevelGetHi: Annotated[NvU32, 92]
|
|
GetHi: Annotated[NvU32, 96]
|
|
Ignored02: Annotated[c.Array[NvU32, Literal[7]], 100]
|
|
Ignored03: Annotated[NvU32, 128]
|
|
Ignored04: Annotated[c.Array[NvU32, Literal[1]], 132]
|
|
GPGet: Annotated[NvU32, 136]
|
|
GPPut: Annotated[NvU32, 140]
|
|
Ignored05: Annotated[c.Array[NvU32, Literal[92]], 144]
|
|
Nvc86fControl: TypeAlias = volatile_struct_Nvc86fControl_struct
|
|
HopperAControlGPFifo: TypeAlias = volatile_struct_Nvc86fControl_struct
|
|
@c.record
|
|
class struct_Nvc96fControl_struct(c.Struct):
|
|
SIZE = 512
|
|
Ignored00: Annotated[c.Array[NvU32, Literal[35]], 0]
|
|
GPPut: Annotated[NvU32, 140]
|
|
Ignored01: Annotated[c.Array[NvU32, Literal[92]], 144]
|
|
@c.record
|
|
class volatile_struct_Nvc96fControl_struct(c.Struct):
|
|
SIZE = 512
|
|
Ignored00: Annotated[c.Array[NvU32, Literal[35]], 0]
|
|
GPPut: Annotated[NvU32, 140]
|
|
Ignored01: Annotated[c.Array[NvU32, Literal[92]], 144]
|
|
Nvc96fControl: TypeAlias = volatile_struct_Nvc96fControl_struct
|
|
BlackwellAControlGPFifo: TypeAlias = volatile_struct_Nvc96fControl_struct
|
|
@c.record
|
|
class struct_NV83DE_ALLOC_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
hDebuggerClient_Obsolete: Annotated[NvHandle, 0]
|
|
hAppClient: Annotated[NvHandle, 4]
|
|
hClass3dObject: Annotated[NvHandle, 8]
|
|
NV83DE_ALLOC_PARAMETERS: TypeAlias = struct_NV83DE_ALLOC_PARAMETERS
|
|
@c.record
|
|
class struct_NVB2CC_ALLOC_PARAMETERS(c.Struct):
|
|
SIZE = 8
|
|
hClientTarget: Annotated[NvHandle, 0]
|
|
hContextTarget: Annotated[NvHandle, 4]
|
|
NVB2CC_ALLOC_PARAMETERS: TypeAlias = struct_NVB2CC_ALLOC_PARAMETERS
|
|
@c.record
|
|
class struct__clc9b5_tag0(c.Struct):
|
|
SIZE = 8192
|
|
Reserved00: Annotated[c.Array[NvV32, Literal[64]], 0]
|
|
Nop: Annotated[NvV32, 256]
|
|
Reserved01: Annotated[c.Array[NvV32, Literal[15]], 260]
|
|
PmTrigger: Annotated[NvV32, 320]
|
|
Reserved02: Annotated[c.Array[NvV32, Literal[54]], 324]
|
|
SetMonitoredFenceType: Annotated[NvV32, 540]
|
|
SetMonitoredFenceSignalAddrBaseUpper: Annotated[NvV32, 544]
|
|
SetMonitoredFenceSignalAddrBaseLower: Annotated[NvV32, 548]
|
|
Reserved03: Annotated[c.Array[NvV32, Literal[6]], 552]
|
|
SetSemaphoreA: Annotated[NvV32, 576]
|
|
SetSemaphoreB: Annotated[NvV32, 580]
|
|
SetSemaphorePayload: Annotated[NvV32, 584]
|
|
SetSemaphorePayloadUpper: Annotated[NvV32, 588]
|
|
Reserved04: Annotated[c.Array[NvV32, Literal[1]], 592]
|
|
SetRenderEnableA: Annotated[NvV32, 596]
|
|
SetRenderEnableB: Annotated[NvV32, 600]
|
|
SetRenderEnableC: Annotated[NvV32, 604]
|
|
SetSrcPhysMode: Annotated[NvV32, 608]
|
|
SetDstPhysMode: Annotated[NvV32, 612]
|
|
Reserved05: Annotated[c.Array[NvV32, Literal[38]], 616]
|
|
LaunchDma: Annotated[NvV32, 768]
|
|
Reserved06: Annotated[c.Array[NvV32, Literal[63]], 772]
|
|
OffsetInUpper: Annotated[NvV32, 1024]
|
|
OffsetInLower: Annotated[NvV32, 1028]
|
|
OffsetOutUpper: Annotated[NvV32, 1032]
|
|
OffsetOutLower: Annotated[NvV32, 1036]
|
|
PitchIn: Annotated[NvV32, 1040]
|
|
PitchOut: Annotated[NvV32, 1044]
|
|
LineLengthIn: Annotated[NvV32, 1048]
|
|
LineCount: Annotated[NvV32, 1052]
|
|
Reserved07: Annotated[c.Array[NvV32, Literal[56]], 1056]
|
|
SetSecureCopyMode: Annotated[NvV32, 1280]
|
|
SetDecryptIv0: Annotated[NvV32, 1284]
|
|
SetDecryptIv1: Annotated[NvV32, 1288]
|
|
SetDecryptIv2: Annotated[NvV32, 1292]
|
|
Reserved_SetAESCounter: Annotated[NvV32, 1296]
|
|
SetDecryptAuthTagCompareAddrUpper: Annotated[NvV32, 1300]
|
|
SetDecryptAuthTagCompareAddrLower: Annotated[NvV32, 1304]
|
|
Reserved08: Annotated[c.Array[NvV32, Literal[5]], 1308]
|
|
SetEncryptAuthTagAddrUpper: Annotated[NvV32, 1328]
|
|
SetEncryptAuthTagAddrLower: Annotated[NvV32, 1332]
|
|
SetEncryptIvAddrUpper: Annotated[NvV32, 1336]
|
|
SetEncryptIvAddrLower: Annotated[NvV32, 1340]
|
|
Reserved09: Annotated[c.Array[NvV32, Literal[16]], 1344]
|
|
SetCompressionParameters: Annotated[NvV32, 1408]
|
|
SetDecompressOutLength: Annotated[NvV32, 1412]
|
|
SetDecompressOutLengthAddrUpper: Annotated[NvV32, 1416]
|
|
SetDecompressOutLengthAddrLower: Annotated[NvV32, 1420]
|
|
SetDecompressChecksum: Annotated[NvV32, 1424]
|
|
Reserved10: Annotated[c.Array[NvV32, Literal[90]], 1428]
|
|
SetMemoryScrubParameters: Annotated[NvV32, 1788]
|
|
SetRemapConstA: Annotated[NvV32, 1792]
|
|
SetRemapConstB: Annotated[NvV32, 1796]
|
|
SetRemapComponents: Annotated[NvV32, 1800]
|
|
SetDstBlockSize: Annotated[NvV32, 1804]
|
|
SetDstWidth: Annotated[NvV32, 1808]
|
|
SetDstHeight: Annotated[NvV32, 1812]
|
|
SetDstDepth: Annotated[NvV32, 1816]
|
|
SetDstLayer: Annotated[NvV32, 1820]
|
|
SetDstOrigin: Annotated[NvV32, 1824]
|
|
Reserved11: Annotated[c.Array[NvV32, Literal[1]], 1828]
|
|
SetSrcBlockSize: Annotated[NvV32, 1832]
|
|
SetSrcWidth: Annotated[NvV32, 1836]
|
|
SetSrcHeight: Annotated[NvV32, 1840]
|
|
SetSrcDepth: Annotated[NvV32, 1844]
|
|
SetSrcLayer: Annotated[NvV32, 1848]
|
|
SetSrcOrigin: Annotated[NvV32, 1852]
|
|
Reserved12: Annotated[c.Array[NvV32, Literal[1]], 1856]
|
|
SrcOriginX: Annotated[NvV32, 1860]
|
|
SrcOriginY: Annotated[NvV32, 1864]
|
|
DstOriginX: Annotated[NvV32, 1868]
|
|
DstOriginY: Annotated[NvV32, 1872]
|
|
Reserved13: Annotated[c.Array[NvV32, Literal[624]], 1876]
|
|
PmTriggerEnd: Annotated[NvV32, 4372]
|
|
Reserved14: Annotated[c.Array[NvV32, Literal[954]], 4376]
|
|
@c.record
|
|
class volatile_struct__clc9b5_tag0(c.Struct):
|
|
SIZE = 8192
|
|
Reserved00: Annotated[c.Array[NvV32, Literal[64]], 0]
|
|
Nop: Annotated[NvV32, 256]
|
|
Reserved01: Annotated[c.Array[NvV32, Literal[15]], 260]
|
|
PmTrigger: Annotated[NvV32, 320]
|
|
Reserved02: Annotated[c.Array[NvV32, Literal[54]], 324]
|
|
SetMonitoredFenceType: Annotated[NvV32, 540]
|
|
SetMonitoredFenceSignalAddrBaseUpper: Annotated[NvV32, 544]
|
|
SetMonitoredFenceSignalAddrBaseLower: Annotated[NvV32, 548]
|
|
Reserved03: Annotated[c.Array[NvV32, Literal[6]], 552]
|
|
SetSemaphoreA: Annotated[NvV32, 576]
|
|
SetSemaphoreB: Annotated[NvV32, 580]
|
|
SetSemaphorePayload: Annotated[NvV32, 584]
|
|
SetSemaphorePayloadUpper: Annotated[NvV32, 588]
|
|
Reserved04: Annotated[c.Array[NvV32, Literal[1]], 592]
|
|
SetRenderEnableA: Annotated[NvV32, 596]
|
|
SetRenderEnableB: Annotated[NvV32, 600]
|
|
SetRenderEnableC: Annotated[NvV32, 604]
|
|
SetSrcPhysMode: Annotated[NvV32, 608]
|
|
SetDstPhysMode: Annotated[NvV32, 612]
|
|
Reserved05: Annotated[c.Array[NvV32, Literal[38]], 616]
|
|
LaunchDma: Annotated[NvV32, 768]
|
|
Reserved06: Annotated[c.Array[NvV32, Literal[63]], 772]
|
|
OffsetInUpper: Annotated[NvV32, 1024]
|
|
OffsetInLower: Annotated[NvV32, 1028]
|
|
OffsetOutUpper: Annotated[NvV32, 1032]
|
|
OffsetOutLower: Annotated[NvV32, 1036]
|
|
PitchIn: Annotated[NvV32, 1040]
|
|
PitchOut: Annotated[NvV32, 1044]
|
|
LineLengthIn: Annotated[NvV32, 1048]
|
|
LineCount: Annotated[NvV32, 1052]
|
|
Reserved07: Annotated[c.Array[NvV32, Literal[56]], 1056]
|
|
SetSecureCopyMode: Annotated[NvV32, 1280]
|
|
SetDecryptIv0: Annotated[NvV32, 1284]
|
|
SetDecryptIv1: Annotated[NvV32, 1288]
|
|
SetDecryptIv2: Annotated[NvV32, 1292]
|
|
Reserved_SetAESCounter: Annotated[NvV32, 1296]
|
|
SetDecryptAuthTagCompareAddrUpper: Annotated[NvV32, 1300]
|
|
SetDecryptAuthTagCompareAddrLower: Annotated[NvV32, 1304]
|
|
Reserved08: Annotated[c.Array[NvV32, Literal[5]], 1308]
|
|
SetEncryptAuthTagAddrUpper: Annotated[NvV32, 1328]
|
|
SetEncryptAuthTagAddrLower: Annotated[NvV32, 1332]
|
|
SetEncryptIvAddrUpper: Annotated[NvV32, 1336]
|
|
SetEncryptIvAddrLower: Annotated[NvV32, 1340]
|
|
Reserved09: Annotated[c.Array[NvV32, Literal[16]], 1344]
|
|
SetCompressionParameters: Annotated[NvV32, 1408]
|
|
SetDecompressOutLength: Annotated[NvV32, 1412]
|
|
SetDecompressOutLengthAddrUpper: Annotated[NvV32, 1416]
|
|
SetDecompressOutLengthAddrLower: Annotated[NvV32, 1420]
|
|
SetDecompressChecksum: Annotated[NvV32, 1424]
|
|
Reserved10: Annotated[c.Array[NvV32, Literal[90]], 1428]
|
|
SetMemoryScrubParameters: Annotated[NvV32, 1788]
|
|
SetRemapConstA: Annotated[NvV32, 1792]
|
|
SetRemapConstB: Annotated[NvV32, 1796]
|
|
SetRemapComponents: Annotated[NvV32, 1800]
|
|
SetDstBlockSize: Annotated[NvV32, 1804]
|
|
SetDstWidth: Annotated[NvV32, 1808]
|
|
SetDstHeight: Annotated[NvV32, 1812]
|
|
SetDstDepth: Annotated[NvV32, 1816]
|
|
SetDstLayer: Annotated[NvV32, 1820]
|
|
SetDstOrigin: Annotated[NvV32, 1824]
|
|
Reserved11: Annotated[c.Array[NvV32, Literal[1]], 1828]
|
|
SetSrcBlockSize: Annotated[NvV32, 1832]
|
|
SetSrcWidth: Annotated[NvV32, 1836]
|
|
SetSrcHeight: Annotated[NvV32, 1840]
|
|
SetSrcDepth: Annotated[NvV32, 1844]
|
|
SetSrcLayer: Annotated[NvV32, 1848]
|
|
SetSrcOrigin: Annotated[NvV32, 1852]
|
|
Reserved12: Annotated[c.Array[NvV32, Literal[1]], 1856]
|
|
SrcOriginX: Annotated[NvV32, 1860]
|
|
SrcOriginY: Annotated[NvV32, 1864]
|
|
DstOriginX: Annotated[NvV32, 1868]
|
|
DstOriginY: Annotated[NvV32, 1872]
|
|
Reserved13: Annotated[c.Array[NvV32, Literal[624]], 1876]
|
|
PmTriggerEnd: Annotated[NvV32, 4372]
|
|
Reserved14: Annotated[c.Array[NvV32, Literal[954]], 4376]
|
|
blackwell_dma_copy_aControlPio: TypeAlias = volatile_struct__clc9b5_tag0
|
|
@c.record
|
|
class UVM_RESERVE_VA_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
requestedBase: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
NV_STATUS: TypeAlias = Annotated[int, ctypes.c_uint32]
|
|
@c.record
|
|
class UVM_RELEASE_VA_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
requestedBase: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_REGION_COMMIT_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
requestedBase: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
streamId: Annotated[UvmStream, 16]
|
|
gpuUuid: Annotated[NvProcessorUuid, 24]
|
|
rmStatus: Annotated[NV_STATUS, 40]
|
|
UvmStream: TypeAlias = Annotated[int, ctypes.c_uint64]
|
|
@c.record
|
|
class struct_nv_uuid(c.Struct):
|
|
SIZE = 16
|
|
uuid: Annotated[c.Array[NvU8, Literal[16]], 0]
|
|
NvProcessorUuid: TypeAlias = struct_nv_uuid
|
|
@c.record
|
|
class UVM_REGION_DECOMMIT_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
requestedBase: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_REGION_SET_STREAM_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
requestedBase: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
newStreamId: Annotated[UvmStream, 16]
|
|
gpuUuid: Annotated[NvProcessorUuid, 24]
|
|
rmStatus: Annotated[NV_STATUS, 40]
|
|
@c.record
|
|
class UVM_SET_STREAM_RUNNING_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
streamId: Annotated[UvmStream, 0]
|
|
rmStatus: Annotated[NV_STATUS, 8]
|
|
@c.record
|
|
class UVM_SET_STREAM_STOPPED_PARAMS(c.Struct):
|
|
SIZE = 272
|
|
streamIdArray: Annotated[c.Array[UvmStream, Literal[32]], 0]
|
|
nStreams: Annotated[NvU64, 256]
|
|
rmStatus: Annotated[NV_STATUS, 264]
|
|
@c.record
|
|
class UVM_RUN_TEST_PARAMS(c.Struct):
|
|
SIZE = 44
|
|
gpuUuid: Annotated[NvProcessorUuid, 0]
|
|
test: Annotated[NvU32, 16]
|
|
multiGpu: Annotated[UVM_RUN_TEST_PARAMS_multiGpu, 20]
|
|
rmStatus: Annotated[NV_STATUS, 40]
|
|
@c.record
|
|
class UVM_RUN_TEST_PARAMS_multiGpu(c.Struct):
|
|
SIZE = 20
|
|
peerGpuUuid: Annotated[NvProcessorUuid, 0]
|
|
peerId: Annotated[NvU32, 16]
|
|
@c.record
|
|
class UVM_ADD_SESSION_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
pidTarget: Annotated[NvU32, 0]
|
|
countersBaseAddress: Annotated[NvP64, 8]
|
|
sessionIndex: Annotated[NvS32, 16]
|
|
rmStatus: Annotated[NV_STATUS, 20]
|
|
NvS32: TypeAlias = Annotated[int, ctypes.c_int32]
|
|
@c.record
|
|
class UVM_REMOVE_SESSION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
sessionIndex: Annotated[NvS32, 0]
|
|
rmStatus: Annotated[NV_STATUS, 4]
|
|
@c.record
|
|
class UVM_ENABLE_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 908
|
|
sessionIndex: Annotated[NvS32, 0]
|
|
config: Annotated[c.Array[UvmCounterConfig, Literal[32]], 4]
|
|
count: Annotated[NvU32, 900]
|
|
rmStatus: Annotated[NV_STATUS, 904]
|
|
@c.record
|
|
class UvmCounterConfig(c.Struct):
|
|
SIZE = 28
|
|
scope: Annotated[NvU32, 0]
|
|
name: Annotated[NvU32, 4]
|
|
gpuid: Annotated[NvProcessorUuid, 8]
|
|
state: Annotated[NvU32, 24]
|
|
@c.record
|
|
class UVM_MAP_COUNTER_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
sessionIndex: Annotated[NvS32, 0]
|
|
scope: Annotated[NvU32, 4]
|
|
counterName: Annotated[NvU32, 8]
|
|
gpuUuid: Annotated[NvProcessorUuid, 12]
|
|
addr: Annotated[NvP64, 32]
|
|
rmStatus: Annotated[NV_STATUS, 40]
|
|
@c.record
|
|
class UVM_CREATE_EVENT_QUEUE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
sessionIndex: Annotated[NvS32, 0]
|
|
eventQueueIndex: Annotated[NvU32, 4]
|
|
queueSize: Annotated[NvU64, 8]
|
|
notificationCount: Annotated[NvU64, 16]
|
|
timeStampType: Annotated[NvU32, 24]
|
|
rmStatus: Annotated[NV_STATUS, 28]
|
|
@c.record
|
|
class UVM_REMOVE_EVENT_QUEUE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
sessionIndex: Annotated[NvS32, 0]
|
|
eventQueueIndex: Annotated[NvU32, 4]
|
|
rmStatus: Annotated[NV_STATUS, 8]
|
|
@c.record
|
|
class UVM_MAP_EVENT_QUEUE_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
sessionIndex: Annotated[NvS32, 0]
|
|
eventQueueIndex: Annotated[NvU32, 4]
|
|
userRODataAddr: Annotated[NvP64, 8]
|
|
userRWDataAddr: Annotated[NvP64, 16]
|
|
readIndexAddr: Annotated[NvP64, 24]
|
|
writeIndexAddr: Annotated[NvP64, 32]
|
|
queueBufferAddr: Annotated[NvP64, 40]
|
|
rmStatus: Annotated[NV_STATUS, 48]
|
|
@c.record
|
|
class UVM_EVENT_CTRL_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
sessionIndex: Annotated[NvS32, 0]
|
|
eventQueueIndex: Annotated[NvU32, 4]
|
|
eventType: Annotated[NvS32, 8]
|
|
enable: Annotated[NvU32, 12]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_REGISTER_MPS_SERVER_PARAMS(c.Struct):
|
|
SIZE = 536
|
|
gpuUuidArray: Annotated[c.Array[NvProcessorUuid, Literal[32]], 0]
|
|
numGpus: Annotated[NvU32, 512]
|
|
serverId: Annotated[NvU64, 520]
|
|
rmStatus: Annotated[NV_STATUS, 528]
|
|
@c.record
|
|
class UVM_REGISTER_MPS_CLIENT_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
serverId: Annotated[NvU64, 0]
|
|
rmStatus: Annotated[NV_STATUS, 8]
|
|
@c.record
|
|
class UVM_GET_GPU_UUID_TABLE_PARAMS(c.Struct):
|
|
SIZE = 520
|
|
gpuUuidArray: Annotated[c.Array[NvProcessorUuid, Literal[32]], 0]
|
|
validCount: Annotated[NvU32, 512]
|
|
rmStatus: Annotated[NV_STATUS, 516]
|
|
@c.record
|
|
class UVM_CREATE_RANGE_GROUP_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
rangeGroupId: Annotated[NvU64, 0]
|
|
rmStatus: Annotated[NV_STATUS, 8]
|
|
@c.record
|
|
class UVM_DESTROY_RANGE_GROUP_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
rangeGroupId: Annotated[NvU64, 0]
|
|
rmStatus: Annotated[NV_STATUS, 8]
|
|
@c.record
|
|
class UVM_REGISTER_GPU_VASPACE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
gpuUuid: Annotated[NvProcessorUuid, 0]
|
|
rmCtrlFd: Annotated[NvS32, 16]
|
|
hClient: Annotated[NvHandle, 20]
|
|
hVaSpace: Annotated[NvHandle, 24]
|
|
rmStatus: Annotated[NV_STATUS, 28]
|
|
@c.record
|
|
class UVM_UNREGISTER_GPU_VASPACE_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
gpuUuid: Annotated[NvProcessorUuid, 0]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_REGISTER_CHANNEL_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
gpuUuid: Annotated[NvProcessorUuid, 0]
|
|
rmCtrlFd: Annotated[NvS32, 16]
|
|
hClient: Annotated[NvHandle, 20]
|
|
hChannel: Annotated[NvHandle, 24]
|
|
base: Annotated[NvU64, 32]
|
|
length: Annotated[NvU64, 40]
|
|
rmStatus: Annotated[NV_STATUS, 48]
|
|
@c.record
|
|
class UVM_UNREGISTER_CHANNEL_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
gpuUuid: Annotated[NvProcessorUuid, 0]
|
|
hClient: Annotated[NvHandle, 16]
|
|
hChannel: Annotated[NvHandle, 20]
|
|
rmStatus: Annotated[NV_STATUS, 24]
|
|
@c.record
|
|
class UVM_ENABLE_PEER_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 36
|
|
gpuUuidA: Annotated[NvProcessorUuid, 0]
|
|
gpuUuidB: Annotated[NvProcessorUuid, 16]
|
|
rmStatus: Annotated[NV_STATUS, 32]
|
|
@c.record
|
|
class UVM_DISABLE_PEER_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 36
|
|
gpuUuidA: Annotated[NvProcessorUuid, 0]
|
|
gpuUuidB: Annotated[NvProcessorUuid, 16]
|
|
rmStatus: Annotated[NV_STATUS, 32]
|
|
@c.record
|
|
class UVM_SET_RANGE_GROUP_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
rangeGroupId: Annotated[NvU64, 0]
|
|
requestedBase: Annotated[NvU64, 8]
|
|
length: Annotated[NvU64, 16]
|
|
rmStatus: Annotated[NV_STATUS, 24]
|
|
@c.record
|
|
class UVM_MAP_EXTERNAL_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 9264
|
|
base: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
offset: Annotated[NvU64, 16]
|
|
perGpuAttributes: Annotated[c.Array[UvmGpuMappingAttributes, Literal[256]], 24]
|
|
gpuAttributesCount: Annotated[NvU64, 9240]
|
|
rmCtrlFd: Annotated[NvS32, 9248]
|
|
hClient: Annotated[NvU32, 9252]
|
|
hMemory: Annotated[NvU32, 9256]
|
|
rmStatus: Annotated[NV_STATUS, 9260]
|
|
@c.record
|
|
class UvmGpuMappingAttributes(c.Struct):
|
|
SIZE = 36
|
|
gpuUuid: Annotated[NvProcessorUuid, 0]
|
|
gpuMappingType: Annotated[NvU32, 16]
|
|
gpuCachingType: Annotated[NvU32, 20]
|
|
gpuFormatType: Annotated[NvU32, 24]
|
|
gpuElementBits: Annotated[NvU32, 28]
|
|
gpuCompressionType: Annotated[NvU32, 32]
|
|
@c.record
|
|
class UVM_FREE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_MEM_MAP_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
regionBase: Annotated[NvP64, 0]
|
|
regionLength: Annotated[NvU64, 8]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_DEBUG_ACCESS_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 64
|
|
sessionIndex: Annotated[NvS32, 0]
|
|
baseAddress: Annotated[NvU64, 8]
|
|
sizeInBytes: Annotated[NvU64, 16]
|
|
accessType: Annotated[NvU32, 24]
|
|
buffer: Annotated[NvU64, 32]
|
|
isBitmaskSet: Annotated[NvBool, 40]
|
|
bitmask: Annotated[NvU64, 48]
|
|
rmStatus: Annotated[NV_STATUS, 56]
|
|
@c.record
|
|
class UVM_REGISTER_GPU_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
gpu_uuid: Annotated[NvProcessorUuid, 0]
|
|
numaEnabled: Annotated[NvBool, 16]
|
|
numaNodeId: Annotated[NvS32, 20]
|
|
rmCtrlFd: Annotated[NvS32, 24]
|
|
hClient: Annotated[NvHandle, 28]
|
|
hSmcPartRef: Annotated[NvHandle, 32]
|
|
rmStatus: Annotated[NV_STATUS, 36]
|
|
@c.record
|
|
class UVM_UNREGISTER_GPU_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
gpu_uuid: Annotated[NvProcessorUuid, 0]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_PAGEABLE_MEM_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pageableMemAccess: Annotated[NvBool, 0]
|
|
rmStatus: Annotated[NV_STATUS, 4]
|
|
@c.record
|
|
class UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS(c.Struct):
|
|
SIZE = 272
|
|
rangeGroupIds: Annotated[c.Array[NvU64, Literal[32]], 0]
|
|
numGroupIds: Annotated[NvU64, 256]
|
|
rmStatus: Annotated[NV_STATUS, 264]
|
|
@c.record
|
|
class UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS(c.Struct):
|
|
SIZE = 272
|
|
rangeGroupIds: Annotated[c.Array[NvU64, Literal[32]], 0]
|
|
numGroupIds: Annotated[NvU64, 256]
|
|
rmStatus: Annotated[NV_STATUS, 264]
|
|
@c.record
|
|
class UVM_SET_PREFERRED_LOCATION_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
requestedBase: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
preferredLocation: Annotated[NvProcessorUuid, 16]
|
|
preferredCpuNumaNode: Annotated[NvS32, 32]
|
|
rmStatus: Annotated[NV_STATUS, 36]
|
|
@c.record
|
|
class UVM_UNSET_PREFERRED_LOCATION_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
requestedBase: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_ENABLE_READ_DUPLICATION_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
requestedBase: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_DISABLE_READ_DUPLICATION_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
requestedBase: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_SET_ACCESSED_BY_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
requestedBase: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
accessedByUuid: Annotated[NvProcessorUuid, 16]
|
|
rmStatus: Annotated[NV_STATUS, 32]
|
|
@c.record
|
|
class UVM_UNSET_ACCESSED_BY_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
requestedBase: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
accessedByUuid: Annotated[NvProcessorUuid, 16]
|
|
rmStatus: Annotated[NV_STATUS, 32]
|
|
@c.record
|
|
class UVM_MIGRATE_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
base: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
destinationUuid: Annotated[NvProcessorUuid, 16]
|
|
flags: Annotated[NvU32, 32]
|
|
semaphoreAddress: Annotated[NvU64, 40]
|
|
semaphorePayload: Annotated[NvU32, 48]
|
|
cpuNumaNode: Annotated[NvS32, 52]
|
|
userSpaceStart: Annotated[NvU64, 56]
|
|
userSpaceLength: Annotated[NvU64, 64]
|
|
rmStatus: Annotated[NV_STATUS, 72]
|
|
@c.record
|
|
class UVM_MIGRATE_RANGE_GROUP_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
rangeGroupId: Annotated[NvU64, 0]
|
|
destinationUuid: Annotated[NvProcessorUuid, 8]
|
|
rmStatus: Annotated[NV_STATUS, 24]
|
|
@c.record
|
|
class UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
gpu_uuid: Annotated[NvProcessorUuid, 0]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
gpu_uuid: Annotated[NvProcessorUuid, 0]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
queueBuffer: Annotated[NvU64, 0]
|
|
queueBufferSize: Annotated[NvU64, 8]
|
|
controlBuffer: Annotated[NvU64, 16]
|
|
processor: Annotated[NvProcessorUuid, 24]
|
|
allProcessors: Annotated[NvU32, 40]
|
|
uvmFd: Annotated[NvU32, 44]
|
|
rmStatus: Annotated[NV_STATUS, 48]
|
|
@c.record
|
|
class UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
notificationThreshold: Annotated[NvU32, 0]
|
|
rmStatus: Annotated[NV_STATUS, 4]
|
|
@c.record
|
|
class UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
eventTypeFlags: Annotated[NvU64, 0]
|
|
rmStatus: Annotated[NV_STATUS, 8]
|
|
@c.record
|
|
class UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
eventTypeFlags: Annotated[NvU64, 0]
|
|
rmStatus: Annotated[NV_STATUS, 8]
|
|
@c.record
|
|
class UVM_TOOLS_ENABLE_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
counterTypeFlags: Annotated[NvU64, 0]
|
|
rmStatus: Annotated[NV_STATUS, 8]
|
|
@c.record
|
|
class UVM_TOOLS_DISABLE_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
counterTypeFlags: Annotated[NvU64, 0]
|
|
rmStatus: Annotated[NV_STATUS, 8]
|
|
@c.record
|
|
class UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
buffer: Annotated[NvU64, 0]
|
|
size: Annotated[NvU64, 8]
|
|
targetVa: Annotated[NvU64, 16]
|
|
bytesRead: Annotated[NvU64, 24]
|
|
rmStatus: Annotated[NV_STATUS, 32]
|
|
@c.record
|
|
class UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
buffer: Annotated[NvU64, 0]
|
|
size: Annotated[NvU64, 8]
|
|
targetVa: Annotated[NvU64, 16]
|
|
bytesWritten: Annotated[NvU64, 24]
|
|
rmStatus: Annotated[NV_STATUS, 32]
|
|
@c.record
|
|
class UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
tablePtr: Annotated[NvU64, 0]
|
|
rmStatus: Annotated[NV_STATUS, 8]
|
|
@c.record
|
|
class UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
base: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
gpuUuid: Annotated[NvProcessorUuid, 16]
|
|
rmStatus: Annotated[NV_STATUS, 32]
|
|
@c.record
|
|
class UVM_UNMAP_EXTERNAL_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
base: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
gpuUuid: Annotated[NvProcessorUuid, 16]
|
|
rmStatus: Annotated[NV_STATUS, 32]
|
|
@c.record
|
|
class UVM_TOOLS_FLUSH_EVENTS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rmStatus: Annotated[NV_STATUS, 0]
|
|
@c.record
|
|
class UVM_ALLOC_SEMAPHORE_POOL_PARAMS(c.Struct):
|
|
SIZE = 9248
|
|
base: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
perGpuAttributes: Annotated[c.Array[UvmGpuMappingAttributes, Literal[256]], 16]
|
|
gpuAttributesCount: Annotated[NvU64, 9232]
|
|
rmStatus: Annotated[NV_STATUS, 9240]
|
|
@c.record
|
|
class UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rmStatus: Annotated[NV_STATUS, 0]
|
|
@c.record
|
|
class UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
gpu_uuid: Annotated[NvProcessorUuid, 0]
|
|
pageableMemAccess: Annotated[NvBool, 16]
|
|
rmStatus: Annotated[NV_STATUS, 20]
|
|
@c.record
|
|
class UVM_POPULATE_PAGEABLE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
flags: Annotated[NvU32, 16]
|
|
rmStatus: Annotated[NV_STATUS, 20]
|
|
@c.record
|
|
class UVM_VALIDATE_VA_RANGE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_CREATE_EXTERNAL_RANGE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
rmStatus: Annotated[NV_STATUS, 16]
|
|
@c.record
|
|
class UVM_MAP_EXTERNAL_SPARSE_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
base: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
gpuUuid: Annotated[NvProcessorUuid, 16]
|
|
rmStatus: Annotated[NV_STATUS, 32]
|
|
@c.record
|
|
class UVM_MM_INITIALIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
uvmFd: Annotated[NvS32, 0]
|
|
rmStatus: Annotated[NV_STATUS, 4]
|
|
UVM_TOOLS_INIT_EVENT_TRACKER_V2_PARAMS: TypeAlias = UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS
|
|
UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2_PARAMS: TypeAlias = UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS
|
|
@c.record
|
|
class UVM_ALLOC_DEVICE_P2P_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
base: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
offset: Annotated[NvU64, 16]
|
|
gpuUuid: Annotated[NvProcessorUuid, 24]
|
|
rmCtrlFd: Annotated[NvS32, 40]
|
|
hClient: Annotated[NvU32, 44]
|
|
hMemory: Annotated[NvU32, 48]
|
|
rmStatus: Annotated[NV_STATUS, 52]
|
|
@c.record
|
|
class UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rmStatus: Annotated[NV_STATUS, 0]
|
|
@c.record
|
|
class UVM_IS_8_SUPPORTED_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
is8Supported: Annotated[NvU32, 0]
|
|
rmStatus: Annotated[NV_STATUS, 4]
|
|
@c.record
|
|
class UVM_INITIALIZE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
flags: Annotated[NvU64, 0]
|
|
rmStatus: Annotated[NV_STATUS, 8]
|
|
@c.record
|
|
class nv_pci_info_t(c.Struct):
|
|
SIZE = 12
|
|
domain: Annotated[NvU32, 0]
|
|
bus: Annotated[NvU8, 4]
|
|
slot: Annotated[NvU8, 5]
|
|
function: Annotated[NvU8, 6]
|
|
vendor_id: Annotated[NvU16, 8]
|
|
device_id: Annotated[NvU16, 10]
|
|
NvU16: TypeAlias = Annotated[int, ctypes.c_uint16]
|
|
@c.record
|
|
class struct_nv_ioctl_xfer(c.Struct):
|
|
SIZE = 16
|
|
cmd: Annotated[NvU32, 0]
|
|
size: Annotated[NvU32, 4]
|
|
ptr: Annotated[NvP64, 8]
|
|
nv_ioctl_xfer_t: TypeAlias = struct_nv_ioctl_xfer
|
|
@c.record
|
|
class struct_nv_ioctl_card_info(c.Struct):
|
|
SIZE = 72
|
|
valid: Annotated[NvBool, 0]
|
|
pci_info: Annotated[nv_pci_info_t, 4]
|
|
gpu_id: Annotated[NvU32, 16]
|
|
interrupt_line: Annotated[NvU16, 20]
|
|
reg_address: Annotated[NvU64, 24]
|
|
reg_size: Annotated[NvU64, 32]
|
|
fb_address: Annotated[NvU64, 40]
|
|
fb_size: Annotated[NvU64, 48]
|
|
minor_number: Annotated[NvU32, 56]
|
|
dev_name: Annotated[c.Array[NvU8, Literal[10]], 60]
|
|
nv_ioctl_card_info_t: TypeAlias = struct_nv_ioctl_card_info
|
|
@c.record
|
|
class struct_nv_ioctl_alloc_os_event(c.Struct):
|
|
SIZE = 16
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
fd: Annotated[NvU32, 8]
|
|
Status: Annotated[NvU32, 12]
|
|
nv_ioctl_alloc_os_event_t: TypeAlias = struct_nv_ioctl_alloc_os_event
|
|
@c.record
|
|
class struct_nv_ioctl_free_os_event(c.Struct):
|
|
SIZE = 16
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
fd: Annotated[NvU32, 8]
|
|
Status: Annotated[NvU32, 12]
|
|
nv_ioctl_free_os_event_t: TypeAlias = struct_nv_ioctl_free_os_event
|
|
@c.record
|
|
class struct_nv_ioctl_status_code(c.Struct):
|
|
SIZE = 12
|
|
domain: Annotated[NvU32, 0]
|
|
bus: Annotated[NvU8, 4]
|
|
slot: Annotated[NvU8, 5]
|
|
status: Annotated[NvU32, 8]
|
|
nv_ioctl_status_code_t: TypeAlias = struct_nv_ioctl_status_code
|
|
@c.record
|
|
class struct_nv_ioctl_rm_api_version(c.Struct):
|
|
SIZE = 72
|
|
cmd: Annotated[NvU32, 0]
|
|
reply: Annotated[NvU32, 4]
|
|
versionString: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[64]], 8]
|
|
nv_ioctl_rm_api_version_t: TypeAlias = struct_nv_ioctl_rm_api_version
|
|
@c.record
|
|
class struct_nv_ioctl_query_device_intr(c.Struct):
|
|
SIZE = 8
|
|
intrStatus: Annotated[NvU32, 0]
|
|
status: Annotated[NvU32, 4]
|
|
nv_ioctl_query_device_intr: TypeAlias = struct_nv_ioctl_query_device_intr
|
|
@c.record
|
|
class struct_nv_ioctl_sys_params(c.Struct):
|
|
SIZE = 8
|
|
memblock_size: Annotated[NvU64, 0]
|
|
nv_ioctl_sys_params_t: TypeAlias = struct_nv_ioctl_sys_params
|
|
@c.record
|
|
class struct_nv_ioctl_register_fd(c.Struct):
|
|
SIZE = 4
|
|
ctl_fd: Annotated[Annotated[int, ctypes.c_int32], 0]
|
|
nv_ioctl_register_fd_t: TypeAlias = struct_nv_ioctl_register_fd
|
|
@c.record
|
|
class struct_nv_ioctl_export_to_dma_buf_fd(c.Struct):
|
|
SIZE = 2608
|
|
fd: Annotated[Annotated[int, ctypes.c_int32], 0]
|
|
hClient: Annotated[NvHandle, 4]
|
|
totalObjects: Annotated[NvU32, 8]
|
|
numObjects: Annotated[NvU32, 12]
|
|
index: Annotated[NvU32, 16]
|
|
totalSize: Annotated[NvU64, 24]
|
|
mappingType: Annotated[NvU8, 32]
|
|
handles: Annotated[c.Array[NvHandle, Literal[128]], 36]
|
|
offsets: Annotated[c.Array[NvU64, Literal[128]], 552]
|
|
sizes: Annotated[c.Array[NvU64, Literal[128]], 1576]
|
|
status: Annotated[NvU32, 2600]
|
|
nv_ioctl_export_to_dma_buf_fd_t: TypeAlias = struct_nv_ioctl_export_to_dma_buf_fd
|
|
@c.record
|
|
class struct_nv_ioctl_wait_open_complete(c.Struct):
|
|
SIZE = 8
|
|
rc: Annotated[Annotated[int, ctypes.c_int32], 0]
|
|
adapterStatus: Annotated[NvU32, 4]
|
|
nv_ioctl_wait_open_complete_t: TypeAlias = struct_nv_ioctl_wait_open_complete
|
|
@c.record
|
|
class struct_offline_addresses(c.Struct):
|
|
SIZE = 520
|
|
addresses: Annotated[c.Array[uint64_t, Literal[64]], 0]
|
|
numEntries: Annotated[uint32_t, 512]
|
|
uint64_t: TypeAlias = Annotated[int, ctypes.c_uint64]
|
|
uint32_t: TypeAlias = Annotated[int, ctypes.c_uint32]
|
|
nv_offline_addresses_t: TypeAlias = struct_offline_addresses
|
|
@c.record
|
|
class struct_nv_ioctl_numa_info(c.Struct):
|
|
SIZE = 560
|
|
nid: Annotated[int32_t, 0]
|
|
status: Annotated[int32_t, 4]
|
|
memblock_size: Annotated[uint64_t, 8]
|
|
numa_mem_addr: Annotated[uint64_t, 16]
|
|
numa_mem_size: Annotated[uint64_t, 24]
|
|
use_auto_online: Annotated[uint8_t, 32]
|
|
offline_addresses: Annotated[nv_offline_addresses_t, 40]
|
|
int32_t: TypeAlias = Annotated[int, ctypes.c_int32]
|
|
uint8_t: TypeAlias = Annotated[int, ctypes.c_ubyte]
|
|
nv_ioctl_numa_info_t: TypeAlias = struct_nv_ioctl_numa_info
|
|
@c.record
|
|
class struct_nv_ioctl_set_numa_status(c.Struct):
|
|
SIZE = 4
|
|
status: Annotated[int32_t, 0]
|
|
nv_ioctl_set_numa_status_t: TypeAlias = struct_nv_ioctl_set_numa_status
|
|
@c.record
|
|
class nv_ioctl_nvos02_parameters_with_fd(c.Struct):
|
|
SIZE = 56
|
|
params: Annotated[NVOS02_PARAMETERS, 0]
|
|
fd: Annotated[Annotated[int, ctypes.c_int32], 48]
|
|
@c.record
|
|
class NVOS02_PARAMETERS(c.Struct):
|
|
SIZE = 48
|
|
hRoot: Annotated[NvHandle, 0]
|
|
hObjectParent: Annotated[NvHandle, 4]
|
|
hObjectNew: Annotated[NvHandle, 8]
|
|
hClass: Annotated[NvV32, 12]
|
|
flags: Annotated[NvV32, 16]
|
|
pMemory: Annotated[NvP64, 24]
|
|
limit: Annotated[NvU64, 32]
|
|
status: Annotated[NvV32, 40]
|
|
@c.record
|
|
class nv_ioctl_nvos33_parameters_with_fd(c.Struct):
|
|
SIZE = 56
|
|
params: Annotated[NVOS33_PARAMETERS, 0]
|
|
fd: Annotated[Annotated[int, ctypes.c_int32], 48]
|
|
@c.record
|
|
class NVOS33_PARAMETERS(c.Struct):
|
|
SIZE = 48
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
hMemory: Annotated[NvHandle, 8]
|
|
offset: Annotated[NvU64, 16]
|
|
length: Annotated[NvU64, 24]
|
|
pLinearAddress: Annotated[NvP64, 32]
|
|
status: Annotated[NvU32, 40]
|
|
flags: Annotated[NvU32, 44]
|
|
@c.record
|
|
class struct_NV_MEMORY_DESC_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: Annotated[NvU64, 0]
|
|
size: Annotated[NvU64, 8]
|
|
addressSpace: Annotated[NvU32, 16]
|
|
cacheAttrib: Annotated[NvU32, 20]
|
|
NV_MEMORY_DESC_PARAMS: TypeAlias = struct_NV_MEMORY_DESC_PARAMS
|
|
@c.record
|
|
class struct_NV_CHANNEL_ALLOC_PARAMS(c.Struct):
|
|
SIZE = 368
|
|
hObjectError: Annotated[NvHandle, 0]
|
|
hObjectBuffer: Annotated[NvHandle, 4]
|
|
gpFifoOffset: Annotated[NvU64, 8]
|
|
gpFifoEntries: Annotated[NvU32, 16]
|
|
flags: Annotated[NvU32, 20]
|
|
hContextShare: Annotated[NvHandle, 24]
|
|
hVASpace: Annotated[NvHandle, 28]
|
|
hUserdMemory: Annotated[c.Array[NvHandle, Literal[8]], 32]
|
|
userdOffset: Annotated[c.Array[NvU64, Literal[8]], 64]
|
|
engineType: Annotated[NvU32, 128]
|
|
cid: Annotated[NvU32, 132]
|
|
subDeviceId: Annotated[NvU32, 136]
|
|
hObjectEccError: Annotated[NvHandle, 140]
|
|
instanceMem: Annotated[NV_MEMORY_DESC_PARAMS, 144]
|
|
userdMem: Annotated[NV_MEMORY_DESC_PARAMS, 168]
|
|
ramfcMem: Annotated[NV_MEMORY_DESC_PARAMS, 192]
|
|
mthdbufMem: Annotated[NV_MEMORY_DESC_PARAMS, 216]
|
|
hPhysChannelGroup: Annotated[NvHandle, 240]
|
|
internalFlags: Annotated[NvU32, 244]
|
|
errorNotifierMem: Annotated[NV_MEMORY_DESC_PARAMS, 248]
|
|
eccErrorNotifierMem: Annotated[NV_MEMORY_DESC_PARAMS, 272]
|
|
ProcessID: Annotated[NvU32, 296]
|
|
SubProcessID: Annotated[NvU32, 300]
|
|
encryptIv: Annotated[c.Array[NvU32, Literal[3]], 304]
|
|
decryptIv: Annotated[c.Array[NvU32, Literal[3]], 316]
|
|
hmacNonce: Annotated[c.Array[NvU32, Literal[8]], 328]
|
|
tpcConfigID: Annotated[NvU32, 360]
|
|
NV_CHANNEL_ALLOC_PARAMS: TypeAlias = struct_NV_CHANNEL_ALLOC_PARAMS
|
|
NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS: TypeAlias = struct_NV_CHANNEL_ALLOC_PARAMS
|
|
@c.record
|
|
class NVOS00_PARAMETERS(c.Struct):
|
|
SIZE = 16
|
|
hRoot: Annotated[NvHandle, 0]
|
|
hObjectParent: Annotated[NvHandle, 4]
|
|
hObjectOld: Annotated[NvHandle, 8]
|
|
status: Annotated[NvV32, 12]
|
|
@c.record
|
|
class NVOS05_PARAMETERS(c.Struct):
|
|
SIZE = 20
|
|
hRoot: Annotated[NvHandle, 0]
|
|
hObjectParent: Annotated[NvHandle, 4]
|
|
hObjectNew: Annotated[NvHandle, 8]
|
|
hClass: Annotated[NvV32, 12]
|
|
status: Annotated[NvV32, 16]
|
|
Callback1ArgVoidReturn: TypeAlias = c.CFUNCTYPE[None, [ctypes.c_void_p]]
|
|
Callback5ArgVoidReturn: TypeAlias = c.CFUNCTYPE[None, [ctypes.c_void_p, ctypes.c_void_p, Annotated[int, ctypes.c_uint32], Annotated[int, ctypes.c_uint32], Annotated[int, ctypes.c_uint32]]]
|
|
@c.record
|
|
class NVOS10_EVENT_KERNEL_CALLBACK(c.Struct):
|
|
SIZE = 16
|
|
func: Annotated[Callback1ArgVoidReturn, 0]
|
|
arg: Annotated[ctypes.c_void_p, 8]
|
|
@c.record
|
|
class NVOS10_EVENT_KERNEL_CALLBACK_EX(c.Struct):
|
|
SIZE = 16
|
|
func: Annotated[Callback5ArgVoidReturn, 0]
|
|
arg: Annotated[ctypes.c_void_p, 8]
|
|
@c.record
|
|
class NVOS_I2C_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
paramSize: Annotated[NvU32, 8]
|
|
paramStructPtr: Annotated[NvP64, 16]
|
|
status: Annotated[NvV32, 24]
|
|
@c.record
|
|
class NVOS21_PARAMETERS(c.Struct):
|
|
SIZE = 32
|
|
hRoot: Annotated[NvHandle, 0]
|
|
hObjectParent: Annotated[NvHandle, 4]
|
|
hObjectNew: Annotated[NvHandle, 8]
|
|
hClass: Annotated[NvV32, 12]
|
|
pAllocParms: Annotated[NvP64, 16]
|
|
paramsSize: Annotated[NvU32, 24]
|
|
status: Annotated[NvV32, 28]
|
|
@c.record
|
|
class NVOS64_PARAMETERS(c.Struct):
|
|
SIZE = 48
|
|
hRoot: Annotated[NvHandle, 0]
|
|
hObjectParent: Annotated[NvHandle, 4]
|
|
hObjectNew: Annotated[NvHandle, 8]
|
|
hClass: Annotated[NvV32, 12]
|
|
pAllocParms: Annotated[NvP64, 16]
|
|
pRightsRequested: Annotated[NvP64, 24]
|
|
paramsSize: Annotated[NvU32, 32]
|
|
flags: Annotated[NvU32, 36]
|
|
status: Annotated[NvV32, 40]
|
|
@c.record
|
|
class NVOS62_PARAMETERS(c.Struct):
|
|
SIZE = 24
|
|
hRoot: Annotated[NvHandle, 0]
|
|
hObjectParent: Annotated[NvHandle, 4]
|
|
hObjectNew: Annotated[NvHandle, 8]
|
|
hClass: Annotated[NvV32, 12]
|
|
paramSize: Annotated[NvU32, 16]
|
|
status: Annotated[NvV32, 20]
|
|
@c.record
|
|
class NVOS65_PARAMETERS(c.Struct):
|
|
SIZE = 32
|
|
hRoot: Annotated[NvHandle, 0]
|
|
hObjectParent: Annotated[NvHandle, 4]
|
|
hObjectNew: Annotated[NvHandle, 8]
|
|
hClass: Annotated[NvV32, 12]
|
|
paramSize: Annotated[NvU32, 16]
|
|
versionMagic: Annotated[NvU32, 20]
|
|
maskSize: Annotated[NvU32, 24]
|
|
status: Annotated[NvV32, 28]
|
|
@c.record
|
|
class NVOS30_PARAMETERS(c.Struct):
|
|
SIZE = 56
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
hChannel: Annotated[NvHandle, 8]
|
|
numChannels: Annotated[NvV32, 12]
|
|
phClients: Annotated[NvP64, 16]
|
|
phDevices: Annotated[NvP64, 24]
|
|
phChannels: Annotated[NvP64, 32]
|
|
flags: Annotated[NvV32, 40]
|
|
timeout: Annotated[NvV32, 44]
|
|
status: Annotated[NvV32, 48]
|
|
BindResultFunc: TypeAlias = c.CFUNCTYPE[None, [ctypes.c_void_p, Annotated[int, ctypes.c_uint32], Annotated[int, ctypes.c_uint32], Annotated[int, ctypes.c_uint32]]]
|
|
@c.record
|
|
class NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS(c.Struct):
|
|
SIZE = 16
|
|
sgt: Annotated[NvP64, 0]
|
|
gem: Annotated[NvP64, 8]
|
|
@c.record
|
|
class NVOS32_BLOCKINFO(c.Struct):
|
|
SIZE = 24
|
|
startOffset: Annotated[NvU64, 0]
|
|
size: Annotated[NvU64, 8]
|
|
flags: Annotated[NvU32, 16]
|
|
@c.record
|
|
class NVOS32_PARAMETERS(c.Struct):
|
|
SIZE = 184
|
|
hRoot: Annotated[NvHandle, 0]
|
|
hObjectParent: Annotated[NvHandle, 4]
|
|
function: Annotated[NvU32, 8]
|
|
hVASpace: Annotated[NvHandle, 12]
|
|
ivcHeapNumber: Annotated[NvS16, 16]
|
|
status: Annotated[NvV32, 20]
|
|
total: Annotated[NvU64, 24]
|
|
free: Annotated[NvU64, 32]
|
|
data: Annotated[NVOS32_PARAMETERS_data, 40]
|
|
NvS16: TypeAlias = Annotated[int, ctypes.c_int16]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data(c.Struct):
|
|
SIZE = 144
|
|
AllocSize: Annotated[NVOS32_PARAMETERS_data_AllocSize, 0]
|
|
AllocTiledPitchHeight: Annotated[NVOS32_PARAMETERS_data_AllocTiledPitchHeight, 0]
|
|
Free: Annotated[NVOS32_PARAMETERS_data_Free, 0]
|
|
ReleaseCompr: Annotated[NVOS32_PARAMETERS_data_ReleaseCompr, 0]
|
|
ReacquireCompr: Annotated[NVOS32_PARAMETERS_data_ReacquireCompr, 0]
|
|
Info: Annotated[NVOS32_PARAMETERS_data_Info, 0]
|
|
Dump: Annotated[NVOS32_PARAMETERS_data_Dump, 0]
|
|
AllocSizeRange: Annotated[NVOS32_PARAMETERS_data_AllocSizeRange, 0]
|
|
AllocHintAlignment: Annotated[NVOS32_PARAMETERS_data_AllocHintAlignment, 0]
|
|
HwAlloc: Annotated[NVOS32_PARAMETERS_data_HwAlloc, 0]
|
|
HwFree: Annotated[NVOS32_PARAMETERS_data_HwFree, 0]
|
|
AllocOsDesc: Annotated[NVOS32_PARAMETERS_data_AllocOsDesc, 0]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_AllocSize(c.Struct):
|
|
SIZE = 120
|
|
owner: Annotated[NvU32, 0]
|
|
hMemory: Annotated[NvHandle, 4]
|
|
type: Annotated[NvU32, 8]
|
|
flags: Annotated[NvU32, 12]
|
|
attr: Annotated[NvU32, 16]
|
|
format: Annotated[NvU32, 20]
|
|
comprCovg: Annotated[NvU32, 24]
|
|
zcullCovg: Annotated[NvU32, 28]
|
|
partitionStride: Annotated[NvU32, 32]
|
|
width: Annotated[NvU32, 36]
|
|
height: Annotated[NvU32, 40]
|
|
size: Annotated[NvU64, 48]
|
|
alignment: Annotated[NvU64, 56]
|
|
offset: Annotated[NvU64, 64]
|
|
limit: Annotated[NvU64, 72]
|
|
address: Annotated[NvP64, 80]
|
|
rangeBegin: Annotated[NvU64, 88]
|
|
rangeEnd: Annotated[NvU64, 96]
|
|
attr2: Annotated[NvU32, 104]
|
|
ctagOffset: Annotated[NvU32, 108]
|
|
numaNode: Annotated[NvS32, 112]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_AllocTiledPitchHeight(c.Struct):
|
|
SIZE = 120
|
|
owner: Annotated[NvU32, 0]
|
|
hMemory: Annotated[NvHandle, 4]
|
|
type: Annotated[NvU32, 8]
|
|
flags: Annotated[NvU32, 12]
|
|
height: Annotated[NvU32, 16]
|
|
pitch: Annotated[NvS32, 20]
|
|
attr: Annotated[NvU32, 24]
|
|
width: Annotated[NvU32, 28]
|
|
format: Annotated[NvU32, 32]
|
|
comprCovg: Annotated[NvU32, 36]
|
|
zcullCovg: Annotated[NvU32, 40]
|
|
partitionStride: Annotated[NvU32, 44]
|
|
size: Annotated[NvU64, 48]
|
|
alignment: Annotated[NvU64, 56]
|
|
offset: Annotated[NvU64, 64]
|
|
limit: Annotated[NvU64, 72]
|
|
address: Annotated[NvP64, 80]
|
|
rangeBegin: Annotated[NvU64, 88]
|
|
rangeEnd: Annotated[NvU64, 96]
|
|
attr2: Annotated[NvU32, 104]
|
|
ctagOffset: Annotated[NvU32, 108]
|
|
numaNode: Annotated[NvS32, 112]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_Free(c.Struct):
|
|
SIZE = 12
|
|
owner: Annotated[NvU32, 0]
|
|
hMemory: Annotated[NvHandle, 4]
|
|
flags: Annotated[NvU32, 8]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_ReleaseCompr(c.Struct):
|
|
SIZE = 12
|
|
owner: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
hMemory: Annotated[NvHandle, 8]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_ReacquireCompr(c.Struct):
|
|
SIZE = 12
|
|
owner: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
hMemory: Annotated[NvHandle, 8]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_Info(c.Struct):
|
|
SIZE = 32
|
|
attr: Annotated[NvU32, 0]
|
|
offset: Annotated[NvU64, 8]
|
|
size: Annotated[NvU64, 16]
|
|
base: Annotated[NvU64, 24]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_Dump(c.Struct):
|
|
SIZE = 24
|
|
flags: Annotated[NvU32, 0]
|
|
pBuffer: Annotated[NvP64, 8]
|
|
numBlocks: Annotated[NvU32, 16]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_AllocSizeRange(c.Struct):
|
|
SIZE = 112
|
|
owner: Annotated[NvU32, 0]
|
|
hMemory: Annotated[NvHandle, 4]
|
|
type: Annotated[NvU32, 8]
|
|
flags: Annotated[NvU32, 12]
|
|
attr: Annotated[NvU32, 16]
|
|
format: Annotated[NvU32, 20]
|
|
comprCovg: Annotated[NvU32, 24]
|
|
zcullCovg: Annotated[NvU32, 28]
|
|
partitionStride: Annotated[NvU32, 32]
|
|
size: Annotated[NvU64, 40]
|
|
alignment: Annotated[NvU64, 48]
|
|
offset: Annotated[NvU64, 56]
|
|
limit: Annotated[NvU64, 64]
|
|
rangeBegin: Annotated[NvU64, 72]
|
|
rangeEnd: Annotated[NvU64, 80]
|
|
address: Annotated[NvP64, 88]
|
|
attr2: Annotated[NvU32, 96]
|
|
ctagOffset: Annotated[NvU32, 100]
|
|
numaNode: Annotated[NvS32, 104]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_AllocHintAlignment(c.Struct):
|
|
SIZE = 88
|
|
alignType: Annotated[NvU32, 0]
|
|
alignAttr: Annotated[NvU32, 4]
|
|
alignInputFlags: Annotated[NvU32, 8]
|
|
alignSize: Annotated[NvU64, 16]
|
|
alignHeight: Annotated[NvU32, 24]
|
|
alignWidth: Annotated[NvU32, 28]
|
|
alignPitch: Annotated[NvU32, 32]
|
|
alignPad: Annotated[NvU32, 36]
|
|
alignMask: Annotated[NvU32, 40]
|
|
alignOutputFlags: Annotated[c.Array[NvU32, Literal[4]], 44]
|
|
alignBank: Annotated[c.Array[NvU32, Literal[4]], 60]
|
|
alignKind: Annotated[NvU32, 76]
|
|
alignAdjust: Annotated[NvU32, 80]
|
|
alignAttr2: Annotated[NvU32, 84]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_HwAlloc(c.Struct):
|
|
SIZE = 144
|
|
allocOwner: Annotated[NvU32, 0]
|
|
allochMemory: Annotated[NvHandle, 4]
|
|
flags: Annotated[NvU32, 8]
|
|
allocType: Annotated[NvU32, 12]
|
|
allocAttr: Annotated[NvU32, 16]
|
|
allocInputFlags: Annotated[NvU32, 20]
|
|
allocSize: Annotated[NvU64, 24]
|
|
allocHeight: Annotated[NvU32, 32]
|
|
allocWidth: Annotated[NvU32, 36]
|
|
allocPitch: Annotated[NvU32, 40]
|
|
allocMask: Annotated[NvU32, 44]
|
|
allocComprCovg: Annotated[NvU32, 48]
|
|
allocZcullCovg: Annotated[NvU32, 52]
|
|
bindResultFunc: Annotated[NvP64, 56]
|
|
pHandle: Annotated[NvP64, 64]
|
|
hResourceHandle: Annotated[NvHandle, 72]
|
|
retAttr: Annotated[NvU32, 76]
|
|
kind: Annotated[NvU32, 80]
|
|
osDeviceHandle: Annotated[NvU64, 88]
|
|
allocAttr2: Annotated[NvU32, 96]
|
|
retAttr2: Annotated[NvU32, 100]
|
|
allocAddr: Annotated[NvU64, 104]
|
|
comprInfo: Annotated[NVOS32_PARAMETERS_data_HwAlloc_comprInfo, 112]
|
|
uncompressedKind: Annotated[NvU32, 136]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_HwAlloc_comprInfo(c.Struct):
|
|
SIZE = 24
|
|
compPageShift: Annotated[NvU32, 0]
|
|
compressedKind: Annotated[NvU32, 4]
|
|
compTagLineMin: Annotated[NvU32, 8]
|
|
compPageIndexLo: Annotated[NvU32, 12]
|
|
compPageIndexHi: Annotated[NvU32, 16]
|
|
compTagLineMultiplier: Annotated[NvU32, 20]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_HwFree(c.Struct):
|
|
SIZE = 8
|
|
hResourceHandle: Annotated[NvHandle, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
@c.record
|
|
class NVOS32_PARAMETERS_data_AllocOsDesc(c.Struct):
|
|
SIZE = 48
|
|
hMemory: Annotated[NvHandle, 0]
|
|
type: Annotated[NvU32, 4]
|
|
flags: Annotated[NvU32, 8]
|
|
attr: Annotated[NvU32, 12]
|
|
attr2: Annotated[NvU32, 16]
|
|
descriptor: Annotated[NvP64, 24]
|
|
limit: Annotated[NvU64, 32]
|
|
descriptorType: Annotated[NvU32, 40]
|
|
@c.record
|
|
class NVOS32_HEAP_DUMP_BLOCK(c.Struct):
|
|
SIZE = 32
|
|
owner: Annotated[NvU32, 0]
|
|
format: Annotated[NvU32, 4]
|
|
begin: Annotated[NvU64, 8]
|
|
align: Annotated[NvU64, 16]
|
|
end: Annotated[NvU64, 24]
|
|
@c.record
|
|
class NV_CONTEXT_DMA_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
flags: Annotated[NvV32, 4]
|
|
hMemory: Annotated[NvHandle, 8]
|
|
offset: Annotated[NvU64, 16]
|
|
limit: Annotated[NvU64, 24]
|
|
@c.record
|
|
class NV_MEMORY_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 128
|
|
owner: Annotated[NvU32, 0]
|
|
type: Annotated[NvU32, 4]
|
|
flags: Annotated[NvU32, 8]
|
|
width: Annotated[NvU32, 12]
|
|
height: Annotated[NvU32, 16]
|
|
pitch: Annotated[NvS32, 20]
|
|
attr: Annotated[NvU32, 24]
|
|
attr2: Annotated[NvU32, 28]
|
|
format: Annotated[NvU32, 32]
|
|
comprCovg: Annotated[NvU32, 36]
|
|
zcullCovg: Annotated[NvU32, 40]
|
|
rangeLo: Annotated[NvU64, 48]
|
|
rangeHi: Annotated[NvU64, 56]
|
|
size: Annotated[NvU64, 64]
|
|
alignment: Annotated[NvU64, 72]
|
|
offset: Annotated[NvU64, 80]
|
|
limit: Annotated[NvU64, 88]
|
|
address: Annotated[NvP64, 96]
|
|
ctagOffset: Annotated[NvU32, 104]
|
|
hVASpace: Annotated[NvHandle, 108]
|
|
internalflags: Annotated[NvU32, 112]
|
|
tag: Annotated[NvU32, 116]
|
|
numaNode: Annotated[NvS32, 120]
|
|
@c.record
|
|
class NV_OS_DESC_MEMORY_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
type: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
attr: Annotated[NvU32, 8]
|
|
attr2: Annotated[NvU32, 12]
|
|
descriptor: Annotated[NvP64, 16]
|
|
limit: Annotated[NvU64, 24]
|
|
descriptorType: Annotated[NvU32, 32]
|
|
tag: Annotated[NvU32, 36]
|
|
@c.record
|
|
class NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
flags: Annotated[NvU32, 0]
|
|
physAddr: Annotated[NvU64, 8]
|
|
size: Annotated[NvU64, 16]
|
|
tag: Annotated[NvU32, 24]
|
|
bGuestAllocated: Annotated[NvBool, 28]
|
|
@c.record
|
|
class NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 120
|
|
owner: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
type: Annotated[NvU32, 8]
|
|
attr: Annotated[NvU32, 12]
|
|
attr2: Annotated[NvU32, 16]
|
|
height: Annotated[NvU32, 20]
|
|
width: Annotated[NvU32, 24]
|
|
pitch: Annotated[NvU32, 28]
|
|
alignment: Annotated[NvU32, 32]
|
|
comprCovg: Annotated[NvU32, 36]
|
|
zcullCovg: Annotated[NvU32, 40]
|
|
kind: Annotated[NvU32, 44]
|
|
bindResultFunc: Annotated[NvP64, 48]
|
|
pHandle: Annotated[NvP64, 56]
|
|
osDeviceHandle: Annotated[NvU64, 64]
|
|
size: Annotated[NvU64, 72]
|
|
allocAddr: Annotated[NvU64, 80]
|
|
compPageShift: Annotated[NvU32, 88]
|
|
compressedKind: Annotated[NvU32, 92]
|
|
compTagLineMin: Annotated[NvU32, 96]
|
|
compPageIndexLo: Annotated[NvU32, 100]
|
|
compPageIndexHi: Annotated[NvU32, 104]
|
|
compTagLineMultiplier: Annotated[NvU32, 108]
|
|
uncompressedKind: Annotated[NvU32, 112]
|
|
tag: Annotated[NvU32, 116]
|
|
@c.record
|
|
class NVOS34_PARAMETERS(c.Struct):
|
|
SIZE = 32
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
hMemory: Annotated[NvHandle, 8]
|
|
pLinearAddress: Annotated[NvP64, 16]
|
|
status: Annotated[NvU32, 24]
|
|
flags: Annotated[NvU32, 28]
|
|
@c.record
|
|
class NVOS38_PARAMETERS(c.Struct):
|
|
SIZE = 72
|
|
hClient: Annotated[NvHandle, 0]
|
|
hObject: Annotated[NvHandle, 4]
|
|
AccessType: Annotated[NvV32, 8]
|
|
DevNodeLength: Annotated[NvV32, 12]
|
|
pDevNode: Annotated[NvP64, 16]
|
|
ParmStrLength: Annotated[NvV32, 24]
|
|
pParmStr: Annotated[NvP64, 32]
|
|
BinaryDataLength: Annotated[NvV32, 40]
|
|
pBinaryData: Annotated[NvP64, 48]
|
|
Data: Annotated[NvV32, 56]
|
|
Entry: Annotated[NvV32, 60]
|
|
status: Annotated[NvV32, 64]
|
|
@c.record
|
|
class NVOS39_PARAMETERS(c.Struct):
|
|
SIZE = 56
|
|
hObjectParent: Annotated[NvHandle, 0]
|
|
hSubDevice: Annotated[NvHandle, 4]
|
|
hObjectNew: Annotated[NvHandle, 8]
|
|
hClass: Annotated[NvV32, 12]
|
|
flags: Annotated[NvV32, 16]
|
|
selector: Annotated[NvU32, 20]
|
|
hMemory: Annotated[NvHandle, 24]
|
|
offset: Annotated[NvU64, 32]
|
|
limit: Annotated[NvU64, 40]
|
|
status: Annotated[NvV32, 48]
|
|
@c.record
|
|
class NvUnixEvent(c.Struct):
|
|
SIZE = 16
|
|
hObject: Annotated[NvHandle, 0]
|
|
NotifyIndex: Annotated[NvV32, 4]
|
|
info32: Annotated[NvV32, 8]
|
|
info16: Annotated[NvU16, 12]
|
|
@c.record
|
|
class NVOS41_PARAMETERS(c.Struct):
|
|
SIZE = 16
|
|
pEvent: Annotated[NvP64, 0]
|
|
MoreEvents: Annotated[NvV32, 8]
|
|
status: Annotated[NvV32, 12]
|
|
@c.record
|
|
class NVOS2C_PARAMETERS(c.Struct):
|
|
SIZE = 32
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
offset: Annotated[NvU32, 8]
|
|
bar: Annotated[NvU32, 12]
|
|
bytes: Annotated[NvU32, 16]
|
|
write: Annotated[NvU32, 20]
|
|
data: Annotated[NvU32, 24]
|
|
status: Annotated[NvU32, 28]
|
|
@c.record
|
|
class NVOS46_PARAMETERS(c.Struct):
|
|
SIZE = 56
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
hDma: Annotated[NvHandle, 8]
|
|
hMemory: Annotated[NvHandle, 12]
|
|
offset: Annotated[NvU64, 16]
|
|
length: Annotated[NvU64, 24]
|
|
flags: Annotated[NvV32, 32]
|
|
dmaOffset: Annotated[NvU64, 40]
|
|
status: Annotated[NvV32, 48]
|
|
@c.record
|
|
class NVOS47_PARAMETERS(c.Struct):
|
|
SIZE = 48
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
hDma: Annotated[NvHandle, 8]
|
|
hMemory: Annotated[NvHandle, 12]
|
|
flags: Annotated[NvV32, 16]
|
|
dmaOffset: Annotated[NvU64, 24]
|
|
size: Annotated[NvU64, 32]
|
|
status: Annotated[NvV32, 40]
|
|
@c.record
|
|
class NVOS49_PARAMETERS(c.Struct):
|
|
SIZE = 16
|
|
hClient: Annotated[NvHandle, 0]
|
|
hChannel: Annotated[NvHandle, 4]
|
|
hCtxDma: Annotated[NvHandle, 8]
|
|
status: Annotated[NvV32, 12]
|
|
@c.record
|
|
class NVOS54_PARAMETERS(c.Struct):
|
|
SIZE = 32
|
|
hClient: Annotated[NvHandle, 0]
|
|
hObject: Annotated[NvHandle, 4]
|
|
cmd: Annotated[NvV32, 8]
|
|
flags: Annotated[NvU32, 12]
|
|
params: Annotated[NvP64, 16]
|
|
paramsSize: Annotated[NvU32, 24]
|
|
status: Annotated[NvV32, 28]
|
|
@c.record
|
|
class NVOS63_PARAMETERS(c.Struct):
|
|
SIZE = 20
|
|
hClient: Annotated[NvHandle, 0]
|
|
hObject: Annotated[NvHandle, 4]
|
|
cmd: Annotated[NvV32, 8]
|
|
paramsSize: Annotated[NvU32, 12]
|
|
status: Annotated[NvV32, 16]
|
|
@c.record
|
|
class NVOS55_PARAMETERS(c.Struct):
|
|
SIZE = 28
|
|
hClient: Annotated[NvHandle, 0]
|
|
hParent: Annotated[NvHandle, 4]
|
|
hObject: Annotated[NvHandle, 8]
|
|
hClientSrc: Annotated[NvHandle, 12]
|
|
hObjectSrc: Annotated[NvHandle, 16]
|
|
flags: Annotated[NvU32, 20]
|
|
status: Annotated[NvU32, 24]
|
|
@c.record
|
|
class NVOS56_PARAMETERS(c.Struct):
|
|
SIZE = 40
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
hMemory: Annotated[NvHandle, 8]
|
|
pOldCpuAddress: Annotated[NvP64, 16]
|
|
pNewCpuAddress: Annotated[NvP64, 24]
|
|
status: Annotated[NvV32, 32]
|
|
@c.record
|
|
class NVOS57_PARAMETERS(c.Struct):
|
|
SIZE = 24
|
|
hClient: Annotated[NvHandle, 0]
|
|
hObject: Annotated[NvHandle, 4]
|
|
sharePolicy: Annotated[RS_SHARE_POLICY, 8]
|
|
status: Annotated[NvU32, 20]
|
|
@c.record
|
|
class struct_RS_SHARE_POLICY(c.Struct):
|
|
SIZE = 12
|
|
target: Annotated[NvU32, 0]
|
|
accessMask: Annotated[RS_ACCESS_MASK, 4]
|
|
type: Annotated[NvU16, 8]
|
|
action: Annotated[NvU8, 10]
|
|
RS_SHARE_POLICY: TypeAlias = struct_RS_SHARE_POLICY
|
|
@c.record
|
|
class struct_RS_ACCESS_MASK(c.Struct):
|
|
SIZE = 4
|
|
limbs: Annotated[c.Array[RsAccessLimb, Literal[1]], 0]
|
|
RS_ACCESS_MASK: TypeAlias = struct_RS_ACCESS_MASK
|
|
RsAccessLimb: TypeAlias = Annotated[int, ctypes.c_uint32]
|
|
@c.record
|
|
class NVPOWERSTATE_PARAMETERS(c.Struct):
|
|
SIZE = 28
|
|
deviceReference: Annotated[NvU32, 0]
|
|
head: Annotated[NvU32, 4]
|
|
state: Annotated[NvU32, 8]
|
|
forceMonitorState: Annotated[NvU8, 12]
|
|
bForcePerfBiosLevel: Annotated[NvU8, 13]
|
|
bIsD3HotTransition: Annotated[NvU8, 14]
|
|
bForcePowerStateFail: Annotated[NvU8, 15]
|
|
errorStatus: Annotated[NvU32, 16]
|
|
fastBootPowerState: Annotated[NvU32, 20]
|
|
bGC8Transition: Annotated[NvU8, 24]
|
|
bGC8InputRailCutOff: Annotated[NvU8, 25]
|
|
PNVPOWERSTATE_PARAMETERS: TypeAlias = c.POINTER[NVPOWERSTATE_PARAMETERS]
|
|
@c.record
|
|
class NV_GR_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 16
|
|
version: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
size: Annotated[NvU32, 8]
|
|
caps: Annotated[NvU32, 12]
|
|
class ChannelPBSize(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
PB_SIZE_4KB = ChannelPBSize.define('PB_SIZE_4KB', 0)
|
|
PB_SIZE_8KB = ChannelPBSize.define('PB_SIZE_8KB', 1)
|
|
PB_SIZE_16KB = ChannelPBSize.define('PB_SIZE_16KB', 2)
|
|
PB_SIZE_32KB = ChannelPBSize.define('PB_SIZE_32KB', 3)
|
|
PB_SIZE_64KB = ChannelPBSize.define('PB_SIZE_64KB', 4)
|
|
|
|
@c.record
|
|
class NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 40
|
|
channelInstance: Annotated[NvV32, 0]
|
|
hObjectBuffer: Annotated[NvHandle, 4]
|
|
hObjectNotify: Annotated[NvHandle, 8]
|
|
offset: Annotated[NvU32, 12]
|
|
pControl: Annotated[NvP64, 16]
|
|
flags: Annotated[NvU32, 24]
|
|
channelPBSize: Annotated[ChannelPBSize, 28]
|
|
subDeviceId: Annotated[NvU32, 32]
|
|
@c.record
|
|
class NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 16
|
|
channelInstance: Annotated[NvV32, 0]
|
|
hObjectNotify: Annotated[NvHandle, 4]
|
|
pControl: Annotated[NvP64, 8]
|
|
@c.record
|
|
class NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 20
|
|
hObjectError: Annotated[NvHandle, 0]
|
|
hObjectEccError: Annotated[NvHandle, 4]
|
|
hVASpace: Annotated[NvHandle, 8]
|
|
engineType: Annotated[NvU32, 12]
|
|
bIsCallingContextVgpuPlugin: Annotated[NvBool, 16]
|
|
@c.record
|
|
class NV_SWRUNLIST_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
engineId: Annotated[NvU32, 0]
|
|
maxTSGs: Annotated[NvU32, 4]
|
|
qosIntrEnableMask: Annotated[NvU32, 8]
|
|
@c.record
|
|
class NV_ME_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 8
|
|
size: Annotated[NvU32, 0]
|
|
caps: Annotated[NvU32, 4]
|
|
@c.record
|
|
class NV_BSP_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
size: Annotated[NvU32, 0]
|
|
prohibitMultipleInstances: Annotated[NvU32, 4]
|
|
engineInstance: Annotated[NvU32, 8]
|
|
@c.record
|
|
class NV_VP_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 80
|
|
size: Annotated[NvU32, 0]
|
|
caps: Annotated[NvU32, 4]
|
|
flags: Annotated[NvU32, 8]
|
|
altUcode: Annotated[NvU32, 12]
|
|
rawUcode: Annotated[NvP64, 16]
|
|
rawUcodeSize: Annotated[NvU32, 24]
|
|
numSubClasses: Annotated[NvU32, 28]
|
|
numSubSets: Annotated[NvU32, 32]
|
|
subClasses: Annotated[NvP64, 40]
|
|
prohibitMultipleInstances: Annotated[NvU32, 48]
|
|
pControl: Annotated[NvP64, 56]
|
|
hMemoryCmdBuffer: Annotated[NvHandle, 64]
|
|
offset: Annotated[NvU64, 72]
|
|
@c.record
|
|
class NV_PPP_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 8
|
|
size: Annotated[NvU32, 0]
|
|
prohibitMultipleInstances: Annotated[NvU32, 4]
|
|
@c.record
|
|
class NV_MSENC_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
size: Annotated[NvU32, 0]
|
|
prohibitMultipleInstances: Annotated[NvU32, 4]
|
|
engineInstance: Annotated[NvU32, 8]
|
|
@c.record
|
|
class NV_SEC2_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 8
|
|
size: Annotated[NvU32, 0]
|
|
prohibitMultipleInstances: Annotated[NvU32, 4]
|
|
@c.record
|
|
class NV_NVJPG_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
size: Annotated[NvU32, 0]
|
|
prohibitMultipleInstances: Annotated[NvU32, 4]
|
|
engineInstance: Annotated[NvU32, 8]
|
|
@c.record
|
|
class NV_OFA_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
size: Annotated[NvU32, 0]
|
|
prohibitMultipleInstances: Annotated[NvU32, 4]
|
|
engineInstance: Annotated[NvU32, 8]
|
|
@c.record
|
|
class NVOS61_PARAMETERS(c.Struct):
|
|
SIZE = 56
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
hVblank: Annotated[NvHandle, 8]
|
|
pProc: Annotated[OSVBLANKCALLBACKPROC, 16]
|
|
LogicalHead: Annotated[NvV32, 24]
|
|
pParm1: Annotated[ctypes.c_void_p, 32]
|
|
pParm2: Annotated[ctypes.c_void_p, 40]
|
|
bAdd: Annotated[NvU32, 48]
|
|
status: Annotated[NvV32, 52]
|
|
OSVBLANKCALLBACKPROC: TypeAlias = c.CFUNCTYPE[None, [ctypes.c_void_p, ctypes.c_void_p]]
|
|
@c.record
|
|
class NV_VASPACE_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 48
|
|
index: Annotated[NvU32, 0]
|
|
flags: Annotated[NvV32, 4]
|
|
vaSize: Annotated[NvU64, 8]
|
|
vaStartInternal: Annotated[NvU64, 16]
|
|
vaLimitInternal: Annotated[NvU64, 24]
|
|
bigPageSize: Annotated[NvU32, 32]
|
|
vaBase: Annotated[NvU64, 40]
|
|
@c.record
|
|
class NV_CTXSHARE_ALLOCATION_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
hVASpace: Annotated[NvHandle, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
subctxId: Annotated[NvU32, 8]
|
|
@c.record
|
|
class NV_TIMEOUT_CONTROL_PARAMETERS(c.Struct):
|
|
SIZE = 12
|
|
cmd: Annotated[NvU32, 0]
|
|
timeoutInMs: Annotated[NvU32, 4]
|
|
deviceInstance: Annotated[NvU32, 8]
|
|
class NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT = NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE.define('NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT', 0)
|
|
NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH = NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE.define('NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH', 1)
|
|
NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH = NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE.define('NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH', 2)
|
|
NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID = NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE.define('NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID', 3)
|
|
|
|
@c.record
|
|
class NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS(c.Struct):
|
|
SIZE = 528
|
|
bDirtyTracking: Annotated[NvBool, 0]
|
|
granularity: Annotated[NvU32, 4]
|
|
accessBitMask: Annotated[c.Array[NvU64, Literal[64]], 8]
|
|
noOfEntries: Annotated[NvU32, 520]
|
|
addrSpace: Annotated[NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE, 524]
|
|
@c.record
|
|
class NV_HOPPER_USERMODE_A_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bBar1Mapping: Annotated[NvBool, 0]
|
|
bPriv: Annotated[NvBool, 1]
|
|
@c.record
|
|
class struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
workSubmitToken: Annotated[NvU32, 0]
|
|
NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS: TypeAlias = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS
|
|
@c.record
|
|
class struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
bar2Addr: Annotated[c.Array[NvU64, Literal[2]], 0]
|
|
NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS: TypeAlias = struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
index: Annotated[NvU32, 0]
|
|
NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS: TypeAlias = struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS
|
|
NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS: TypeAlias = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS(c.Struct):
|
|
SIZE = 6
|
|
cpuCapability: Annotated[NvU8, 0]
|
|
gpusCapability: Annotated[NvU8, 1]
|
|
environment: Annotated[NvU8, 2]
|
|
ccFeature: Annotated[NvU8, 3]
|
|
devToolsMode: Annotated[NvU8, 4]
|
|
multiGpuMode: Annotated[NvU8, 5]
|
|
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bAcceptClientRequest: Annotated[NvBool, 0]
|
|
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bAcceptClientRequest: Annotated[NvBool, 0]
|
|
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
protectedMemSizeInKb: Annotated[NvU64, 8]
|
|
unprotectedMemSizeInKb: Annotated[NvU64, 16]
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
protectedMemSizeInKb: Annotated[NvU64, 8]
|
|
unprotectedMemSizeInKb: Annotated[NvU64, 16]
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
numSupportedSec2CCSecureChannels: Annotated[NvU32, 4]
|
|
numSupportedCeCCSecureChannels: Annotated[NvU32, 8]
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS(c.Struct):
|
|
SIZE = 9228
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
certChain: Annotated[c.Array[NvU8, Literal[4096]], 4]
|
|
certChainSize: Annotated[NvU32, 4100]
|
|
attestationCertChain: Annotated[c.Array[NvU8, Literal[5120]], 4104]
|
|
attestationCertChainSize: Annotated[NvU32, 9224]
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS(c.Struct):
|
|
SIZE = 12336
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
nonce: Annotated[c.Array[NvU8, Literal[32]], 4]
|
|
attestationReport: Annotated[c.Array[NvU8, Literal[8192]], 36]
|
|
attestationReportSize: Annotated[NvU32, 8228]
|
|
isCecAttestationReportPresent: Annotated[NvBool, 8232]
|
|
cecAttestationReport: Annotated[c.Array[NvU8, Literal[4096]], 8233]
|
|
cecAttestationReportSize: Annotated[NvU32, 12332]
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
maxSec2Channels: Annotated[NvU32, 4]
|
|
maxCeChannels: Annotated[NvU32, 8]
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
keyRotationState: Annotated[NvU32, 4]
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS: TypeAlias = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bEnable: Annotated[NvBool, 0]
|
|
bSkipSubmit: Annotated[NvBool, 1]
|
|
NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS: TypeAlias = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_BIND_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
engineType: Annotated[NvU32, 0]
|
|
NVA06C_CTRL_BIND_PARAMS: TypeAlias = struct_NVA06F_CTRL_BIND_PARAMS
|
|
@c.record
|
|
class struct_NVA06C_CTRL_TIMESLICE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
timesliceUs: Annotated[NvU64, 0]
|
|
NVA06C_CTRL_TIMESLICE_PARAMS: TypeAlias = struct_NVA06C_CTRL_TIMESLICE_PARAMS
|
|
NVA06C_CTRL_SET_TIMESLICE_PARAMS: TypeAlias = struct_NVA06C_CTRL_TIMESLICE_PARAMS
|
|
NVA06C_CTRL_GET_TIMESLICE_PARAMS: TypeAlias = struct_NVA06C_CTRL_TIMESLICE_PARAMS
|
|
@c.record
|
|
class struct_NVA06C_CTRL_PREEMPT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bWait: Annotated[NvBool, 0]
|
|
bManualTimeout: Annotated[NvBool, 1]
|
|
timeoutUs: Annotated[NvU32, 4]
|
|
NVA06C_CTRL_PREEMPT_PARAMS: TypeAlias = struct_NVA06C_CTRL_PREEMPT_PARAMS
|
|
@c.record
|
|
class struct_NVA06C_CTRL_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
tsgID: Annotated[NvU32, 0]
|
|
NVA06C_CTRL_GET_INFO_PARAMS: TypeAlias = struct_NVA06C_CTRL_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
tsgInterleaveLevel: Annotated[NvU32, 0]
|
|
NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS: TypeAlias = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS
|
|
NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS: TypeAlias = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS
|
|
NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS: TypeAlias = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS
|
|
class enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE.define('NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE', 0)
|
|
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE.define('NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B', 1)
|
|
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE.define('NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B', 2)
|
|
|
|
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE: TypeAlias = enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE
|
|
@c.record
|
|
class struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD(c.Struct):
|
|
SIZE = 4
|
|
size: Annotated[NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE, 0]
|
|
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD: TypeAlias = struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD
|
|
@c.record
|
|
class struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
l1: Annotated[NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD, 0]
|
|
t1: Annotated[NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD, 4]
|
|
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS: TypeAlias = struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS
|
|
@c.record
|
|
class struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS(c.Struct):
|
|
SIZE = 88
|
|
methodBufferMemdesc: Annotated[c.Array[NV2080_CTRL_INTERNAL_MEMDESC_INFO, Literal[2]], 0]
|
|
bar2Addr: Annotated[c.Array[NvU64, Literal[2]], 64]
|
|
numValidEntries: Annotated[NvU32, 80]
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO(c.Struct):
|
|
SIZE = 32
|
|
base: Annotated[NvU64, 0]
|
|
size: Annotated[NvU64, 8]
|
|
alignment: Annotated[NvU64, 16]
|
|
addressSpace: Annotated[NvU32, 24]
|
|
cpuCacheAttrib: Annotated[NvU32, 28]
|
|
NV2080_CTRL_INTERNAL_MEMDESC_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO
|
|
NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS: TypeAlias = struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS
|
|
@c.record
|
|
class struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bRealtime: Annotated[NvBool, 0]
|
|
NVA06C_CTRL_MAKE_REALTIME_PARAMS: TypeAlias = struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS
|
|
NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS: TypeAlias = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS
|
|
NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS: TypeAlias = struct_NVA06C_CTRL_TIMESLICE_PARAMS
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
subDeviceId: Annotated[NvU32, 4]
|
|
pFmt: Annotated[NvP64, 8]
|
|
NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS
|
|
@c.record
|
|
class struct_NV_CTRL_VASPACE_PAGE_LEVEL(c.Struct):
|
|
SIZE = 112
|
|
pFmt: Annotated[c.POINTER[struct_MMU_FMT_LEVEL], 0]
|
|
levelFmt: Annotated[MMU_FMT_LEVEL, 8]
|
|
sublevelFmt: Annotated[c.Array[MMU_FMT_LEVEL, Literal[2]], 32]
|
|
physAddress: Annotated[NvU64, 80]
|
|
aperture: Annotated[NvU32, 88]
|
|
size: Annotated[NvU64, 96]
|
|
entryIndex: Annotated[NvU32, 104]
|
|
@c.record
|
|
class struct_MMU_FMT_LEVEL(c.Struct):
|
|
SIZE = 24
|
|
virtAddrBitLo: Annotated[NvU8, 0]
|
|
virtAddrBitHi: Annotated[NvU8, 1]
|
|
entrySize: Annotated[NvU8, 2]
|
|
bPageTable: Annotated[NvBool, 3]
|
|
numSubLevels: Annotated[NvU8, 4]
|
|
pageLevelIdTag: Annotated[NvU32, 8]
|
|
subLevels: Annotated[c.POINTER[struct_MMU_FMT_LEVEL], 16]
|
|
MMU_FMT_LEVEL: TypeAlias = struct_MMU_FMT_LEVEL
|
|
NV_CTRL_VASPACE_PAGE_LEVEL: TypeAlias = struct_NV_CTRL_VASPACE_PAGE_LEVEL
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS(c.Struct):
|
|
SIZE = 712
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
subDeviceId: Annotated[NvU32, 4]
|
|
virtAddress: Annotated[NvU64, 8]
|
|
pageSize: Annotated[NvU64, 16]
|
|
flags: Annotated[NvU64, 24]
|
|
numLevels: Annotated[NvU32, 32]
|
|
levels: Annotated[c.Array[NV_CTRL_VASPACE_PAGE_LEVEL, Literal[6]], 40]
|
|
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
subDeviceId: Annotated[NvU32, 4]
|
|
pageSize: Annotated[NvU64, 8]
|
|
virtAddrLo: Annotated[NvU64, 16]
|
|
virtAddrHi: Annotated[NvU64, 24]
|
|
NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
subDeviceId: Annotated[NvU32, 4]
|
|
pageSize: Annotated[NvU64, 8]
|
|
virtAddrLo: Annotated[NvU64, 16]
|
|
virtAddrHi: Annotated[NvU64, 24]
|
|
NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS
|
|
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS(c.Struct):
|
|
SIZE = 184
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
subDeviceId: Annotated[NvU32, 4]
|
|
pageSize: Annotated[NvU64, 8]
|
|
virtAddrLo: Annotated[NvU64, 16]
|
|
virtAddrHi: Annotated[NvU64, 24]
|
|
numLevelsToCopy: Annotated[NvU32, 32]
|
|
levels: Annotated[c.Array[struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level, Literal[6]], 40]
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level(c.Struct):
|
|
SIZE = 24
|
|
physAddress: Annotated[NvU64, 0]
|
|
size: Annotated[NvU64, 8]
|
|
aperture: Annotated[NvU32, 16]
|
|
pageShift: Annotated[NvU8, 20]
|
|
NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
subDeviceId: Annotated[NvU32, 4]
|
|
requiredVaRange: Annotated[NvU64, 8]
|
|
NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
hSubDevice: Annotated[NvHandle, 0]
|
|
subDeviceId: Annotated[NvU32, 4]
|
|
bytesFree: Annotated[NvU64, 8]
|
|
bytesTotal: Annotated[NvU64, 16]
|
|
largestFreeOffset: Annotated[NvU64, 24]
|
|
largestFreeSize: Annotated[NvU64, 32]
|
|
usableBytesFree: Annotated[NvU64, 40]
|
|
numFreeBlocks: Annotated[NvU32, 48]
|
|
NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS: TypeAlias = struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS
|
|
NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS: TypeAlias = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS
|
|
NVA06F_CTRL_BIND_PARAMS: TypeAlias = struct_NVA06F_CTRL_BIND_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bNotifyEachChannelInTSG: Annotated[NvBool, 0]
|
|
NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS: TypeAlias = struct_NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
channelInterleaveLevel: Annotated[NvU32, 0]
|
|
NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS: TypeAlias = struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS
|
|
NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS: TypeAlias = struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS
|
|
NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS: TypeAlias = struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_RESTART_RUNLIST_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bForceRestart: Annotated[NvBool, 0]
|
|
bBypassWait: Annotated[NvBool, 1]
|
|
NVA06F_CTRL_RESTART_RUNLIST_PARAMS: TypeAlias = struct_NVA06F_CTRL_RESTART_RUNLIST_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bImmediate: Annotated[NvBool, 0]
|
|
NVA06F_CTRL_STOP_CHANNEL_PARAMS: TypeAlias = struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS
|
|
@c.record
|
|
class struct_NVA06F_CTRL_GET_CONTEXT_ID_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
contextId: Annotated[NvU32, 0]
|
|
NVA06F_CTRL_GET_CONTEXT_ID_PARAMS: TypeAlias = struct_NVA06F_CTRL_GET_CONTEXT_ID_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hObject: Annotated[NvHandle, 0]
|
|
mapFlags: Annotated[NvU32, 4]
|
|
addrSpaceType: Annotated[NvU32, 8]
|
|
NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hObject: Annotated[NvHandle, 0]
|
|
index: Annotated[NvU32, 4]
|
|
data: Annotated[struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data, 8]
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data(c.Struct):
|
|
SIZE = 8
|
|
hResult: Annotated[NvHandle, 0]
|
|
iResult: Annotated[NvU64, 0]
|
|
NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hObject: Annotated[NvHandle, 0]
|
|
hClient: Annotated[NvHandle, 4]
|
|
maskResult: Annotated[RS_ACCESS_MASK, 8]
|
|
NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
sharePolicy: Annotated[RS_SHARE_POLICY, 0]
|
|
NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hParent: Annotated[NvHandle, 0]
|
|
classId: Annotated[NvU32, 4]
|
|
hObject: Annotated[NvHandle, 8]
|
|
NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS: TypeAlias = struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hObject: Annotated[NvHandle, 0]
|
|
sharePolicy: Annotated[RS_SHARE_POLICY, 4]
|
|
NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hObject1: Annotated[NvHandle, 0]
|
|
hObject2: Annotated[NvHandle, 4]
|
|
bDuplicates: Annotated[NvBool, 8]
|
|
NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
devDescriptor: Annotated[NvU64, 0]
|
|
channel: Annotated[NvU32, 8]
|
|
NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS: TypeAlias = struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
state: Annotated[NvU32, 0]
|
|
count: Annotated[NvU32, 4]
|
|
missedCount: Annotated[NvU32, 8]
|
|
bCircularBuffer: Annotated[NvBool, 12]
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS: TypeAlias = struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
state: Annotated[NvU32, 0]
|
|
bCircularBuffer: Annotated[NvBool, 4]
|
|
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS: TypeAlias = struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY(c.Struct):
|
|
SIZE = 56
|
|
counter: Annotated[NvU64, 0]
|
|
line: Annotated[NvU32, 8]
|
|
filename: Annotated[c.Array[NvU8, Literal[12]], 12]
|
|
tag: Annotated[NvU16, 24]
|
|
cpuNum: Annotated[NvU8, 26]
|
|
irql: Annotated[NvU8, 27]
|
|
threadId: Annotated[NvU64, 32]
|
|
data0: Annotated[NvU32, 40]
|
|
data1: Annotated[NvU32, 44]
|
|
data2: Annotated[NvU32, 48]
|
|
NV0000_CTRL_DIAG_LOCK_METER_ENTRY: TypeAlias = struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY
|
|
@c.record
|
|
class struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS(c.Struct):
|
|
SIZE = 3592
|
|
entryCount: Annotated[NvU32, 0]
|
|
entries: Annotated[c.Array[NV0000_CTRL_DIAG_LOCK_METER_ENTRY, Literal[64]], 8]
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS: TypeAlias = struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS
|
|
@c.record
|
|
class struct_RPC_METER_ENTRY(c.Struct):
|
|
SIZE = 32
|
|
startTimeInNs: Annotated[NvU64, 0]
|
|
endTimeInNs: Annotated[NvU64, 8]
|
|
rpcDataTag: Annotated[NvU64, 16]
|
|
rpcExtraData: Annotated[NvU64, 24]
|
|
RPC_METER_ENTRY: TypeAlias = struct_RPC_METER_ENTRY
|
|
@c.record
|
|
class struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rpcProfileCmd: Annotated[NvU32, 0]
|
|
NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS: TypeAlias = struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS(c.Struct):
|
|
SIZE = 3224
|
|
firstEntryOffset: Annotated[NvU32, 0]
|
|
outputEntryCount: Annotated[NvU32, 4]
|
|
remainingEntryCount: Annotated[NvU32, 8]
|
|
elapsedTimeInNs: Annotated[NvU64, 16]
|
|
rpcProfilerBuffer: Annotated[c.Array[RPC_METER_ENTRY, Literal[100]], 24]
|
|
NV0000_CTRL_DIAG_DUMP_RPC_PARAMS: TypeAlias = struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
event: Annotated[NvU32, 0]
|
|
action: Annotated[NvU32, 4]
|
|
NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS: TypeAlias = struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
event: Annotated[NvU32, 0]
|
|
status: Annotated[NvU32, 4]
|
|
NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS: TypeAlias = struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS(c.Struct):
|
|
SIZE = 128
|
|
gpuIds: Annotated[c.Array[NvU32, Literal[32]], 0]
|
|
NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
gpuId: Annotated[NvU32, 0]
|
|
gpuFlags: Annotated[NvU32, 4]
|
|
deviceInstance: Annotated[NvU32, 8]
|
|
subDeviceInstance: Annotated[NvU32, 12]
|
|
szName: Annotated[NvP64, 16]
|
|
sliStatus: Annotated[NvU32, 24]
|
|
boardId: Annotated[NvU32, 28]
|
|
gpuInstance: Annotated[NvU32, 32]
|
|
numaId: Annotated[NvS32, 36]
|
|
NV0000_CTRL_GPU_GET_ID_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
gpuId: Annotated[NvU32, 0]
|
|
gpuFlags: Annotated[NvU32, 4]
|
|
deviceInstance: Annotated[NvU32, 8]
|
|
subDeviceInstance: Annotated[NvU32, 12]
|
|
sliStatus: Annotated[NvU32, 16]
|
|
boardId: Annotated[NvU32, 20]
|
|
gpuInstance: Annotated[NvU32, 24]
|
|
numaId: Annotated[NvS32, 28]
|
|
NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpuId: Annotated[NvU32, 0]
|
|
status: Annotated[NvU32, 4]
|
|
NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
deviceIds: Annotated[NvU32, 0]
|
|
NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS(c.Struct):
|
|
SIZE = 256
|
|
gpuIds: Annotated[c.Array[NvU32, Literal[32]], 0]
|
|
excludedGpuIds: Annotated[c.Array[NvU32, Literal[32]], 128]
|
|
NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gpuId: Annotated[NvU32, 0]
|
|
domain: Annotated[NvU32, 4]
|
|
bus: Annotated[NvU16, 8]
|
|
slot: Annotated[NvU16, 10]
|
|
NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS(c.Struct):
|
|
SIZE = 132
|
|
gpuIds: Annotated[c.Array[NvU32, Literal[32]], 0]
|
|
failedId: Annotated[NvU32, 128]
|
|
NV0000_CTRL_GPU_ATTACH_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS(c.Struct):
|
|
SIZE = 128
|
|
gpuIds: Annotated[c.Array[NvU32, Literal[32]], 0]
|
|
NV0000_CTRL_GPU_DETACH_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_VIDEO_LINKS(c.Struct):
|
|
SIZE = 36
|
|
gpuId: Annotated[NvU32, 0]
|
|
connectedGpuIds: Annotated[c.Array[NvU32, Literal[8]], 4]
|
|
NV0000_CTRL_GPU_VIDEO_LINKS: TypeAlias = struct_NV0000_CTRL_GPU_VIDEO_LINKS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS(c.Struct):
|
|
SIZE = 1152
|
|
links: Annotated[c.Array[NV0000_CTRL_GPU_VIDEO_LINKS, Literal[32]], 0]
|
|
NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpuId: Annotated[NvU32, 0]
|
|
svmSize: Annotated[NvU32, 4]
|
|
NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS(c.Struct):
|
|
SIZE = 272
|
|
gpuUuid: Annotated[c.Array[NvU8, Literal[256]], 0]
|
|
flags: Annotated[NvU32, 256]
|
|
gpuId: Annotated[NvU32, 260]
|
|
deviceInstance: Annotated[NvU32, 264]
|
|
subdeviceInstance: Annotated[NvU32, 268]
|
|
NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS(c.Struct):
|
|
SIZE = 268
|
|
gpuId: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
gpuUuid: Annotated[c.Array[NvU8, Literal[256]], 8]
|
|
uuidStrLen: Annotated[NvU32, 264]
|
|
NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gpuId: Annotated[NvU32, 0]
|
|
newState: Annotated[NvU32, 4]
|
|
flags: Annotated[NvU32, 8]
|
|
NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gpuId: Annotated[NvU32, 0]
|
|
drainState: Annotated[NvU32, 4]
|
|
flags: Annotated[NvU32, 8]
|
|
NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_DISCOVER_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
domain: Annotated[NvU32, 0]
|
|
bus: Annotated[NvU8, 4]
|
|
slot: Annotated[NvU8, 5]
|
|
function: Annotated[NvU8, 6]
|
|
NV0000_CTRL_GPU_DISCOVER_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_DISCOVER_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
enableMask: Annotated[NvU32, 0]
|
|
NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gpuId: Annotated[NvU32, 0]
|
|
mask: Annotated[NvU32, 4]
|
|
bSkipHwNvlinkDisable: Annotated[NvBool, 8]
|
|
NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 396
|
|
hContext: Annotated[NvHandle, 0]
|
|
opType: Annotated[NvU32, 4]
|
|
index: Annotated[NvV32, 8]
|
|
dataType: Annotated[NvU32, 12]
|
|
data: Annotated[struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data, 16]
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data(c.Struct):
|
|
SIZE = 380
|
|
configSet: Annotated[struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configSet, 0]
|
|
configEx: Annotated[struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configEx, 0]
|
|
reservedProperty: Annotated[struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_reservedProperty, 0]
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configSet(c.Struct):
|
|
SIZE = 8
|
|
newValue: Annotated[NvU32, 0]
|
|
oldValue: Annotated[NvU32, 4]
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configEx(c.Struct):
|
|
SIZE = 380
|
|
paramData: Annotated[c.Array[NvU8, Literal[373]], 0]
|
|
paramSize: Annotated[NvU32, 376]
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_reservedProperty(c.Struct):
|
|
SIZE = 48
|
|
propertyId: Annotated[NvU32, 0]
|
|
propertyIn: Annotated[c.Array[NvU32, Literal[6]], 4]
|
|
propertyOut: Annotated[c.Array[NvU32, Literal[5]], 28]
|
|
NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
hDevice: Annotated[NvHandle, 0]
|
|
hChannel: Annotated[NvHandle, 4]
|
|
numChannels: Annotated[NvV32, 8]
|
|
phClients: Annotated[NvP64, 16]
|
|
phDevices: Annotated[NvP64, 24]
|
|
phChannels: Annotated[NvP64, 32]
|
|
flags: Annotated[NvV32, 40]
|
|
timeout: Annotated[NvV32, 44]
|
|
NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
image: Annotated[NvU8, 0]
|
|
totalSize: Annotated[NvU64, 8]
|
|
pData: Annotated[NvP64, 16]
|
|
NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
mode: Annotated[NvU8, 0]
|
|
NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
mode: Annotated[NvU8, 0]
|
|
bwModeScope: Annotated[NvU8, 1]
|
|
NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_ACTIVE_DEVICE(c.Struct):
|
|
SIZE = 12
|
|
gpuId: Annotated[NvU32, 0]
|
|
gpuInstanceId: Annotated[NvU32, 4]
|
|
computeInstanceId: Annotated[NvU32, 8]
|
|
NV0000_CTRL_GPU_ACTIVE_DEVICE: TypeAlias = struct_NV0000_CTRL_GPU_ACTIVE_DEVICE
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS(c.Struct):
|
|
SIZE = 3076
|
|
numDevices: Annotated[NvU32, 0]
|
|
devices: Annotated[c.Array[NV0000_CTRL_GPU_ACTIVE_DEVICE, Literal[256]], 4]
|
|
NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gpuId: Annotated[NvU32, 0]
|
|
NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gpuId: Annotated[NvU32, 0]
|
|
NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gpuId: Annotated[NvU32, 0]
|
|
pid: Annotated[NvU32, 4]
|
|
newState: Annotated[NvU32, 8]
|
|
NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gpuId: Annotated[NvU32, 0]
|
|
pid: Annotated[NvU32, 4]
|
|
state: Annotated[NvU32, 8]
|
|
NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
gpuId: Annotated[NvU32, 0]
|
|
pid: Annotated[NvU32, 4]
|
|
subPid: Annotated[NvU32, 8]
|
|
gpuUtil: Annotated[NvU32, 12]
|
|
fbUtil: Annotated[NvU32, 16]
|
|
maxFbUsage: Annotated[NvU64, 24]
|
|
startTime: Annotated[NvU64, 32]
|
|
endTime: Annotated[NvU64, 40]
|
|
NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS(c.Struct):
|
|
SIZE = 16012
|
|
gpuId: Annotated[NvU32, 0]
|
|
pid: Annotated[NvU32, 4]
|
|
pidTbl: Annotated[c.Array[NvU32, Literal[4000]], 8]
|
|
pidCount: Annotated[NvU32, 16008]
|
|
NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpuId: Annotated[NvU32, 0]
|
|
pid: Annotated[NvU32, 4]
|
|
NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS: TypeAlias = struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
gsyncIds: Annotated[c.Array[NvU32, Literal[4]], 0]
|
|
NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS: TypeAlias = struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gsyncId: Annotated[NvU32, 0]
|
|
gsyncFlags: Annotated[NvU32, 4]
|
|
gsyncInstance: Annotated[NvU32, 8]
|
|
NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
component: Annotated[NvU32, 0]
|
|
size: Annotated[NvU32, 4]
|
|
NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pBuffer: Annotated[NvP64, 0]
|
|
component: Annotated[NvU32, 8]
|
|
size: Annotated[NvU32, 12]
|
|
NV0000_CTRL_NVD_GET_DUMP_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
timestamp: Annotated[NvU64, 0]
|
|
cpuClkId: Annotated[NvU8, 8]
|
|
NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS(c.Struct):
|
|
SIZE = 15404
|
|
component: Annotated[NvU32, 0]
|
|
version: Annotated[NvU32, 4]
|
|
runtimeSizes: Annotated[c.Array[NvU8, Literal[16]], 8]
|
|
printFlags: Annotated[NvU32, 24]
|
|
signature: Annotated[c.Array[NvU32, Literal[4]], 28]
|
|
bufferTags: Annotated[c.Array[NvU32, Literal[3840]], 44]
|
|
NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
component: Annotated[NvU32, 0]
|
|
buffer: Annotated[NvU32, 4]
|
|
tag: Annotated[NvU32, 8]
|
|
size: Annotated[NvU32, 12]
|
|
flags: Annotated[NvU32, 16]
|
|
pos: Annotated[NvU32, 20]
|
|
overflow: Annotated[NvU32, 24]
|
|
NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS(c.Struct):
|
|
SIZE = 4016
|
|
component: Annotated[NvU32, 0]
|
|
buffer: Annotated[NvU32, 4]
|
|
blockNum: Annotated[NvU32, 8]
|
|
size: Annotated[NvU32, 12]
|
|
data: Annotated[c.Array[NvU8, Literal[4000]], 16]
|
|
NV0000_CTRL_NVD_GET_NVLOG_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY(c.Struct):
|
|
SIZE = 12
|
|
tag: Annotated[NvU32, 0]
|
|
value: Annotated[NvU32, 4]
|
|
attribute: Annotated[NvU32, 8]
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY: TypeAlias = struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS(c.Struct):
|
|
SIZE = 2436
|
|
reqIdx: Annotated[NvU16, 0]
|
|
rptIdx: Annotated[NvU16, 2]
|
|
GPUTag: Annotated[NvU32, 4]
|
|
rptTime: Annotated[NvU32, 8]
|
|
startIdx: Annotated[NvU16, 12]
|
|
endIdx: Annotated[NvU16, 14]
|
|
rptType: Annotated[NvU16, 16]
|
|
flags: Annotated[NvU32, 20]
|
|
rptCount: Annotated[NvU16, 24]
|
|
owner: Annotated[NvU32, 28]
|
|
processId: Annotated[NvU32, 32]
|
|
report: Annotated[c.Array[NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY, Literal[200]], 36]
|
|
NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS: TypeAlias = struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
tsBufferSize: Annotated[NvU32, 0]
|
|
pTSBuffer: Annotated[NvP64, 8]
|
|
NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS: TypeAlias = struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS(c.Struct):
|
|
SIZE = 104
|
|
subProcessID: Annotated[NvU32, 0]
|
|
subProcessName: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[100]], 4]
|
|
NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS: TypeAlias = struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bIsSubProcessDisabled: Annotated[NvBool, 0]
|
|
NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS: TypeAlias = struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS
|
|
@c.record
|
|
class struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnabled: Annotated[NvBool, 0]
|
|
NV0000_SYNC_GPU_BOOST_INFO_PARAMS: TypeAlias = struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG(c.Struct):
|
|
SIZE = 140
|
|
gpuCount: Annotated[NvU32, 0]
|
|
gpuIds: Annotated[c.Array[NvU32, Literal[32]], 4]
|
|
boostGroupId: Annotated[NvU32, 132]
|
|
bBridgeless: Annotated[NvBool, 136]
|
|
NV0000_SYNC_GPU_BOOST_GROUP_CONFIG: TypeAlias = struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG
|
|
@c.record
|
|
class struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS(c.Struct):
|
|
SIZE = 140
|
|
boostConfig: Annotated[NV0000_SYNC_GPU_BOOST_GROUP_CONFIG, 0]
|
|
NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS: TypeAlias = struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
boostGroupId: Annotated[NvU32, 0]
|
|
NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS: TypeAlias = struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS
|
|
@c.record
|
|
class struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS(c.Struct):
|
|
SIZE = 2244
|
|
groupCount: Annotated[NvU32, 0]
|
|
pBoostGroups: Annotated[c.Array[NV0000_SYNC_GPU_BOOST_GROUP_CONFIG, Literal[16]], 4]
|
|
NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS: TypeAlias = struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
featuresMask: Annotated[NvU32, 0]
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
sizeOfStrings: Annotated[NvU32, 0]
|
|
pDriverVersionBuffer: Annotated[NvP64, 8]
|
|
pVersionBuffer: Annotated[NvP64, 16]
|
|
pTitleBuffer: Annotated[NvP64, 24]
|
|
changelistNumber: Annotated[NvU32, 32]
|
|
officialChangelistNumber: Annotated[NvU32, 36]
|
|
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS
|
|
class enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA = enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE.define('NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA', 0)
|
|
NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE = enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE.define('NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE', 1)
|
|
|
|
NV0000_CTRL_SYSTEM_SH_SOC_TYPE: TypeAlias = enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS(c.Struct):
|
|
SIZE = 108
|
|
type: Annotated[NvU32, 0]
|
|
capabilities: Annotated[NvU32, 4]
|
|
clock: Annotated[NvU32, 8]
|
|
L1DataCacheSize: Annotated[NvU32, 12]
|
|
L2DataCacheSize: Annotated[NvU32, 16]
|
|
dataCacheLineSize: Annotated[NvU32, 20]
|
|
numLogicalCpus: Annotated[NvU32, 24]
|
|
numPhysicalCpus: Annotated[NvU32, 28]
|
|
name: Annotated[c.Array[NvU8, Literal[52]], 32]
|
|
family: Annotated[NvU32, 84]
|
|
model: Annotated[NvU32, 88]
|
|
stepping: Annotated[NvU8, 92]
|
|
coresOnDie: Annotated[NvU32, 96]
|
|
bCCEnabled: Annotated[NvBool, 100]
|
|
selfHostedSocType: Annotated[NV0000_CTRL_SYSTEM_SH_SOC_TYPE, 104]
|
|
NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS(c.Struct):
|
|
SIZE = 152
|
|
vendorId: Annotated[NvU16, 0]
|
|
deviceId: Annotated[NvU16, 2]
|
|
subSysVendorId: Annotated[NvU16, 4]
|
|
subSysDeviceId: Annotated[NvU16, 6]
|
|
HBvendorId: Annotated[NvU16, 8]
|
|
HBdeviceId: Annotated[NvU16, 10]
|
|
HBsubSysVendorId: Annotated[NvU16, 12]
|
|
HBsubSysDeviceId: Annotated[NvU16, 14]
|
|
sliBondId: Annotated[NvU32, 16]
|
|
vendorNameString: Annotated[c.Array[NvU8, Literal[32]], 20]
|
|
subSysVendorNameString: Annotated[c.Array[NvU8, Literal[32]], 52]
|
|
chipsetNameString: Annotated[c.Array[NvU8, Literal[32]], 84]
|
|
sliBondNameString: Annotated[c.Array[NvU8, Literal[32]], 116]
|
|
flags: Annotated[NvU32, 148]
|
|
NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bIsPresent: Annotated[NvBool, 0]
|
|
NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
waitApiLock: Annotated[NvU64, 0]
|
|
holdRoApiLock: Annotated[NvU64, 8]
|
|
holdRwApiLock: Annotated[NvU64, 16]
|
|
waitGpuLock: Annotated[NvU64, 24]
|
|
holdGpuLock: Annotated[NvU64, 32]
|
|
NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS(c.Struct):
|
|
SIZE = 132
|
|
numClasses: Annotated[NvU32, 0]
|
|
classes: Annotated[c.Array[NvU32, Literal[32]], 4]
|
|
NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
eventType: Annotated[NvU32, 0]
|
|
eventData: Annotated[NvU32, 4]
|
|
bEventDataForced: Annotated[NvBool, 8]
|
|
NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
systemType: Annotated[NvU32, 0]
|
|
NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS: TypeAlias = struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS(c.Struct):
|
|
SIZE = 520
|
|
cmd: Annotated[NvU32, 0]
|
|
count: Annotated[NvU32, 4]
|
|
data: Annotated[c.Array[NvU8, Literal[512]], 8]
|
|
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_HWBC_INFO(c.Struct):
|
|
SIZE = 16
|
|
hwbcId: Annotated[NvU32, 0]
|
|
firmwareVersion: Annotated[NvU32, 4]
|
|
subordinateBus: Annotated[NvU32, 8]
|
|
secondaryBus: Annotated[NvU32, 12]
|
|
NV0000_CTRL_SYSTEM_HWBC_INFO: TypeAlias = struct_NV0000_CTRL_SYSTEM_HWBC_INFO
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS(c.Struct):
|
|
SIZE = 2048
|
|
hwbcInfo: Annotated[c.Array[NV0000_CTRL_SYSTEM_HWBC_INFO, Literal[128]], 0]
|
|
NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
command: Annotated[NvU16, 0]
|
|
locale: Annotated[NvU16, 2]
|
|
data: Annotated[NvU32, 4]
|
|
NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 136
|
|
cmdCount: Annotated[NvU32, 0]
|
|
succeeded: Annotated[NvU32, 4]
|
|
cmdData: Annotated[c.Array[struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_cmdData, Literal[16]], 8]
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_cmdData(c.Struct):
|
|
SIZE = 8
|
|
command: Annotated[NvU16, 0]
|
|
locale: Annotated[NvU16, 2]
|
|
data: Annotated[NvU32, 4]
|
|
NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS(c.Struct):
|
|
SIZE = 176
|
|
gpuIds: Annotated[c.Array[NvU32, Literal[32]], 0]
|
|
gpuCount: Annotated[NvU32, 128]
|
|
p2pCaps: Annotated[NvU32, 132]
|
|
p2pOptimalReadCEs: Annotated[NvU32, 136]
|
|
p2pOptimalWriteCEs: Annotated[NvU32, 140]
|
|
p2pCapsStatus: Annotated[c.Array[NvU8, Literal[9]], 144]
|
|
busPeerIds: Annotated[NvP64, 160]
|
|
busEgmPeerIds: Annotated[NvP64, 168]
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 8348
|
|
gpuIds: Annotated[c.Array[NvU32, Literal[32]], 0]
|
|
gpuCount: Annotated[NvU32, 128]
|
|
p2pCaps: Annotated[NvU32, 132]
|
|
p2pOptimalReadCEs: Annotated[NvU32, 136]
|
|
p2pOptimalWriteCEs: Annotated[NvU32, 140]
|
|
p2pCapsStatus: Annotated[c.Array[NvU8, Literal[9]], 144]
|
|
busPeerIds: Annotated[c.Array[NvU32, Literal[1024]], 156]
|
|
busEgmPeerIds: Annotated[c.Array[NvU32, Literal[1024]], 4252]
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS
|
|
NV0000_CTRL_P2P_CAPS_MATRIX_ROW: TypeAlias = c.Array[Annotated[int, ctypes.c_uint32], Literal[8]]
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS(c.Struct):
|
|
SIZE = 1352
|
|
grpACount: Annotated[NvU32, 0]
|
|
grpBCount: Annotated[NvU32, 4]
|
|
gpuIdGrpA: Annotated[c.Array[NvU32, Literal[8]], 8]
|
|
gpuIdGrpB: Annotated[c.Array[NvU32, Literal[8]], 40]
|
|
p2pCaps: Annotated[c.Array[NV0000_CTRL_P2P_CAPS_MATRIX_ROW, Literal[8]], 72]
|
|
a2bOptimalReadCes: Annotated[c.Array[NV0000_CTRL_P2P_CAPS_MATRIX_ROW, Literal[8]], 328]
|
|
a2bOptimalWriteCes: Annotated[c.Array[NV0000_CTRL_P2P_CAPS_MATRIX_ROW, Literal[8]], 584]
|
|
b2aOptimalReadCes: Annotated[c.Array[NV0000_CTRL_P2P_CAPS_MATRIX_ROW, Literal[8]], 840]
|
|
b2aOptimalWriteCes: Annotated[c.Array[NV0000_CTRL_P2P_CAPS_MATRIX_ROW, Literal[8]], 1096]
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
cmd: Annotated[NvU32, 0]
|
|
input: Annotated[c.Array[NvS32, Literal[2]], 4]
|
|
result: Annotated[c.Array[NvS32, Literal[4]], 12]
|
|
NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 148
|
|
objHndl: Annotated[NvU32, 0]
|
|
blockId: Annotated[NvU32, 4]
|
|
nextExpectedSampleTimems: Annotated[NvU32, 8]
|
|
countersReq: Annotated[NvU32, 12]
|
|
countersReturned: Annotated[NvU32, 16]
|
|
counterBlock: Annotated[c.Array[NvU32, Literal[32]], 20]
|
|
NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS
|
|
NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS
|
|
NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS(c.Struct):
|
|
SIZE = 1164
|
|
cmd: Annotated[NvU32, 0]
|
|
input: Annotated[NvU32, 4]
|
|
resultSz: Annotated[NvU32, 8]
|
|
result: Annotated[c.Array[NvU32, Literal[288]], 12]
|
|
NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
method: Annotated[NvU32, 0]
|
|
inData: Annotated[NvP64, 8]
|
|
inDataSize: Annotated[NvU16, 16]
|
|
outStatus: Annotated[NvU32, 20]
|
|
outData: Annotated[NvP64, 24]
|
|
outDataSize: Annotated[NvU16, 32]
|
|
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
moduleMask: Annotated[NvU32, 0]
|
|
NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE(c.Struct):
|
|
SIZE = 8
|
|
frameTime: Annotated[NvU16, 0]
|
|
renderTime: Annotated[NvU16, 2]
|
|
targetTime: Annotated[NvU16, 4]
|
|
sleepTime: Annotated[NvU8, 6]
|
|
sampleNumber: Annotated[NvU8, 7]
|
|
NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS(c.Struct):
|
|
SIZE = 514
|
|
samples: Annotated[c.Array[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE, Literal[64]], 0]
|
|
nextSampleNumber: Annotated[NvU8, 512]
|
|
NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
sampleData: Annotated[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE, 0]
|
|
NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS(c.Struct):
|
|
SIZE = 1288
|
|
szHostDriverVersionBuffer: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[256]], 0]
|
|
szHostVersionBuffer: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[256]], 256]
|
|
szHostTitleBuffer: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[256]], 512]
|
|
szPluginTitleBuffer: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[256]], 768]
|
|
szHostUnameBuffer: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[256]], 1024]
|
|
iHostChangelistNumber: Annotated[NvU32, 1280]
|
|
iPluginChangelistNumber: Annotated[NvU32, 1284]
|
|
NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS(c.Struct):
|
|
SIZE = 65
|
|
gpuCount: Annotated[NvU8, 0]
|
|
gpuBus: Annotated[c.Array[NvU8, Literal[32]], 1]
|
|
gpuExternalPowerStatus: Annotated[c.Array[NvU8, Literal[32]], 33]
|
|
NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
privStatusFlags: Annotated[NvU8, 0]
|
|
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS
|
|
class enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS.define('NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP', 1)
|
|
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS.define('NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED', 2)
|
|
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS.define('NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS', 3)
|
|
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS.define('NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED', 4)
|
|
|
|
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS: TypeAlias = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
fabricStatus: Annotated[NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS, 0]
|
|
NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
host_min_supported_version: Annotated[NvU32, 0]
|
|
host_max_supported_version: Annotated[NvU32, 4]
|
|
user_min_supported_version: Annotated[NvU32, 8]
|
|
user_max_supported_version: Annotated[NvU32, 12]
|
|
NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS: TypeAlias = struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
min_version: Annotated[NvU32, 0]
|
|
max_version: Annotated[NvU32, 4]
|
|
NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS: TypeAlias = struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
rm_instance_id: Annotated[NvU64, 0]
|
|
NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT(c.Struct):
|
|
SIZE = 24
|
|
batteryStateOfChargePercent: Annotated[NvU8, 0]
|
|
batteryCurrentLimitmA: Annotated[NvU32, 4]
|
|
restOfSytemReservedPowermW: Annotated[NvU32, 8]
|
|
minCpuTdpmW: Annotated[NvU32, 12]
|
|
maxCpuTdpmW: Annotated[NvU32, 16]
|
|
shortTimescaleBatteryCurrentLimitmA: Annotated[NvU32, 20]
|
|
NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT: TypeAlias = struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS(c.Struct):
|
|
SIZE = 860
|
|
gpuId: Annotated[NvU32, 0]
|
|
tpp: Annotated[NvU32, 4]
|
|
ratedTgp: Annotated[NvU32, 8]
|
|
subFunc: Annotated[NvU32, 12]
|
|
ctgpOffsetmW: Annotated[NvS32, 16]
|
|
targetTppOffsetmW: Annotated[NvS32, 20]
|
|
maxOutputOffsetmW: Annotated[NvS32, 24]
|
|
minOutputOffsetmW: Annotated[NvS32, 28]
|
|
ctgpBattOffsetmW: Annotated[NvS32, 32]
|
|
targetTppBattOffsetmW: Annotated[NvS32, 36]
|
|
dcRosReserveOverridemW: Annotated[NvU32, 40]
|
|
dcTspLongTimescaleLimitmA: Annotated[NvU32, 44]
|
|
dcTspShortTimescaleLimitmA: Annotated[NvU32, 48]
|
|
bRequireDcSysPowerLimitsTable: Annotated[NvBool, 52]
|
|
bAllowDcRestOfSystemReserveOverride: Annotated[NvBool, 53]
|
|
bSupportDcTsp: Annotated[NvBool, 54]
|
|
bEnableForAC: Annotated[NvBool, 55]
|
|
bEnableForDC: Annotated[NvBool, 56]
|
|
version: Annotated[NvU8, 57]
|
|
samplingPeriodmS: Annotated[NvU16, 58]
|
|
samplingMulti: Annotated[NvU16, 60]
|
|
filterType: Annotated[NvU8, 62]
|
|
filterParam: Annotated[struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam, 63]
|
|
filterReserved: Annotated[NvU16, 64]
|
|
bIsBoostController: Annotated[NvBool, 66]
|
|
incRatio: Annotated[NvU16, 68]
|
|
decRatio: Annotated[NvU16, 70]
|
|
bSupportBatt: Annotated[NvBool, 72]
|
|
cpuType: Annotated[NvU8, 73]
|
|
gpuType: Annotated[NvU8, 74]
|
|
sysPwrIndex: Annotated[NvU32, 76]
|
|
sysPwrGetInfo: Annotated[c.Array[NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT, Literal[32]], 80]
|
|
bIsTspSupported: Annotated[NvBool, 848]
|
|
sysPwrLimitsTableVersion: Annotated[NvU8, 849]
|
|
type: Annotated[NvU32, 852]
|
|
cpuTdpmw: Annotated[NvU32, 856]
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam(c.Struct):
|
|
SIZE = 1
|
|
weight: Annotated[NvU8, 0]
|
|
windowSize: Annotated[NvU8, 0]
|
|
NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS
|
|
NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bExternalFabricMgmt: Annotated[NvBool, 0]
|
|
NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS: TypeAlias = struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
clientCount: Annotated[NvU32, 0]
|
|
resourceCount: Annotated[NvU64, 8]
|
|
NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS(c.Struct):
|
|
SIZE = 1032
|
|
driverVersionBuffer: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[256]], 0]
|
|
versionBuffer: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[256]], 256]
|
|
driverBranch: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[256]], 512]
|
|
titleBuffer: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[256]], 768]
|
|
changelistNumber: Annotated[NvU32, 1024]
|
|
officialChangelistNumber: Annotated[NvU32, 1028]
|
|
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
cmd: Annotated[NvU32, 0]
|
|
mode: Annotated[NvU32, 4]
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
command: Annotated[NvU16, 0]
|
|
locale: Annotated[NvU16, 2]
|
|
data: Annotated[NvU32, 4]
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 136
|
|
cmdCount: Annotated[NvU32, 0]
|
|
succeeded: Annotated[NvU32, 4]
|
|
cmdData: Annotated[c.Array[struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_cmdData, Literal[16]], 8]
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_cmdData(c.Struct):
|
|
SIZE = 8
|
|
command: Annotated[NvU16, 0]
|
|
locale: Annotated[NvU16, 2]
|
|
data: Annotated[NvU32, 4]
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
cmd: Annotated[NvU32, 0]
|
|
input: Annotated[c.Array[NvS32, Literal[2]], 4]
|
|
result: Annotated[c.Array[NvS32, Literal[4]], 12]
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 148
|
|
objHndl: Annotated[NvU32, 0]
|
|
blockId: Annotated[NvU32, 4]
|
|
nextExpectedSampleTimems: Annotated[NvU32, 8]
|
|
countersReq: Annotated[NvU32, 12]
|
|
countersReturned: Annotated[NvU32, 16]
|
|
counterBlock: Annotated[c.Array[NvU32, Literal[32]], 20]
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS(c.Struct):
|
|
SIZE = 1164
|
|
cmd: Annotated[NvU32, 0]
|
|
input: Annotated[NvU32, 4]
|
|
resultSz: Annotated[NvU32, 8]
|
|
result: Annotated[c.Array[NvU32, Literal[288]], 12]
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE(c.Struct):
|
|
SIZE = 8
|
|
frameTime: Annotated[NvU16, 0]
|
|
renderTime: Annotated[NvU16, 2]
|
|
targetTime: Annotated[NvU16, 4]
|
|
sleepTime: Annotated[NvU8, 6]
|
|
sampleNumber: Annotated[NvU8, 7]
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS(c.Struct):
|
|
SIZE = 514
|
|
samples: Annotated[c.Array[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE, Literal[64]], 0]
|
|
nextSampleNumber: Annotated[NvU8, 512]
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
sampleData: Annotated[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE, 0]
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS: TypeAlias = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
offset: Annotated[NvU64, 0]
|
|
length: Annotated[NvU64, 8]
|
|
cacheOps: Annotated[NvU32, 16]
|
|
hDevice: Annotated[NvHandle, 20]
|
|
hObject: Annotated[NvHandle, 24]
|
|
internalOnly: Annotated[NvU64, 32]
|
|
NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
fd: Annotated[NvS32, 0]
|
|
NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS
|
|
class enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE = enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE.define('NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE', 0)
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM = enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE.define('NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM', 1)
|
|
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE: TypeAlias = enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT(c.Struct):
|
|
SIZE = 16
|
|
type: Annotated[NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE, 0]
|
|
data: Annotated[struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data, 4]
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data(c.Struct):
|
|
SIZE = 12
|
|
rmObject: Annotated[struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data_rmObject, 0]
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data_rmObject(c.Struct):
|
|
SIZE = 12
|
|
hDevice: Annotated[NvHandle, 0]
|
|
hParent: Annotated[NvHandle, 4]
|
|
hObject: Annotated[NvHandle, 8]
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT: TypeAlias = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
object: Annotated[NV0000_CTRL_OS_UNIX_EXPORT_OBJECT, 0]
|
|
fd: Annotated[NvS32, 16]
|
|
flags: Annotated[NvU32, 20]
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
fd: Annotated[NvS32, 0]
|
|
object: Annotated[NV0000_CTRL_OS_UNIX_EXPORT_OBJECT, 4]
|
|
NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpuId: Annotated[NvU32, 0]
|
|
minorNum: Annotated[NvU32, 4]
|
|
NV0000_CTRL_OS_GET_GPU_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
fd: Annotated[NvS32, 0]
|
|
deviceInstance: Annotated[NvU32, 4]
|
|
gpuInstanceId: Annotated[NvU32, 8]
|
|
maxObjects: Annotated[NvU16, 12]
|
|
metadata: Annotated[c.Array[NvU8, Literal[64]], 14]
|
|
NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS(c.Struct):
|
|
SIZE = 76
|
|
hDevice: Annotated[NvHandle, 0]
|
|
maxObjects: Annotated[NvU16, 4]
|
|
metadata: Annotated[c.Array[NvU8, Literal[64]], 6]
|
|
fd: Annotated[NvS32, 72]
|
|
NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS(c.Struct):
|
|
SIZE = 2128
|
|
fd: Annotated[NvS32, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
maxObjects: Annotated[NvU16, 8]
|
|
metadata: Annotated[c.Array[NvU8, Literal[64]], 10]
|
|
objects: Annotated[c.Array[NvHandle, Literal[512]], 76]
|
|
numObjects: Annotated[NvU16, 2124]
|
|
index: Annotated[NvU16, 2126]
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS(c.Struct):
|
|
SIZE = 652
|
|
fd: Annotated[NvS32, 0]
|
|
hParent: Annotated[NvHandle, 4]
|
|
objects: Annotated[c.Array[NvHandle, Literal[128]], 8]
|
|
objectTypes: Annotated[c.Array[NvU8, Literal[128]], 520]
|
|
numObjects: Annotated[NvU16, 648]
|
|
index: Annotated[NvU16, 650]
|
|
NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS: TypeAlias = struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
vgpuName: Annotated[c.Array[NvU8, Literal[16]], 0]
|
|
gpuPciId: Annotated[NvU32, 16]
|
|
gpuPciBdf: Annotated[NvU32, 20]
|
|
vgpuTypeId: Annotated[NvU32, 24]
|
|
vgpuId: Annotated[NvU16, 28]
|
|
gpuInstanceId: Annotated[NvU32, 32]
|
|
placementId: Annotated[NvU32, 36]
|
|
NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS: TypeAlias = struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS(c.Struct):
|
|
SIZE = 524
|
|
gpuPciId: Annotated[NvU32, 0]
|
|
gpuPciBdf: Annotated[NvU32, 4]
|
|
numVgpuTypes: Annotated[NvU32, 8]
|
|
vgpuTypeIds: Annotated[c.Array[NvU32, Literal[64]], 12]
|
|
availableInstances: Annotated[c.Array[NvU32, Literal[64]], 268]
|
|
NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS: TypeAlias = struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS(c.Struct):
|
|
SIZE = 18
|
|
vgpuName: Annotated[c.Array[NvU8, Literal[16]], 0]
|
|
vgpuId: Annotated[NvU16, 16]
|
|
NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS: TypeAlias = struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
returnStatus: Annotated[NvU32, 0]
|
|
gpuId: Annotated[NvU32, 4]
|
|
NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS: TypeAlias = struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
vgpuName: Annotated[c.Array[NvU8, Literal[16]], 0]
|
|
mode: Annotated[NvU32, 16]
|
|
sysfs_val: Annotated[NvU32, 20]
|
|
NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS: TypeAlias = struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_BIF_RESET_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
flags: Annotated[NvU32, 0]
|
|
NV0080_CTRL_BIF_RESET_PARAMS: TypeAlias = struct_NV0080_CTRL_BIF_RESET_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
aspmFeatureSupported: Annotated[NvU32, 0]
|
|
NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS: TypeAlias = struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bL0sEnable: Annotated[NvBool, 0]
|
|
bL1Enable: Annotated[NvBool, 1]
|
|
NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS: TypeAlias = struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
pciePowerControlMask: Annotated[NvU32, 0]
|
|
pciePowerControlIdentifiedKeyOrder: Annotated[NvU32, 4]
|
|
pciePowerControlIdentifiedKeyLocation: Annotated[NvU32, 8]
|
|
NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS: TypeAlias = struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
capsTblSize: Annotated[NvU32, 0]
|
|
capsTbl: Annotated[NvP64, 8]
|
|
instanceId: Annotated[NvU32, 16]
|
|
NV0080_CTRL_BSP_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2(c.Struct):
|
|
SIZE = 12
|
|
capsTbl: Annotated[c.Array[NvU8, Literal[8]], 0]
|
|
instanceId: Annotated[NvU32, 8]
|
|
NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2: TypeAlias = struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK(c.Struct):
|
|
SIZE = 32
|
|
pageSize: Annotated[NvU64, 0]
|
|
pteEntrySize: Annotated[NvU64, 8]
|
|
comptagLine: Annotated[NvU32, 16]
|
|
kind: Annotated[NvU32, 20]
|
|
pteFlags: Annotated[NvU32, 24]
|
|
NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK: TypeAlias = struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS(c.Struct):
|
|
SIZE = 184
|
|
gpuAddr: Annotated[NvU64, 0]
|
|
subDeviceId: Annotated[NvU32, 8]
|
|
skipVASpaceInit: Annotated[NvU8, 12]
|
|
pteBlocks: Annotated[c.Array[NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK, Literal[5]], 16]
|
|
hVASpace: Annotated[NvHandle, 176]
|
|
NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS(c.Struct):
|
|
SIZE = 184
|
|
gpuAddr: Annotated[NvU64, 0]
|
|
subDeviceId: Annotated[NvU32, 8]
|
|
pteBlocks: Annotated[c.Array[NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK, Literal[5]], 16]
|
|
hVASpace: Annotated[NvHandle, 176]
|
|
NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
pageCount: Annotated[NvU32, 0]
|
|
hwResource: Annotated[struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource, 4]
|
|
comprInfo: Annotated[struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo, 20]
|
|
offset: Annotated[NvU64, 32]
|
|
gpuAddr: Annotated[NvU64, 40]
|
|
pageArray: Annotated[NvP64, 48]
|
|
pteMem: Annotated[NvP64, 56]
|
|
pteMemPfn: Annotated[NvU32, 64]
|
|
pageSize: Annotated[NvU32, 68]
|
|
startPageIndex: Annotated[NvU32, 72]
|
|
flags: Annotated[NvU32, 76]
|
|
hSrcVASpace: Annotated[NvHandle, 80]
|
|
hTgtVASpace: Annotated[NvHandle, 84]
|
|
peerId: Annotated[NvU32, 88]
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource(c.Struct):
|
|
SIZE = 16
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
hMemory: Annotated[NvHandle, 8]
|
|
subDeviceId: Annotated[NvU32, 12]
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo(c.Struct):
|
|
SIZE = 12
|
|
fbKind: Annotated[NvU32, 0]
|
|
sysKind: Annotated[NvU32, 4]
|
|
compTagStartOffset: Annotated[NvU32, 8]
|
|
NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_FLUSH_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
targetUnit: Annotated[NvU32, 0]
|
|
NV0080_CTRL_DMA_FLUSH_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_FLUSH_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT(c.Struct):
|
|
SIZE = 8
|
|
pageTableSize: Annotated[NvU32, 0]
|
|
pageTableCoverage: Annotated[NvU32, 4]
|
|
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT: TypeAlias = struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS(c.Struct):
|
|
SIZE = 192
|
|
vaBitCount: Annotated[NvU32, 0]
|
|
pdeCoverageBitCount: Annotated[NvU32, 4]
|
|
num4KPageTableFormats: Annotated[NvU32, 8]
|
|
bigPageSize: Annotated[NvU32, 12]
|
|
compressionPageSize: Annotated[NvU32, 16]
|
|
dualPageTableSupported: Annotated[NvU32, 20]
|
|
idealVRAMPageSize: Annotated[NvU32, 24]
|
|
pageTableBigFormat: Annotated[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT, 28]
|
|
pageTable4KFormat: Annotated[c.Array[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT, Literal[16]], 36]
|
|
hVASpace: Annotated[NvHandle, 164]
|
|
vaRangeLo: Annotated[NvU64, 168]
|
|
vaSpaceId: Annotated[NvU32, 176]
|
|
supportedPageSizeMask: Annotated[NvU64, 184]
|
|
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK(c.Struct):
|
|
SIZE = 32
|
|
ptePhysAddr: Annotated[NvU64, 0]
|
|
pteCacheAttrib: Annotated[NvU32, 8]
|
|
pteEntrySize: Annotated[NvU32, 12]
|
|
pageSize: Annotated[NvU32, 16]
|
|
pteAddrSpace: Annotated[NvU32, 20]
|
|
pdeVASpaceSize: Annotated[NvU32, 24]
|
|
pdeFlags: Annotated[NvU32, 28]
|
|
NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK: TypeAlias = struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS(c.Struct):
|
|
SIZE = 208
|
|
gpuAddr: Annotated[NvU64, 0]
|
|
pdeVirtAddr: Annotated[NvU64, 8]
|
|
pdeEntrySize: Annotated[NvU32, 16]
|
|
pdeAddrSpace: Annotated[NvU32, 20]
|
|
pdeSize: Annotated[NvU32, 24]
|
|
subDeviceId: Annotated[NvU32, 28]
|
|
pteBlocks: Annotated[c.Array[NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK, Literal[5]], 32]
|
|
pdbAddr: Annotated[NvU64, 192]
|
|
hVASpace: Annotated[NvHandle, 200]
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hVASpace: Annotated[NvHandle, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
capsTblSize: Annotated[NvU32, 0]
|
|
capsTbl: Annotated[c.Array[NvU8, Literal[8]], 4]
|
|
NV0080_CTRL_DMA_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
vaSpaceSize: Annotated[NvU64, 0]
|
|
hVASpace: Annotated[NvHandle, 8]
|
|
NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
physAddr: Annotated[NvU64, 0]
|
|
numEntries: Annotated[NvU32, 8]
|
|
aperture: Annotated[NvU32, 12]
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(c.Struct):
|
|
SIZE = 64
|
|
pdeIndex: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
ptParams: Annotated[c.Array[NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS, Literal[2]], 8]
|
|
hVASpace: Annotated[NvHandle, 40]
|
|
pPdeBuffer: Annotated[NvP64, 48]
|
|
subDeviceId: Annotated[NvU32, 56]
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hVASpace: Annotated[NvHandle, 0]
|
|
NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hVASpace: Annotated[NvHandle, 0]
|
|
NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
physAddress: Annotated[NvU64, 0]
|
|
numEntries: Annotated[NvU32, 8]
|
|
flags: Annotated[NvU32, 12]
|
|
hVASpace: Annotated[NvHandle, 16]
|
|
chId: Annotated[NvU32, 20]
|
|
subDeviceId: Annotated[NvU32, 24]
|
|
pasid: Annotated[NvU32, 28]
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hVASpace: Annotated[NvHandle, 0]
|
|
subDeviceId: Annotated[NvU32, 4]
|
|
NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS: TypeAlias = struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FB_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
capsTblSize: Annotated[NvU32, 0]
|
|
capsTbl: Annotated[NvP64, 8]
|
|
NV0080_CTRL_FB_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_FB_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
Size: Annotated[NvU64, 0]
|
|
Address: Annotated[NvU64, 8]
|
|
AddressSpace: Annotated[NvU32, 16]
|
|
MaxCompbitLine: Annotated[NvU32, 20]
|
|
comptagsPerCacheLine: Annotated[NvU32, 24]
|
|
cacheLineSize: Annotated[NvU32, 28]
|
|
cacheLineSizePerSlice: Annotated[NvU32, 32]
|
|
cacheLineFetchAlignment: Annotated[NvU32, 36]
|
|
backingStoreBase: Annotated[NvU64, 40]
|
|
gobsPerComptagPerSlice: Annotated[NvU32, 48]
|
|
backingStoreCbcBase: Annotated[NvU32, 52]
|
|
comptaglineAllocationPolicy: Annotated[NvU32, 56]
|
|
privRegionStartOffset: Annotated[NvU64, 64]
|
|
cbcCoveragePerSlice: Annotated[NvU32, 72]
|
|
NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS: TypeAlias = struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
capsTbl: Annotated[c.Array[NvU8, Literal[3]], 0]
|
|
NV0080_CTRL_FB_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
value: Annotated[NvU32, 0]
|
|
NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS: TypeAlias = struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS
|
|
class enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY.define('NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT', 0)
|
|
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY.define('NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS', 1)
|
|
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY.define('NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS', 2)
|
|
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY.define('NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS', 3)
|
|
|
|
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY: TypeAlias = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
capsTblSize: Annotated[NvU32, 0]
|
|
capsTbl: Annotated[NvP64, 8]
|
|
NV0080_CTRL_FIFO_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
engineId: Annotated[NvU32, 0]
|
|
alignment: Annotated[NvU32, 4]
|
|
size: Annotated[NvU32, 8]
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM(c.Struct):
|
|
SIZE = 8
|
|
hChannel1: Annotated[NvHandle, 0]
|
|
hChannel2: Annotated[NvHandle, 4]
|
|
NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM: TypeAlias = struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM(c.Struct):
|
|
SIZE = 8
|
|
hChannel: Annotated[NvHandle, 0]
|
|
tsDivisor: Annotated[NvU32, 4]
|
|
NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM: TypeAlias = struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hRunlist: Annotated[NvHandle, 0]
|
|
engineID: Annotated[NvU32, 4]
|
|
NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
numChannels: Annotated[NvU32, 0]
|
|
pChannelHandleList: Annotated[NvP64, 8]
|
|
pChannelList: Annotated[NvP64, 16]
|
|
NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
engineID: Annotated[NvU32, 0]
|
|
gpEntries: Annotated[NvU32, 4]
|
|
pbEntries: Annotated[NvU32, 8]
|
|
NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hChannel: Annotated[NvHandle, 0]
|
|
property: Annotated[NvU32, 4]
|
|
value: Annotated[NvU64, 8]
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
engineID: Annotated[NvU32, 0]
|
|
NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
engineID: Annotated[NvU32, 0]
|
|
NV0080_CTRL_FIFO_START_RUNLIST_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
capsTbl: Annotated[c.Array[NvU8, Literal[2]], 0]
|
|
NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 16396
|
|
numChannels: Annotated[NvU32, 0]
|
|
hChannels: Annotated[c.Array[NvHandle, Literal[4096]], 4]
|
|
flags: Annotated[NvU32, 16388]
|
|
timeout: Annotated[NvU32, 16392]
|
|
NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS: TypeAlias = struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
numClasses: Annotated[NvU32, 0]
|
|
classList: Annotated[NvP64, 8]
|
|
NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
numSubDevices: Annotated[NvU32, 0]
|
|
NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS(c.Struct):
|
|
SIZE = 36
|
|
ConnectionCount: Annotated[NvU32, 0]
|
|
Order: Annotated[c.Array[NvU32, Literal[8]], 4]
|
|
NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
subDeviceInstance: Annotated[NvU32, 0]
|
|
NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
subDeviceInstance: Annotated[NvU32, 0]
|
|
NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
enable: Annotated[NvU32, 0]
|
|
NV0080_CTRL_GPU_SET_VIDLINK_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
newState: Annotated[NvU32, 0]
|
|
NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
swStatePersistence: Annotated[NvU32, 0]
|
|
NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
virtualizationMode: Annotated[NvU32, 0]
|
|
isGridBuild: Annotated[NvBool, 4]
|
|
NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
defaultSetting: Annotated[NvU32, 0]
|
|
currentSetting: Annotated[NvU32, 4]
|
|
pendingSetting: Annotated[NvU32, 8]
|
|
NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
setting: Annotated[NvU32, 0]
|
|
NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
isVgx: Annotated[NvBool, 0]
|
|
NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
totalVFs: Annotated[NvU32, 0]
|
|
firstVfOffset: Annotated[NvU32, 4]
|
|
vfFeatureMask: Annotated[NvU32, 8]
|
|
FirstVFBar0Address: Annotated[NvU64, 16]
|
|
FirstVFBar1Address: Annotated[NvU64, 24]
|
|
FirstVFBar2Address: Annotated[NvU64, 32]
|
|
bar0Size: Annotated[NvU64, 40]
|
|
bar1Size: Annotated[NvU64, 48]
|
|
bar2Size: Annotated[NvU64, 56]
|
|
b64bitBar0: Annotated[NvBool, 64]
|
|
b64bitBar1: Annotated[NvBool, 65]
|
|
b64bitBar2: Annotated[NvBool, 66]
|
|
bSriovEnabled: Annotated[NvBool, 67]
|
|
bSriovHeavyEnabled: Annotated[NvBool, 68]
|
|
bEmulateVFBar0TlbInvalidationRegister: Annotated[NvBool, 69]
|
|
bClientRmAllocatedCtxBuffer: Annotated[NvBool, 70]
|
|
bNonPowerOf2ChannelCountSupported: Annotated[NvBool, 71]
|
|
bVfResizableBAR1Supported: Annotated[NvBool, 72]
|
|
NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS(c.Struct):
|
|
SIZE = 404
|
|
numClasses: Annotated[NvU32, 0]
|
|
classList: Annotated[c.Array[NvU32, Literal[100]], 4]
|
|
NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM(c.Struct):
|
|
SIZE = 8
|
|
subDeviceInst: Annotated[NvU32, 0]
|
|
hSubDevice: Annotated[NvHandle, 4]
|
|
NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM: TypeAlias = struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
brands: Annotated[NvU32, 0]
|
|
NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
vfBar1SizeMB: Annotated[NvU32, 0]
|
|
numVfs: Annotated[NvU32, 4]
|
|
NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bHeterogeneousMode: Annotated[NvBool, 0]
|
|
NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bHeterogeneousMode: Annotated[NvBool, 0]
|
|
NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GR_ROUTE_INFO(c.Struct):
|
|
SIZE = 16
|
|
flags: Annotated[NvU32, 0]
|
|
route: Annotated[NvU64, 8]
|
|
NV0080_CTRL_GR_ROUTE_INFO: TypeAlias = struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
@c.record
|
|
class struct_NV0080_CTRL_GR_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
capsTblSize: Annotated[NvU32, 0]
|
|
capsTbl: Annotated[NvP64, 8]
|
|
NV0080_CTRL_GR_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NVXXXX_CTRL_XXX_INFO(c.Struct):
|
|
SIZE = 8
|
|
index: Annotated[NvU32, 0]
|
|
data: Annotated[NvU32, 4]
|
|
NV0080_CTRL_GR_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV0080_CTRL_GR_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
grInfoListSize: Annotated[NvU32, 0]
|
|
grInfoList: Annotated[NvP64, 8]
|
|
NV0080_CTRL_GR_GET_INFO_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_GET_INFO_PARAMS
|
|
class enum_NV0080_CTRL_GR_TPC_PARTITION_MODE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE.define('NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE', 0)
|
|
NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE.define('NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC', 1)
|
|
NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE.define('NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC', 2)
|
|
|
|
NV0080_CTRL_GR_TPC_PARTITION_MODE: TypeAlias = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE
|
|
@c.record
|
|
class struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hChannelGroup: Annotated[NvHandle, 0]
|
|
mode: Annotated[NV0080_CTRL_GR_TPC_PARTITION_MODE, 4]
|
|
bEnableAllTpcs: Annotated[NvBool, 8]
|
|
grRouteInfo: Annotated[NV0080_CTRL_GR_ROUTE_INFO, 16]
|
|
NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
|
|
NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
|
|
NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
capsTbl: Annotated[c.Array[NvU8, Literal[23]], 0]
|
|
grRouteInfo: Annotated[NV0080_CTRL_GR_ROUTE_INFO, 24]
|
|
bCapsPopulated: Annotated[NvBool, 40]
|
|
NV0080_CTRL_GR_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 488
|
|
grInfoListSize: Annotated[NvU32, 0]
|
|
grInfoList: Annotated[c.Array[NV0080_CTRL_GR_INFO, Literal[58]], 4]
|
|
grRouteInfo: Annotated[NV0080_CTRL_GR_ROUTE_INFO, 472]
|
|
NV0080_CTRL_GR_GET_INFO_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
capsTblSize: Annotated[NvU32, 0]
|
|
capsTbl: Annotated[NvP64, 8]
|
|
NV0080_CTRL_HOST_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
capsTbl: Annotated[c.Array[NvU8, Literal[3]], 0]
|
|
NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
params: Annotated[NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS, 0]
|
|
NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS: TypeAlias = struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
params: Annotated[NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS, 0]
|
|
NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS: TypeAlias = struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 804
|
|
numClients: Annotated[NvU32, 0]
|
|
clientHandles: Annotated[c.Array[NvHandle, Literal[200]], 4]
|
|
NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS: TypeAlias = struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
capsTblSize: Annotated[NvU32, 0]
|
|
capsTbl: Annotated[NvP64, 8]
|
|
NV0080_CTRL_MSENC_GET_CAPS_PARAMS: TypeAlias = struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
capsTbl: Annotated[c.Array[NvU8, Literal[4]], 0]
|
|
instanceId: Annotated[NvU32, 4]
|
|
NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
capsTbl: Annotated[c.Array[NvU8, Literal[9]], 0]
|
|
instanceId: Annotated[NvU32, 12]
|
|
NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bActivate: Annotated[NvBool, 0]
|
|
NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS: TypeAlias = struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bCudaLimit: Annotated[NvBool, 0]
|
|
NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS: TypeAlias = struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
cmd: Annotated[NvU32, 0]
|
|
NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS: TypeAlias = struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS
|
|
@c.record
|
|
class struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
subDeviceInstance: Annotated[NvU32, 0]
|
|
width: Annotated[NvU16, 4]
|
|
height: Annotated[NvU16, 6]
|
|
depth: Annotated[NvU16, 8]
|
|
pitch: Annotated[NvU16, 10]
|
|
baseAddress: Annotated[NvU64, 16]
|
|
size: Annotated[NvU64, 24]
|
|
NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS: TypeAlias = struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS
|
|
NV2080_CTRL_BIOS_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
biosInfoListSize: Annotated[NvU32, 0]
|
|
biosInfoList: Annotated[NvP64, 8]
|
|
NV2080_CTRL_BIOS_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 124
|
|
biosInfoListSize: Annotated[NvU32, 0]
|
|
biosInfoList: Annotated[c.Array[NV2080_CTRL_BIOS_INFO, Literal[15]], 4]
|
|
NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_NBSI_REG_STRING(c.Struct):
|
|
SIZE = 520
|
|
size: Annotated[NvU32, 0]
|
|
type: Annotated[NvU32, 4]
|
|
value: Annotated[struct_NV2080_CTRL_BIOS_NBSI_REG_STRING_value, 8]
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_NBSI_REG_STRING_value(c.Struct):
|
|
SIZE = 512
|
|
ascii: Annotated[c.Array[NvU8, Literal[256]], 0]
|
|
unicode: Annotated[c.Array[NvU16, Literal[256]], 0]
|
|
hash: Annotated[NvU16, 0]
|
|
NV2080_CTRL_BIOS_NBSI_REG_STRING: TypeAlias = struct_NV2080_CTRL_BIOS_NBSI_REG_STRING
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS(c.Struct):
|
|
SIZE = 1064
|
|
module: Annotated[NvU32, 0]
|
|
path: Annotated[NV2080_CTRL_BIOS_NBSI_REG_STRING, 4]
|
|
valueName: Annotated[NV2080_CTRL_BIOS_NBSI_REG_STRING, 524]
|
|
retBuf: Annotated[NvP64, 1048]
|
|
retSize: Annotated[NvU32, 1056]
|
|
errorCode: Annotated[NvU32, 1060]
|
|
NV2080_CTRL_BIOS_GET_NBSI_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS(c.Struct):
|
|
SIZE = 1308
|
|
module: Annotated[NvU32, 0]
|
|
path: Annotated[NV2080_CTRL_BIOS_NBSI_REG_STRING, 4]
|
|
valueName: Annotated[NV2080_CTRL_BIOS_NBSI_REG_STRING, 524]
|
|
retBuf: Annotated[c.Array[NvU8, Literal[256]], 1044]
|
|
retSize: Annotated[NvU32, 1300]
|
|
errorCode: Annotated[NvU32, 1304]
|
|
NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
globType: Annotated[NvU16, 0]
|
|
globIndex: Annotated[NvU8, 2]
|
|
globSource: Annotated[NvU16, 4]
|
|
retBufOffset: Annotated[NvU32, 8]
|
|
retBuf: Annotated[NvP64, 16]
|
|
retSize: Annotated[NvU32, 24]
|
|
totalObjSize: Annotated[NvU32, 28]
|
|
errorCode: Annotated[NvU32, 32]
|
|
NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
BoardID: Annotated[NvU32, 0]
|
|
chipSKU: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[9]], 4]
|
|
chipSKUMod: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[5]], 13]
|
|
skuConfigVersion: Annotated[NvU32, 20]
|
|
project: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[5]], 24]
|
|
projectSKU: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[5]], 29]
|
|
CDP: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[6]], 34]
|
|
projectSKUMod: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[2]], 40]
|
|
businessCycle: Annotated[NvU32, 44]
|
|
NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
vbiosPostTime: Annotated[NvU64, 0]
|
|
NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
version: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS: TypeAlias = struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pciDeviceId: Annotated[NvU32, 0]
|
|
pciSubSystemId: Annotated[NvU32, 4]
|
|
pciRevisionId: Annotated[NvU32, 8]
|
|
pciExtDeviceId: Annotated[NvU32, 12]
|
|
NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS
|
|
NV2080_CTRL_BUS_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
busInfoListSize: Annotated[NvU32, 0]
|
|
busInfoList: Annotated[NvP64, 8]
|
|
NV2080_CTRL_BUS_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 420
|
|
busInfoListSize: Annotated[NvU32, 0]
|
|
busInfoList: Annotated[c.Array[NV2080_CTRL_BUS_INFO, Literal[52]], 4]
|
|
NV2080_CTRL_BUS_GET_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_PCI_BAR_INFO(c.Struct):
|
|
SIZE = 24
|
|
flags: Annotated[NvU32, 0]
|
|
barSize: Annotated[NvU32, 4]
|
|
barSizeBytes: Annotated[NvU64, 8]
|
|
barOffset: Annotated[NvU64, 16]
|
|
NV2080_CTRL_BUS_PCI_BAR_INFO: TypeAlias = struct_NV2080_CTRL_BUS_PCI_BAR_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS(c.Struct):
|
|
SIZE = 200
|
|
pciBarCount: Annotated[NvU32, 0]
|
|
pciBarInfo: Annotated[c.Array[NV2080_CTRL_BUS_PCI_BAR_INFO, Literal[8]], 8]
|
|
NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pcieLinkWidth: Annotated[NvU32, 0]
|
|
failingReason: Annotated[NvU32, 4]
|
|
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
busSpeed: Annotated[NvU32, 0]
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hMemory: Annotated[NvHandle, 0]
|
|
NV2080_CTRL_BUS_MAP_BAR2_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hMemory: Annotated[NvHandle, 0]
|
|
NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
hMemory: Annotated[NvHandle, 0]
|
|
offset: Annotated[NvU32, 4]
|
|
size: Annotated[NvU32, 8]
|
|
NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
command: Annotated[NvU8, 0]
|
|
deviceState: Annotated[NvU32, 4]
|
|
NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 76
|
|
pexCounterMask: Annotated[NvU32, 0]
|
|
pexTotalCorrectableErrors: Annotated[NvU32, 4]
|
|
pexCorrectableErrors: Annotated[NvU16, 8]
|
|
pexTotalNonFatalErrors: Annotated[NvU8, 10]
|
|
pexTotalFatalErrors: Annotated[NvU8, 11]
|
|
pexTotalUnsupportedReqs: Annotated[NvU8, 12]
|
|
pexCounters: Annotated[c.Array[NvU16, Literal[31]], 14]
|
|
NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
pexCounterMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pexCounterMask: Annotated[NvU32, 0]
|
|
bFreezeRmCounter: Annotated[NvBool, 4]
|
|
NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 18
|
|
pexLaneErrorStatus: Annotated[NvU16, 0]
|
|
pexLaneCounter: Annotated[c.Array[NvU8, Literal[16]], 2]
|
|
NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
bPexLtrRegkeyOverride: Annotated[NvBool, 0]
|
|
bPexRootPortLtrSupported: Annotated[NvBool, 1]
|
|
bPexGpuLtrSupported: Annotated[NvBool, 2]
|
|
pexLtrSnoopLatencyValue: Annotated[NvU16, 4]
|
|
pexLtrSnoopLatencyScale: Annotated[NvU8, 6]
|
|
pexLtrNoSnoopLatencyValue: Annotated[NvU16, 8]
|
|
pexLtrNoSnoopLatencyScale: Annotated[NvU8, 10]
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pexLtrSnoopLatencyValue: Annotated[NvU16, 0]
|
|
pexLtrSnoopLatencyScale: Annotated[NvU8, 2]
|
|
pexLtrNoSnoopLatencyValue: Annotated[NvU16, 4]
|
|
pexLtrNoSnoopLatencyScale: Annotated[NvU8, 6]
|
|
NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
pexCounterMask: Annotated[NvU32, 0]
|
|
pexCounters: Annotated[c.Array[NvU32, Literal[7]], 4]
|
|
NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
pexCounterMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_BFD_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
valid: Annotated[NvBool, 0]
|
|
deviceID: Annotated[NvU16, 2]
|
|
vendorID: Annotated[NvU16, 4]
|
|
domain: Annotated[NvU32, 8]
|
|
bus: Annotated[NvU16, 12]
|
|
device: Annotated[NvU16, 14]
|
|
function: Annotated[NvU8, 16]
|
|
NV2080_CTRL_BUS_GET_BFD_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_BFD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR(c.Struct):
|
|
SIZE = 640
|
|
params: Annotated[c.Array[NV2080_CTRL_BUS_GET_BFD_PARAMS, Literal[32]], 0]
|
|
NV2080_CTRL_BUS_GET_BFD_PARAMSARR: TypeAlias = struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS(c.Struct):
|
|
SIZE = 9
|
|
aspmDisableFlags: Annotated[c.Array[NvBool, Literal[9]], 0]
|
|
NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnable: Annotated[NvBool, 0]
|
|
NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS(c.Struct):
|
|
SIZE = 128
|
|
nvlinkPeerIdMask: Annotated[c.Array[NvU32, Literal[32]], 0]
|
|
NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
eomMode: Annotated[NvU8, 0]
|
|
eomNblks: Annotated[NvU8, 1]
|
|
eomNerrs: Annotated[NvU8, 2]
|
|
NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
regAddress: Annotated[NvU32, 0]
|
|
laneSelectMask: Annotated[NvU32, 4]
|
|
regValue: Annotated[NvU16, 8]
|
|
NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS(c.Struct):
|
|
SIZE = 76
|
|
eomMode: Annotated[NvU8, 0]
|
|
eomNblks: Annotated[NvU8, 1]
|
|
eomNerrs: Annotated[NvU8, 2]
|
|
eomBerEyeSel: Annotated[NvU8, 3]
|
|
eomPamEyeSel: Annotated[NvU8, 4]
|
|
laneMask: Annotated[NvU32, 8]
|
|
eomStatus: Annotated[c.Array[NvU16, Literal[32]], 12]
|
|
NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
capType: Annotated[NvU32, 0]
|
|
dbdf: Annotated[NvU32, 4]
|
|
atomicsCaps: Annotated[NvU32, 8]
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO(c.Struct):
|
|
SIZE = 8
|
|
bSupported: Annotated[NvBool, 0]
|
|
attributes: Annotated[NvU32, 4]
|
|
NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO: TypeAlias = struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS(c.Struct):
|
|
SIZE = 112
|
|
capType: Annotated[NvU32, 0]
|
|
dbdf: Annotated[NvU32, 4]
|
|
atomicOp: Annotated[c.Array[NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO, Literal[13]], 8]
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
bIsLinkUp: Annotated[NvBool, 0]
|
|
nrLinks: Annotated[NvU32, 4]
|
|
maxNrLinks: Annotated[NvU32, 8]
|
|
linkMask: Annotated[NvU32, 12]
|
|
perLinkBwMBps: Annotated[NvU32, 16]
|
|
perLinkLaneWidth: Annotated[NvU32, 20]
|
|
remoteType: Annotated[NvU32, 24]
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bDisable: Annotated[NvBool, 0]
|
|
NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
connectionType: Annotated[NvU32, 0]
|
|
peerId: Annotated[NvU32, 4]
|
|
bEgmPeer: Annotated[NvBool, 8]
|
|
bSpaAccessOnly: Annotated[NvBool, 9]
|
|
bUseUuid: Annotated[NvBool, 10]
|
|
remoteGpuId: Annotated[NvU32, 12]
|
|
remoteGpuUuid: Annotated[c.Array[NvU8, Literal[16]], 16]
|
|
NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
connectionType: Annotated[NvU32, 0]
|
|
peerId: Annotated[NvU32, 4]
|
|
bUseUuid: Annotated[NvBool, 8]
|
|
remoteGpuId: Annotated[NvU32, 12]
|
|
remoteGpuUuid: Annotated[c.Array[NvU8, Literal[16]], 16]
|
|
NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
atomicsCaps: Annotated[NvU32, 0]
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
ceEngineType: Annotated[NvU32, 0]
|
|
capsTblSize: Annotated[NvU32, 4]
|
|
capsTbl: Annotated[NvP64, 8]
|
|
NV2080_CTRL_CE_GET_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
ceEngineType: Annotated[NvU32, 0]
|
|
capsTbl: Annotated[c.Array[NvU8, Literal[2]], 4]
|
|
NV2080_CTRL_CE_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
ceEngineType: Annotated[NvU32, 0]
|
|
pceMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 148
|
|
ceEngineType: Annotated[NvU32, 0]
|
|
pceLceMap: Annotated[c.Array[NvU32, Literal[32]], 4]
|
|
grceSharedLceMap: Annotated[c.Array[NvU32, Literal[4]], 132]
|
|
NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS(c.Struct):
|
|
SIZE = 152
|
|
pceLceMap: Annotated[c.Array[NvU32, Literal[32]], 0]
|
|
grceConfig: Annotated[c.Array[NvU32, Literal[4]], 128]
|
|
exposeCeMask: Annotated[NvU32, 144]
|
|
bUpdateNvlinkPceLce: Annotated[NvBool, 148]
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
stubbedCeMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS
|
|
NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
size: Annotated[NvU32, 0]
|
|
NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS(c.Struct):
|
|
SIZE = 132
|
|
hshubPceMasks: Annotated[c.Array[NvU32, Literal[32]], 0]
|
|
fbhubPceMask: Annotated[NvU32, 128]
|
|
NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS(c.Struct):
|
|
SIZE = 136
|
|
capsTbl: Annotated[c.Array[c.Array[NvU8, Literal[2]], Literal[64]], 0]
|
|
present: Annotated[NvU64, 128]
|
|
NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
|
|
NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
ceEngineType: Annotated[NvU32, 0]
|
|
shimInstance: Annotated[NvU32, 4]
|
|
shimLocalLceIdx: Annotated[NvU32, 8]
|
|
NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS(c.Struct):
|
|
SIZE = 156
|
|
pceLceMap: Annotated[c.Array[NvU32, Literal[32]], 0]
|
|
grceConfig: Annotated[c.Array[NvU32, Literal[4]], 128]
|
|
exposeCeMask: Annotated[NvU32, 144]
|
|
bUpdateNvlinkPceLce: Annotated[NvBool, 148]
|
|
shimInstance: Annotated[NvU32, 152]
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS(c.Struct):
|
|
SIZE = 136
|
|
connectingHubPceMasks: Annotated[c.Array[NvU32, Literal[32]], 0]
|
|
fbhubPceMask: Annotated[NvU32, 128]
|
|
shimInstance: Annotated[NvU32, 132]
|
|
NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS
|
|
class enum_NV2080_CTRL_CE_LCE_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_CE_LCE_TYPE_PCIE = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_PCIE', 1)
|
|
NV2080_CTRL_CE_LCE_TYPE_DECOMP = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_DECOMP', 2)
|
|
NV2080_CTRL_CE_LCE_TYPE_SCRUB = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_SCRUB', 3)
|
|
NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER', 4)
|
|
NV2080_CTRL_CE_LCE_TYPE_C2C = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_C2C', 5)
|
|
NV2080_CTRL_CE_LCE_TYPE_PCIE_RD = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_PCIE_RD', 6)
|
|
NV2080_CTRL_CE_LCE_TYPE_PCIE_WR = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_PCIE_WR', 7)
|
|
NV2080_CTRL_CE_LCE_TYPE_C2C_H2D = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_C2C_H2D', 8)
|
|
NV2080_CTRL_CE_LCE_TYPE_C2C_D2H = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_C2C_D2H', 9)
|
|
|
|
NV2080_CTRL_CE_LCE_TYPE: TypeAlias = enum_NV2080_CTRL_CE_LCE_TYPE
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
lceType: Annotated[NV2080_CTRL_CE_LCE_TYPE, 0]
|
|
numPces: Annotated[NvU32, 4]
|
|
numLces: Annotated[NvU32, 8]
|
|
supportedPceMask: Annotated[NvU32, 12]
|
|
supportedLceMask: Annotated[NvU32, 16]
|
|
pcePerHshub: Annotated[NvU32, 20]
|
|
NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
decompLceMask: Annotated[NvU64, 0]
|
|
shimInstance: Annotated[NvU32, 8]
|
|
NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
lceIndex: Annotated[NvU32, 0]
|
|
bDecompEnabled: Annotated[NvBool, 4]
|
|
NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS: TypeAlias = struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hClient: Annotated[NvHandle, 0]
|
|
hDevice: Annotated[NvHandle, 4]
|
|
engine: Annotated[NvU32, 8]
|
|
hVASpace: Annotated[NvHandle, 12]
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS: TypeAlias = struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS
|
|
NV2080_CTRL_DMA_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_DMA_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 2052
|
|
dmaInfoTblSize: Annotated[NvU32, 0]
|
|
dmaInfoTbl: Annotated[c.Array[NV2080_CTRL_DMA_INFO, Literal[256]], 4]
|
|
NV2080_CTRL_DMA_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_DMA_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO(c.Struct):
|
|
SIZE = 12
|
|
srcAddr: Annotated[NvU32, 0]
|
|
dstAddr: Annotated[NvU32, 4]
|
|
relComptagIndex: Annotated[NvU16, 8]
|
|
NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO: TypeAlias = struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO(c.Struct):
|
|
SIZE = 24
|
|
hMemory: Annotated[NvHandle, 0]
|
|
offset: Annotated[NvU64, 8]
|
|
size: Annotated[NvU64, 16]
|
|
NV2080_CTRL_DMABUF_MEM_HANDLE_INFO: TypeAlias = struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS(c.Struct):
|
|
SIZE = 3104
|
|
fd: Annotated[NvS32, 0]
|
|
totalObjects: Annotated[NvU32, 4]
|
|
numObjects: Annotated[NvU32, 8]
|
|
index: Annotated[NvU32, 12]
|
|
totalSize: Annotated[NvU64, 16]
|
|
mappingType: Annotated[NvU8, 24]
|
|
handles: Annotated[c.Array[NV2080_CTRL_DMABUF_MEM_HANDLE_INFO, Literal[128]], 32]
|
|
NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS: TypeAlias = struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
sramParityUncorrectedUnique: Annotated[NvU64, 0]
|
|
sramSecDedUncorrectedUnique: Annotated[NvU64, 8]
|
|
sramCorrectedUnique: Annotated[NvU64, 16]
|
|
dramUncorrectedTotal: Annotated[NvU64, 24]
|
|
dramCorrectedTotal: Annotated[NvU64, 32]
|
|
lastClearedTimestamp: Annotated[NvU32, 40]
|
|
sramBucketL2: Annotated[NvU64, 48]
|
|
sramBucketSM: Annotated[NvU64, 56]
|
|
sramBucketPcie: Annotated[NvU64, 64]
|
|
sramBucketFirmware: Annotated[NvU64, 72]
|
|
sramBucketOther: Annotated[NvU64, 80]
|
|
sramErrorThresholdExceeded: Annotated[NvBool, 88]
|
|
NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
sramCorUni: Annotated[NvU64, 0]
|
|
sramUncParityUni: Annotated[NvU64, 8]
|
|
sramUncSecDedUni: Annotated[NvU64, 16]
|
|
dramCorTot: Annotated[NvU64, 24]
|
|
dramUncTot: Annotated[NvU64, 32]
|
|
NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS: TypeAlias = struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
event: Annotated[NvU32, 0]
|
|
action: Annotated[NvU32, 4]
|
|
bNotifyState: Annotated[NvBool, 8]
|
|
info32: Annotated[NvU32, 12]
|
|
info16: Annotated[NvU16, 16]
|
|
NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS
|
|
class enum_NV2080_EVENT_HDACODEC_DSTATE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0 = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0', 0)
|
|
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1 = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1', 1)
|
|
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2 = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2', 2)
|
|
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT', 3)
|
|
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD', 4)
|
|
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX', 5)
|
|
|
|
NV2080_EVENT_HDACODEC_DSTATE: TypeAlias = enum_NV2080_EVENT_HDACODEC_DSTATE
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hMemory: Annotated[NvHandle, 0]
|
|
NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hSemMemory: Annotated[NvHandle, 0]
|
|
semOffset: Annotated[NvU32, 4]
|
|
NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
guestMSIAddr: Annotated[NvU64, 0]
|
|
guestMSIData: Annotated[NvU32, 8]
|
|
hSemMemory: Annotated[NvHandle, 12]
|
|
isReset: Annotated[NvBool, 16]
|
|
vgpuUuid: Annotated[c.Array[NvU8, Literal[16]], 17]
|
|
domainId: Annotated[NvU64, 40]
|
|
NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hSemMemory: Annotated[NvHandle, 0]
|
|
isSemaMemValidationEnabled: Annotated[NvBool, 4]
|
|
NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hEvent: Annotated[NvHandle, 0]
|
|
NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS
|
|
class enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL = enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD.define('NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL', 0)
|
|
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE = enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD.define('NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE', 1)
|
|
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM = enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD.define('NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM', 2)
|
|
|
|
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD: TypeAlias = enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
hEventBuffer: Annotated[NvHandle, 0]
|
|
recordSize: Annotated[NvU32, 4]
|
|
levelOfDetail: Annotated[NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD, 8]
|
|
eventFilter: Annotated[NvU32, 12]
|
|
bAllUsers: Annotated[NvBool, 16]
|
|
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hEventBuffer: Annotated[NvHandle, 0]
|
|
tracepointMask: Annotated[NvU64, 8]
|
|
gspLoggingBufferSize: Annotated[NvU32, 16]
|
|
gspLoggingBufferWatermark: Annotated[NvU32, 20]
|
|
NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS: TypeAlias = struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS
|
|
NV2080_CTRL_FB_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
fbInfoListSize: Annotated[NvU32, 0]
|
|
fbInfoList: Annotated[NvP64, 8]
|
|
NV2080_CTRL_FB_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 460
|
|
fbInfoListSize: Annotated[NvU32, 0]
|
|
fbInfoList: Annotated[c.Array[NV2080_CTRL_FB_INFO, Literal[57]], 4]
|
|
NV2080_CTRL_FB_GET_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
cpuVirtAddress: Annotated[NvP64, 0]
|
|
gpuVirtAddress: Annotated[NvU64, 8]
|
|
NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
flags: Annotated[NvU32, 0]
|
|
driveStrengthRiseCount: Annotated[NvU32, 4]
|
|
driveStrengthFallCount: Annotated[NvU32, 8]
|
|
driveStrengthTermCount: Annotated[NvU32, 12]
|
|
slewStrengthRiseCount: Annotated[NvU32, 16]
|
|
slewStrengthFallCount: Annotated[NvU32, 20]
|
|
NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
flags: Annotated[NvU32, 0]
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS(c.Struct):
|
|
SIZE = 4024
|
|
addressArray: Annotated[c.Array[NvU64, Literal[500]], 0]
|
|
addressArraySize: Annotated[NvU32, 4000]
|
|
addressAlign: Annotated[NvU32, 4004]
|
|
memBlockSizeBytes: Annotated[NvU64, 4008]
|
|
flags: Annotated[NvU32, 4016]
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_IS_KIND_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
operation: Annotated[NvU32, 0]
|
|
kind: Annotated[NvU32, 4]
|
|
result: Annotated[NvBool, 8]
|
|
NV2080_CTRL_FB_IS_KIND_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_IS_KIND_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
powerState: Annotated[NvU32, 0]
|
|
writeMode: Annotated[NvU32, 4]
|
|
bypassMode: Annotated[NvU32, 8]
|
|
rcmState: Annotated[NvU32, 12]
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG: TypeAlias = c.Array[Annotated[int, ctypes.c_ubyte], Literal[17]]
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO(c.Struct):
|
|
SIZE = 48
|
|
base: Annotated[NvU64, 0]
|
|
limit: Annotated[NvU64, 8]
|
|
reserved: Annotated[NvU64, 16]
|
|
performance: Annotated[NvU32, 24]
|
|
supportCompressed: Annotated[NvBool, 28]
|
|
supportISO: Annotated[NvBool, 29]
|
|
bProtected: Annotated[NvBool, 30]
|
|
blackList: Annotated[NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG, 31]
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS(c.Struct):
|
|
SIZE = 776
|
|
numFBRegions: Annotated[NvU32, 0]
|
|
fbRegion: Annotated[c.Array[NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO, Literal[16]], 8]
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO(c.Struct):
|
|
SIZE = 32
|
|
pageAddressWithEccOn: Annotated[NvU64, 0]
|
|
pageAddressWithEccOff: Annotated[NvU64, 8]
|
|
rbcAddress: Annotated[NvU32, 16]
|
|
source: Annotated[NvU32, 20]
|
|
status: Annotated[NvU32, 24]
|
|
timestamp: Annotated[NvU32, 28]
|
|
NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO: TypeAlias = struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS(c.Struct):
|
|
SIZE = 2064
|
|
offlined: Annotated[c.Array[NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO, Literal[64]], 0]
|
|
pageSize: Annotated[NvU32, 2048]
|
|
validEntries: Annotated[NvU32, 2052]
|
|
numPagesAdded: Annotated[NvU32, 2056]
|
|
NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS(c.Struct):
|
|
SIZE = 2056
|
|
offlined: Annotated[c.Array[NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO, Literal[64]], 0]
|
|
validEntries: Annotated[NvU32, 2048]
|
|
bRetirementPending: Annotated[NvBool, 2052]
|
|
retirementPending: Annotated[NvU8, 2053]
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS
|
|
class enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS', 0)
|
|
NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY', 1)
|
|
NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS', 2)
|
|
|
|
NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE: TypeAlias = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE
|
|
class enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE', 0)
|
|
NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST', 1)
|
|
|
|
NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE: TypeAlias = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE
|
|
@c.record
|
|
class struct_ACR_REQUEST_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
clientId: Annotated[NvU32, 0]
|
|
reqReadMask: Annotated[NvU32, 4]
|
|
reqWriteMask: Annotated[NvU32, 8]
|
|
regionSize: Annotated[NvU32, 12]
|
|
ACR_REQUEST_PARAMS: TypeAlias = struct_ACR_REQUEST_PARAMS
|
|
@c.record
|
|
class struct_ACR_REGION_ID_PROP(c.Struct):
|
|
SIZE = 32
|
|
regionId: Annotated[NvU32, 0]
|
|
readMask: Annotated[NvU32, 4]
|
|
writeMask: Annotated[NvU32, 8]
|
|
regionSize: Annotated[NvU32, 12]
|
|
clientMask: Annotated[NvU32, 16]
|
|
physicalAddress: Annotated[NvU64, 24]
|
|
ACR_REGION_ID_PROP: TypeAlias = struct_ACR_REGION_ID_PROP
|
|
@c.record
|
|
class struct_ACR_STATUS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
allocStatus: Annotated[NvU32, 0]
|
|
regionId: Annotated[NvU32, 4]
|
|
physicalAddress: Annotated[NvU64, 8]
|
|
ACR_STATUS_PARAMS: TypeAlias = struct_ACR_STATUS_PARAMS
|
|
@c.record
|
|
class struct_ACR_REGION_HANDLE(c.Struct):
|
|
SIZE = 20
|
|
hClient: Annotated[NvHandle, 0]
|
|
hParent: Annotated[NvHandle, 4]
|
|
hMemory: Annotated[NvHandle, 8]
|
|
hClass: Annotated[NvU32, 12]
|
|
hDevice: Annotated[NvHandle, 16]
|
|
ACR_REGION_HANDLE: TypeAlias = struct_ACR_REGION_HANDLE
|
|
@c.record
|
|
class struct_ACR_FALCON_LS_STATUS(c.Struct):
|
|
SIZE = 4
|
|
falconId: Annotated[NvU16, 0]
|
|
bIsInLs: Annotated[NvBool, 2]
|
|
ACR_FALCON_LS_STATUS: TypeAlias = struct_ACR_FALCON_LS_STATUS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
queryType: Annotated[NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE, 0]
|
|
errorCode: Annotated[NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE, 4]
|
|
acrRegionIdProp: Annotated[ACR_REGION_ID_PROP, 8]
|
|
clientReq: Annotated[ACR_REQUEST_PARAMS, 40]
|
|
clientReqStatus: Annotated[ACR_STATUS_PARAMS, 56]
|
|
handle: Annotated[ACR_REGION_HANDLE, 72]
|
|
falconStatus: Annotated[ACR_FALCON_LS_STATUS, 92]
|
|
NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
sourceMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pCompBitCopyObj: Annotated[NvP64, 0]
|
|
pSwizzleParams: Annotated[NvP64, 8]
|
|
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
fbpIndex: Annotated[NvU8, 0]
|
|
ltcMask: Annotated[NvU32, 4]
|
|
ltcCount: Annotated[NvU32, 8]
|
|
ltsMask: Annotated[NvU32, 12]
|
|
ltsCount: Annotated[NvU32, 16]
|
|
NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
CBCBaseAddress: Annotated[NvU32, 0]
|
|
backingStorePA: Annotated[NvU64, 8]
|
|
backingStoreVA: Annotated[c.POINTER[NvU8], 16]
|
|
backingStoreChunkPA: Annotated[NvU64, 24]
|
|
backingStoreChunkVA: Annotated[c.POINTER[NvU8], 32]
|
|
backingStoreChunkSize: Annotated[NvU32, 40]
|
|
cacheWriteBitMap: Annotated[c.POINTER[NvU8], 48]
|
|
backingStoreChunkOverfetch: Annotated[NvBool, 56]
|
|
PageSizeSrc: Annotated[NvU32, 60]
|
|
PageSizeDest: Annotated[NvU32, 64]
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
fcbits: Annotated[c.POINTER[NvU32], 0]
|
|
compbits: Annotated[c.POINTER[NvU32], 8]
|
|
dataPhysicalStart: Annotated[NvU64, 16]
|
|
surfaceOffset: Annotated[NvU64, 24]
|
|
comptagLine: Annotated[NvU32, 32]
|
|
upper64KBCompbitSel: Annotated[NvBool, 36]
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
fcbits: Annotated[NvU32, 0]
|
|
compbits: Annotated[NvU32, 4]
|
|
writeFc: Annotated[NvBool, 8]
|
|
dataPhysicalStart: Annotated[NvU64, 16]
|
|
surfaceOffset: Annotated[NvU64, 24]
|
|
comptagLine: Annotated[NvU32, 32]
|
|
upper64KBCompbitSel: Annotated[NvBool, 36]
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
SrcDataPhysicalStart: Annotated[NvU64, 0]
|
|
SrcComptagLine: Annotated[NvU32, 8]
|
|
page64KB: Annotated[NvU32, 12]
|
|
compbitBuffer: Annotated[c.POINTER[NvU32], 16]
|
|
upper64KBCompbitSel: Annotated[NvBool, 24]
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
DstDataPhysicalStart: Annotated[NvU64, 0]
|
|
DstComptagLine: Annotated[NvU32, 8]
|
|
page64KB: Annotated[NvU32, 12]
|
|
compbitBuffer: Annotated[c.POINTER[NvU32], 16]
|
|
upper64KBCompbitSel: Annotated[NvBool, 24]
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bForceBar1: Annotated[NvBool, 0]
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pAmapConfParams: Annotated[NvP64, 0]
|
|
pCbcSwizzleParams: Annotated[NvP64, 8]
|
|
NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS
|
|
class enum_CTRL_CMD_FB_CBC_OP(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
CTRL_CMD_FB_CBC_OP_CLEAN = enum_CTRL_CMD_FB_CBC_OP.define('CTRL_CMD_FB_CBC_OP_CLEAN', 0)
|
|
CTRL_CMD_FB_CBC_OP_INVALIDATE = enum_CTRL_CMD_FB_CBC_OP.define('CTRL_CMD_FB_CBC_OP_INVALIDATE', 1)
|
|
|
|
CTRL_CMD_FB_CBC_OP: TypeAlias = enum_CTRL_CMD_FB_CBC_OP
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
fbCBCOp: Annotated[CTRL_CMD_FB_CBC_OP, 0]
|
|
NV2080_CTRL_CMD_FB_CBC_OP_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS(c.Struct):
|
|
SIZE = 512
|
|
pCompTags: Annotated[c.Array[NvU32, Literal[127]], 0]
|
|
numCompTags: Annotated[NvU32, 508]
|
|
NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
attr: Annotated[NvU32, 0]
|
|
attr2: Annotated[NvU32, 4]
|
|
size: Annotated[NvU32, 8]
|
|
ctagOffset: Annotated[NvU32, 12]
|
|
hwResId: Annotated[NvU32, 16]
|
|
retCompTagLineMin: Annotated[NvU32, 20]
|
|
retCompTagLineMax: Annotated[NvU32, 24]
|
|
NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hwResId: Annotated[NvU32, 0]
|
|
NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS
|
|
class enum_NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_CMD_FB_SET_VPR = enum_NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE.define('NV2080_CTRL_CMD_FB_SET_VPR', 0)
|
|
|
|
NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE: TypeAlias = enum_NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE
|
|
class enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC = enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE.define('NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC', 0)
|
|
NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST = enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE.define('NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST', 1)
|
|
|
|
NV2080_CTRL_CMD_FB_VPR_ERROR_CODE: TypeAlias = enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE
|
|
@c.record
|
|
class struct_VPR_REQUEST_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
startAddr: Annotated[NvU32, 0]
|
|
size: Annotated[NvU32, 4]
|
|
VPR_REQUEST_PARAMS: TypeAlias = struct_VPR_REQUEST_PARAMS
|
|
@c.record
|
|
class struct_VPR_STATUS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
status: Annotated[NvU32, 0]
|
|
VPR_STATUS_PARAMS: TypeAlias = struct_VPR_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
requestType: Annotated[NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE, 0]
|
|
requestParams: Annotated[VPR_REQUEST_PARAMS, 4]
|
|
statusParams: Annotated[VPR_STATUS_PARAMS, 12]
|
|
NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS
|
|
PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS: TypeAlias = c.POINTER[struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS]
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS(c.Struct):
|
|
SIZE = 264
|
|
offlinedPages: Annotated[c.Array[NvU32, Literal[64]], 0]
|
|
pageSize: Annotated[NvU32, 256]
|
|
validEntries: Annotated[NvU32, 260]
|
|
NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
defaultPageSize: Annotated[NvU32, 0]
|
|
comptagsPerCacheLine: Annotated[NvU32, 4]
|
|
unpackedComptagLinesPerCacheLine: Annotated[NvU32, 8]
|
|
compCacheLineSizePerLTC: Annotated[NvU32, 12]
|
|
unpackedCompCacheLineSizePerLTC: Annotated[NvU32, 16]
|
|
slicesPerLTC: Annotated[NvU32, 20]
|
|
numActiveLTCs: Annotated[NvU32, 24]
|
|
familyName: Annotated[NvU32, 28]
|
|
chipName: Annotated[NvU32, 32]
|
|
bitsPerRAMEntry: Annotated[NvU32, 36]
|
|
ramBankWidth: Annotated[NvU32, 40]
|
|
bitsPerComptagLine: Annotated[NvU32, 44]
|
|
ramEntriesPerCompCacheLine: Annotated[NvU32, 48]
|
|
comptagLineSize: Annotated[NvU32, 52]
|
|
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_SET_RRD_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rrd: Annotated[NvU32, 0]
|
|
NV2080_CTRL_FB_SET_RRD_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_SET_RRD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
limit: Annotated[NvU8, 0]
|
|
NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS
|
|
NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS
|
|
NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnable: Annotated[NvBool, 0]
|
|
NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS(c.Struct):
|
|
SIZE = 88
|
|
alignType: Annotated[NvU32, 0]
|
|
alignAttr: Annotated[NvU32, 4]
|
|
alignInputFlags: Annotated[NvU32, 8]
|
|
alignHead: Annotated[NvU32, 12]
|
|
alignSize: Annotated[NvU64, 16]
|
|
alignHeight: Annotated[NvU32, 24]
|
|
alignWidth: Annotated[NvU32, 28]
|
|
alignPitch: Annotated[NvU32, 32]
|
|
alignPad: Annotated[NvU32, 36]
|
|
alignMask: Annotated[NvU32, 40]
|
|
alignOutputFlags: Annotated[c.Array[NvU32, Literal[4]], 44]
|
|
alignBank: Annotated[c.Array[NvU32, Literal[4]], 60]
|
|
alignKind: Annotated[NvU32, 76]
|
|
alignAdjust: Annotated[NvU32, 80]
|
|
alignAttr2: Annotated[NvU32, 84]
|
|
NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
cbcBaseAddress: Annotated[NvU32, 0]
|
|
compCacheLineSize: Annotated[NvU32, 4]
|
|
backingStoreStartPA: Annotated[NvU64, 8]
|
|
backingStoreAllocPA: Annotated[NvU64, 16]
|
|
backingStoreChunkOverfetch: Annotated[NvU32, 24]
|
|
NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_REMAP_ENTRY(c.Struct):
|
|
SIZE = 12
|
|
remapRegVal: Annotated[NvU32, 0]
|
|
timestamp: Annotated[NvU32, 4]
|
|
fbpa: Annotated[NvU8, 8]
|
|
sublocation: Annotated[NvU8, 9]
|
|
source: Annotated[NvU8, 10]
|
|
flags: Annotated[NvU8, 11]
|
|
NV2080_CTRL_FB_REMAP_ENTRY: TypeAlias = struct_NV2080_CTRL_FB_REMAP_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS(c.Struct):
|
|
SIZE = 6152
|
|
entryCount: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU8, 4]
|
|
entries: Annotated[c.Array[NV2080_CTRL_FB_REMAP_ENTRY, Literal[512]], 8]
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
data: Annotated[c.Array[NvU8, Literal[24]], 0]
|
|
NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
swizzId: Annotated[NvU32, 0]
|
|
fbpEnMask: Annotated[NvU64, 8]
|
|
NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
ltcEnMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
ltsEnMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
fbpaEnMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
fbpaSubpEnMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
fbpLogicalIndex: Annotated[NvU32, 4]
|
|
NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
ropEnMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
swizzId: Annotated[NvU32, 4]
|
|
ltcEnMask: Annotated[NvU32, 8]
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
swizzId: Annotated[NvU32, 4]
|
|
ltsEnMask: Annotated[NvU32, 8]
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
swizzId: Annotated[NvU32, 4]
|
|
fbpaEnMask: Annotated[NvU32, 8]
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
swizzId: Annotated[NvU32, 4]
|
|
ropEnMask: Annotated[NvU32, 8]
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
swizzId: Annotated[NvU32, 4]
|
|
fbpaSubpEnMask: Annotated[NvU64, 8]
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
sysIdx: Annotated[NvU32, 0]
|
|
sysl2LtcEnMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
sysIdx: Annotated[NvU32, 0]
|
|
sysl2LtsEnMask: Annotated[NvU64, 8]
|
|
NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
pacEnMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
logicalLtcEnMask: Annotated[NvU64, 8]
|
|
NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
fbpIndex: Annotated[NvU32, 0]
|
|
swizzId: Annotated[NvU32, 4]
|
|
logicalLtcEnMask: Annotated[NvU64, 8]
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_QUERY(c.Struct):
|
|
SIZE = 32
|
|
queryType: Annotated[NvU16, 0]
|
|
reserved: Annotated[c.Array[NvU8, Literal[2]], 2]
|
|
status: Annotated[NvU32, 4]
|
|
queryParams: Annotated[struct_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams, 8]
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams(c.Struct):
|
|
SIZE = 24
|
|
inv: Annotated[NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS, 0]
|
|
fbp: Annotated[NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS, 0]
|
|
ltc: Annotated[NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS, 0]
|
|
lts: Annotated[NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS, 0]
|
|
fbpa: Annotated[NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS, 0]
|
|
rop: Annotated[NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS, 0]
|
|
dmLtc: Annotated[NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS, 0]
|
|
dmLts: Annotated[NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS, 0]
|
|
dmFbpa: Annotated[NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS, 0]
|
|
dmRop: Annotated[NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS, 0]
|
|
dmFbpaSubp: Annotated[NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS, 0]
|
|
fbpaSubp: Annotated[NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS, 0]
|
|
fbpLogicalMap: Annotated[NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS, 0]
|
|
sysl2Ltc: Annotated[NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS, 0]
|
|
pac: Annotated[NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS, 0]
|
|
logicalLtc: Annotated[NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS, 0]
|
|
dmLogicalLtc: Annotated[NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS, 0]
|
|
sysl2Lts: Annotated[NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS, 0]
|
|
NV2080_CTRL_FB_FS_INFO_QUERY: TypeAlias = struct_NV2080_CTRL_FB_FS_INFO_QUERY
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS(c.Struct):
|
|
SIZE = 3848
|
|
numQueries: Annotated[NvU16, 0]
|
|
reserved: Annotated[c.Array[NvU8, Literal[6]], 2]
|
|
queries: Annotated[c.Array[NV2080_CTRL_FB_FS_INFO_QUERY, Literal[120]], 8]
|
|
NV2080_CTRL_FB_GET_FS_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
histogram: Annotated[c.Array[NvU32, Literal[5]], 0]
|
|
NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO(c.Struct):
|
|
SIZE = 16
|
|
pageNumber: Annotated[NvU64, 0]
|
|
source: Annotated[NvU8, 8]
|
|
NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO: TypeAlias = struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS(c.Struct):
|
|
SIZE = 1040
|
|
offlined: Annotated[c.Array[NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO, Literal[64]], 0]
|
|
validEntries: Annotated[NvU32, 1024]
|
|
baseIndex: Annotated[NvU32, 1028]
|
|
bMore: Annotated[NvBool, 1032]
|
|
NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO(c.Struct):
|
|
SIZE = 24
|
|
client: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
beginAddr: Annotated[NvU64, 8]
|
|
size: Annotated[NvU64, 16]
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_INFO: TypeAlias = struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_CLIENT_INFO(c.Struct):
|
|
SIZE = 112
|
|
handle: Annotated[NvHandle, 0]
|
|
pid: Annotated[NvU32, 4]
|
|
subProcessID: Annotated[NvU32, 8]
|
|
subProcessName: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[100]], 12]
|
|
NV2080_CTRL_CMD_FB_CLIENT_INFO: TypeAlias = struct_NV2080_CTRL_CMD_FB_CLIENT_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
allocCount: Annotated[NvU64, 0]
|
|
pAllocInfo: Annotated[NvP64, 8]
|
|
clientCount: Annotated[NvU64, 16]
|
|
pClientInfo: Annotated[NvP64, 24]
|
|
NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bOnline: Annotated[NvBool, 0]
|
|
NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS(c.Struct):
|
|
SIZE = 544
|
|
numaNodeId: Annotated[NvS32, 0]
|
|
numaMemAddr: Annotated[NvU64, 8]
|
|
numaMemSize: Annotated[NvU64, 16]
|
|
numaOfflineAddressesCount: Annotated[NvU32, 24]
|
|
numaOfflineAddresses: Annotated[c.Array[NvU64, Literal[64]], 32]
|
|
NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
maxSubmittedSemaphoreValueOffset: Annotated[NvU64, 0]
|
|
monitoredFenceThresholdOffset: Annotated[NvU64, 8]
|
|
size: Annotated[NvU64, 16]
|
|
caps: Annotated[NvU32, 24]
|
|
NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_STATS_ENTRY(c.Struct):
|
|
SIZE = 48
|
|
totalSize: Annotated[NvU64, 0]
|
|
rsvdSize: Annotated[NvU64, 8]
|
|
osSize: Annotated[NvU64, 16]
|
|
r1Size: Annotated[NvU64, 24]
|
|
r2Size: Annotated[NvU64, 32]
|
|
freeSize: Annotated[NvU64, 40]
|
|
NV2080_CTRL_CMD_FB_STATS_ENTRY: TypeAlias = struct_NV2080_CTRL_CMD_FB_STATS_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gfid: Annotated[NvU32, 0]
|
|
invalidateAll: Annotated[NvBool, 4]
|
|
NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS: TypeAlias = struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO(c.Struct):
|
|
SIZE = 24
|
|
allocSize: Annotated[NvU64, 0]
|
|
numBlocks: Annotated[NvU32, 8]
|
|
rsvdSize: Annotated[NvU64, 16]
|
|
NV2080_CTRL_CMD_FB_STATS_OWNER_INFO: TypeAlias = struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS(c.Struct):
|
|
SIZE = 4856
|
|
version: Annotated[NvU64, 0]
|
|
fbSizeInfo: Annotated[NV2080_CTRL_CMD_FB_STATS_ENTRY, 8]
|
|
fbBlockInfo: Annotated[c.Array[NV2080_CTRL_CMD_FB_STATS_OWNER_INFO, Literal[200]], 56]
|
|
NV2080_CTRL_CMD_FB_STATS_GET_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
bStaticBar1Enabled: Annotated[NvBool, 0]
|
|
staticBar1StartOffset: Annotated[NvU64, 8]
|
|
staticBar1Size: Annotated[NvU64, 16]
|
|
NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
currentConfiguration: Annotated[NvU32, 0]
|
|
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
newConfiguration: Annotated[NvU32, 0]
|
|
NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_GET_STATUS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
fbStatus: Annotated[NvU32, 0]
|
|
NV2080_CTRL_FB_GET_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_GET_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
isSupported: Annotated[NvU32, 0]
|
|
NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
currentStatus: Annotated[NvU32, 0]
|
|
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hChannel: Annotated[NvHandle, 0]
|
|
base: Annotated[NvU64, 8]
|
|
numEntries: Annotated[NvU32, 16]
|
|
NV2080_CTRL_CMD_SET_GPFIFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_BIND_CHANNEL(c.Struct):
|
|
SIZE = 8
|
|
hClient: Annotated[NvHandle, 0]
|
|
hChannel: Annotated[NvHandle, 4]
|
|
NV2080_CTRL_FIFO_BIND_CHANNEL: TypeAlias = struct_NV2080_CTRL_FIFO_BIND_CHANNEL
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS(c.Struct):
|
|
SIZE = 132
|
|
bindChannelCount: Annotated[NvU32, 0]
|
|
bindChannels: Annotated[c.Array[NV2080_CTRL_FIFO_BIND_CHANNEL, Literal[16]], 4]
|
|
NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
flags: Annotated[NvU32, 0]
|
|
NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
physChannelCount: Annotated[NvU32, 0]
|
|
physChannelCountInUse: Annotated[NvU32, 4]
|
|
NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS
|
|
NV2080_CTRL_FIFO_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 2056
|
|
fifoInfoTblSize: Annotated[NvU32, 0]
|
|
fifoInfoTbl: Annotated[c.Array[NV2080_CTRL_FIFO_INFO, Literal[256]], 4]
|
|
engineType: Annotated[NvU32, 2052]
|
|
NV2080_CTRL_FIFO_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
hChannel: Annotated[NvHandle, 0]
|
|
NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 536
|
|
bDisable: Annotated[NvBool, 0]
|
|
numChannels: Annotated[NvU32, 4]
|
|
bOnlyDisableScheduling: Annotated[NvBool, 8]
|
|
bRewindGpPut: Annotated[NvBool, 9]
|
|
pRunlistPreemptEvent: Annotated[NvP64, 16]
|
|
hClientList: Annotated[c.Array[NvHandle, Literal[64]], 24]
|
|
hChannelList: Annotated[c.Array[NvHandle, Literal[64]], 280]
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_MEM_INFO(c.Struct):
|
|
SIZE = 24
|
|
aperture: Annotated[NvU32, 0]
|
|
base: Annotated[NvU64, 8]
|
|
size: Annotated[NvU64, 16]
|
|
NV2080_CTRL_FIFO_MEM_INFO: TypeAlias = struct_NV2080_CTRL_FIFO_MEM_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO(c.Struct):
|
|
SIZE = 104
|
|
inst: Annotated[NV2080_CTRL_FIFO_MEM_INFO, 0]
|
|
ramfc: Annotated[NV2080_CTRL_FIFO_MEM_INFO, 24]
|
|
methodBuf: Annotated[c.Array[NV2080_CTRL_FIFO_MEM_INFO, Literal[2]], 48]
|
|
methodBufCount: Annotated[NvU32, 96]
|
|
NV2080_CTRL_FIFO_CHANNEL_MEM_INFO: TypeAlias = struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS(c.Struct):
|
|
SIZE = 112
|
|
hChannel: Annotated[NvHandle, 0]
|
|
chMemInfo: Annotated[NV2080_CTRL_FIFO_CHANNEL_MEM_INFO, 8]
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
aperture: Annotated[NvU32, 0]
|
|
attribute: Annotated[NvU32, 4]
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS(c.Struct):
|
|
SIZE = 20824
|
|
engineId: Annotated[NvU32, 0]
|
|
count: Annotated[NvU32, 4]
|
|
entry: Annotated[c.Array[struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_entry, Literal[200]], 8]
|
|
schedPolicy: Annotated[NvU32, 20808]
|
|
arrEnabled: Annotated[NvU32, 20812]
|
|
arrAvgFactor: Annotated[NvU32, 20816]
|
|
targetTimesliceNs: Annotated[NvU32, 20820]
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_entry(c.Struct):
|
|
SIZE = 104
|
|
timestampNs: Annotated[NvU64, 0]
|
|
timeRunTotalNs: Annotated[NvS64, 8]
|
|
timeRunNs: Annotated[NvU32, 16]
|
|
swrlId: Annotated[NvU32, 20]
|
|
targetTimeSlice: Annotated[NvU32, 24]
|
|
cumulativePreemptionTime: Annotated[NvU64, 32]
|
|
counters: Annotated[c.Array[NvU64, Literal[8]], 40]
|
|
NvS64: TypeAlias = Annotated[int, ctypes.c_int64]
|
|
NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_DEVICE_ENTRY(c.Struct):
|
|
SIZE = 100
|
|
engineData: Annotated[c.Array[NvU32, Literal[16]], 0]
|
|
pbdmaIds: Annotated[c.Array[NvU32, Literal[2]], 64]
|
|
pbdmaFaultIds: Annotated[c.Array[NvU32, Literal[2]], 72]
|
|
numPbdmas: Annotated[NvU32, 80]
|
|
engineName: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[16]], 84]
|
|
NV2080_CTRL_FIFO_DEVICE_ENTRY: TypeAlias = struct_NV2080_CTRL_FIFO_DEVICE_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS(c.Struct):
|
|
SIZE = 3212
|
|
baseIndex: Annotated[NvU32, 0]
|
|
numEntries: Annotated[NvU32, 4]
|
|
bMore: Annotated[NvBool, 8]
|
|
entries: Annotated[c.Array[NV2080_CTRL_FIFO_DEVICE_ENTRY, Literal[32]], 12]
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
engineType: Annotated[NvU32, 0]
|
|
vChid: Annotated[NvU32, 4]
|
|
faultType: Annotated[NvU32, 8]
|
|
NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
flags: Annotated[NvU32, 0]
|
|
schedPolicy: Annotated[NvU32, 4]
|
|
NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hClient: Annotated[NvHandle, 0]
|
|
hChannel: Annotated[NvHandle, 4]
|
|
hUserdMemory: Annotated[NvHandle, 8]
|
|
gpFifoEntries: Annotated[NvU32, 12]
|
|
gpFifoOffset: Annotated[NvU64, 16]
|
|
userdOffset: Annotated[NvU64, 24]
|
|
NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bDisable: Annotated[NvBool, 0]
|
|
NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: Annotated[NvU64, 0]
|
|
size: Annotated[NvU64, 8]
|
|
addressSpace: Annotated[NvU32, 16]
|
|
cacheAttrib: Annotated[NvU32, 20]
|
|
NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 516
|
|
runlistId: Annotated[NvU32, 0]
|
|
bitMask: Annotated[c.Array[NvU32, Literal[128]], 4]
|
|
NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS(c.Struct):
|
|
SIZE = 520
|
|
numChannels: Annotated[NvU32, 0]
|
|
hClientList: Annotated[c.Array[NvHandle, Literal[64]], 4]
|
|
hChannelList: Annotated[c.Array[NvHandle, Literal[64]], 260]
|
|
bEnableAfterKeyRotation: Annotated[NvBool, 516]
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS(c.Struct):
|
|
SIZE = 264
|
|
numChannels: Annotated[NvU32, 0]
|
|
hChannelList: Annotated[c.Array[NvHandle, Literal[64]], 4]
|
|
bEnableAfterKeyRotation: Annotated[NvBool, 260]
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
engineId: Annotated[NvU32, 0]
|
|
schedPolicy: Annotated[NvU32, 4]
|
|
arrEnabled: Annotated[NvU32, 8]
|
|
targetTimesliceNs: Annotated[NvU32, 12]
|
|
arrAvgFactor: Annotated[NvU32, 16]
|
|
NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
engineId: Annotated[NvU32, 0]
|
|
schedPolicy: Annotated[NvU32, 4]
|
|
enableArr: Annotated[NvU32, 8]
|
|
timesliceTargetNs: Annotated[NvU32, 12]
|
|
frequencyForARR: Annotated[NvU32, 16]
|
|
avgFactorForARR: Annotated[NvU32, 20]
|
|
NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 44
|
|
engineId: Annotated[NvU32, 0]
|
|
supportedSchedulers: Annotated[c.Array[NvU32, Literal[3]], 4]
|
|
bIsArrModeSupported: Annotated[NvBool, 16]
|
|
maxTimesliceNs: Annotated[NvU32, 20]
|
|
minTimesliceNs: Annotated[NvU32, 24]
|
|
maxFrequencyForARR: Annotated[NvU32, 28]
|
|
minFrequencyForARR: Annotated[NvU32, 32]
|
|
maxAvgFactorForARR: Annotated[NvU32, 36]
|
|
minAvgFactorForARR: Annotated[NvU32, 40]
|
|
NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS(c.Struct):
|
|
SIZE = 1552
|
|
hClient: Annotated[NvHandle, 0]
|
|
hChannelOrTsg: Annotated[NvHandle, 4]
|
|
tsgId: Annotated[NvU32, 8]
|
|
numChannels: Annotated[NvU32, 12]
|
|
channelUniqueID: Annotated[c.Array[NvU32, Literal[128]], 16]
|
|
vasUniqueID: Annotated[c.Array[NvU32, Literal[128]], 528]
|
|
veid: Annotated[c.Array[NvU32, Literal[128]], 1040]
|
|
NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS(c.Struct):
|
|
SIZE = 1540
|
|
hClients: Annotated[c.Array[NvHandle, Literal[128]], 0]
|
|
hChannels: Annotated[c.Array[NvHandle, Literal[128]], 512]
|
|
numChannels: Annotated[NvU32, 1024]
|
|
channelUniqueIDs: Annotated[c.Array[NvU32, Literal[128]], 1028]
|
|
NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS: TypeAlias = struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLA_RANGE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
base: Annotated[NvU64, 0]
|
|
size: Annotated[NvU64, 8]
|
|
mode: Annotated[NvU32, 16]
|
|
hVASpace: Annotated[NvHandle, 20]
|
|
NV2080_CTRL_FLA_RANGE_PARAMS: TypeAlias = struct_NV2080_CTRL_FLA_RANGE_PARAMS
|
|
class enum_NV2080_CTRL_FLA_ADDRSPACE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_FLA_ADDRSPACE_SYSMEM = enum_NV2080_CTRL_FLA_ADDRSPACE.define('NV2080_CTRL_FLA_ADDRSPACE_SYSMEM', 0)
|
|
NV2080_CTRL_FLA_ADDRSPACE_FBMEM = enum_NV2080_CTRL_FLA_ADDRSPACE.define('NV2080_CTRL_FLA_ADDRSPACE_FBMEM', 1)
|
|
|
|
NV2080_CTRL_FLA_ADDRSPACE: TypeAlias = enum_NV2080_CTRL_FLA_ADDRSPACE
|
|
class enum_NV2080_CTRL_FLA_ACTION(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_FLA_ACTION_BIND = enum_NV2080_CTRL_FLA_ACTION.define('NV2080_CTRL_FLA_ACTION_BIND', 0)
|
|
NV2080_CTRL_FLA_ACTION_UNBIND = enum_NV2080_CTRL_FLA_ACTION.define('NV2080_CTRL_FLA_ACTION_UNBIND', 1)
|
|
|
|
NV2080_CTRL_FLA_ACTION: TypeAlias = enum_NV2080_CTRL_FLA_ACTION
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
imbPhysAddr: Annotated[NvU64, 0]
|
|
addrSpace: Annotated[NV2080_CTRL_FLA_ADDRSPACE, 8]
|
|
flaAction: Annotated[NV2080_CTRL_FLA_ACTION, 12]
|
|
NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS: TypeAlias = struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
base: Annotated[NvU64, 0]
|
|
size: Annotated[NvU64, 8]
|
|
NV2080_CTRL_FLA_GET_RANGE_PARAMS: TypeAlias = struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
totalSize: Annotated[NvU64, 0]
|
|
freeSize: Annotated[NvU64, 8]
|
|
NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
flcnID: Annotated[NvU32, 0]
|
|
heapSize: Annotated[NvU32, 4]
|
|
heapFree: Annotated[NvU32, 8]
|
|
NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
engine: Annotated[NvU32, 0]
|
|
engineArch: Annotated[NvU32, 4]
|
|
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER(c.Struct):
|
|
SIZE = 36
|
|
mask: Annotated[c.Array[NvU8, Literal[36]], 0]
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER: TypeAlias = struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
engine: Annotated[NvU32, 0]
|
|
pageSize: Annotated[NvU32, 4]
|
|
offset: Annotated[NvUPtr, 8]
|
|
size: Annotated[NvU32, 16]
|
|
queueFeatureId: Annotated[NvU8, 20]
|
|
NvUPtr: TypeAlias = Annotated[int, ctypes.c_uint64]
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 44
|
|
engine: Annotated[NvU32, 0]
|
|
eventFilter: Annotated[NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER, 4]
|
|
queueId: Annotated[NvU8, 40]
|
|
NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS
|
|
NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS
|
|
NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
hUserClient: Annotated[NvHandle, 0]
|
|
hChannel: Annotated[NvHandle, 4]
|
|
alignment: Annotated[NvU64, 8]
|
|
size: Annotated[NvU64, 16]
|
|
bufferHandle: Annotated[NvP64, 24]
|
|
pageCount: Annotated[NvU64, 32]
|
|
physAddr: Annotated[NvU64, 40]
|
|
aperture: Annotated[NvU32, 48]
|
|
kind: Annotated[NvU32, 52]
|
|
pageSize: Annotated[NvU32, 56]
|
|
bIsContigous: Annotated[NvBool, 60]
|
|
bDeviceDescendant: Annotated[NvBool, 61]
|
|
uuid: Annotated[c.Array[NvU8, Literal[16]], 62]
|
|
NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hChannel: Annotated[NvHandle, 0]
|
|
totalBufferSize: Annotated[NvU64, 8]
|
|
NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpioPin: Annotated[NvU32, 0]
|
|
bInput: Annotated[NvBool, 4]
|
|
NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpioPin: Annotated[NvU32, 0]
|
|
value: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpioPin: Annotated[NvU32, 0]
|
|
value: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
function: Annotated[NvU32, 0]
|
|
pin: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS
|
|
NV2080_CTRL_GPU_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
gpuInfoListSize: Annotated[NvU32, 0]
|
|
gpuInfoList: Annotated[NvP64, 8]
|
|
NV2080_CTRL_GPU_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 524
|
|
gpuInfoListSize: Annotated[NvU32, 0]
|
|
gpuInfoList: Annotated[c.Array[NV2080_CTRL_GPU_INFO, Literal[65]], 4]
|
|
NV2080_CTRL_GPU_GET_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS(c.Struct):
|
|
SIZE = 132
|
|
gpuNameStringFlags: Annotated[NvU32, 0]
|
|
gpuNameString: Annotated[struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString, 4]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString(c.Struct):
|
|
SIZE = 128
|
|
ascii: Annotated[c.Array[NvU8, Literal[64]], 0]
|
|
unicode: Annotated[c.Array[NvU16, Literal[64]], 0]
|
|
NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS(c.Struct):
|
|
SIZE = 64
|
|
gpuShortNameString: Annotated[c.Array[NvU8, Literal[64]], 0]
|
|
NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_POWER_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
target: Annotated[NvU32, 0]
|
|
newLevel: Annotated[NvU32, 4]
|
|
oldLevel: Annotated[NvU32, 8]
|
|
NV2080_CTRL_GPU_SET_POWER_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_POWER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_SDM_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
subdeviceMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_GET_SDM_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_SDM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_SDM_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
subdeviceMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_SET_SDM_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_SDM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
type: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_REG_OP(c.Struct):
|
|
SIZE = 32
|
|
regOp: Annotated[NvU8, 0]
|
|
regType: Annotated[NvU8, 1]
|
|
regStatus: Annotated[NvU8, 2]
|
|
regQuad: Annotated[NvU8, 3]
|
|
regGroupMask: Annotated[NvU32, 4]
|
|
regSubGroupMask: Annotated[NvU32, 8]
|
|
regOffset: Annotated[NvU32, 12]
|
|
regValueHi: Annotated[NvU32, 16]
|
|
regValueLo: Annotated[NvU32, 20]
|
|
regAndNMaskHi: Annotated[NvU32, 24]
|
|
regAndNMaskLo: Annotated[NvU32, 28]
|
|
NV2080_CTRL_GPU_REG_OP: TypeAlias = struct_NV2080_CTRL_GPU_REG_OP
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
hClientTarget: Annotated[NvHandle, 0]
|
|
hChannelTarget: Annotated[NvHandle, 4]
|
|
bNonTransactional: Annotated[NvU32, 8]
|
|
reserved00: Annotated[c.Array[NvU32, Literal[2]], 12]
|
|
regOpCount: Annotated[NvU32, 20]
|
|
regOps: Annotated[NvP64, 24]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 32]
|
|
NV2080_CTRL_GR_ROUTE_INFO: TypeAlias = struct_NV0080_CTRL_GR_ROUTE_INFO
|
|
NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
engineCount: Annotated[NvU32, 0]
|
|
engineList: Annotated[NvP64, 8]
|
|
NV2080_CTRL_GPU_GET_ENGINES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS(c.Struct):
|
|
SIZE = 340
|
|
engineCount: Annotated[NvU32, 0]
|
|
engineList: Annotated[c.Array[NvU32, Literal[84]], 4]
|
|
NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
engineType: Annotated[NvU32, 0]
|
|
numClasses: Annotated[NvU32, 4]
|
|
classList: Annotated[NvP64, 8]
|
|
NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
engineType: Annotated[NvU32, 0]
|
|
mmuFaultId: Annotated[NvU32, 4]
|
|
bSubcontextSupported: Annotated[NvBool, 8]
|
|
NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
mode: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_QUERY_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY(c.Struct):
|
|
SIZE = 32
|
|
gpuPhysAddr: Annotated[NvU64, 0]
|
|
gpuVirtAddr: Annotated[NvU64, 8]
|
|
size: Annotated[NvU64, 16]
|
|
physAttr: Annotated[NvU32, 24]
|
|
bufferId: Annotated[NvU16, 28]
|
|
bInitialize: Annotated[NvU8, 30]
|
|
bNonmapped: Annotated[NvU8, 31]
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY: TypeAlias = struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS(c.Struct):
|
|
SIZE = 560
|
|
engineType: Annotated[NvU32, 0]
|
|
hClient: Annotated[NvHandle, 4]
|
|
ChID: Annotated[NvU32, 8]
|
|
hChanClient: Annotated[NvHandle, 12]
|
|
hObject: Annotated[NvHandle, 16]
|
|
hVirtMemory: Annotated[NvHandle, 20]
|
|
virtAddress: Annotated[NvU64, 24]
|
|
size: Annotated[NvU64, 32]
|
|
entryCount: Annotated[NvU32, 40]
|
|
promoteEntry: Annotated[c.Array[NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY, Literal[16]], 48]
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS
|
|
PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS: TypeAlias = c.POINTER[struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
engineType: Annotated[NvU32, 0]
|
|
hClient: Annotated[NvHandle, 4]
|
|
ChID: Annotated[NvU32, 8]
|
|
hChanClient: Annotated[NvHandle, 12]
|
|
hObject: Annotated[NvHandle, 16]
|
|
NV2080_CTRL_GPU_EVICT_CTX_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS
|
|
PNV2080_CTRL_GPU_EVICT_CTX_PARAMS: TypeAlias = c.POINTER[struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
engineType: Annotated[NvU32, 0]
|
|
hClient: Annotated[NvHandle, 4]
|
|
ChID: Annotated[NvU32, 8]
|
|
hChanClient: Annotated[NvHandle, 12]
|
|
hObject: Annotated[NvHandle, 16]
|
|
hVirtMemory: Annotated[NvHandle, 20]
|
|
physAddress: Annotated[NvU64, 24]
|
|
physAttr: Annotated[NvU32, 32]
|
|
hDmaHandle: Annotated[NvHandle, 36]
|
|
index: Annotated[NvU32, 40]
|
|
size: Annotated[NvU64, 48]
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS
|
|
PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS: TypeAlias = c.POINTER[struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
eccIntrStatus: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS(c.Struct):
|
|
SIZE = 8
|
|
count: Annotated[NvU64, 0]
|
|
NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS(c.Struct):
|
|
SIZE = 40
|
|
enabled: Annotated[NvBool, 0]
|
|
scrubComplete: Annotated[NvBool, 1]
|
|
supported: Annotated[NvBool, 2]
|
|
dbe: Annotated[NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS, 8]
|
|
dbeNonResettable: Annotated[NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS, 16]
|
|
sbe: Annotated[NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS, 24]
|
|
sbeNonResettable: Annotated[NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS, 32]
|
|
NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1464
|
|
units: Annotated[c.Array[NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS, Literal[36]], 0]
|
|
bFatalPoisonError: Annotated[NvBool, 1440]
|
|
uncorrectableError: Annotated[NvU8, 1441]
|
|
flags: Annotated[NvU32, 1444]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 1448]
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
rules: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rules: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
currentConfiguration: Annotated[NvU32, 0]
|
|
defaultConfiguration: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
newConfiguration: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
statuses: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU8, 4]
|
|
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gpcMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: Annotated[NvU32, 0]
|
|
tpcMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: Annotated[NvU32, 0]
|
|
zcullMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS(c.Struct):
|
|
SIZE = 136
|
|
buildDate: Annotated[NvU32, 0]
|
|
marketingName: Annotated[c.Array[NvU8, Literal[24]], 4]
|
|
serialNumber: Annotated[c.Array[NvU8, Literal[16]], 28]
|
|
memoryManufacturer: Annotated[NvU8, 44]
|
|
memoryPartID: Annotated[c.Array[NvU8, Literal[20]], 45]
|
|
memoryDateCode: Annotated[c.Array[NvU8, Literal[6]], 65]
|
|
productPartNumber: Annotated[c.Array[NvU8, Literal[20]], 71]
|
|
boardRevision: Annotated[c.Array[NvU8, Literal[3]], 91]
|
|
boardType: Annotated[NvU8, 94]
|
|
board699PartNumber: Annotated[c.Array[NvU8, Literal[20]], 95]
|
|
board965PartNumber: Annotated[c.Array[NvU8, Literal[20]], 115]
|
|
NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ID_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gpuId: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_GET_ID_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
mode: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
currentMode: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS(c.Struct):
|
|
SIZE = 144
|
|
engineType: Annotated[NvU32, 0]
|
|
partnershipClassId: Annotated[NvU32, 4]
|
|
runqueue: Annotated[NvU32, 8]
|
|
numPartners: Annotated[NvU32, 12]
|
|
partnerList: Annotated[c.Array[NvU32, Literal[32]], 16]
|
|
NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS(c.Struct):
|
|
SIZE = 268
|
|
index: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
length: Annotated[NvU32, 8]
|
|
data: Annotated[c.Array[NvU8, Literal[256]], 12]
|
|
NV2080_CTRL_GPU_GET_GID_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS(c.Struct):
|
|
SIZE = 5
|
|
objectType: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[3]], 0]
|
|
version: Annotated[NvU8, 3]
|
|
subversion: Annotated[NvU8, 4]
|
|
NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
isOptimusEnabled: Annotated[NvBool, 0]
|
|
NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
targetEngine: Annotated[NvU32, 0]
|
|
ipVersion: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
attribute: Annotated[NvU32, 0]
|
|
bSupported: Annotated[NvBool, 4]
|
|
NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
attribute: Annotated[NvU32, 0]
|
|
value: Annotated[NvU32, 4]
|
|
NV2080_CTRL_CMD_GPU_ILLUM_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS
|
|
NV2080_CTRL_GPU_GET_ILLUM_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS
|
|
NV2080_CTRL_GPU_SET_ILLUM_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
version: Annotated[c.Array[NvU8, Literal[16]], 0]
|
|
NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fwVersion: Annotated[NvU32, 0]
|
|
oemVersion: Annotated[NvU8, 4]
|
|
siliconRevision: Annotated[NvU8, 5]
|
|
hwbcResourceType: Annotated[NvU8, 6]
|
|
NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS(c.Struct):
|
|
SIZE = 1204
|
|
bridgeCount: Annotated[NvU8, 0]
|
|
hPhysicalBridges: Annotated[c.Array[NvHandle, Literal[100]], 4]
|
|
bridgeList: Annotated[c.Array[NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS, Literal[100]], 404]
|
|
NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
bus: Annotated[NvU8, 0]
|
|
device: Annotated[NvU8, 1]
|
|
func: Annotated[NvU8, 2]
|
|
oemVersion: Annotated[NvU8, 3]
|
|
siliconRevision: Annotated[NvU8, 4]
|
|
hwbcResourceType: Annotated[NvU8, 5]
|
|
domain: Annotated[NvU32, 8]
|
|
fwVersion: Annotated[NvU32, 12]
|
|
NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS(c.Struct):
|
|
SIZE = 2004
|
|
bridgeCount: Annotated[NvU8, 0]
|
|
physicalBridgeIds: Annotated[c.Array[NvU32, Literal[100]], 4]
|
|
bridgeList: Annotated[c.Array[NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS, Literal[100]], 404]
|
|
NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
scrubberStatus: Annotated[NvU32, 0]
|
|
remainingTimeMs: Annotated[NvU32, 4]
|
|
scrubStartAddr: Annotated[NvU64, 8]
|
|
scrubEndAddr: Annotated[NvU64, 16]
|
|
NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
minStartAddr: Annotated[NvU64, 0]
|
|
maxEndAddr: Annotated[NvU64, 8]
|
|
NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
gpcId: Annotated[NvU32, 0]
|
|
numPesInGpc: Annotated[NvU32, 4]
|
|
activePesMask: Annotated[NvU32, 8]
|
|
maxTpcPerGpcCount: Annotated[NvU32, 12]
|
|
tpcToPesMap: Annotated[c.Array[NvU32, Literal[10]], 16]
|
|
NV2080_CTRL_GPU_GET_PES_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS(c.Struct):
|
|
SIZE = 504
|
|
oemInfo: Annotated[c.Array[NvU8, Literal[504]], 0]
|
|
NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS
|
|
class enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS = enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS', 0)
|
|
NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE = enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE', 1)
|
|
|
|
NV2080_CTRL_VPR_INFO_QUERY_TYPE: TypeAlias = enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
queryType: Annotated[NV2080_CTRL_VPR_INFO_QUERY_TYPE, 0]
|
|
bIsVprEnabled: Annotated[NvBool, 4]
|
|
vprStartAddressInBytes: Annotated[NvU64, 8]
|
|
vprEndAddressInBytes: Annotated[NvU64, 16]
|
|
NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS
|
|
class enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264', 0)
|
|
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC', 1)
|
|
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1 = enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1', 2)
|
|
|
|
NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE: TypeAlias = enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
queryType: Annotated[NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE, 0]
|
|
encoderCapacity: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
encoderSessionCount: Annotated[NvU32, 0]
|
|
averageEncodeFps: Annotated[NvU32, 4]
|
|
averageEncodeLatency: Annotated[NvU32, 8]
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVENC_SW_SESSION_INFO(c.Struct):
|
|
SIZE = 32
|
|
processId: Annotated[NvU32, 0]
|
|
subProcessId: Annotated[NvU32, 4]
|
|
sessionId: Annotated[NvU32, 8]
|
|
codecType: Annotated[NvU32, 12]
|
|
hResolution: Annotated[NvU32, 16]
|
|
vResolution: Annotated[NvU32, 20]
|
|
averageEncodeFps: Annotated[NvU32, 24]
|
|
averageEncodeLatency: Annotated[NvU32, 28]
|
|
NV2080_CTRL_NVENC_SW_SESSION_INFO: TypeAlias = struct_NV2080_CTRL_NVENC_SW_SESSION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
sessionInfoTblEntry: Annotated[NvU32, 0]
|
|
sessionInfoTbl: Annotated[NvP64, 8]
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
fabricBaseAddr: Annotated[NvU64, 0]
|
|
NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
handle: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
statusMask: Annotated[NvU32, 0]
|
|
xusbData: Annotated[NvU32, 4]
|
|
ppcData: Annotated[NvU32, 8]
|
|
NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_PARTITION_SPAN(c.Struct):
|
|
SIZE = 16
|
|
lo: Annotated[NvU64, 0]
|
|
hi: Annotated[NvU64, 8]
|
|
NV2080_CTRL_GPU_PARTITION_SPAN: TypeAlias = struct_NV2080_CTRL_GPU_PARTITION_SPAN
|
|
@c.record
|
|
class struct_NV2080_CTRL_EXEC_PARTITION_SPAN(c.Struct):
|
|
SIZE = 16
|
|
lo: Annotated[NvU64, 0]
|
|
hi: Annotated[NvU64, 8]
|
|
NV2080_CTRL_EXEC_PARTITION_SPAN: TypeAlias = struct_NV2080_CTRL_EXEC_PARTITION_SPAN
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_PARTITION_INFO(c.Struct):
|
|
SIZE = 48
|
|
swizzId: Annotated[NvU32, 0]
|
|
uuid: Annotated[c.Array[NvU8, Literal[16]], 4]
|
|
partitionFlag: Annotated[NvU32, 20]
|
|
bValid: Annotated[NvBool, 24]
|
|
placement: Annotated[NV2080_CTRL_GPU_PARTITION_SPAN, 32]
|
|
NV2080_CTRL_GPU_SET_PARTITION_INFO: TypeAlias = struct_NV2080_CTRL_GPU_SET_PARTITION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS(c.Struct):
|
|
SIZE = 392
|
|
partitionCount: Annotated[NvU32, 0]
|
|
partitionInfo: Annotated[c.Array[NV2080_CTRL_GPU_SET_PARTITION_INFO, Literal[8]], 8]
|
|
NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PARTITION_INFO(c.Struct):
|
|
SIZE = 232
|
|
swizzId: Annotated[NvU32, 0]
|
|
partitionFlag: Annotated[NvU32, 4]
|
|
grEngCount: Annotated[NvU32, 8]
|
|
veidCount: Annotated[NvU32, 12]
|
|
smCount: Annotated[NvU32, 16]
|
|
ceCount: Annotated[NvU32, 20]
|
|
nvEncCount: Annotated[NvU32, 24]
|
|
nvDecCount: Annotated[NvU32, 28]
|
|
nvJpgCount: Annotated[NvU32, 32]
|
|
nvOfaCount: Annotated[NvU32, 36]
|
|
gpcCount: Annotated[NvU32, 40]
|
|
virtualGpcCount: Annotated[NvU32, 44]
|
|
gfxGpcCount: Annotated[NvU32, 48]
|
|
gpcsPerGr: Annotated[c.Array[NvU32, Literal[8]], 52]
|
|
virtualGpcsPerGr: Annotated[c.Array[NvU32, Literal[8]], 84]
|
|
gfxGpcPerGr: Annotated[c.Array[NvU32, Literal[8]], 116]
|
|
veidsPerGr: Annotated[c.Array[NvU32, Literal[8]], 148]
|
|
memSize: Annotated[NvU64, 184]
|
|
span: Annotated[NV2080_CTRL_GPU_PARTITION_SPAN, 192]
|
|
bValid: Annotated[NvBool, 208]
|
|
bPartitionError: Annotated[NvBool, 209]
|
|
validCTSIdMask: Annotated[NvU64, 216]
|
|
validGfxCTSIdMask: Annotated[NvU64, 224]
|
|
NV2080_CTRL_GPU_GET_PARTITION_INFO: TypeAlias = struct_NV2080_CTRL_GPU_GET_PARTITION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS(c.Struct):
|
|
SIZE = 1864
|
|
queryPartitionInfo: Annotated[c.Array[NV2080_CTRL_GPU_GET_PARTITION_INFO, Literal[8]], 0]
|
|
validPartitionCount: Annotated[NvU32, 1856]
|
|
bGetAllPartitionInfo: Annotated[NvBool, 1860]
|
|
NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS(c.Struct):
|
|
SIZE = 44
|
|
swizzId: Annotated[NvU32, 0]
|
|
gpcCountPerSmcEng: Annotated[c.Array[NvU32, Literal[8]], 4]
|
|
updateSmcEngMask: Annotated[NvU32, 36]
|
|
bUseAllGPCs: Annotated[NvBool, 40]
|
|
NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_FAULT_PACKET(c.Struct):
|
|
SIZE = 32
|
|
data: Annotated[c.Array[NvU8, Literal[32]], 0]
|
|
NV2080_CTRL_GPU_FAULT_PACKET: TypeAlias = struct_NV2080_CTRL_GPU_FAULT_PACKET
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
faultPacket: Annotated[NV2080_CTRL_GPU_FAULT_PACKET, 0]
|
|
NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS
|
|
NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS(c.Struct):
|
|
SIZE = 1008
|
|
engineList: Annotated[c.Array[NvU32, Literal[84]], 0]
|
|
runlistPriBase: Annotated[c.Array[NvU32, Literal[84]], 336]
|
|
runlistId: Annotated[c.Array[NvU32, Literal[84]], 672]
|
|
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS(c.Struct):
|
|
SIZE = 672
|
|
engineList: Annotated[c.Array[NvU32, Literal[84]], 0]
|
|
hwEngineID: Annotated[c.Array[NvU32, Literal[84]], 336]
|
|
NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
sessionCount: Annotated[NvU32, 0]
|
|
averageFPS: Annotated[NvU32, 4]
|
|
averageLatency: Annotated[NvU32, 8]
|
|
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO(c.Struct):
|
|
SIZE = 52
|
|
processId: Annotated[NvU32, 0]
|
|
subProcessId: Annotated[NvU32, 4]
|
|
vgpuInstanceId: Annotated[NvU32, 8]
|
|
sessionId: Annotated[NvU32, 12]
|
|
sessionType: Annotated[NvU32, 16]
|
|
displayOrdinal: Annotated[NvU32, 20]
|
|
sessionFlags: Annotated[NvU32, 24]
|
|
hMaxResolution: Annotated[NvU32, 28]
|
|
vMaxResolution: Annotated[NvU32, 32]
|
|
hResolution: Annotated[NvU32, 36]
|
|
vResolution: Annotated[NvU32, 40]
|
|
averageFPS: Annotated[NvU32, 44]
|
|
averageLatency: Annotated[NvU32, 48]
|
|
NV2080_CTRL_NVFBC_SW_SESSION_INFO: TypeAlias = struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS(c.Struct):
|
|
SIZE = 13316
|
|
sessionInfoCount: Annotated[NvU32, 0]
|
|
sessionInfoTbl: Annotated[c.Array[NV2080_CTRL_NVFBC_SW_SESSION_INFO, Literal[256]], 4]
|
|
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
firstAsyncCEIdx: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
vmmuSegmentSize: Annotated[NvU64, 0]
|
|
NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS(c.Struct):
|
|
SIZE = 280
|
|
partitionFlag: Annotated[NvU32, 0]
|
|
partitionCount: Annotated[NvU32, 4]
|
|
availableSpans: Annotated[c.Array[NV2080_CTRL_GPU_PARTITION_SPAN, Literal[8]], 8]
|
|
availableSpansCount: Annotated[NvU32, 136]
|
|
totalPartitionCount: Annotated[NvU32, 140]
|
|
totalSpans: Annotated[c.Array[NV2080_CTRL_GPU_PARTITION_SPAN, Literal[8]], 144]
|
|
totalSpansCount: Annotated[NvU32, 272]
|
|
bStaticInfo: Annotated[NvBool, 276]
|
|
NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS
|
|
NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
partitioningMode: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO(c.Struct):
|
|
SIZE = 64
|
|
partitionFlag: Annotated[NvU32, 0]
|
|
grCount: Annotated[NvU32, 4]
|
|
gfxGrCount: Annotated[NvU32, 8]
|
|
gpcCount: Annotated[NvU32, 12]
|
|
virtualGpcCount: Annotated[NvU32, 16]
|
|
gfxGpcCount: Annotated[NvU32, 20]
|
|
veidCount: Annotated[NvU32, 24]
|
|
smCount: Annotated[NvU32, 28]
|
|
ceCount: Annotated[NvU32, 32]
|
|
nvEncCount: Annotated[NvU32, 36]
|
|
nvDecCount: Annotated[NvU32, 40]
|
|
nvJpgCount: Annotated[NvU32, 44]
|
|
nvOfaCount: Annotated[NvU32, 48]
|
|
memorySize: Annotated[NvU64, 56]
|
|
NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO: TypeAlias = struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS(c.Struct):
|
|
SIZE = 2568
|
|
descCount: Annotated[NvU32, 0]
|
|
partitionDescs: Annotated[c.Array[NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO, Literal[40]], 8]
|
|
NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
maxSupportedPageSize: Annotated[NvU64, 0]
|
|
NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
gpcId: Annotated[NvU32, 0]
|
|
count: Annotated[NvU32, 4]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 8]
|
|
NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
swizzId: Annotated[c.Array[NvU32, Literal[9]], 0]
|
|
partitionCount: Annotated[NvU32, 36]
|
|
NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS(c.Struct):
|
|
SIZE = 3812
|
|
idType: Annotated[NvU32, 0]
|
|
id: Annotated[NvU32, 4]
|
|
pidTblCount: Annotated[NvU32, 8]
|
|
pidTbl: Annotated[c.Array[NvU32, Literal[950]], 12]
|
|
NV2080_CTRL_GPU_GET_PIDS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO(c.Struct):
|
|
SIZE = 8
|
|
computeInstanceId: Annotated[NvU32, 0]
|
|
gpuInstanceId: Annotated[NvU32, 4]
|
|
NV2080_CTRL_SMC_SUBSCRIPTION_INFO: TypeAlias = struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA(c.Struct):
|
|
SIZE = 48
|
|
memPrivate: Annotated[NvU64, 0]
|
|
memSharedOwned: Annotated[NvU64, 8]
|
|
memSharedDuped: Annotated[NvU64, 16]
|
|
protectedMemPrivate: Annotated[NvU64, 24]
|
|
protectedMemSharedOwned: Annotated[NvU64, 32]
|
|
protectedMemSharedDuped: Annotated[NvU64, 40]
|
|
NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA: TypeAlias = struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA
|
|
@c.record
|
|
class union_NV2080_CTRL_GPU_PID_INFO_DATA(c.Struct):
|
|
SIZE = 48
|
|
vidMemUsage: Annotated[NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA, 0]
|
|
NV2080_CTRL_GPU_PID_INFO_DATA: TypeAlias = union_NV2080_CTRL_GPU_PID_INFO_DATA
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_PID_INFO(c.Struct):
|
|
SIZE = 72
|
|
pid: Annotated[NvU32, 0]
|
|
index: Annotated[NvU32, 4]
|
|
result: Annotated[NvU32, 8]
|
|
data: Annotated[NV2080_CTRL_GPU_PID_INFO_DATA, 16]
|
|
smcSubscription: Annotated[NV2080_CTRL_SMC_SUBSCRIPTION_INFO, 64]
|
|
NV2080_CTRL_GPU_PID_INFO: TypeAlias = struct_NV2080_CTRL_GPU_PID_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS(c.Struct):
|
|
SIZE = 14408
|
|
pidInfoListCount: Annotated[NvU32, 0]
|
|
pidInfoList: Annotated[c.Array[NV2080_CTRL_GPU_PID_INFO, Literal[200]], 8]
|
|
NV2080_CTRL_GPU_GET_PID_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
faultType: Annotated[NvU32, 0]
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS
|
|
class enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT', 0)
|
|
NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT', 1)
|
|
NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM', 2)
|
|
NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG', 3)
|
|
NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX', 4)
|
|
|
|
NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE: TypeAlias = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG(c.Struct):
|
|
SIZE = 8
|
|
type: Annotated[NvU32, 0]
|
|
data: Annotated[struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data, 4]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data(c.Struct):
|
|
SIZE = 4
|
|
timeslice: Annotated[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE, 0]
|
|
NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG: TypeAlias = struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
config: Annotated[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG, 0]
|
|
NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 260
|
|
numConfigs: Annotated[NvU32, 0]
|
|
configList: Annotated[c.Array[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG, Literal[32]], 4]
|
|
NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_GFID_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
domain: Annotated[NvU32, 0]
|
|
bus: Annotated[NvU8, 4]
|
|
device: Annotated[NvU8, 5]
|
|
func: Annotated[NvU8, 6]
|
|
gfid: Annotated[NvU32, 8]
|
|
gfidMask: Annotated[NvU32, 12]
|
|
NV2080_CTRL_GPU_GET_GFID_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_GFID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
gfid: Annotated[NvU32, 0]
|
|
bEnable: Annotated[NvBool, 4]
|
|
fabricPartitionId: Annotated[NvU32, 8]
|
|
NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
addressStart: Annotated[NvU64, 0]
|
|
addressLength: Annotated[NvU64, 8]
|
|
protection: Annotated[NvU32, 16]
|
|
NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
egmGpaFabricBaseAddr: Annotated[NvU64, 0]
|
|
NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS(c.Struct):
|
|
SIZE = 2608
|
|
engineCount: Annotated[NvU32, 0]
|
|
engineList: Annotated[c.Array[NvU32, Literal[200]], 4]
|
|
engineStateLoadTime: Annotated[c.Array[NvU64, Literal[200]], 808]
|
|
engineIsInit: Annotated[c.Array[NvBool, Literal[200]], 2408]
|
|
NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 20804
|
|
engineCount: Annotated[NvU32, 0]
|
|
engineID: Annotated[c.Array[NvU32, Literal[200]], 4]
|
|
engineName: Annotated[c.Array[c.Array[Annotated[bytes, ctypes.c_char], Literal[100]], Literal[200]], 804]
|
|
NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS(c.Struct):
|
|
SIZE = 3240
|
|
hClientTarget: Annotated[NvHandle, 0]
|
|
hChannelTarget: Annotated[NvHandle, 4]
|
|
bNonTransactional: Annotated[NvU32, 8]
|
|
reserved00: Annotated[c.Array[NvU32, Literal[2]], 12]
|
|
regOpCount: Annotated[NvU32, 20]
|
|
regOps: Annotated[c.Array[NV2080_CTRL_GPU_REG_OP, Literal[100]], 24]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 3224]
|
|
NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO(c.Struct):
|
|
SIZE = 52
|
|
gpuId: Annotated[NvU32, 0]
|
|
gpuUuid: Annotated[c.Array[NvU8, Literal[16]], 4]
|
|
p2pCaps: Annotated[NvU32, 20]
|
|
p2pOptimalReadCEs: Annotated[NvU32, 24]
|
|
p2pOptimalWriteCEs: Annotated[NvU32, 28]
|
|
p2pCapsStatus: Annotated[c.Array[NvU8, Literal[9]], 32]
|
|
busPeerId: Annotated[NvU32, 44]
|
|
busEgmPeerId: Annotated[NvU32, 48]
|
|
NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO: TypeAlias = struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS(c.Struct):
|
|
SIZE = 1672
|
|
bAllCaps: Annotated[NvBool, 0]
|
|
bUseUuid: Annotated[NvBool, 1]
|
|
peerGpuCount: Annotated[NvU32, 4]
|
|
peerGpuCaps: Annotated[c.Array[NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO, Literal[32]], 8]
|
|
NV2080_CTRL_GET_P2P_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_COMPUTE_PROFILE(c.Struct):
|
|
SIZE = 20
|
|
computeSize: Annotated[NvU8, 0]
|
|
gfxGpcCount: Annotated[NvU32, 4]
|
|
gpcCount: Annotated[NvU32, 8]
|
|
veidCount: Annotated[NvU32, 12]
|
|
smCount: Annotated[NvU32, 16]
|
|
NV2080_CTRL_GPU_COMPUTE_PROFILE: TypeAlias = struct_NV2080_CTRL_GPU_COMPUTE_PROFILE
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS(c.Struct):
|
|
SIZE = 168
|
|
partitionFlag: Annotated[NvU32, 0]
|
|
profileCount: Annotated[NvU32, 4]
|
|
profiles: Annotated[c.Array[NV2080_CTRL_GPU_COMPUTE_PROFILE, Literal[8]], 8]
|
|
NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
state: Annotated[NvU8, 0]
|
|
status: Annotated[NV_STATUS, 4]
|
|
clusterUuid: Annotated[c.Array[NvU8, Literal[16]], 8]
|
|
fabricPartitionId: Annotated[NvU16, 24]
|
|
fabricCaps: Annotated[NvU64, 32]
|
|
fabricCliqueId: Annotated[NvU32, 40]
|
|
fabricHealthMask: Annotated[NvU32, 44]
|
|
NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pciDevId: Annotated[NvU32, 0]
|
|
chipSku: Annotated[c.Array[NvU8, Literal[4]], 4]
|
|
chipMajor: Annotated[NvU32, 8]
|
|
chipMinor: Annotated[NvU32, 12]
|
|
NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
swizzId: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS(c.Struct):
|
|
SIZE = 1832
|
|
hClientTarget: Annotated[NvHandle, 0]
|
|
hChannelTarget: Annotated[NvHandle, 4]
|
|
bNonTransactional: Annotated[NvU32, 8]
|
|
regOpCount: Annotated[NvU32, 12]
|
|
smIds: Annotated[c.Array[NvU32, Literal[50]], 16]
|
|
regOps: Annotated[c.Array[NV2080_CTRL_GPU_REG_OP, Literal[50]], 216]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 1816]
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bResetRequired: Annotated[NvBool, 0]
|
|
NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bDrainRecommended: Annotated[NvBool, 0]
|
|
NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 16388
|
|
sessionInfoTblEntry: Annotated[NvU32, 0]
|
|
sessionInfoTbl: Annotated[c.Array[NV2080_CTRL_NVENC_SW_SESSION_INFO, Literal[512]], 4]
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO(c.Struct):
|
|
SIZE = 20
|
|
engDesc: Annotated[NvU32, 0]
|
|
ctxAttr: Annotated[NvU32, 4]
|
|
ctxBufferSize: Annotated[NvU32, 8]
|
|
addrSpaceList: Annotated[NvU32, 12]
|
|
registerBase: Annotated[NvU32, 16]
|
|
NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO: TypeAlias = struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS(c.Struct):
|
|
SIZE = 1284
|
|
numConstructedFalcons: Annotated[NvU32, 0]
|
|
constructedFalconsTable: Annotated[c.Array[NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO, Literal[64]], 4]
|
|
NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_VF_MSIX_CAPS(c.Struct):
|
|
SIZE = 12
|
|
msix_header: Annotated[NvU32, 0]
|
|
msix_table: Annotated[NvU32, 4]
|
|
msix_pba: Annotated[NvU32, 8]
|
|
NV2080_VF_MSIX_CAPS: TypeAlias = struct_NV2080_VF_MSIX_CAPS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
gfid: Annotated[NvU32, 0]
|
|
vfMsixCap: Annotated[NV2080_VF_MSIX_CAPS, 4]
|
|
NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS
|
|
class enum_NV2080_CTRL_GPU_RECOVERY_ACTION(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_GPU_RECOVERY_ACTION_NONE = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_NONE', 0)
|
|
NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET', 1)
|
|
NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT', 2)
|
|
NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P', 3)
|
|
NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET', 4)
|
|
|
|
NV2080_CTRL_GPU_RECOVERY_ACTION: TypeAlias = enum_NV2080_CTRL_GPU_RECOVERY_ACTION
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
action: Annotated[NV2080_CTRL_GPU_RECOVERY_ACTION, 0]
|
|
NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bFipsEnabled: Annotated[NvBool, 0]
|
|
NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS
|
|
class enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID = enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE.define('NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID', 0)
|
|
NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC = enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE.define('NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC', 1)
|
|
NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC = enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE.define('NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC', 2)
|
|
|
|
NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE: TypeAlias = enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE
|
|
@c.record
|
|
class struct_NV2080_RAFTS_FLOORSWEEP_INFO(c.Struct):
|
|
SIZE = 12
|
|
unitType: Annotated[NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE, 0]
|
|
parentId: Annotated[NvU32, 4]
|
|
mask: Annotated[NvU32, 8]
|
|
NV2080_RAFTS_FLOORSWEEP_INFO: TypeAlias = struct_NV2080_RAFTS_FLOORSWEEP_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS(c.Struct):
|
|
SIZE = 344
|
|
tpcCountMatrix: Annotated[c.Array[c.Array[NvU8, Literal[12]], Literal[2]], 0]
|
|
bValid: Annotated[NvBool, 24]
|
|
floorSweepConfig: Annotated[c.Array[NV2080_RAFTS_FLOORSWEEP_INFO, Literal[26]], 28]
|
|
gfxGpcCount: Annotated[NvU8, 340]
|
|
gfxTpcPerGpcCount: Annotated[NvU8, 341]
|
|
maxUgpuTpcDiff: Annotated[NvU8, 342]
|
|
NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS(c.Struct):
|
|
SIZE = 152
|
|
partitionFlag: Annotated[NvU32, 0]
|
|
computeSize: Annotated[NvU32, 4]
|
|
totalProfileCount: Annotated[NvU32, 8]
|
|
totalSpans: Annotated[c.Array[NV2080_CTRL_EXEC_PARTITION_SPAN, Literal[8]], 16]
|
|
totalSpansCount: Annotated[NvU32, 144]
|
|
NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpc: Annotated[NvU32, 0]
|
|
tpcReconfigMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPUMON_SAMPLE(c.Struct):
|
|
SIZE = 8
|
|
timeStamp: Annotated[NvU64, 0]
|
|
NV2080_CTRL_GPUMON_SAMPLE: TypeAlias = struct_NV2080_CTRL_GPUMON_SAMPLE
|
|
@c.record
|
|
class struct_NV2080_CTRL_GPUMON_SAMPLES(c.Struct):
|
|
SIZE = 24
|
|
type: Annotated[NvU8, 0]
|
|
bufSize: Annotated[NvU32, 4]
|
|
count: Annotated[NvU32, 8]
|
|
tracker: Annotated[NvU32, 12]
|
|
pSamples: Annotated[NvP64, 16]
|
|
NV2080_CTRL_GPUMON_SAMPLES: TypeAlias = struct_NV2080_CTRL_GPUMON_SAMPLES
|
|
NV2080_CTRL_GR_INFO: TypeAlias = struct_NVXXXX_CTRL_XXX_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
grInfoListSize: Annotated[NvU32, 0]
|
|
grInfoList: Annotated[NvP64, 8]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 16]
|
|
NV2080_CTRL_GR_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hChannel: Annotated[NvHandle, 0]
|
|
hShareClient: Annotated[NvHandle, 4]
|
|
hShareChannel: Annotated[NvHandle, 8]
|
|
zcullMode: Annotated[NvU32, 12]
|
|
NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
widthAlignPixels: Annotated[NvU32, 0]
|
|
heightAlignPixels: Annotated[NvU32, 4]
|
|
pixelSquaresByAliquots: Annotated[NvU32, 8]
|
|
aliquotTotal: Annotated[NvU32, 12]
|
|
zcullRegionByteMultiplier: Annotated[NvU32, 16]
|
|
zcullRegionHeaderSize: Annotated[NvU32, 20]
|
|
zcullSubregionHeaderSize: Annotated[NvU32, 24]
|
|
subregionCount: Annotated[NvU32, 28]
|
|
subregionWidthAlignPixels: Annotated[NvU32, 32]
|
|
subregionHeightAlignPixels: Annotated[NvU32, 36]
|
|
NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hChannel: Annotated[NvHandle, 0]
|
|
pmMode: Annotated[NvU32, 4]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 8]
|
|
NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hClient: Annotated[NvHandle, 0]
|
|
hChannel: Annotated[NvHandle, 4]
|
|
vMemPtr: Annotated[NvU64, 8]
|
|
zcullMode: Annotated[NvU32, 16]
|
|
NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
hClient: Annotated[NvHandle, 0]
|
|
hChannel: Annotated[NvHandle, 4]
|
|
vMemPtr: Annotated[NvU64, 8]
|
|
pmMode: Annotated[NvU32, 16]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 24]
|
|
NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hClient: Annotated[NvHandle, 0]
|
|
hChannel: Annotated[NvHandle, 4]
|
|
vMemPtr: Annotated[NvU64, 8]
|
|
NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS(c.Struct):
|
|
SIZE = 152
|
|
mapValueCount: Annotated[NvU32, 0]
|
|
mapValues: Annotated[c.Array[NvU8, Literal[128]], 4]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 136]
|
|
NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hChannel: Annotated[NvHandle, 0]
|
|
smpcMode: Annotated[NvU32, 4]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 8]
|
|
NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS(c.Struct):
|
|
SIZE = 1944
|
|
smId: Annotated[c.Array[struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_smId, Literal[240]], 0]
|
|
smCount: Annotated[NvU32, 1920]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 1928]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_smId(c.Struct):
|
|
SIZE = 8
|
|
gpcId: Annotated[NvU32, 0]
|
|
tpcId: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
flags: Annotated[NvU32, 0]
|
|
hChannel: Annotated[NvHandle, 4]
|
|
gfxpPreemptMode: Annotated[NvU32, 8]
|
|
cilpPreemptMode: Annotated[NvU32, 12]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 16]
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS
|
|
class enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN', 0)
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL', 1)
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL', 2)
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB', 3)
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV', 4)
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL', 5)
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL', 6)
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU', 7)
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP', 8)
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END', 9)
|
|
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS: TypeAlias = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS(c.Struct):
|
|
SIZE = 112
|
|
flags: Annotated[NvU32, 0]
|
|
hClient: Annotated[NvHandle, 4]
|
|
hChannel: Annotated[NvHandle, 8]
|
|
vMemPtrs: Annotated[c.Array[NvU64, Literal[9]], 16]
|
|
gfxpPreemptMode: Annotated[NvU32, 88]
|
|
cilpPreemptMode: Annotated[NvU32, 92]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 96]
|
|
NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hChannel: Annotated[NvHandle, 0]
|
|
samplingMode: Annotated[NvU32, 4]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 8]
|
|
NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
ropUnitCount: Annotated[NvU32, 0]
|
|
ropOperationsFactor: Annotated[NvU32, 4]
|
|
ropOperationsCount: Annotated[NvU32, 8]
|
|
NV2080_CTRL_GR_GET_ROP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hChannel: Annotated[NvHandle, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
saveCnt: Annotated[NvU32, 8]
|
|
restoreCnt: Annotated[NvU32, 12]
|
|
wfiSaveCnt: Annotated[NvU32, 16]
|
|
ctaSaveCnt: Annotated[NvU32, 20]
|
|
cilpSaveCnt: Annotated[NvU32, 24]
|
|
gfxpSaveCnt: Annotated[NvU32, 28]
|
|
NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hChannel: Annotated[NvHandle, 0]
|
|
totalBufferSize: Annotated[NvU64, 8]
|
|
NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_CTX_BUFFER_INFO(c.Struct):
|
|
SIZE = 80
|
|
alignment: Annotated[NvU64, 0]
|
|
size: Annotated[NvU64, 8]
|
|
bufferHandle: Annotated[NvP64, 16]
|
|
pageCount: Annotated[NvU64, 24]
|
|
physAddr: Annotated[NvU64, 32]
|
|
bufferType: Annotated[NvU32, 40]
|
|
aperture: Annotated[NvU32, 44]
|
|
kind: Annotated[NvU32, 48]
|
|
pageSize: Annotated[NvU32, 52]
|
|
bIsContigous: Annotated[NvBool, 56]
|
|
bGlobalBuffer: Annotated[NvBool, 57]
|
|
bLocalBuffer: Annotated[NvBool, 58]
|
|
bDeviceDescendant: Annotated[NvBool, 59]
|
|
uuid: Annotated[c.Array[NvU8, Literal[16]], 60]
|
|
NV2080_CTRL_GR_CTX_BUFFER_INFO: TypeAlias = struct_NV2080_CTRL_GR_CTX_BUFFER_INFO
|
|
PNV2080_CTRL_GR_CTX_BUFFER_INFO: TypeAlias = c.POINTER[struct_NV2080_CTRL_GR_CTX_BUFFER_INFO]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS(c.Struct):
|
|
SIZE = 5136
|
|
hUserClient: Annotated[NvHandle, 0]
|
|
hChannel: Annotated[NvHandle, 4]
|
|
bufferCount: Annotated[NvU32, 8]
|
|
ctxBufferInfo: Annotated[c.Array[NV2080_CTRL_GR_CTX_BUFFER_INFO, Literal[64]], 16]
|
|
NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS(c.Struct):
|
|
SIZE = 6168
|
|
globalSmId: Annotated[c.Array[struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_globalSmId, Literal[512]], 0]
|
|
numSm: Annotated[NvU16, 6144]
|
|
numTpc: Annotated[NvU16, 6146]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 6152]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_globalSmId(c.Struct):
|
|
SIZE = 12
|
|
gpcId: Annotated[NvU16, 0]
|
|
localTpcId: Annotated[NvU16, 2]
|
|
localSmId: Annotated[NvU16, 4]
|
|
globalTpcId: Annotated[NvU16, 6]
|
|
virtualGpcId: Annotated[NvU16, 8]
|
|
migratableTpcId: Annotated[NvU16, 10]
|
|
NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
chID: Annotated[NvU32, 0]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 8]
|
|
NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC(c.Struct):
|
|
SIZE = 32
|
|
errorCounter: Annotated[NvU64, 0]
|
|
errorTimestamp: Annotated[NvU64, 8]
|
|
warningCounter: Annotated[NvU64, 16]
|
|
warningTimestamp: Annotated[NvU64, 24]
|
|
NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC: TypeAlias = struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC(c.Struct):
|
|
SIZE = 320
|
|
tpc: Annotated[c.Array[NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC, Literal[10]], 0]
|
|
NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC: TypeAlias = struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_VAT_ALARM_DATA(c.Struct):
|
|
SIZE = 3200
|
|
gpc: Annotated[c.Array[NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC, Literal[10]], 0]
|
|
NV2080_CTRL_GR_VAT_ALARM_DATA: TypeAlias = struct_NV2080_CTRL_GR_VAT_ALARM_DATA
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS(c.Struct):
|
|
SIZE = 3208
|
|
smVatAlarm: Annotated[NV2080_CTRL_GR_VAT_ALARM_DATA, 0]
|
|
maxGpcCount: Annotated[NvU32, 3200]
|
|
maxTpcPerGpcCount: Annotated[NvU32, 3204]
|
|
NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS
|
|
PNV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS: TypeAlias = c.POINTER[struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
attribBufferSize: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
maxSlots: Annotated[NvU32, 0]
|
|
slotStride: Annotated[NvU32, 4]
|
|
ctrlStructSize: Annotated[NvU64, 8]
|
|
ctrlStructAlign: Annotated[NvU64, 16]
|
|
poolSize: Annotated[NvU64, 24]
|
|
poolAlign: Annotated[NvU64, 32]
|
|
NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
maxSlots: Annotated[NvU32, 0]
|
|
hMemory: Annotated[NvHandle, 4]
|
|
offset: Annotated[NvU32, 8]
|
|
size: Annotated[NvU32, 12]
|
|
NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS(c.Struct):
|
|
SIZE = 272
|
|
numSlots: Annotated[NvU32, 0]
|
|
slots: Annotated[c.Array[NvU32, Literal[64]], 4]
|
|
hMemory: Annotated[NvHandle, 260]
|
|
offset: Annotated[NvU32, 264]
|
|
size: Annotated[NvU32, 268]
|
|
NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS(c.Struct):
|
|
SIZE = 276
|
|
numSlots: Annotated[NvU32, 0]
|
|
slots: Annotated[c.Array[NvU32, Literal[64]], 4]
|
|
bRemoveSpecificSlots: Annotated[NvBool, 260]
|
|
hMemory: Annotated[NvHandle, 264]
|
|
offset: Annotated[NvU32, 268]
|
|
size: Annotated[NvU32, 272]
|
|
NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS
|
|
NV2080_CTRL_GR_GET_CAPS_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS
|
|
NV2080_CTRL_GR_GET_INFO_V2_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 0]
|
|
gpcMask: Annotated[NvU32, 16]
|
|
NV2080_CTRL_GR_GET_GPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 0]
|
|
gpcId: Annotated[NvU32, 16]
|
|
tpcMask: Annotated[NvU32, 20]
|
|
NV2080_CTRL_GR_GET_TPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS
|
|
NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS: TypeAlias = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 0]
|
|
engineId: Annotated[NvU32, 16]
|
|
alignment: Annotated[NvU32, 20]
|
|
size: Annotated[NvU32, 24]
|
|
bInfoPopulated: Annotated[NvBool, 28]
|
|
NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 0]
|
|
imla0: Annotated[NvU8, 16]
|
|
fmla16: Annotated[NvU8, 17]
|
|
dp: Annotated[NvU8, 18]
|
|
fmla32: Annotated[NvU8, 19]
|
|
ffma: Annotated[NvU8, 20]
|
|
imla1: Annotated[NvU8, 21]
|
|
imla2: Annotated[NvU8, 22]
|
|
imla3: Annotated[NvU8, 23]
|
|
imla4: Annotated[NvU8, 24]
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
|
|
class enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD.define('NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL', 0)
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD.define('NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE', 1)
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD.define('NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT', 2)
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD.define('NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM', 3)
|
|
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD: TypeAlias = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
hEventBuffer: Annotated[NvHandle, 0]
|
|
recordSize: Annotated[NvU32, 4]
|
|
levelOfDetail: Annotated[NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD, 8]
|
|
eventFilter: Annotated[NvU32, 12]
|
|
bAllUsers: Annotated[NvBool, 16]
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
physSyspipeId: Annotated[NvU32, 0]
|
|
gpcMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 0]
|
|
gpcId: Annotated[NvU32, 16]
|
|
ppcMask: Annotated[NvU32, 20]
|
|
NV2080_CTRL_GR_GET_PPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: Annotated[NvU32, 0]
|
|
numTpcs: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hChannel: Annotated[NvHandle, 0]
|
|
zcullMode: Annotated[NvU32, 4]
|
|
pmMode: Annotated[NvU32, 8]
|
|
smpcMode: Annotated[NvU32, 12]
|
|
cilpPreemptMode: Annotated[NvU32, 16]
|
|
gfxpPreemptMode: Annotated[NvU32, 20]
|
|
NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS
|
|
NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: Annotated[NvU32, 0]
|
|
zcullMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS
|
|
class enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE', 0)
|
|
NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD', 1)
|
|
NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU', 2)
|
|
NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED', 3)
|
|
NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN', 4)
|
|
NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY', 5)
|
|
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE: TypeAlias = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hEventBuffer: Annotated[NvHandle, 0]
|
|
recordSize: Annotated[NvU32, 4]
|
|
levelOfDetail: Annotated[NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD, 8]
|
|
eventFilter: Annotated[NvU32, 12]
|
|
bAllUsers: Annotated[NvBool, 16]
|
|
reasonCode: Annotated[NvU32, 20]
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 0]
|
|
physGfxGpcMask: Annotated[NvU32, 16]
|
|
numGfxTpc: Annotated[NvU32, 20]
|
|
NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
gpc: Annotated[NvU32, 0]
|
|
tpcReconfigMask: Annotated[NvU32, 4]
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 8]
|
|
NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gpcCount: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: Annotated[NvU32, 0]
|
|
chipletGpcMap: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: Annotated[NvU32, 0]
|
|
tpcMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: Annotated[NvU32, 0]
|
|
ppcMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
swizzId: Annotated[NvU32, 0]
|
|
gpcId: Annotated[NvU32, 4]
|
|
chipletGpcMap: Annotated[NvU32, 8]
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpcId: Annotated[NvU32, 0]
|
|
ropMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
chipletSyspipeMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
swizzId: Annotated[NvU16, 0]
|
|
physSyspipeIdCount: Annotated[NvU16, 2]
|
|
physSyspipeId: Annotated[c.Array[NvU8, Literal[8]], 4]
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
swizzId: Annotated[NvU32, 0]
|
|
grIdx: Annotated[NvU32, 4]
|
|
gpcEnMask: Annotated[NvU32, 8]
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
syspipeId: Annotated[NvU32, 0]
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS(c.Struct):
|
|
SIZE = 20
|
|
queryType: Annotated[NvU16, 0]
|
|
reserved: Annotated[c.Array[NvU8, Literal[2]], 2]
|
|
status: Annotated[NvU32, 4]
|
|
queryData: Annotated[struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData, 8]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData(c.Struct):
|
|
SIZE = 12
|
|
gpcCountData: Annotated[NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS, 0]
|
|
chipletGpcMapData: Annotated[NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS, 0]
|
|
tpcMaskData: Annotated[NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS, 0]
|
|
ppcMaskData: Annotated[NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS, 0]
|
|
partitionGpcMapData: Annotated[NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS, 0]
|
|
syspipeMaskData: Annotated[NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS, 0]
|
|
partitionChipletSyspipeData: Annotated[NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS, 0]
|
|
dmGpcMaskData: Annotated[NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS, 0]
|
|
partitionSyspipeIdData: Annotated[NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS, 0]
|
|
ropMaskData: Annotated[NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS, 0]
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS(c.Struct):
|
|
SIZE = 1928
|
|
numQueries: Annotated[NvU16, 0]
|
|
reserved: Annotated[c.Array[NvU8, Literal[6]], 2]
|
|
queries: Annotated[c.Array[NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS, Literal[96]], 8]
|
|
NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
gspFeatures: Annotated[NvU32, 0]
|
|
bValid: Annotated[NvBool, 4]
|
|
bDefaultGspRmGpu: Annotated[NvBool, 5]
|
|
firmwareVersion: Annotated[c.Array[NvU8, Literal[64]], 6]
|
|
NV2080_CTRL_GSP_GET_FEATURES_PARAMS: TypeAlias = struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT(c.Struct):
|
|
SIZE = 32
|
|
allocatedSize: Annotated[NvU64, 0]
|
|
usableSize: Annotated[NvU64, 8]
|
|
memTrackOverhead: Annotated[NvU64, 16]
|
|
allocationCount: Annotated[NvU32, 24]
|
|
NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT: TypeAlias = struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT
|
|
@c.record
|
|
class struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS(c.Struct):
|
|
SIZE = 88
|
|
gfid: Annotated[NvU32, 0]
|
|
managedSize: Annotated[NvU64, 8]
|
|
largestFreeChunkSize: Annotated[NvU64, 16]
|
|
current: Annotated[NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT, 24]
|
|
peak: Annotated[NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT, 56]
|
|
NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
allocatedSize: Annotated[NvU64, 0]
|
|
peakAllocatedSize: Annotated[NvU64, 8]
|
|
managedSize: Annotated[NvU64, 16]
|
|
allocationCount: Annotated[NvU32, 24]
|
|
peakAllocationCount: Annotated[NvU32, 28]
|
|
largestFreeChunkSize: Annotated[NvU64, 32]
|
|
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS(c.Struct):
|
|
SIZE = 16
|
|
allocations: Annotated[NvU32, 0]
|
|
peakAllocations: Annotated[NvU32, 4]
|
|
objectSize: Annotated[NvU64, 8]
|
|
NV2080_CTRL_GSP_LIBOS_POOL_STATS: TypeAlias = struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS(c.Struct):
|
|
SIZE = 1040
|
|
poolStats: Annotated[c.Array[NV2080_CTRL_GSP_LIBOS_POOL_STATS, Literal[64]], 0]
|
|
totalHeapSize: Annotated[NvU64, 1024]
|
|
poolCount: Annotated[NvU8, 1032]
|
|
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hshubNcisocMask: Annotated[NvU32, 0]
|
|
hshubNvlMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
ecMode: Annotated[NvU32, 0]
|
|
status: Annotated[NvU32, 4]
|
|
NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 532
|
|
version: Annotated[NvU32, 0]
|
|
port: Annotated[NvU32, 4]
|
|
flags: Annotated[NvU32, 8]
|
|
inputCount: Annotated[NvU32, 12]
|
|
inputBuffer: Annotated[c.Array[NvU8, Literal[256]], 16]
|
|
outputCount: Annotated[NvU32, 272]
|
|
outputBuffer: Annotated[c.Array[NvU8, Literal[256]], 276]
|
|
NV2080_CTRL_I2C_READ_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 276
|
|
version: Annotated[NvU32, 0]
|
|
port: Annotated[NvU32, 4]
|
|
flags: Annotated[NvU32, 8]
|
|
inputCount: Annotated[NvU32, 12]
|
|
inputBuffer: Annotated[c.Array[NvU8, Literal[256]], 16]
|
|
encrClientID: Annotated[NvU32, 272]
|
|
NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_I2C_RW_REG_PARAMS(c.Struct):
|
|
SIZE = 276
|
|
version: Annotated[NvU32, 0]
|
|
port: Annotated[NvU32, 4]
|
|
flags: Annotated[NvU32, 8]
|
|
addr: Annotated[NvU32, 12]
|
|
reg: Annotated[NvU8, 16]
|
|
bufsize: Annotated[NvU8, 17]
|
|
buffer: Annotated[c.Array[NvU8, Literal[255]], 18]
|
|
NV2080_CTRL_I2C_RW_REG_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_RW_REG_PARAMS
|
|
NV2080_CTRL_I2C_READ_REG_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_RW_REG_PARAMS
|
|
NV2080_CTRL_I2C_WRITE_REG_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_RW_REG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_I2C_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
token: Annotated[NvU32, 0]
|
|
cmd: Annotated[NvU32, 4]
|
|
port: Annotated[NvU32, 8]
|
|
flags: Annotated[NvU32, 12]
|
|
data: Annotated[NvP64, 16]
|
|
status: Annotated[NvU32, 24]
|
|
dataBuffSize: Annotated[NvU32, 28]
|
|
speed: Annotated[NvU32, 32]
|
|
encrClientID: Annotated[NvU32, 36]
|
|
NV2080_CTRL_I2C_ACCESS_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_ACCESS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
head: Annotated[NvU32, 0]
|
|
authType: Annotated[NvU32, 4]
|
|
status: Annotated[NvU32, 8]
|
|
NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS(c.Struct):
|
|
SIZE = 36
|
|
feHwSysCap: Annotated[NvU32, 0]
|
|
windowPresentMask: Annotated[NvU32, 4]
|
|
bFbRemapperEnabled: Annotated[NvBool, 8]
|
|
numHeads: Annotated[NvU32, 12]
|
|
i2cPort: Annotated[NvU32, 16]
|
|
internalDispActiveMask: Annotated[NvU32, 20]
|
|
embeddedDisplayPortMask: Annotated[NvU32, 24]
|
|
bExternalMuxSupported: Annotated[NvBool, 28]
|
|
bInternalMuxSupported: Annotated[NvBool, 29]
|
|
numDispChannels: Annotated[NvU32, 32]
|
|
NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
bOneToOneComptagLineAllocation: Annotated[NvBool, 0]
|
|
bUseOneToFourComptagLineAllocation: Annotated[NvBool, 1]
|
|
bUseRawModeComptaglineAllocation: Annotated[NvBool, 2]
|
|
bDisableCompbitBacking: Annotated[NvBool, 3]
|
|
bDisablePostL2Compression: Annotated[NvBool, 4]
|
|
bEnabledEccFBPA: Annotated[NvBool, 5]
|
|
bL2PreFill: Annotated[NvBool, 6]
|
|
l2CacheSize: Annotated[NvU64, 8]
|
|
bFbpaPresent: Annotated[NvBool, 16]
|
|
comprPageSize: Annotated[NvU32, 20]
|
|
comprPageShift: Annotated[NvU32, 24]
|
|
ramType: Annotated[NvU32, 28]
|
|
ltcCount: Annotated[NvU32, 32]
|
|
ltsPerLtcCount: Annotated[NvU32, 36]
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 520
|
|
accessCounterIndex: Annotated[NvU32, 0]
|
|
bufferSize: Annotated[NvU32, 4]
|
|
bufferPteArray: Annotated[c.Array[NvU64, Literal[64]], 8]
|
|
NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
accessCounterIndex: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS(c.Struct):
|
|
SIZE = 23
|
|
capsTbl: Annotated[c.Array[NvU8, Literal[23]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_CAPS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 184
|
|
engineCaps: Annotated[c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_CAPS, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER(c.Struct):
|
|
SIZE = 2884
|
|
globalSmId: Annotated[c.Array[struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_globalSmId, Literal[240]], 0]
|
|
numSm: Annotated[NvU16, 2880]
|
|
numTpc: Annotated[NvU16, 2882]
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_globalSmId(c.Struct):
|
|
SIZE = 12
|
|
gpcId: Annotated[NvU16, 0]
|
|
localTpcId: Annotated[NvU16, 2]
|
|
localSmId: Annotated[NvU16, 4]
|
|
globalTpcId: Annotated[NvU16, 6]
|
|
virtualGpcId: Annotated[NvU16, 8]
|
|
migratableTpcId: Annotated[NvU16, 10]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS(c.Struct):
|
|
SIZE = 23072
|
|
globalSmOrder: Annotated[c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BSP_CAPS(c.Struct):
|
|
SIZE = 8
|
|
capsTbl: Annotated[c.Array[NvU8, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_BSP_CAPS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BSP_CAPS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
caps: Annotated[c.Array[NV2080_CTRL_INTERNAL_BSP_CAPS, Literal[8]], 0]
|
|
valid: Annotated[c.Array[NvBool, Literal[8]], 64]
|
|
NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MSENC_CAPS(c.Struct):
|
|
SIZE = 4
|
|
capsTbl: Annotated[c.Array[NvU8, Literal[4]], 0]
|
|
NV2080_CTRL_INTERNAL_MSENC_CAPS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MSENC_CAPS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
caps: Annotated[c.Array[NV2080_CTRL_INTERNAL_MSENC_CAPS, Literal[8]], 0]
|
|
valid: Annotated[c.Array[NvBool, Literal[8]], 32]
|
|
NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS(c.Struct):
|
|
SIZE = 296
|
|
gpcMask: Annotated[NvU32, 0]
|
|
tpcMask: Annotated[c.Array[NvU32, Literal[12]], 4]
|
|
tpcCount: Annotated[c.Array[NvU32, Literal[12]], 52]
|
|
physGpcMask: Annotated[NvU32, 100]
|
|
mmuPerGpc: Annotated[c.Array[NvU32, Literal[12]], 104]
|
|
tpcToPesMap: Annotated[c.Array[NvU32, Literal[10]], 152]
|
|
numPesPerGpc: Annotated[c.Array[NvU32, Literal[12]], 192]
|
|
zcullMask: Annotated[c.Array[NvU32, Literal[12]], 240]
|
|
physGfxGpcMask: Annotated[NvU32, 288]
|
|
numGfxTpc: Annotated[NvU32, 292]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS(c.Struct):
|
|
SIZE = 2368
|
|
floorsweepingMasks: Annotated[c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS(c.Struct):
|
|
SIZE = 1056
|
|
hUserClient: Annotated[NvHandle, 0]
|
|
hChannel: Annotated[NvHandle, 4]
|
|
bufferType: Annotated[NvU32, 8]
|
|
firstPage: Annotated[NvU32, 12]
|
|
numPages: Annotated[NvU32, 16]
|
|
physAddrs: Annotated[c.Array[NvU64, Literal[128]], 24]
|
|
bNoMorePages: Annotated[NvBool, 1048]
|
|
NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS: TypeAlias = struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GR_INFO(c.Struct):
|
|
SIZE = 8
|
|
index: Annotated[NvU32, 0]
|
|
data: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_GR_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO(c.Struct):
|
|
SIZE = 464
|
|
infoList: Annotated[c.Array[NV2080_CTRL_INTERNAL_GR_INFO, Literal[58]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 3712
|
|
engineInfo: Annotated[c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_INFO, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO(c.Struct):
|
|
SIZE = 40
|
|
widthAlignPixels: Annotated[NvU32, 0]
|
|
heightAlignPixels: Annotated[NvU32, 4]
|
|
pixelSquaresByAliquots: Annotated[NvU32, 8]
|
|
aliquotTotal: Annotated[NvU32, 12]
|
|
zcullRegionByteMultiplier: Annotated[NvU32, 16]
|
|
zcullRegionHeaderSize: Annotated[NvU32, 20]
|
|
zcullSubregionHeaderSize: Annotated[NvU32, 24]
|
|
subregionCount: Annotated[NvU32, 28]
|
|
subregionWidthAlignPixels: Annotated[NvU32, 32]
|
|
subregionHeightAlignPixels: Annotated[NvU32, 36]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS(c.Struct):
|
|
SIZE = 320
|
|
engineZcullInfo: Annotated[c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO(c.Struct):
|
|
SIZE = 12
|
|
ropUnitCount: Annotated[NvU32, 0]
|
|
ropOperationsFactor: Annotated[NvU32, 4]
|
|
ropOperationsCount: Annotated[NvU32, 8]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
engineRopInfo: Annotated[c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS(c.Struct):
|
|
SIZE = 48
|
|
mask: Annotated[c.Array[NvU32, Literal[12]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS(c.Struct):
|
|
SIZE = 384
|
|
enginePpcMasks: Annotated[c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO(c.Struct):
|
|
SIZE = 8
|
|
size: Annotated[NvU32, 0]
|
|
alignment: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO(c.Struct):
|
|
SIZE = 208
|
|
engine: Annotated[c.Array[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO, Literal[26]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS(c.Struct):
|
|
SIZE = 1664
|
|
engineContextBuffersInfo: Annotated[c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER(c.Struct):
|
|
SIZE = 9
|
|
imla0: Annotated[NvU8, 0]
|
|
fmla16: Annotated[NvU8, 1]
|
|
dp: Annotated[NvU8, 2]
|
|
fmla32: Annotated[NvU8, 3]
|
|
ffma: Annotated[NvU8, 4]
|
|
imla1: Annotated[NvU8, 5]
|
|
imla2: Annotated[NvU8, 6]
|
|
imla3: Annotated[NvU8, 7]
|
|
imla4: Annotated[NvU8, 8]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
smIssueRateModifier: Annotated[c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS(c.Struct):
|
|
SIZE = 88
|
|
chipSubRev: Annotated[NvU8, 0]
|
|
emulationRev1: Annotated[NvU32, 4]
|
|
isCmpSku: Annotated[NvBool, 8]
|
|
pciDeviceId: Annotated[NvU32, 12]
|
|
pciSubDeviceId: Annotated[NvU32, 16]
|
|
pciRevisionId: Annotated[NvU32, 20]
|
|
regBases: Annotated[c.Array[NvU32, Literal[16]], 24]
|
|
NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 0]
|
|
bEnable: Annotated[NvBool, 16]
|
|
NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
grRouteInfo: Annotated[NV2080_CTRL_GR_ROUTE_INFO, 0]
|
|
offset: Annotated[NvU32, 16]
|
|
NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE(c.Struct):
|
|
SIZE = 4
|
|
fecsRecordSize: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
fecsRecordSize: Annotated[c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES(c.Struct):
|
|
SIZE = 32
|
|
fecsRecordSize: Annotated[NvU32, 0]
|
|
timestampHiTagMask: Annotated[NvU32, 4]
|
|
timestampHiTagShift: Annotated[NvU8, 8]
|
|
timestampVMask: Annotated[NvU64, 16]
|
|
numLowerBitsZeroShift: Annotated[NvU8, 24]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS(c.Struct):
|
|
SIZE = 256
|
|
fecsTraceDefines: Annotated[c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DEVICE_INFO(c.Struct):
|
|
SIZE = 48
|
|
faultId: Annotated[NvU32, 0]
|
|
instanceId: Annotated[NvU32, 4]
|
|
typeEnum: Annotated[NvU32, 8]
|
|
resetId: Annotated[NvU32, 12]
|
|
devicePriBase: Annotated[NvU32, 16]
|
|
isEngine: Annotated[NvU32, 20]
|
|
rlEngId: Annotated[NvU32, 24]
|
|
runlistPriBase: Annotated[NvU32, 28]
|
|
groupId: Annotated[NvU32, 32]
|
|
ginTargetId: Annotated[NvU32, 36]
|
|
deviceBroadcastPriBase: Annotated[NvU32, 40]
|
|
groupLocalInstanceId: Annotated[NvU32, 44]
|
|
NV2080_CTRL_INTERNAL_DEVICE_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_DEVICE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS(c.Struct):
|
|
SIZE = 24580
|
|
numEntries: Annotated[NvU32, 0]
|
|
deviceInfoTable: Annotated[c.Array[NV2080_CTRL_INTERNAL_DEVICE_INFO, Literal[512]], 4]
|
|
NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS(c.Struct):
|
|
SIZE = 8204
|
|
userRegisterAccessMapSize: Annotated[NvU32, 0]
|
|
compressedSize: Annotated[NvU32, 4]
|
|
compressedData: Annotated[c.Array[NvU8, Literal[4096]], 8]
|
|
profilingRangesSize: Annotated[NvU32, 4104]
|
|
profilingRanges: Annotated[c.Array[NvU8, Literal[4096]], 4108]
|
|
NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NV_RANGE(c.Struct):
|
|
SIZE = 16
|
|
lo: Annotated[NvU64, 0]
|
|
hi: Annotated[NvU64, 8]
|
|
NV2080_CTRL_INTERNAL_NV_RANGE: TypeAlias = struct_NV2080_CTRL_INTERNAL_NV_RANGE
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
swizzId: Annotated[NvU32, 0]
|
|
memAddrRange: Annotated[NV2080_CTRL_INTERNAL_NV_RANGE, 8]
|
|
NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bTeardown: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS
|
|
NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES(c.Struct):
|
|
SIZE = 1
|
|
bPerSubCtxheaderSupported: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pdbTable: Annotated[c.Array[NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
instMemPhysAddr: Annotated[NvU64, 0]
|
|
instMemSize: Annotated[NvU64, 8]
|
|
instMemAddrSpace: Annotated[NvU32, 16]
|
|
instMemCpuCacheAttr: Annotated[NvU32, 20]
|
|
NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
ipVersion: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
smcMode: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
head: Annotated[NvU32, 0]
|
|
rgLineNum: Annotated[NvU32, 4]
|
|
intrLine: Annotated[NvU32, 8]
|
|
bEnable: Annotated[NvBool, 12]
|
|
NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO(c.Struct):
|
|
SIZE = 72
|
|
partitionFlag: Annotated[NvU32, 0]
|
|
grCount: Annotated[NvU32, 4]
|
|
gfxGrCount: Annotated[NvU32, 8]
|
|
gpcCount: Annotated[NvU32, 12]
|
|
virtualGpcCount: Annotated[NvU32, 16]
|
|
gfxGpcCount: Annotated[NvU32, 20]
|
|
veidCount: Annotated[NvU32, 24]
|
|
smCount: Annotated[NvU32, 28]
|
|
ceCount: Annotated[NvU32, 32]
|
|
nvEncCount: Annotated[NvU32, 36]
|
|
nvDecCount: Annotated[NvU32, 40]
|
|
nvJpgCount: Annotated[NvU32, 44]
|
|
nvOfaCount: Annotated[NvU32, 48]
|
|
validCTSIdMask: Annotated[NvU64, 56]
|
|
validGfxCTSIdMask: Annotated[NvU64, 64]
|
|
NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS(c.Struct):
|
|
SIZE = 4328
|
|
count: Annotated[NvU32, 0]
|
|
table: Annotated[c.Array[NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO, Literal[60]], 8]
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
partitionableMemSize: Annotated[NvU64, 0]
|
|
bottomRsvdSize: Annotated[NvU64, 8]
|
|
topRsvdSize: Annotated[NvU64, 16]
|
|
partitionableStartAddr: Annotated[NvU64, 24]
|
|
partitionableEndAddr: Annotated[NvU64, 32]
|
|
NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
engineMask: Annotated[c.Array[NvU64, Literal[4]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS(c.Struct):
|
|
SIZE = 4112
|
|
rlBuffers: Annotated[c.Array[c.Array[NV2080_CTRL_INTERNAL_MEMDESC_INFO, Literal[2]], Literal[64]], 0]
|
|
runlistIdMask: Annotated[NvU64, 4096]
|
|
swizzId: Annotated[NvU32, 4104]
|
|
NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS(c.Struct):
|
|
SIZE = 492
|
|
tegraImpImportData: Annotated[TEGRA_IMP_IMPORT_DATA, 0]
|
|
@c.record
|
|
class struct_TEGRA_IMP_IMPORT_DATA(c.Struct):
|
|
SIZE = 492
|
|
max_iso_bw_kbps: Annotated[NvU32, 0]
|
|
num_dram_channels: Annotated[NvU32, 4]
|
|
num_dram_clk_entries: Annotated[NvU32, 8]
|
|
dram_clk_instance: Annotated[c.Array[DRAM_CLK_INSTANCE, Literal[24]], 12]
|
|
TEGRA_IMP_IMPORT_DATA: TypeAlias = struct_TEGRA_IMP_IMPORT_DATA
|
|
@c.record
|
|
class struct_DRAM_CLK_INSTANCE(c.Struct):
|
|
SIZE = 20
|
|
dram_clk_freq_khz: Annotated[NvU32, 0]
|
|
mchub_clk_khz: Annotated[NvU32, 4]
|
|
mc_clk_khz: Annotated[NvU32, 8]
|
|
max_iso_bw_kbps: Annotated[NvU32, 12]
|
|
switch_latency_ns: Annotated[NvU32, 16]
|
|
DRAM_CLK_INSTANCE: TypeAlias = struct_DRAM_CLK_INSTANCE
|
|
NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS(c.Struct):
|
|
SIZE = 6
|
|
pciDeviceId: Annotated[NvU16, 0]
|
|
pciSubDeviceId: Annotated[NvU16, 2]
|
|
iseGPUBridge: Annotated[NvBool, 4]
|
|
approvedBusType: Annotated[NvU8, 5]
|
|
NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
local2Remote: Annotated[NvU32, 0]
|
|
remote2Local: Annotated[NvU32, 4]
|
|
localP2PDomainRemoteAddr: Annotated[NvU64, 8]
|
|
remoteP2PDomainLocalAddr: Annotated[NvU64, 16]
|
|
remoteWMBoxLocalAddr: Annotated[NvU64, 24]
|
|
p2pWmbTag: Annotated[NvU64, 32]
|
|
bNeedWarBug999673: Annotated[NvBool, 40]
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
local2Remote: Annotated[NvU32, 0]
|
|
remote2Local: Annotated[NvU32, 4]
|
|
localP2PDomainRemoteAddr: Annotated[NvU64, 8]
|
|
remoteP2PDomainLocalAddr: Annotated[NvU64, 16]
|
|
remoteWMBoxAddrU64: Annotated[NvU64, 24]
|
|
p2pWmbTag: Annotated[NvU64, 32]
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
peerIdx: Annotated[NvU32, 0]
|
|
bNeedWarBug999673: Annotated[NvBool, 4]
|
|
NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
peerId: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
peerId: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS(c.Struct):
|
|
SIZE = 2056
|
|
gfid: Annotated[NvU32, 0]
|
|
numEntries: Annotated[NvU32, 4]
|
|
gpaEntries: Annotated[c.Array[NvU64, Literal[128]], 8]
|
|
spaEntries: Annotated[c.Array[NvU64, Literal[128]], 1032]
|
|
NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
addressSpace: Annotated[NvU32, 0]
|
|
physicalAddr: Annotated[NvU64, 8]
|
|
limit: Annotated[NvU64, 16]
|
|
cacheSnoop: Annotated[NvU32, 24]
|
|
hclass: Annotated[NvU32, 28]
|
|
channelInstance: Annotated[NvU32, 32]
|
|
valid: Annotated[NvBool, 36]
|
|
pbTargetAperture: Annotated[NvU32, 40]
|
|
channelPBSize: Annotated[NvU32, 44]
|
|
subDeviceId: Annotated[NvU32, 48]
|
|
NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
replayableFaultBufferSize: Annotated[NvU32, 0]
|
|
replayableShadowFaultBufferMetadataSize: Annotated[NvU32, 4]
|
|
nonReplayableFaultBufferSize: Annotated[NvU32, 8]
|
|
nonReplayableShadowFaultBufferMetadataSize: Annotated[NvU32, 12]
|
|
NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
moduleIndex: Annotated[NvU32, 0]
|
|
size: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS
|
|
class enum_NV2080_INTR_CATEGORY(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_INTR_CATEGORY_DEFAULT = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_DEFAULT', 0)
|
|
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE', 1)
|
|
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION', 2)
|
|
NV2080_INTR_CATEGORY_RUNLIST = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_RUNLIST', 3)
|
|
NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION', 4)
|
|
NV2080_INTR_CATEGORY_UVM_OWNED = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_UVM_OWNED', 5)
|
|
NV2080_INTR_CATEGORY_UVM_SHARED = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_UVM_SHARED', 6)
|
|
NV2080_INTR_CATEGORY_ENUM_COUNT = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_ENUM_COUNT', 7)
|
|
|
|
NV2080_INTR_CATEGORY: TypeAlias = enum_NV2080_INTR_CATEGORY
|
|
@c.record
|
|
class struct_NV2080_INTR_CATEGORY_SUBTREE_MAP(c.Struct):
|
|
SIZE = 2
|
|
subtreeStart: Annotated[NvU8, 0]
|
|
subtreeEnd: Annotated[NvU8, 1]
|
|
NV2080_INTR_CATEGORY_SUBTREE_MAP: TypeAlias = struct_NV2080_INTR_CATEGORY_SUBTREE_MAP
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY(c.Struct):
|
|
SIZE = 16
|
|
engineIdx: Annotated[NvU16, 0]
|
|
pmcIntrMask: Annotated[NvU32, 4]
|
|
vectorStall: Annotated[NvU32, 8]
|
|
vectorNonStall: Annotated[NvU32, 12]
|
|
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY: TypeAlias = struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS(c.Struct):
|
|
SIZE = 2068
|
|
tableLen: Annotated[NvU32, 0]
|
|
table: Annotated[c.Array[NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY, Literal[128]], 4]
|
|
subtreeMap: Annotated[c.Array[NV2080_INTR_CATEGORY_SUBTREE_MAP, Literal[7]], 2052]
|
|
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bReservation: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
bReservation: Annotated[NvBool, 0]
|
|
bClientHandlesGrGating: Annotated[NvBool, 1]
|
|
bRmHandlesIdleSlow: Annotated[NvBool, 2]
|
|
NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
displayMask: Annotated[NvU32, 0]
|
|
numHeads: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS(c.Struct):
|
|
SIZE = 240
|
|
fbMemPageRanges: Annotated[c.Array[NV2080_CTRL_INTERNAL_NV_RANGE, Literal[15]], 0]
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
runlistId: Annotated[NvU32, 0]
|
|
numChannels: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
memBoundaryCfgA: Annotated[NvU64, 0]
|
|
memBoundaryCfgB: Annotated[NvU64, 8]
|
|
memBoundaryCfgC: Annotated[NvU32, 16]
|
|
memBoundaryCfg: Annotated[NvU32, 20]
|
|
memBoundaryCfgValInit: Annotated[NvU32, 24]
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS
|
|
NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
data: Annotated[c.Array[NvU32, Literal[8]], 0]
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
powerState: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X(c.Struct):
|
|
SIZE = 8
|
|
flags: Annotated[NvBool, 0]
|
|
duration: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bActivate: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
flags: Annotated[NvU32, 0]
|
|
bBridgeless: Annotated[NvBool, 4]
|
|
currLimits: Annotated[c.Array[NvU32, Literal[2]], 8]
|
|
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hysteresisus: Annotated[NvU64, 0]
|
|
bHystersisEnable: Annotated[NvBool, 8]
|
|
bSliGpuBoostSyncEnable: Annotated[NvBool, 9]
|
|
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 2064
|
|
hClient: Annotated[NvHandle, 0]
|
|
hObject: Annotated[NvHandle, 4]
|
|
faultBufferSize: Annotated[NvU32, 8]
|
|
faultBufferPteArray: Annotated[c.Array[NvU64, Literal[256]], 16]
|
|
NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 24032
|
|
shadowFaultBufferQueuePhysAddr: Annotated[NvU64, 0]
|
|
shadowFaultBufferSize: Annotated[NvU32, 8]
|
|
shadowFaultBufferMetadataSize: Annotated[NvU32, 12]
|
|
shadowFaultBufferPteArray: Annotated[c.Array[NvU64, Literal[3000]], 16]
|
|
shadowFaultBufferType: Annotated[NvU32, 24016]
|
|
faultBufferSharedMemoryPhysAddr: Annotated[NvU64, 24024]
|
|
NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
shadowFaultBufferType: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS(c.Struct):
|
|
SIZE = 184
|
|
PdeCopyParams: Annotated[NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS, 0]
|
|
NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X(c.Struct):
|
|
SIZE = 16
|
|
flags: Annotated[NvU32, 0]
|
|
boostDuration: Annotated[NvU32, 4]
|
|
gfId: Annotated[NvU32, 8]
|
|
bOverrideInfinite: Annotated[NvBool, 12]
|
|
NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X(c.Struct):
|
|
SIZE = 8
|
|
bIsCudaClient: Annotated[NvBool, 0]
|
|
gfId: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO(c.Struct):
|
|
SIZE = 28
|
|
skylineVgpcSize: Annotated[c.Array[NvU8, Literal[12]], 0]
|
|
singletonVgpcMask: Annotated[NvU32, 12]
|
|
maxInstances: Annotated[NvU32, 16]
|
|
computeSizeFlag: Annotated[NvU32, 20]
|
|
numNonSingletonVgpcs: Annotated[NvU32, 24]
|
|
NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS(c.Struct):
|
|
SIZE = 228
|
|
skylineTable: Annotated[c.Array[NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO, Literal[8]], 0]
|
|
validEntries: Annotated[NvU32, 224]
|
|
NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS
|
|
NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS
|
|
NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS
|
|
NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS
|
|
NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS: TypeAlias = struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bZbcSurfacesExist: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO(c.Struct):
|
|
SIZE = 56
|
|
enginesMask: Annotated[c.Array[NvU64, Literal[4]], 0]
|
|
partitionFlags: Annotated[NvU32, 32]
|
|
gpcMask: Annotated[NvU32, 36]
|
|
virtualGpcCount: Annotated[NvU32, 40]
|
|
veidOffset: Annotated[NvU32, 44]
|
|
veidCount: Annotated[NvU32, 48]
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
swizzId: Annotated[NvU32, 0]
|
|
uuid: Annotated[c.Array[NvU8, Literal[16]], 4]
|
|
info: Annotated[NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO, 24]
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
|
|
NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
|
|
NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
flags: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
bPcieGen4Capable: Annotated[NvBool, 0]
|
|
bIsC2CLinkUp: Annotated[NvBool, 1]
|
|
bIsDeviceMultiFunction: Annotated[NvBool, 2]
|
|
bGcxPmuCfgSpaceRestore: Annotated[NvBool, 3]
|
|
NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
programPeerMask: Annotated[NvU32, 0]
|
|
invalidatePeerMask: Annotated[NvU32, 4]
|
|
programPciePeerMask: Annotated[NvU32, 8]
|
|
NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS(c.Struct):
|
|
SIZE = 36
|
|
linkMask: Annotated[NvU32, 0]
|
|
hshubIds: Annotated[c.Array[NvU8, Literal[32]], 4]
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
numHshubs: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
hshubId: Annotated[NvU8, 0]
|
|
NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
egmPeerId: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
bGet: Annotated[NvBool, 0]
|
|
addr: Annotated[NvU64, 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bCyaMaskL1: Annotated[NvBool, 0]
|
|
bEnableAspmDtL1: Annotated[NvBool, 1]
|
|
NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
maxActiveVGpuVMCount: Annotated[NvU8, 0]
|
|
NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bRawMode: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
ccuSampleSize: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO(c.Struct):
|
|
SIZE = 16
|
|
phyAddr: Annotated[NvU64, 0]
|
|
shrBufSize: Annotated[NvU32, 8]
|
|
cntBlkSize: Annotated[NvU32, 12]
|
|
NV2080_CTRL_INTERNAL_CCU_MAP_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS(c.Struct):
|
|
SIZE = 144
|
|
mapInfo: Annotated[c.Array[NV2080_CTRL_INTERNAL_CCU_MAP_INFO, Literal[9]], 0]
|
|
NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bDevShrBuf: Annotated[NvBool, 0]
|
|
bMigShrBuf: Annotated[NvBool, 1]
|
|
NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO(c.Struct):
|
|
SIZE = 40
|
|
gpuId: Annotated[NvU32, 0]
|
|
gpuInstance: Annotated[NvU32, 4]
|
|
p2pCaps: Annotated[NvU32, 8]
|
|
p2pOptimalReadCEs: Annotated[NvU32, 12]
|
|
p2pOptimalWriteCEs: Annotated[NvU32, 16]
|
|
p2pCapsStatus: Annotated[c.Array[NvU8, Literal[9]], 20]
|
|
busPeerId: Annotated[NvU32, 32]
|
|
busEgmPeerId: Annotated[NvU32, 36]
|
|
NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS(c.Struct):
|
|
SIZE = 1284
|
|
peerGpuCount: Annotated[NvU32, 0]
|
|
peerGpuInfos: Annotated[c.Array[NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO, Literal[32]], 4]
|
|
NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS(c.Struct):
|
|
SIZE = 132
|
|
peerGpuIdCount: Annotated[NvU32, 0]
|
|
peerGpuIds: Annotated[c.Array[NvU32, Literal[32]], 4]
|
|
NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
bCommonPciSwitchFound: Annotated[NvBool, 0]
|
|
p2pReadCapsStatus: Annotated[NvU8, 1]
|
|
p2pWriteCapsStatus: Annotated[NvU8, 2]
|
|
NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
enableRo: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
bSave: Annotated[NvBool, 0]
|
|
bUseVbios: Annotated[NvBool, 1]
|
|
bReturnEarly: Annotated[NvBool, 2]
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
bSave: Annotated[NvBool, 0]
|
|
bUseVbios: Annotated[NvBool, 1]
|
|
bVbiosCallSuccessful: Annotated[NvBool, 2]
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE(c.Struct):
|
|
SIZE = 24
|
|
computeSize: Annotated[NvU8, 0]
|
|
gfxGpcCount: Annotated[NvU32, 4]
|
|
gpcCount: Annotated[NvU32, 8]
|
|
veidCount: Annotated[NvU32, 12]
|
|
smCount: Annotated[NvU32, 16]
|
|
physicalSlots: Annotated[NvU32, 20]
|
|
NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE: TypeAlias = struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS(c.Struct):
|
|
SIZE = 196
|
|
profileCount: Annotated[NvU32, 0]
|
|
profiles: Annotated[c.Array[NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE, Literal[8]], 4]
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bStreamState: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bExtDevFound: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
timingParameters: Annotated[NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS, 0]
|
|
@c.record
|
|
class struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
gpuId: Annotated[NvU32, 0]
|
|
output: Annotated[NvU32, 4]
|
|
protocol: Annotated[NvU32, 8]
|
|
structure: Annotated[NvU32, 12]
|
|
adjust: Annotated[NvU32, 16]
|
|
hDeltaStep: Annotated[NvU32, 20]
|
|
hDeltaMax: Annotated[NvU32, 24]
|
|
vDeltaStep: Annotated[NvU32, 28]
|
|
vDeltaMax: Annotated[NvU32, 32]
|
|
hSyncEnd: Annotated[NvU32, 36]
|
|
hBlankEnd: Annotated[NvU32, 40]
|
|
hBlankStart: Annotated[NvU32, 44]
|
|
hTotal: Annotated[NvU32, 48]
|
|
vSyncEnd: Annotated[NvU32, 52]
|
|
vBlankEnd: Annotated[NvU32, 56]
|
|
vBlankStart: Annotated[NvU32, 60]
|
|
vInterlacedBlankEnd: Annotated[NvU32, 64]
|
|
vInterlacedBlankStart: Annotated[NvU32, 68]
|
|
vTotal: Annotated[NvU32, 72]
|
|
refreshX10K: Annotated[NvU32, 76]
|
|
pixelClockHz: Annotated[NvU64, 80]
|
|
bOptimized: Annotated[NvBool, 88]
|
|
NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS: TypeAlias = struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS
|
|
NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
displayIds: Annotated[c.Array[NvU32, Literal[4]], 0]
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS(c.Struct):
|
|
SIZE = 52
|
|
slave: Annotated[c.Array[NvU32, Literal[4]], 0]
|
|
localSlave: Annotated[c.Array[NvU32, Literal[4]], 16]
|
|
master: Annotated[c.Array[NvU32, Literal[4]], 32]
|
|
regStatus: Annotated[NvU32, 48]
|
|
NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
headIdx: Annotated[NvU32, 0]
|
|
vActiveLines: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
displays: Annotated[NvU32, 0]
|
|
displayId: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bEnableMaster: Annotated[NvBool, 0]
|
|
bRasterSyncGpioSaved: Annotated[NvBool, 1]
|
|
bRasterSyncGpioDirection: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hClient: Annotated[NvHandle, 0]
|
|
hSysMem: Annotated[NvHandle, 4]
|
|
bEnteringGcoffState: Annotated[NvBool, 8]
|
|
sysmemAddrOfSuspendResumeData: Annotated[NvU64, 16]
|
|
NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bDisableActiveChannels: Annotated[NvBool, 0]
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
hostReservedFb: Annotated[NvU64, 0]
|
|
vgpuTypeId: Annotated[NvU32, 8]
|
|
NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS(c.Struct):
|
|
SIZE = 4104
|
|
status: Annotated[NvU32, 0]
|
|
backLightDataSize: Annotated[NvU16, 4]
|
|
backLightData: Annotated[c.Array[NvU8, Literal[4096]], 6]
|
|
NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
numActiveLinksPerIoctrl: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
numLinksPerIoctrl: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bIsSysCtrlSupported: Annotated[NvBool, 0]
|
|
bIsPlatformLegacy: Annotated[NvBool, 1]
|
|
NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI(c.Struct):
|
|
SIZE = 8
|
|
sensorId: Annotated[NvU32, 0]
|
|
limit: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI: TypeAlias = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA(c.Struct):
|
|
SIZE = 12
|
|
type: Annotated[NvU8, 0]
|
|
data: Annotated[struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data, 4]
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data(c.Struct):
|
|
SIZE = 8
|
|
smbpbi: Annotated[NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI, 0]
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA: TypeAlias = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
flags: Annotated[NvU8, 0]
|
|
syncData: Annotated[NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA, 4]
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS
|
|
NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS
|
|
NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
flag: Annotated[NvU8, 0]
|
|
bStatus: Annotated[NvBool, 1]
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnable: Annotated[NvBool, 0]
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bEnable: Annotated[NvBool, 0]
|
|
clientLimit: Annotated[NvU32, 4]
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
targetTemp: Annotated[NvS32, 0]
|
|
NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnable: Annotated[NvBool, 0]
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
ctgpOffsetmW: Annotated[NvU32, 0]
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bVpsPs20Supported: Annotated[NvBool, 0]
|
|
vPstateIdxHighest: Annotated[NvU32, 4]
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pStateIdx: Annotated[NvU32, 0]
|
|
vPstateIdxMapping: Annotated[NvU32, 4]
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
vPstateIdx: Annotated[NvU32, 0]
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bIsGC6Satisfied: Annotated[NvBool, 0]
|
|
bIsGCOFFSatisfied: Annotated[NvBool, 1]
|
|
NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
maxSec2SecureChannels: Annotated[NvU32, 0]
|
|
maxCeSecureChannels: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bDisable: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
pinSetIn: Annotated[NvU32, 0]
|
|
pinSetOut: Annotated[NvU32, 4]
|
|
bMasterScanLock: Annotated[NvBool, 8]
|
|
masterScanLockPin: Annotated[NvU32, 12]
|
|
bSlaveScanLock: Annotated[NvBool, 16]
|
|
slaveScanLockPin: Annotated[NvU32, 20]
|
|
NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pinSet: Annotated[NvU32, 0]
|
|
gpioFunction: Annotated[NvU32, 4]
|
|
gpioPin: Annotated[NvU32, 8]
|
|
gpioDirection: Annotated[NvBool, 12]
|
|
NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_EDID_DATA(c.Struct):
|
|
SIZE = 524
|
|
status: Annotated[NvU32, 0]
|
|
acpiId: Annotated[NvU32, 4]
|
|
bufferSize: Annotated[NvU32, 8]
|
|
edidBuffer: Annotated[c.Array[NvU8, Literal[512]], 12]
|
|
NV2080_CTRL_INTERNAL_EDID_DATA: TypeAlias = struct_NV2080_CTRL_INTERNAL_EDID_DATA
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS(c.Struct):
|
|
SIZE = 8388
|
|
tableLen: Annotated[NvU32, 0]
|
|
edidTable: Annotated[c.Array[NV2080_CTRL_INTERNAL_EDID_DATA, Literal[16]], 4]
|
|
NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
numProbes: Annotated[NvU64, 0]
|
|
NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bwMode: Annotated[NvU8, 0]
|
|
bLocalEgmEnabled: Annotated[NvBool, 1]
|
|
NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bwMode: Annotated[NvU8, 0]
|
|
NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS(c.Struct):
|
|
SIZE = 2
|
|
bIsBar1Trusted: Annotated[NvBool, 0]
|
|
bIsPcieTrusted: Annotated[NvBool, 1]
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK(c.Struct):
|
|
SIZE = 12
|
|
ivMask: Annotated[c.Array[NvU32, Literal[3]], 0]
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK: TypeAlias = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
engineId: Annotated[NvU32, 0]
|
|
ivMaskSet: Annotated[c.Array[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK, Literal[3]], 4]
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS(c.Struct):
|
|
SIZE = 76
|
|
engineId: Annotated[NvU32, 0]
|
|
ivMaskSet: Annotated[c.Array[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK, Literal[6]], 4]
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
globalH2DKey: Annotated[NvU32, 0]
|
|
updatedEncryptIVMask: Annotated[c.Array[NvU32, Literal[3]], 4]
|
|
updatedDecryptIVMask: Annotated[c.Array[NvU32, Literal[3]], 16]
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
exceptionType: Annotated[NvU32, 0]
|
|
globalH2DKey: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bAcceptClientRequest: Annotated[NvBool, 0]
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
attackerAdvantage: Annotated[NvU64, 0]
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
logicalUprocId: Annotated[NvU8, 0]
|
|
NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS
|
|
class enum_NV2080_CTRL_MEMMGR_MEMORY_OP(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = enum_NV2080_CTRL_MEMMGR_MEMORY_OP.define('NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY', 0)
|
|
NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = enum_NV2080_CTRL_MEMMGR_MEMORY_OP.define('NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET', 1)
|
|
|
|
NV2080_CTRL_MEMMGR_MEMORY_OP: TypeAlias = enum_NV2080_CTRL_MEMMGR_MEMORY_OP
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO(c.Struct):
|
|
SIZE = 32
|
|
baseAddr: Annotated[NvU64, 0]
|
|
size: Annotated[NvU64, 8]
|
|
offset: Annotated[NvU64, 16]
|
|
aperture: Annotated[NvU32, 24]
|
|
cpuCacheAttrib: Annotated[NvU32, 28]
|
|
NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS(c.Struct):
|
|
SIZE = 96
|
|
src: Annotated[NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO, 0]
|
|
authTag: Annotated[c.Array[NvU8, Literal[16]], 32]
|
|
dst: Annotated[NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO, 48]
|
|
transferSize: Annotated[NvU64, 80]
|
|
value: Annotated[NvU32, 88]
|
|
memop: Annotated[NV2080_CTRL_MEMMGR_MEMORY_OP, 92]
|
|
NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
addrSysPhys: Annotated[NvU64, 0]
|
|
addrWidth: Annotated[NvU32, 8]
|
|
mask: Annotated[NvU32, 12]
|
|
maskWidth: Annotated[NvU32, 16]
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
peerId: Annotated[NvU32, 0]
|
|
addrSysPhys: Annotated[NvU64, 8]
|
|
addrWidth: Annotated[NvU32, 16]
|
|
mask: Annotated[NvU32, 20]
|
|
maskWidth: Annotated[NvU32, 24]
|
|
NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
limitMin: Annotated[NvU32, 0]
|
|
limitRated: Annotated[NvU32, 4]
|
|
limitMax: Annotated[NvU32, 8]
|
|
limitCurr: Annotated[NvU32, 12]
|
|
limitBattRated: Annotated[NvU32, 16]
|
|
limitBattMax: Annotated[NvU32, 20]
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
physAddr: Annotated[NvU64, 0]
|
|
NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
polledDataMask: Annotated[NvU64, 0]
|
|
pollFrequencyMs: Annotated[NvU32, 8]
|
|
NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
tracepointMask: Annotated[NvU64, 0]
|
|
bufferAddr: Annotated[NvU64, 8]
|
|
bufferSize: Annotated[NvU32, 16]
|
|
bufferWatermark: Annotated[NvU32, 20]
|
|
flag: Annotated[NvU8, 24]
|
|
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS(c.Struct):
|
|
SIZE = 3
|
|
bMaxwellSec2Enabled: Annotated[NvBool, 0]
|
|
bNv95A1TsecEnabled: Annotated[NvBool, 1]
|
|
bHopperSec2WorkLaunchAEnabled: Annotated[NvBool, 2]
|
|
NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS
|
|
NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS: TypeAlias = struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bInPMTransition: Annotated[NvBool, 0]
|
|
newPMLevel: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bSuccessful: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
freeHeapSize: Annotated[NvU64, 0]
|
|
NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
attribute: Annotated[NvU32, 0]
|
|
value: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bApplyStereoPinAlwaysHiWar: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
maxHshubs: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rasterSyncDecodeMode: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
spaValue: Annotated[NvU64, 0]
|
|
NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
peerMask: Annotated[NvU32, 0]
|
|
bEnable: Annotated[NvBool, 4]
|
|
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
mode: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
seedData: Annotated[c.Array[NvU32, Literal[7]], 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
remoteDeviceType: Annotated[NvU32, 0]
|
|
ipVerDlPl: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
seedData: Annotated[c.Array[NvU32, Literal[7]], 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO(c.Struct):
|
|
SIZE = 24
|
|
remoteSid: Annotated[NvU64, 0]
|
|
remoteDeviceType: Annotated[NvU32, 8]
|
|
remoteLinkId: Annotated[NvU32, 12]
|
|
localSid: Annotated[NvU64, 16]
|
|
NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
bInitnegotiateConfigGood: Annotated[NvBool, 0]
|
|
remoteLocalSidInfo: Annotated[NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO, 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bPollDone: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
mode: Annotated[NvU64, 0]
|
|
bSync: Annotated[NvBool, 8]
|
|
linkMode: Annotated[NvU32, 12]
|
|
linkModeParams: Annotated[struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams, 16]
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams(c.Struct):
|
|
SIZE = 32
|
|
linkModeOffParams: Annotated[NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS, 0]
|
|
linkModePreHsParams: Annotated[NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS, 0]
|
|
linkModeInitPhase1Params: Annotated[NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS, 0]
|
|
linkModePostInitNegotiateParams: Annotated[NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS, 0]
|
|
linkModePostInitOptimizeParams: Annotated[NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
mode: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
mode: Annotated[NvU64, 0]
|
|
bSync: Annotated[NvBool, 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
sublinkMode: Annotated[NvU32, 0]
|
|
sublinkSubMode: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
mode: Annotated[NvU64, 0]
|
|
bSync: Annotated[NvBool, 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
mode: Annotated[NvU64, 0]
|
|
bSync: Annotated[NvBool, 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
laneRxdetStatusMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bSync: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
ipVerDlPl: Annotated[NvU32, 0]
|
|
token: Annotated[NvU64, 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bUnlocked: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE(c.Struct):
|
|
SIZE = 56
|
|
type: Annotated[NvU8, 0]
|
|
callbackParams: Annotated[struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams, 8]
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams(c.Struct):
|
|
SIZE = 48
|
|
getDlLinkMode: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS, 0]
|
|
setDlLinkMode: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS, 0]
|
|
getTlLinkMode: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS, 0]
|
|
setTlLinkMode: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS, 0]
|
|
getTxSublinkMode: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS, 0]
|
|
setTxSublinkMode: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS, 0]
|
|
getRxSublinkMode: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS, 0]
|
|
setRxSublinkMode: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS, 0]
|
|
getRxSublinkDetect: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS, 0]
|
|
setRxSublinkDetect: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS, 0]
|
|
writeDiscoveryToken: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS, 0]
|
|
readDiscoveryToken: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS, 0]
|
|
getUphyLoad: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS(c.Struct):
|
|
SIZE = 64
|
|
linkId: Annotated[NvU32, 0]
|
|
callbackType: Annotated[NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE, 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
linkId: Annotated[NvU32, 0]
|
|
remoteLocalSidInfo: Annotated[NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO, 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnableAli: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
updateType: Annotated[NvBool, 0]
|
|
bSysMem: Annotated[NvBool, 1]
|
|
peerMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
peerId: Annotated[NvU32, 0]
|
|
peerLinkMask: Annotated[NvU32, 4]
|
|
bEgmPeer: Annotated[NvBool, 8]
|
|
bNvswitchConn: Annotated[NvBool, 9]
|
|
NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
peerMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS(c.Struct):
|
|
SIZE = 92
|
|
xid: Annotated[NvU32, 0]
|
|
message: Annotated[c.Array[NvU8, Literal[81]], 4]
|
|
len: Annotated[NvU32, 88]
|
|
NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
mapTypeMask: Annotated[NvU32, 0]
|
|
peerMask: Annotated[NvU32, 4]
|
|
bL2Entry: Annotated[NvBool, 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
bSave: Annotated[NvBool, 0]
|
|
linkMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
flags: Annotated[NvU32, 0]
|
|
bSysmem: Annotated[NvBool, 4]
|
|
peerLinkMask: Annotated[NvU32, 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bNvlinkSysmemEnabled: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gpuInst: Annotated[NvU32, 0]
|
|
peerLinkMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS(c.Struct):
|
|
SIZE = 40
|
|
remoteDeviceType: Annotated[NvU64, 0]
|
|
remoteChipSid: Annotated[NvU64, 8]
|
|
linkId: Annotated[NvU32, 16]
|
|
laneRxdetStatusMask: Annotated[NvU32, 20]
|
|
remoteLinkNumber: Annotated[NvU32, 24]
|
|
remotePciDeviceId: Annotated[NvU32, 28]
|
|
remoteDomain: Annotated[NvU32, 32]
|
|
remoteBus: Annotated[NvU8, 36]
|
|
remoteDevice: Annotated[NvU8, 37]
|
|
remoteFunction: Annotated[NvU8, 38]
|
|
bConnected: Annotated[NvBool, 39]
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkMask: Annotated[NvU32, 0]
|
|
initializedLinks: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkMask: Annotated[NvU32, 0]
|
|
bSync: Annotated[NvBool, 4]
|
|
NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS(c.Struct):
|
|
SIZE = 264
|
|
postRxDetLinkMask: Annotated[NvU64, 0]
|
|
laneRxdetStatusMask: Annotated[c.Array[NvU32, Literal[64]], 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkMask: Annotated[NvU32, 0]
|
|
bSync: Annotated[NvBool, 4]
|
|
NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES(c.Struct):
|
|
SIZE = 16
|
|
bValid: Annotated[NvBool, 0]
|
|
linkId: Annotated[NvU8, 1]
|
|
ioctrlId: Annotated[NvU32, 4]
|
|
pllMasterLinkId: Annotated[NvU8, 8]
|
|
pllSlaveLinkId: Annotated[NvU8, 9]
|
|
ipVerDlPl: Annotated[NvU32, 12]
|
|
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS(c.Struct):
|
|
SIZE = 1056
|
|
ioctrlMask: Annotated[NvU32, 0]
|
|
ioctrlNumEntries: Annotated[NvU8, 4]
|
|
ioctrlSize: Annotated[NvU32, 8]
|
|
discoveredLinks: Annotated[NvU64, 16]
|
|
ipVerNvlink: Annotated[NvU32, 24]
|
|
linkInfo: Annotated[c.Array[NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES, Literal[64]], 28]
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES(c.Struct):
|
|
SIZE = 8
|
|
ipVerIoctrl: Annotated[NvU32, 0]
|
|
ipVerMinion: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
ioctrlIdx: Annotated[NvU32, 0]
|
|
PublicId: Annotated[NvU32, 4]
|
|
localDiscoveredLinks: Annotated[NvU32, 8]
|
|
localGlobalLinkOffset: Annotated[NvU32, 12]
|
|
ioctrlDiscoverySize: Annotated[NvU32, 16]
|
|
numDevices: Annotated[NvU8, 20]
|
|
ipRevisions: Annotated[NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES, 24]
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
bPlatformLinerateDefined: Annotated[NvBool, 0]
|
|
platformLineRate: Annotated[NvU32, 4]
|
|
nvlinkLinkSpeed: Annotated[NvU32, 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
linkMask: Annotated[NvU32, 0]
|
|
bActiveOnly: Annotated[NvBool, 4]
|
|
bIsLinkActive: Annotated[c.Array[NvBool, Literal[64]], 5]
|
|
NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkMask: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
linkMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES(c.Struct):
|
|
SIZE = 56
|
|
bLinkConnectedToSystem: Annotated[NvBool, 0]
|
|
bLinkConnectedToPeer: Annotated[NvBool, 1]
|
|
bLinkReset: Annotated[NvBool, 2]
|
|
subLinkWidth: Annotated[NvU8, 3]
|
|
linkState: Annotated[NvU32, 4]
|
|
txSublinkState: Annotated[NvU32, 8]
|
|
rxSublinkState: Annotated[NvU32, 12]
|
|
bLaneReversal: Annotated[NvBool, 16]
|
|
nvlinkLinkClockKHz: Annotated[NvU32, 20]
|
|
nvlinkLineRateMbps: Annotated[NvU32, 24]
|
|
nvlinkLinkClockMhz: Annotated[NvU32, 28]
|
|
nvlinkLinkDataRateKiBps: Annotated[NvU32, 32]
|
|
nvlinkRefClkType: Annotated[NvU8, 36]
|
|
nvlinkReqLinkClockMhz: Annotated[NvU32, 40]
|
|
nvlinkMinL1Threshold: Annotated[NvU32, 44]
|
|
nvlinkMaxL1Threshold: Annotated[NvU32, 48]
|
|
nvlinkL1ThresholdUnits: Annotated[NvU32, 52]
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS(c.Struct):
|
|
SIZE = 3600
|
|
linkMask: Annotated[NvU64, 0]
|
|
nvlinkRefClkSpeedKHz: Annotated[NvU32, 8]
|
|
bSublinkStateInst: Annotated[NvBool, 12]
|
|
linkInfo: Annotated[c.Array[NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES, Literal[64]], 16]
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
sysmemLinkMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS(c.Struct):
|
|
SIZE = 264
|
|
bLegacyForcedConfig: Annotated[NvBool, 0]
|
|
bOverrideComputePeerMode: Annotated[NvBool, 1]
|
|
phase: Annotated[NvU32, 4]
|
|
linkConnection: Annotated[c.Array[NvU32, Literal[64]], 8]
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bLaneShutdownOnUnload: Annotated[NvBool, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
notUsed: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
sysmemLinkMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
ctrlParamVal: Annotated[NvU32, 0]
|
|
NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
responseVal: Annotated[NvU32, 0]
|
|
NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
architecture: Annotated[NvU32, 0]
|
|
implementation: Annotated[NvU32, 4]
|
|
revision: Annotated[NvU32, 8]
|
|
subRevision: Annotated[NvU8, 12]
|
|
NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
engines: Annotated[NvU32, 0]
|
|
NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
manufacturer: Annotated[NvU32, 0]
|
|
NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bOwnedByRm: Annotated[NvBool, 0]
|
|
NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY(c.Struct):
|
|
SIZE = 8
|
|
nv2080EngineType: Annotated[NvU32, 0]
|
|
notificationIntrVector: Annotated[NvU32, 4]
|
|
NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY: TypeAlias = struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS(c.Struct):
|
|
SIZE = 2052
|
|
numEntries: Annotated[NvU32, 0]
|
|
entries: Annotated[c.Array[NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY, Literal[256]], 4]
|
|
NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY(c.Struct):
|
|
SIZE = 16
|
|
nv2080IntrType: Annotated[NvU32, 0]
|
|
pmcIntrMask: Annotated[NvU32, 4]
|
|
intrVectorStall: Annotated[NvU32, 8]
|
|
intrVectorNonStall: Annotated[NvU32, 12]
|
|
NV2080_CTRL_MC_STATIC_INTR_ENTRY: TypeAlias = struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY
|
|
@c.record
|
|
class struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS(c.Struct):
|
|
SIZE = 516
|
|
numEntries: Annotated[NvU32, 0]
|
|
entries: Annotated[c.Array[NV2080_CTRL_MC_STATIC_INTR_ENTRY, Literal[32]], 4]
|
|
NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS: TypeAlias = struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
component: Annotated[NvU32, 0]
|
|
size: Annotated[NvU32, 4]
|
|
NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
pBuffer: Annotated[NvP64, 0]
|
|
component: Annotated[NvU32, 8]
|
|
size: Annotated[NvU32, 12]
|
|
NV2080_CTRL_NVD_GET_DUMP_PARAMS: TypeAlias = struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS(c.Struct):
|
|
SIZE = 32
|
|
userMinOffset: Annotated[NvS32, 0]
|
|
userMaxOffset: Annotated[NvS32, 4]
|
|
factoryMinOffset: Annotated[NvU32, 8]
|
|
factoryMaxOffset: Annotated[NvU32, 12]
|
|
lastActiveClock: Annotated[NvU32, 16]
|
|
lastActiveVolt: Annotated[NvU32, 20]
|
|
lastActivePoint: Annotated[NvU32, 24]
|
|
kappa: Annotated[NvU32, 28]
|
|
NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS: TypeAlias = struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS
|
|
@c.record
|
|
class struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG(c.Struct):
|
|
SIZE = 72
|
|
pstateVer: Annotated[NvU32, 0]
|
|
gpcOverclock: Annotated[NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS, 4]
|
|
mclkOverclock: Annotated[NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS, 36]
|
|
bUserOverclocked: Annotated[NvBool, 68]
|
|
bFactoryOverclocked: Annotated[NvBool, 69]
|
|
NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG: TypeAlias = struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG
|
|
@c.record
|
|
class struct_NV2080_NOCAT_JOURNAL_GPU_STATE(c.Struct):
|
|
SIZE = 240
|
|
bValid: Annotated[NvBool, 0]
|
|
strap: Annotated[NvU32, 4]
|
|
deviceId: Annotated[NvU16, 8]
|
|
vendorId: Annotated[NvU16, 10]
|
|
subsystemVendor: Annotated[NvU16, 12]
|
|
subsystemId: Annotated[NvU16, 14]
|
|
revision: Annotated[NvU16, 16]
|
|
type: Annotated[NvU16, 18]
|
|
vbiosVersion: Annotated[NvU32, 20]
|
|
bOptimus: Annotated[NvBool, 24]
|
|
bMsHybrid: Annotated[NvBool, 25]
|
|
bFullPower: Annotated[NvBool, 26]
|
|
vbiosOemVersion: Annotated[NvU32, 28]
|
|
memoryType: Annotated[NvU16, 32]
|
|
tag: Annotated[c.Array[NvU8, Literal[65]], 34]
|
|
vbiosProject: Annotated[c.Array[NvU8, Literal[65]], 99]
|
|
bInFullchipReset: Annotated[NvBool, 164]
|
|
bInSecBusReset: Annotated[NvBool, 165]
|
|
bInGc6Reset: Annotated[NvBool, 166]
|
|
overclockCfg: Annotated[NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG, 168]
|
|
NV2080_NOCAT_JOURNAL_GPU_STATE: TypeAlias = struct_NV2080_NOCAT_JOURNAL_GPU_STATE
|
|
@c.record
|
|
class struct_NV2080_NOCAT_JOURNAL_ENTRY(c.Struct):
|
|
SIZE = 1272
|
|
recType: Annotated[NvU8, 0]
|
|
bugcheck: Annotated[NvU32, 4]
|
|
tdrBucketId: Annotated[NvU32, 8]
|
|
source: Annotated[c.Array[NvU8, Literal[65]], 12]
|
|
subsystem: Annotated[NvU32, 80]
|
|
errorCode: Annotated[NvU64, 88]
|
|
diagBufferLen: Annotated[NvU32, 96]
|
|
diagBuffer: Annotated[c.Array[NvU8, Literal[1024]], 100]
|
|
faultingEngine: Annotated[c.Array[NvU8, Literal[65]], 1124]
|
|
mmuFaultType: Annotated[NvU32, 1192]
|
|
mmuErrorSrc: Annotated[NvU32, 1196]
|
|
tdrReason: Annotated[c.Array[NvU8, Literal[65]], 1200]
|
|
NV2080_NOCAT_JOURNAL_ENTRY: TypeAlias = struct_NV2080_NOCAT_JOURNAL_ENTRY
|
|
@c.record
|
|
class struct_NV2080_NOCAT_JOURNAL_RECORD(c.Struct):
|
|
SIZE = 1544
|
|
GPUTag: Annotated[NvU32, 0]
|
|
loadAddress: Annotated[NvU64, 8]
|
|
timeStamp: Annotated[NvU64, 16]
|
|
stateMask: Annotated[NvU64, 24]
|
|
nocatGpuState: Annotated[NV2080_NOCAT_JOURNAL_GPU_STATE, 32]
|
|
nocatJournalEntry: Annotated[NV2080_NOCAT_JOURNAL_ENTRY, 272]
|
|
NV2080_NOCAT_JOURNAL_RECORD: TypeAlias = struct_NV2080_NOCAT_JOURNAL_RECORD
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS(c.Struct):
|
|
SIZE = 15656
|
|
flags: Annotated[NvU32, 0]
|
|
nocatRecordCount: Annotated[NvU32, 4]
|
|
nocatOutstandingRecordCount: Annotated[NvU32, 8]
|
|
journalRecords: Annotated[c.Array[NV2080_NOCAT_JOURNAL_RECORD, Literal[10]], 16]
|
|
activityCounters: Annotated[c.Array[NvU32, Literal[32]], 15456]
|
|
reserved: Annotated[c.Array[NvU8, Literal[65]], 15584]
|
|
NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS: TypeAlias = struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS
|
|
@c.record
|
|
class struct_NV2080CtrlNocatJournalDataTdrReason(c.Struct):
|
|
SIZE = 96
|
|
flags: Annotated[NvU32, 0]
|
|
source: Annotated[c.Array[NvU8, Literal[65]], 4]
|
|
subsystem: Annotated[NvU32, 72]
|
|
errorCode: Annotated[NvU64, 80]
|
|
reasonCode: Annotated[NvU32, 88]
|
|
NV2080CtrlNocatJournalDataTdrReason: TypeAlias = struct_NV2080CtrlNocatJournalDataTdrReason
|
|
@c.record
|
|
class struct_NV2080CtrlNocatJournalSetTag(c.Struct):
|
|
SIZE = 72
|
|
flags: Annotated[NvU32, 0]
|
|
tag: Annotated[c.Array[NvU8, Literal[65]], 4]
|
|
NV2080CtrlNocatJournalSetTag: TypeAlias = struct_NV2080CtrlNocatJournalSetTag
|
|
@c.record
|
|
class struct_NV2080CtrlNocatJournalRclog(c.Struct):
|
|
SIZE = 92
|
|
flags: Annotated[NvU32, 0]
|
|
rclogSize: Annotated[NvU32, 4]
|
|
rmGpuId: Annotated[NvU32, 8]
|
|
APIType: Annotated[NvU32, 12]
|
|
contextType: Annotated[NvU32, 16]
|
|
exceptType: Annotated[NvU32, 20]
|
|
processImageName: Annotated[c.Array[NvU8, Literal[65]], 24]
|
|
NV2080CtrlNocatJournalRclog: TypeAlias = struct_NV2080CtrlNocatJournalRclog
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS(c.Struct):
|
|
SIZE = 104
|
|
dataType: Annotated[NvU32, 0]
|
|
targetRecordType: Annotated[NvU32, 4]
|
|
nocatJournalData: Annotated[struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData, 8]
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData(c.Struct):
|
|
SIZE = 96
|
|
tdrReason: Annotated[NV2080CtrlNocatJournalDataTdrReason, 0]
|
|
tagData: Annotated[NV2080CtrlNocatJournalSetTag, 0]
|
|
rclog: Annotated[NV2080CtrlNocatJournalRclog, 0]
|
|
NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080CtrlNocatJournalInsertRecord(c.Struct):
|
|
SIZE = 1208
|
|
flags: Annotated[NvU32, 0]
|
|
timestamp: Annotated[NvU64, 8]
|
|
recType: Annotated[NvU8, 16]
|
|
bugcheck: Annotated[NvU32, 20]
|
|
source: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[65]], 24]
|
|
subsystem: Annotated[NvU32, 92]
|
|
errorCode: Annotated[NvU64, 96]
|
|
faultingEngine: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[65]], 104]
|
|
tdrReason: Annotated[NvU32, 172]
|
|
diagBufferLen: Annotated[NvU32, 176]
|
|
diagBuffer: Annotated[c.Array[NvU8, Literal[1024]], 180]
|
|
NV2080CtrlNocatJournalInsertRecord: TypeAlias = struct_NV2080CtrlNocatJournalInsertRecord
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS(c.Struct):
|
|
SIZE = 1208
|
|
nocatJournalRecord: Annotated[NV2080CtrlNocatJournalInsertRecord, 0]
|
|
NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
capsTbl: Annotated[NvU32, 0]
|
|
lowestNvlinkVersion: Annotated[NvU8, 4]
|
|
highestNvlinkVersion: Annotated[NvU8, 5]
|
|
lowestNciVersion: Annotated[NvU8, 6]
|
|
highestNciVersion: Annotated[NvU8, 7]
|
|
discoveredLinkMask: Annotated[NvU32, 8]
|
|
enabledLinkMask: Annotated[NvU32, 12]
|
|
discoveredLinks: Annotated[NvU64, 16]
|
|
enabledLinks: Annotated[NvU64, 24]
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_DEVICE_INFO(c.Struct):
|
|
SIZE = 56
|
|
deviceIdFlags: Annotated[NvU32, 0]
|
|
domain: Annotated[NvU32, 4]
|
|
bus: Annotated[NvU16, 8]
|
|
device: Annotated[NvU16, 10]
|
|
function: Annotated[NvU16, 12]
|
|
pciDeviceId: Annotated[NvU32, 16]
|
|
deviceType: Annotated[NvU64, 24]
|
|
deviceUUID: Annotated[c.Array[NvU8, Literal[16]], 32]
|
|
fabricRecoveryStatusMask: Annotated[NvU32, 48]
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO: TypeAlias = struct_NV2080_CTRL_NVLINK_DEVICE_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO(c.Struct):
|
|
SIZE = 208
|
|
capsTbl: Annotated[NvU32, 0]
|
|
phyType: Annotated[NvU8, 4]
|
|
subLinkWidth: Annotated[NvU8, 5]
|
|
linkState: Annotated[NvU32, 8]
|
|
rxSublinkStatus: Annotated[NvU8, 12]
|
|
txSublinkStatus: Annotated[NvU8, 13]
|
|
bLaneReversal: Annotated[NvBool, 14]
|
|
nvlinkVersion: Annotated[NvU8, 15]
|
|
nciVersion: Annotated[NvU8, 16]
|
|
phyVersion: Annotated[NvU8, 17]
|
|
nvlinkLinkClockKHz: Annotated[NvU32, 20]
|
|
nvlinkCommonClockSpeedKHz: Annotated[NvU32, 24]
|
|
nvlinkRefClkSpeedKHz: Annotated[NvU32, 28]
|
|
nvlinkCommonClockSpeedMhz: Annotated[NvU32, 32]
|
|
nvlinkLineRateMbps: Annotated[NvU32, 36]
|
|
nvlinkLinkClockMhz: Annotated[NvU32, 40]
|
|
nvlinkRefClkType: Annotated[NvU8, 44]
|
|
nvlinkLinkDataRateKiBps: Annotated[NvU32, 48]
|
|
nvlinkRefClkSpeedMhz: Annotated[NvU32, 52]
|
|
connected: Annotated[NvBool, 56]
|
|
loopProperty: Annotated[NvU8, 57]
|
|
remoteDeviceLinkNumber: Annotated[NvU8, 58]
|
|
localDeviceLinkNumber: Annotated[NvU8, 59]
|
|
remoteLinkSid: Annotated[NvU64, 64]
|
|
localLinkSid: Annotated[NvU64, 72]
|
|
laneRxdetStatusMask: Annotated[NvU32, 80]
|
|
nvlinkMinL1Threshold: Annotated[NvU32, 84]
|
|
nvlinkMaxL1Threshold: Annotated[NvU32, 88]
|
|
nvlinkL1ThresholdUnits: Annotated[NvU32, 92]
|
|
remoteDeviceInfo: Annotated[NV2080_CTRL_NVLINK_DEVICE_INFO, 96]
|
|
localDeviceInfo: Annotated[NV2080_CTRL_NVLINK_DEVICE_INFO, 152]
|
|
NV2080_CTRL_NVLINK_LINK_STATUS_INFO: TypeAlias = struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO
|
|
class enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US = enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT.define('NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US', 0)
|
|
NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US = enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT.define('NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US', 1)
|
|
|
|
NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT: TypeAlias = enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS(c.Struct):
|
|
SIZE = 13320
|
|
enabledLinkMask: Annotated[NvU32, 0]
|
|
bSublinkStateInst: Annotated[NvBool, 4]
|
|
linkInfo: Annotated[c.Array[NV2080_CTRL_NVLINK_LINK_STATUS_INFO, Literal[64]], 8]
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_ERR_INFO(c.Struct):
|
|
SIZE = 112
|
|
TLErrlog: Annotated[NvU32, 0]
|
|
TLIntrEn: Annotated[NvU32, 4]
|
|
TLCTxErrStatus0: Annotated[NvU32, 8]
|
|
TLCTxErrStatus1: Annotated[NvU32, 12]
|
|
TLCTxSysErrStatus0: Annotated[NvU32, 16]
|
|
TLCRxErrStatus0: Annotated[NvU32, 20]
|
|
TLCRxErrStatus1: Annotated[NvU32, 24]
|
|
TLCRxSysErrStatus0: Annotated[NvU32, 28]
|
|
TLCTxErrLogEn0: Annotated[NvU32, 32]
|
|
TLCTxErrLogEn1: Annotated[NvU32, 36]
|
|
TLCTxSysErrLogEn0: Annotated[NvU32, 40]
|
|
TLCRxErrLogEn0: Annotated[NvU32, 44]
|
|
TLCRxErrLogEn1: Annotated[NvU32, 48]
|
|
TLCRxSysErrLogEn0: Annotated[NvU32, 52]
|
|
MIFTxErrStatus0: Annotated[NvU32, 56]
|
|
MIFRxErrStatus0: Annotated[NvU32, 60]
|
|
NVLIPTLnkErrStatus0: Annotated[NvU32, 64]
|
|
NVLIPTLnkErrLogEn0: Annotated[NvU32, 68]
|
|
NVLIPTLnkCtrlLinkStateRequest: Annotated[NvU32, 72]
|
|
DLSpeedStatusTx: Annotated[NvU32, 76]
|
|
DLSpeedStatusRx: Annotated[NvU32, 80]
|
|
NVLDLRxSlsmErrCntl: Annotated[NvU32, 84]
|
|
NVLDLTopLinkState: Annotated[NvU32, 88]
|
|
NVLDLTopIntr: Annotated[NvU32, 92]
|
|
DLStatMN00: Annotated[NvU32, 96]
|
|
DLStatUC01: Annotated[NvU32, 100]
|
|
MinionNvlinkLinkIntr: Annotated[NvU32, 104]
|
|
bExcessErrorDL: Annotated[NvBool, 108]
|
|
NV2080_CTRL_NVLINK_ERR_INFO: TypeAlias = struct_NV2080_CTRL_NVLINK_ERR_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO(c.Struct):
|
|
SIZE = 8
|
|
NVLIPTErrStatus0: Annotated[NvU32, 0]
|
|
NVLIPTErrLogEn0: Annotated[NvU32, 4]
|
|
NV2080_CTRL_NVLINK_COMMON_ERR_INFO: TypeAlias = struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS(c.Struct):
|
|
SIZE = 7204
|
|
linkMask: Annotated[NvU32, 0]
|
|
linkErrInfo: Annotated[c.Array[NV2080_CTRL_NVLINK_ERR_INFO, Literal[64]], 4]
|
|
ioctrlMask: Annotated[NvU32, 7172]
|
|
commonErrInfo: Annotated[c.Array[NV2080_CTRL_NVLINK_COMMON_ERR_INFO, Literal[3]], 7176]
|
|
ErrInfoFlags: Annotated[NvU8, 7200]
|
|
NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES(c.Struct):
|
|
SIZE = 264
|
|
bTx0TlCounterOverflow: Annotated[NvBool, 0]
|
|
bTx1TlCounterOverflow: Annotated[NvBool, 1]
|
|
bRx0TlCounterOverflow: Annotated[NvBool, 2]
|
|
bRx1TlCounterOverflow: Annotated[NvBool, 3]
|
|
value: Annotated[c.Array[NvU64, Literal[32]], 8]
|
|
NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 16912
|
|
counterMask: Annotated[NvU32, 0]
|
|
linkMask: Annotated[NvU64, 8]
|
|
counters: Annotated[c.Array[NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES, Literal[64]], 16]
|
|
NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
counterMask: Annotated[NvU32, 0]
|
|
linkMask: Annotated[NvU64, 8]
|
|
NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES(c.Struct):
|
|
SIZE = 16
|
|
overFlow: Annotated[NvBool, 0]
|
|
value: Annotated[NvU64, 8]
|
|
NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES: TypeAlias = struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS(c.Struct):
|
|
SIZE = 28696
|
|
linkMask: Annotated[NvU64, 0]
|
|
counterMask: Annotated[c.Array[NvU64, Literal[2]], 8]
|
|
counter: Annotated[c.Array[c.Array[NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES, Literal[28]], Literal[64]], 24]
|
|
NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
linkMask: Annotated[NvU64, 0]
|
|
counterMask: Annotated[c.Array[NvU64, Literal[2]], 8]
|
|
NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkMask: Annotated[NvU32, 0]
|
|
bFatalError: Annotated[NvBool, 4]
|
|
NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS
|
|
class enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR', 1)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR', 2)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR', 3)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR', 4)
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX', 5)
|
|
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE: TypeAlias = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG(c.Struct):
|
|
SIZE = 16
|
|
errType: Annotated[NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE, 0]
|
|
errSettings: Annotated[NvU64, 8]
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG: TypeAlias = struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS(c.Struct):
|
|
SIZE = 1032
|
|
linkMask: Annotated[NvU64, 0]
|
|
errCfg: Annotated[c.Array[NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG, Literal[64]], 8]
|
|
NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO(c.Struct):
|
|
SIZE = 20
|
|
txErrInfo: Annotated[NvU32, 0]
|
|
packetErrInfo: Annotated[NvU32, 4]
|
|
authErrInfo: Annotated[NvU32, 8]
|
|
linkStatus: Annotated[NvU32, 12]
|
|
errInjectStatus: Annotated[NvU32, 16]
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO: TypeAlias = struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS(c.Struct):
|
|
SIZE = 1288
|
|
linkMask: Annotated[NvU64, 0]
|
|
errInfo: Annotated[c.Array[NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO, Literal[64]], 8]
|
|
NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS(c.Struct):
|
|
SIZE = 260
|
|
linkMask: Annotated[NvU32, 0]
|
|
numRecoveries: Annotated[c.Array[NvU32, Literal[64]], 4]
|
|
NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkId: Annotated[NvU32, 0]
|
|
remoteType: Annotated[NvU32, 4]
|
|
NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS(c.Struct):
|
|
SIZE = 80
|
|
linkId: Annotated[NvU32, 0]
|
|
supportedCounts: Annotated[NvU64, 8]
|
|
fatalErrorCounts: Annotated[c.Array[NvU8, Literal[63]], 16]
|
|
NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE(c.Struct):
|
|
SIZE = 8
|
|
errorsPerMinute: Annotated[NvU32, 0]
|
|
timestamp: Annotated[NvU32, 4]
|
|
NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE: TypeAlias = struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS(c.Struct):
|
|
SIZE = 92
|
|
linkId: Annotated[NvU32, 0]
|
|
numDailyMaxNonfatalErrorRates: Annotated[NvU32, 4]
|
|
dailyMaxNonfatalErrorRates: Annotated[c.Array[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE, Literal[5]], 8]
|
|
numMonthlyMaxNonfatalErrorRates: Annotated[NvU32, 48]
|
|
monthlyMaxNonfatalErrorRates: Annotated[c.Array[NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE, Literal[5]], 52]
|
|
NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnabled: Annotated[NvBool, 0]
|
|
NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkId: Annotated[NvU8, 0]
|
|
params: Annotated[NvU32, 4]
|
|
NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkMask: Annotated[NvU32, 0]
|
|
powerState: Annotated[NvU32, 4]
|
|
NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkId: Annotated[NvU32, 0]
|
|
powerState: Annotated[NvU32, 4]
|
|
NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS
|
|
class enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
TLC_RX_LNK = enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE.define('TLC_RX_LNK', 0)
|
|
TLC_TX_SYS = enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE.define('TLC_TX_SYS', 1)
|
|
|
|
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE: TypeAlias = enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE
|
|
class enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
TX_SYS_TX_RSP_STATUS_HW_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE.define('TX_SYS_TX_RSP_STATUS_HW_ERR', 0)
|
|
TX_SYS_TX_RSP_STATUS_UR_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE.define('TX_SYS_TX_RSP_STATUS_UR_ERR', 1)
|
|
TX_SYS_TX_RSP_STATUS_PRIV_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE.define('TX_SYS_TX_RSP_STATUS_PRIV_ERR', 2)
|
|
|
|
NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE: TypeAlias = enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE
|
|
class enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
RX_LNK_RX_RSP_STATUS_HW_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE.define('RX_LNK_RX_RSP_STATUS_HW_ERR', 0)
|
|
RX_LNK_RX_RSP_STATUS_UR_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE.define('RX_LNK_RX_RSP_STATUS_UR_ERR', 1)
|
|
RX_LNK_RX_RSP_STATUS_PRIV_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE.define('RX_LNK_RX_RSP_STATUS_PRIV_ERR', 2)
|
|
|
|
NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE: TypeAlias = enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE
|
|
@c.record
|
|
class union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE(c.Struct):
|
|
SIZE = 4
|
|
txSysErrorType: Annotated[NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE, 0]
|
|
rxLnkErrorType: Annotated[NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE, 0]
|
|
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE: TypeAlias = union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
linkId: Annotated[NvU32, 0]
|
|
device: Annotated[NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE, 4]
|
|
bBroadcast: Annotated[NvBool, 8]
|
|
errorType: Annotated[NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE, 12]
|
|
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
linkId: Annotated[NvU32, 0]
|
|
numLanes: Annotated[NvU8, 4]
|
|
figureOfMeritValues: Annotated[c.Array[NvU16, Literal[4]], 6]
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
peerMask: Annotated[NvU32, 0]
|
|
bEnable: Annotated[NvBool, 4]
|
|
NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkId: Annotated[NvU8, 0]
|
|
lane: Annotated[NvU8, 1]
|
|
addr: Annotated[NvU16, 2]
|
|
phyConfigData: Annotated[NvU32, 4]
|
|
NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_LANE_ERROR(c.Struct):
|
|
SIZE = 12
|
|
bValid: Annotated[NvBool, 0]
|
|
eccErrorValue: Annotated[NvU32, 4]
|
|
overflowed: Annotated[NvBool, 8]
|
|
NV2080_CTRL_NVLINK_LANE_ERROR: TypeAlias = struct_NV2080_CTRL_NVLINK_LANE_ERROR
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR(c.Struct):
|
|
SIZE = 56
|
|
errorLane: Annotated[c.Array[NV2080_CTRL_NVLINK_LANE_ERROR, Literal[4]], 0]
|
|
eccDecFailed: Annotated[NvU32, 48]
|
|
eccDecFailedOverflowed: Annotated[NvBool, 52]
|
|
NV2080_CTRL_NVLINK_LINK_ECC_ERROR: TypeAlias = struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS(c.Struct):
|
|
SIZE = 3588
|
|
linkMask: Annotated[NvU32, 0]
|
|
errorLink: Annotated[c.Array[NV2080_CTRL_NVLINK_LINK_ECC_ERROR, Literal[64]], 4]
|
|
NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES(c.Struct):
|
|
SIZE = 32
|
|
value: Annotated[c.Array[NvU64, Literal[4]], 0]
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES: TypeAlias = struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 2064
|
|
counterMask: Annotated[NvU16, 0]
|
|
linkMask: Annotated[NvU64, 8]
|
|
counters: Annotated[c.Array[NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES, Literal[64]], 16]
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bLockPowerMode: Annotated[NvBool, 0]
|
|
NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
linkId: Annotated[NvU32, 0]
|
|
counterValidMask: Annotated[NvU32, 4]
|
|
counterValues: Annotated[c.Array[NvU32, Literal[16]], 8]
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkId: Annotated[NvU32, 0]
|
|
loopbackMode: Annotated[NvU8, 4]
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO(c.Struct):
|
|
SIZE = 6
|
|
bValid: Annotated[NvBool, 0]
|
|
passCount: Annotated[NvU16, 2]
|
|
failCount: Annotated[NvU16, 4]
|
|
NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO: TypeAlias = struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 196
|
|
linkMask: Annotated[NvU32, 0]
|
|
refreshCount: Annotated[c.Array[NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO, Literal[32]], 4]
|
|
NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
linkMask: Annotated[NvU32, 0]
|
|
NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
bGet: Annotated[NvBool, 0]
|
|
addr: Annotated[NvU64, 8]
|
|
NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
discoveredLinks: Annotated[NvU64, 0]
|
|
connectedLinksMask: Annotated[NvU32, 8]
|
|
bridgeSensableLinks: Annotated[NvU64, 16]
|
|
bridgedLinks: Annotated[NvU32, 24]
|
|
initDisabledLinksMask: Annotated[NvU32, 28]
|
|
vbiosDisabledLinkMask: Annotated[NvU64, 32]
|
|
initializedLinks: Annotated[NvU32, 40]
|
|
bEnableTrainingAtLoad: Annotated[NvBool, 44]
|
|
bEnableSafeModeAtLoad: Annotated[NvBool, 45]
|
|
NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
initDisabledLinksMask: Annotated[NvU32, 0]
|
|
bSkipHwNvlinkDisable: Annotated[NvBool, 4]
|
|
NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS
|
|
class enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NVLINK_EOM_CONTROL_START_EOM = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND.define('NVLINK_EOM_CONTROL_START_EOM', 0)
|
|
NVLINK_EOM_CONTROL_END_EOM = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND.define('NVLINK_EOM_CONTROL_END_EOM', 1)
|
|
NVLINK_EOM_CONTROL_CONFIG_EOM = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND.define('NVLINK_EOM_CONTROL_CONFIG_EOM', 2)
|
|
NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND.define('NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE', 3)
|
|
|
|
NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND: TypeAlias = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT(c.Struct):
|
|
SIZE = 4
|
|
upper: Annotated[NvU8, 0]
|
|
middle: Annotated[NvU8, 1]
|
|
lower: Annotated[NvU8, 2]
|
|
composite: Annotated[NvU8, 3]
|
|
NV2080_CTRL_NVLINK_EOM_MEASUREMENT: TypeAlias = struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 28
|
|
cmd: Annotated[NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND, 0]
|
|
linkId: Annotated[NvU32, 4]
|
|
params: Annotated[NvU32, 8]
|
|
measurements: Annotated[c.Array[NV2080_CTRL_NVLINK_EOM_MEASUREMENT, Literal[4]], 12]
|
|
NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS(c.Struct):
|
|
SIZE = 5124
|
|
data: Annotated[c.Array[NvU8, Literal[5120]], 0]
|
|
dataSize: Annotated[NvU32, 5120]
|
|
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
l1Threshold: Annotated[NvU32, 0]
|
|
l1ExitThreshold: Annotated[NvU32, 4]
|
|
NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
l1Threshold: Annotated[NvU32, 0]
|
|
l1ExitThreshold: Annotated[NvU32, 4]
|
|
NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS(c.Struct):
|
|
SIZE = 5124
|
|
buffer: Annotated[c.Array[NvU8, Literal[5120]], 0]
|
|
dataSize: Annotated[NvU32, 5120]
|
|
NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkId: Annotated[NvU32, 0]
|
|
bIsGpuDegraded: Annotated[NvBool, 4]
|
|
NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
bIsEnoughNvLink: Annotated[NvBool, 0]
|
|
numBridge: Annotated[NvU32, 4]
|
|
bridgePresenceMask: Annotated[NvU32, 8]
|
|
NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
linkId: Annotated[NvU32, 0]
|
|
NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PORT_EVENT(c.Struct):
|
|
SIZE = 24
|
|
portEventType: Annotated[NvU32, 0]
|
|
gpuId: Annotated[NvU32, 4]
|
|
linkId: Annotated[NvU32, 8]
|
|
time: Annotated[NvU64, 16]
|
|
NV2080_CTRL_NVLINK_PORT_EVENT: TypeAlias = struct_NV2080_CTRL_NVLINK_PORT_EVENT
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS(c.Struct):
|
|
SIZE = 1560
|
|
portEventIndex: Annotated[NvU64, 0]
|
|
nextPortEventIndex: Annotated[NvU64, 8]
|
|
portEventCount: Annotated[NvU32, 16]
|
|
bOverflow: Annotated[NvBool, 20]
|
|
portEvent: Annotated[c.Array[NV2080_CTRL_NVLINK_PORT_EVENT, Literal[64]], 24]
|
|
NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
linkId: Annotated[NvU32, 0]
|
|
NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bReducedNvlinkConfig: Annotated[NvBool, 0]
|
|
NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_DATA(c.Struct):
|
|
SIZE = 496
|
|
data: Annotated[c.Array[NvU8, Literal[496]], 0]
|
|
NV2080_CTRL_NVLINK_PRM_DATA: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_DATA
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS(c.Struct):
|
|
SIZE = 510
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
plane_ind: Annotated[NvU8, 497]
|
|
admin_status: Annotated[NvU8, 498]
|
|
lp_msb: Annotated[NvU8, 499]
|
|
local_port: Annotated[NvU8, 500]
|
|
swid: Annotated[NvU8, 501]
|
|
e: Annotated[NvU8, 502]
|
|
fd: Annotated[NvU8, 503]
|
|
ps_e: Annotated[NvU8, 504]
|
|
ls_e: Annotated[NvU8, 505]
|
|
ee_ps: Annotated[NvU8, 506]
|
|
ee_ls: Annotated[NvU8, 507]
|
|
ee: Annotated[NvU8, 508]
|
|
ase: Annotated[NvU8, 509]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS(c.Struct):
|
|
SIZE = 503
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
lane_mask: Annotated[NvU8, 497]
|
|
lp_msb: Annotated[NvU8, 498]
|
|
pnat: Annotated[NvU8, 499]
|
|
local_port: Annotated[NvU8, 500]
|
|
local_tx_precoding_admin: Annotated[NvU8, 501]
|
|
local_rx_precoding_admin: Annotated[NvU8, 502]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS(c.Struct):
|
|
SIZE = 526
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
test_mode: Annotated[NvBool, 497]
|
|
plane_ind: Annotated[NvU8, 498]
|
|
port_type: Annotated[NvU8, 499]
|
|
lp_msb: Annotated[NvU8, 500]
|
|
pnat: Annotated[NvU8, 501]
|
|
local_port: Annotated[NvU8, 502]
|
|
fec_override_admin_10g_40g: Annotated[NvU8, 503]
|
|
fec_override_admin_25g: Annotated[NvU8, 504]
|
|
fec_override_admin_50g: Annotated[NvU8, 505]
|
|
fec_override_admin_100g: Annotated[NvU8, 506]
|
|
fec_override_admin_56g: Annotated[NvU8, 507]
|
|
rs_fec_correction_bypass_admin: Annotated[NvU8, 508]
|
|
fec_override_admin_200g_4x: Annotated[NvU16, 510]
|
|
fec_override_admin_400g_8x: Annotated[NvU16, 512]
|
|
fec_override_admin_50g_1x: Annotated[NvU16, 514]
|
|
fec_override_admin_100g_2x: Annotated[NvU16, 516]
|
|
fec_override_admin_400g_4x: Annotated[NvU16, 518]
|
|
fec_override_admin_800g_8x: Annotated[NvU16, 520]
|
|
fec_override_admin_100g_1x: Annotated[NvU16, 522]
|
|
fec_override_admin_200g_2x: Annotated[NvU16, 524]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS(c.Struct):
|
|
SIZE = 520
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
lp_msb: Annotated[NvU8, 497]
|
|
local_port: Annotated[NvU8, 498]
|
|
l1_req_en: Annotated[NvBool, 499]
|
|
l1_fw_req_en: Annotated[NvBool, 500]
|
|
l1_cap_adv: Annotated[NvBool, 501]
|
|
l1_fw_cap_adv: Annotated[NvBool, 502]
|
|
hp_queues_bitmap: Annotated[NvU32, 504]
|
|
l1_hw_active_time: Annotated[NvU16, 508]
|
|
l1_hw_inactive_time: Annotated[NvU16, 510]
|
|
qem: Annotated[c.Array[NvU8, Literal[8]], 512]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS(c.Struct):
|
|
SIZE = 499
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
access_reg_group: Annotated[NvU8, 497]
|
|
feature_group: Annotated[NvU8, 498]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS(c.Struct):
|
|
SIZE = 498
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
slot_index: Annotated[NvU8, 497]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS(c.Struct):
|
|
SIZE = 498
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
slot_index: Annotated[NvU8, 497]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS(c.Struct):
|
|
SIZE = 498
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
slot_index: Annotated[NvU8, 497]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS(c.Struct):
|
|
SIZE = 498
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
slot_index: Annotated[NvU8, 497]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS(c.Struct):
|
|
SIZE = 504
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
itre: Annotated[NvBool, 497]
|
|
i_e: Annotated[NvU8, 498]
|
|
lp_msb: Annotated[NvU8, 499]
|
|
local_port: Annotated[NvU8, 500]
|
|
protocol: Annotated[NvU8, 501]
|
|
admin_mtu: Annotated[NvU16, 502]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS(c.Struct):
|
|
SIZE = 503
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
width: Annotated[NvU8, 497]
|
|
plane_ind: Annotated[NvU8, 498]
|
|
lp_msb: Annotated[NvU8, 499]
|
|
local_port: Annotated[NvU8, 500]
|
|
m_lane_m: Annotated[NvBool, 501]
|
|
rxtx: Annotated[NvBool, 502]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS(c.Struct):
|
|
SIZE = 502
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
trap_id: Annotated[NvU16, 498]
|
|
action: Annotated[NvU8, 500]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS(c.Struct):
|
|
SIZE = 504
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
port_type: Annotated[NvU8, 497]
|
|
plane_ind: Annotated[NvU8, 498]
|
|
lp_msb: Annotated[NvU8, 499]
|
|
pnat: Annotated[NvU8, 500]
|
|
local_port: Annotated[NvU8, 501]
|
|
page_select: Annotated[NvU8, 502]
|
|
module_info_ext: Annotated[NvU8, 503]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS(c.Struct):
|
|
SIZE = 512
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
le: Annotated[NvBool, 497]
|
|
port_type: Annotated[NvU8, 498]
|
|
lane: Annotated[NvU8, 499]
|
|
lp_msb: Annotated[NvU8, 500]
|
|
pnat: Annotated[NvU8, 501]
|
|
local_port: Annotated[NvU8, 502]
|
|
sw: Annotated[NvBool, 503]
|
|
dm_ig: Annotated[NvBool, 504]
|
|
p: Annotated[NvBool, 505]
|
|
e: Annotated[NvBool, 506]
|
|
modulation: Annotated[NvU8, 507]
|
|
prbs_mode_admin: Annotated[NvU8, 508]
|
|
prbs_fec_admin: Annotated[NvBool, 509]
|
|
lane_rate_admin: Annotated[NvU16, 510]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS(c.Struct):
|
|
SIZE = 509
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
grp: Annotated[NvU8, 497]
|
|
port_type: Annotated[NvU8, 498]
|
|
lp_msb: Annotated[NvU8, 499]
|
|
pnat: Annotated[NvU8, 500]
|
|
local_port: Annotated[NvU8, 501]
|
|
swid: Annotated[NvU8, 502]
|
|
prio_tc: Annotated[NvU8, 503]
|
|
grp_profile: Annotated[NvU8, 504]
|
|
plane_ind: Annotated[NvU8, 505]
|
|
counters_cap: Annotated[NvBool, 506]
|
|
lp_gl: Annotated[NvBool, 507]
|
|
clr: Annotated[NvBool, 508]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS(c.Struct):
|
|
SIZE = 497
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS(c.Struct):
|
|
SIZE = 504
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
port_type: Annotated[NvU8, 497]
|
|
phy_test_mode_admin: Annotated[NvU8, 498]
|
|
lp_msb: Annotated[NvU8, 499]
|
|
local_port: Annotated[NvU8, 500]
|
|
swid: Annotated[NvU8, 501]
|
|
plane_ind: Annotated[NvU8, 502]
|
|
phy_status_admin: Annotated[NvU8, 503]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS(c.Struct):
|
|
SIZE = 503
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
plane_ind: Annotated[NvU8, 497]
|
|
port_type: Annotated[NvU8, 498]
|
|
lp_msb: Annotated[NvU8, 499]
|
|
pnat: Annotated[NvU8, 500]
|
|
local_port: Annotated[NvU8, 501]
|
|
hist_type: Annotated[NvU8, 502]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS(c.Struct):
|
|
SIZE = 505
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
c_db: Annotated[NvBool, 497]
|
|
port_type: Annotated[NvU8, 498]
|
|
lane_speed: Annotated[NvU8, 499]
|
|
lane: Annotated[NvU8, 500]
|
|
tx_policy: Annotated[NvBool, 501]
|
|
pnat: Annotated[NvU8, 502]
|
|
local_port: Annotated[NvU8, 503]
|
|
lp_msb: Annotated[NvU8, 504]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS(c.Struct):
|
|
SIZE = 500
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
lp_msb: Annotated[NvU8, 497]
|
|
pnat: Annotated[NvU8, 498]
|
|
local_port: Annotated[NvU8, 499]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS(c.Struct):
|
|
SIZE = 512
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
le: Annotated[NvBool, 497]
|
|
port_type: Annotated[NvU8, 498]
|
|
lane: Annotated[NvU8, 499]
|
|
lp_msb: Annotated[NvU8, 500]
|
|
pnat: Annotated[NvU8, 501]
|
|
local_port: Annotated[NvU8, 502]
|
|
sw: Annotated[NvBool, 503]
|
|
dm_ig: Annotated[NvBool, 504]
|
|
p: Annotated[NvBool, 505]
|
|
s: Annotated[NvBool, 506]
|
|
e: Annotated[NvBool, 507]
|
|
modulation: Annotated[NvU8, 508]
|
|
prbs_mode_admin: Annotated[NvU8, 509]
|
|
lane_rate_oper: Annotated[NvU16, 510]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS(c.Struct):
|
|
SIZE = 524
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
proto_mask: Annotated[NvU8, 497]
|
|
transmit_allowed: Annotated[NvBool, 498]
|
|
plane_ind: Annotated[NvU8, 499]
|
|
port_type: Annotated[NvU8, 500]
|
|
lp_msb: Annotated[NvU8, 501]
|
|
local_port: Annotated[NvU8, 502]
|
|
tx_ready_e: Annotated[NvU8, 503]
|
|
ee_tx_ready: Annotated[NvBool, 504]
|
|
an_disable_admin: Annotated[NvBool, 505]
|
|
ext_eth_proto_admin: Annotated[NvU32, 508]
|
|
eth_proto_admin: Annotated[NvU32, 512]
|
|
ib_proto_admin: Annotated[NvU16, 516]
|
|
ib_link_width_admin: Annotated[NvU16, 518]
|
|
xdr_2x_slow_admin: Annotated[NvBool, 520]
|
|
force_lt_frames_admin: Annotated[NvU8, 521]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS(c.Struct):
|
|
SIZE = 502
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
port_type: Annotated[NvU8, 497]
|
|
lane: Annotated[NvU8, 498]
|
|
lp_msb: Annotated[NvU8, 499]
|
|
pnat: Annotated[NvU8, 500]
|
|
local_port: Annotated[NvU8, 501]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS(c.Struct):
|
|
SIZE = 504
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
admin_status: Annotated[NvU8, 497]
|
|
module: Annotated[NvU8, 498]
|
|
slot_index: Annotated[NvU8, 499]
|
|
rst: Annotated[NvBool, 500]
|
|
e: Annotated[NvU8, 501]
|
|
ee: Annotated[NvBool, 502]
|
|
ase: Annotated[NvBool, 503]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS(c.Struct):
|
|
SIZE = 506
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
plane_ind: Annotated[NvU8, 497]
|
|
port_type: Annotated[NvU8, 498]
|
|
op_mod: Annotated[NvBool, 499]
|
|
apply_im: Annotated[NvBool, 500]
|
|
lp_msb: Annotated[NvU8, 501]
|
|
local_port: Annotated[NvU8, 502]
|
|
lb_en: Annotated[NvU16, 504]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
counterMask: Annotated[c.Array[NvU64, Literal[2]], 0]
|
|
NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS(c.Struct):
|
|
SIZE = 544
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
segment_type: Annotated[NvU16, 498]
|
|
seq_num: Annotated[NvU8, 500]
|
|
vhca_id_valid: Annotated[NvBool, 501]
|
|
inline_dump: Annotated[NvBool, 502]
|
|
vhca_id: Annotated[NvU16, 504]
|
|
index1: Annotated[NvU32, 508]
|
|
index2: Annotated[NvU32, 512]
|
|
num_of_obj2: Annotated[NvU16, 516]
|
|
num_of_obj1: Annotated[NvU16, 518]
|
|
device_opaque: Annotated[NvU64, 520]
|
|
mkey: Annotated[NvU32, 528]
|
|
address: Annotated[NvU64, 536]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS(c.Struct):
|
|
SIZE = 498
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
trace_owner: Annotated[NvBool, 497]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS(c.Struct):
|
|
SIZE = 500
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
trace_mode: Annotated[NvU8, 497]
|
|
log_trace_buffer_size: Annotated[NvU8, 498]
|
|
trace_mkey: Annotated[NvU8, 499]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS(c.Struct):
|
|
SIZE = 502
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
modify_field_select: Annotated[NvU16, 498]
|
|
arm_event: Annotated[NvBool, 500]
|
|
trace_status: Annotated[NvU8, 501]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS(c.Struct):
|
|
SIZE = 497
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS(c.Struct):
|
|
SIZE = 532
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
enable_all: Annotated[NvU8, 497]
|
|
log_delay: Annotated[NvU8, 498]
|
|
source_id_bitmask: Annotated[c.Array[NvU32, Literal[8]], 500]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS(c.Struct):
|
|
SIZE = 504
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
log_level: Annotated[NvU8, 497]
|
|
log_bit_mask: Annotated[NvU32, 500]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS(c.Struct):
|
|
SIZE = 502
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
warning_inactive_time: Annotated[NvU8, 497]
|
|
warning_active_time: Annotated[NvU8, 498]
|
|
critical_inactive_time: Annotated[NvU8, 499]
|
|
critical_active_time: Annotated[NvU8, 500]
|
|
cc: Annotated[NvBool, 501]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS(c.Struct):
|
|
SIZE = 497
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS(c.Struct):
|
|
SIZE = 499
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
lp_msb: Annotated[NvU8, 497]
|
|
local_port: Annotated[NvU8, 498]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS(c.Struct):
|
|
SIZE = 520
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
lp_msb: Annotated[NvU8, 497]
|
|
local_port: Annotated[NvU8, 498]
|
|
cnt_64bit: Annotated[NvU8, 499]
|
|
stop_at_ff: Annotated[NvBool, 500]
|
|
counter_rst: Annotated[NvBool, 501]
|
|
counter_en: Annotated[NvBool, 502]
|
|
force_count_mask: Annotated[NvU8, 503]
|
|
cnt_type: Annotated[c.Array[NvU8, Literal[8]], 504]
|
|
cnt_val: Annotated[c.Array[NvU8, Literal[8]], 512]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS(c.Struct):
|
|
SIZE = 504
|
|
bWrite: Annotated[NvBool, 0]
|
|
prm: Annotated[NV2080_CTRL_NVLINK_PRM_DATA, 1]
|
|
ib_port: Annotated[NvU16, 498]
|
|
lp_msb: Annotated[NvU8, 500]
|
|
local_port: Annotated[NvU8, 501]
|
|
split_num: Annotated[NvU8, 502]
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS(c.Struct):
|
|
SIZE = 37
|
|
ibGuid: Annotated[c.Array[NvU8, Literal[16]], 0]
|
|
rackGuid: Annotated[c.Array[NvU8, Literal[16]], 16]
|
|
chassisPhysicalSlotNumber: Annotated[NvU8, 32]
|
|
computeSlotIndex: Annotated[NvU8, 33]
|
|
nodeIndex: Annotated[NvU8, 34]
|
|
peerType: Annotated[NvU8, 35]
|
|
moduleId: Annotated[NvU8, 36]
|
|
NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD(c.Struct):
|
|
SIZE = 4
|
|
pllIndex: Annotated[NvU8, 0]
|
|
address: Annotated[NvU16, 2]
|
|
NV2080_CTRL_NVLINK_UPHY_CLN_CMD: TypeAlias = struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS(c.Struct):
|
|
SIZE = 148
|
|
linkMask: Annotated[NvU32, 0]
|
|
uphyCmd: Annotated[c.Array[NV2080_CTRL_NVLINK_UPHY_CLN_CMD, Literal[18]], 4]
|
|
data: Annotated[c.Array[NvU32, Literal[18]], 76]
|
|
NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
rbmModesList: Annotated[c.Array[NvU8, Literal[23]], 0]
|
|
rbmTotalModes: Annotated[NvU8, 23]
|
|
NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
rbmMode: Annotated[NvU8, 0]
|
|
NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
rbmMode: Annotated[NvU8, 0]
|
|
NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
localDeviceInfo: Annotated[NV2080_CTRL_NVLINK_DEVICE_INFO, 0]
|
|
NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS
|
|
class enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL', 0)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL', 1)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL', 2)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION', 3)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT', 4)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL', 5)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE', 6)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL', 7)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL', 8)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR', 9)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL', 10)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL', 11)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL', 12)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL', 13)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL', 14)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL', 15)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL', 16)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL', 17)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL', 18)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL', 19)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL', 20)
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX', 21)
|
|
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY: TypeAlias = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
linkMask: Annotated[NvU32, 0]
|
|
severity: Annotated[NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY, 4]
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS
|
|
class enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED', 0)
|
|
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE', 1)
|
|
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED', 2)
|
|
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED', 3)
|
|
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE', 4)
|
|
|
|
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE: TypeAlias = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG(c.Struct):
|
|
SIZE = 8
|
|
mode: Annotated[NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE, 0]
|
|
toggleActiveTime: Annotated[NvU8, 4]
|
|
toggleInactiveTime: Annotated[NvU8, 5]
|
|
bTrigger: Annotated[NvBool, 6]
|
|
NV2080_CTRL_NVLINK_L1_FORCE_CONFIG: TypeAlias = struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
linkMask: Annotated[NvU32, 0]
|
|
config: Annotated[NV2080_CTRL_NVLINK_L1_FORCE_CONFIG, 4]
|
|
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS(c.Struct):
|
|
SIZE = 260
|
|
linkMask: Annotated[NvU32, 0]
|
|
config: Annotated[c.Array[NV2080_CTRL_NVLINK_L1_FORCE_CONFIG, Literal[32]], 4]
|
|
NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS: TypeAlias = struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_BOOST_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
flags: Annotated[NvU32, 0]
|
|
duration: Annotated[NvU32, 4]
|
|
NV2080_CTRL_PERF_BOOST_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_BOOST_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bAcquire: Annotated[NvBool, 0]
|
|
NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
powerState: Annotated[NvU32, 0]
|
|
NV2080_CTRL_PERF_POWERSTATE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
powerStateInfo: Annotated[NV2080_CTRL_PERF_POWERSTATE_PARAMS, 0]
|
|
NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
powerState: Annotated[NvU32, 0]
|
|
NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS
|
|
class enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM', 0)
|
|
NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342', 1)
|
|
NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL', 2)
|
|
NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS', 3)
|
|
NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE', 4)
|
|
NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS', 5)
|
|
|
|
NV2080_CTRL_PERF_RATED_TDP_CLIENT: TypeAlias = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT
|
|
class enum_NV2080_CTRL_PERF_RATED_TDP_ACTION(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT', 0)
|
|
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED', 1)
|
|
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT', 2)
|
|
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK', 3)
|
|
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR', 4)
|
|
|
|
NV2080_CTRL_PERF_RATED_TDP_ACTION: TypeAlias = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION
|
|
class enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_PERF_VPSTATE_RATED_TDP = enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE.define('NV2080_CTRL_PERF_VPSTATE_RATED_TDP', 0)
|
|
NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST = enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE.define('NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST', 1)
|
|
NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES = enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE.define('NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES', 2)
|
|
|
|
NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE: TypeAlias = enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST(c.Struct):
|
|
SIZE = 8
|
|
action: Annotated[NV2080_CTRL_PERF_RATED_TDP_ACTION, 0]
|
|
vPstateType: Annotated[NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE, 4]
|
|
NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST: TypeAlias = struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
rm: Annotated[struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm, 0]
|
|
output: Annotated[NV2080_CTRL_PERF_RATED_TDP_ACTION, 8]
|
|
outputVPstate: Annotated[NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE, 12]
|
|
inputs: Annotated[c.Array[NV2080_CTRL_PERF_RATED_TDP_ACTION, Literal[5]], 16]
|
|
vPstateTypes: Annotated[c.Array[NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE, Literal[5]], 36]
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm(c.Struct):
|
|
SIZE = 8
|
|
clientActiveMask: Annotated[NvU32, 0]
|
|
bRegkeyLimitRatedTdp: Annotated[NvU8, 4]
|
|
NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
client: Annotated[NV2080_CTRL_PERF_RATED_TDP_CLIENT, 0]
|
|
input: Annotated[NV2080_CTRL_PERF_RATED_TDP_ACTION, 4]
|
|
vPstateType: Annotated[NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE, 8]
|
|
NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS
|
|
NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS
|
|
NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE(c.Struct):
|
|
SIZE = 128
|
|
util: Annotated[NvU32, 0]
|
|
vgpuScale: Annotated[NvU32, 4]
|
|
procId: Annotated[NvU32, 8]
|
|
subProcessID: Annotated[NvU32, 12]
|
|
subProcessName: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[100]], 16]
|
|
pOsPidInfo: Annotated[NvU64, 120]
|
|
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE: TypeAlias = struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE(c.Struct):
|
|
SIZE = 776
|
|
base: Annotated[NV2080_CTRL_GPUMON_SAMPLE, 0]
|
|
fb: Annotated[NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE, 8]
|
|
gr: Annotated[NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE, 136]
|
|
nvenc: Annotated[NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE, 264]
|
|
nvdec: Annotated[NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE, 392]
|
|
nvjpg: Annotated[NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE, 520]
|
|
nvofa: Annotated[NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE, 648]
|
|
NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE: TypeAlias = struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE
|
|
NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM: TypeAlias = struct_NV2080_CTRL_GPUMON_SAMPLES
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS(c.Struct):
|
|
SIZE = 55888
|
|
type: Annotated[NvU8, 0]
|
|
bufSize: Annotated[NvU32, 4]
|
|
count: Annotated[NvU32, 8]
|
|
tracker: Annotated[NvU32, 12]
|
|
samples: Annotated[c.Array[NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE, Literal[72]], 16]
|
|
NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
prevPstate: Annotated[NvU32, 0]
|
|
action: Annotated[NvU32, 4]
|
|
NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
bGpuIsIdle: Annotated[NvBool, 0]
|
|
bRestoreToMax: Annotated[NvBool, 1]
|
|
idleTimeUs: Annotated[NvU64, 8]
|
|
busyTimeUs: Annotated[NvU64, 16]
|
|
NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_CLK_INFO(c.Struct):
|
|
SIZE = 24
|
|
flags: Annotated[NvU32, 0]
|
|
domain: Annotated[NvU32, 4]
|
|
currentFreq: Annotated[NvU32, 8]
|
|
defaultFreq: Annotated[NvU32, 12]
|
|
minFreq: Annotated[NvU32, 16]
|
|
maxFreq: Annotated[NvU32, 20]
|
|
NV2080_CTRL_PERF_GET_CLK_INFO: TypeAlias = struct_NV2080_CTRL_PERF_GET_CLK_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
level: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
perfGetClkInfoList: Annotated[NvP64, 8]
|
|
perfGetClkInfoListSize: Annotated[NvU32, 16]
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS(c.Struct):
|
|
SIZE = 780
|
|
level: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
perfGetClkInfoList: Annotated[c.Array[NV2080_CTRL_PERF_GET_CLK_INFO, Literal[32]], 8]
|
|
perfGetClkInfoListSize: Annotated[NvU32, 776]
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS
|
|
class enum_NV2080_CTRL_CMD_PERF_VID_ENG(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVENC', 1)
|
|
NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC', 2)
|
|
NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG', 3)
|
|
NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA', 4)
|
|
|
|
NV2080_CTRL_CMD_PERF_VID_ENG: TypeAlias = enum_NV2080_CTRL_CMD_PERF_VID_ENG
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
engineType: Annotated[NV2080_CTRL_CMD_PERF_VID_ENG, 0]
|
|
clkPercentBusy: Annotated[NvU32, 4]
|
|
samplingPeriodUs: Annotated[NvU32, 8]
|
|
NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
powerStateInfo: Annotated[NV2080_CTRL_PERF_POWERSTATE_PARAMS, 0]
|
|
NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
videoEvent: Annotated[NvU32, 0]
|
|
NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS
|
|
NV2080_CTRL_PERF_PSTATES_ID: TypeAlias = Annotated[int, ctypes.c_uint32]
|
|
@c.record
|
|
class struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
currPstate: Annotated[NvU32, 0]
|
|
NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS: TypeAlias = struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
moduleId: Annotated[NvU32, 0]
|
|
nvswitchSupport: Annotated[NvU8, 4]
|
|
NV2080_CTRL_PMGR_MODULE_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS
|
|
class enum_NV2080_CTRL_GC6_FLAVOR_ID(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID = enum_NV2080_CTRL_GC6_FLAVOR_ID.define('NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID', 0)
|
|
NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS = enum_NV2080_CTRL_GC6_FLAVOR_ID.define('NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS', 1)
|
|
NV2080_CTRL_GC6_FLAVOR_ID_MAX = enum_NV2080_CTRL_GC6_FLAVOR_ID.define('NV2080_CTRL_GC6_FLAVOR_ID_MAX', 4)
|
|
|
|
NV2080_CTRL_GC6_FLAVOR_ID: TypeAlias = enum_NV2080_CTRL_GC6_FLAVOR_ID
|
|
@c.record
|
|
class struct_NV2080_CTRL_GC6_ENTRY_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
flavorId: Annotated[NV2080_CTRL_GC6_FLAVOR_ID, 0]
|
|
stepMask: Annotated[NvU32, 4]
|
|
params: Annotated[struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params, 8]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params(c.Struct):
|
|
SIZE = 3
|
|
bIsRTD3Transition: Annotated[NvBool, 0]
|
|
bIsRTD3CoreRailPowerCut: Annotated[NvBool, 1]
|
|
bSkipPstateSanity: Annotated[NvBool, 2]
|
|
NV2080_CTRL_GC6_ENTRY_PARAMS: TypeAlias = struct_NV2080_CTRL_GC6_ENTRY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_GC6_EXIT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
flavorId: Annotated[NV2080_CTRL_GC6_FLAVOR_ID, 0]
|
|
params: Annotated[struct_NV2080_CTRL_GC6_EXIT_PARAMS_params, 4]
|
|
@c.record
|
|
class struct_NV2080_CTRL_GC6_EXIT_PARAMS_params(c.Struct):
|
|
SIZE = 3
|
|
bIsGpuSelfWake: Annotated[NvBool, 0]
|
|
bIsRTD3Transition: Annotated[NvBool, 1]
|
|
bIsRTD3HotTransition: Annotated[NvBool, 2]
|
|
NV2080_CTRL_GC6_EXIT_PARAMS: TypeAlias = struct_NV2080_CTRL_GC6_EXIT_PARAMS
|
|
class enum_NV2080_CTRL_GC6_STEP_ID(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV2080_CTRL_GC6_STEP_ID_SR_ENTRY = enum_NV2080_CTRL_GC6_STEP_ID.define('NV2080_CTRL_GC6_STEP_ID_SR_ENTRY', 0)
|
|
NV2080_CTRL_GC6_STEP_ID_GPU_OFF = enum_NV2080_CTRL_GC6_STEP_ID.define('NV2080_CTRL_GC6_STEP_ID_GPU_OFF', 1)
|
|
NV2080_CTRL_GC6_STEP_ID_MAX = enum_NV2080_CTRL_GC6_STEP_ID.define('NV2080_CTRL_GC6_STEP_ID_MAX', 2)
|
|
|
|
NV2080_CTRL_GC6_STEP_ID: TypeAlias = enum_NV2080_CTRL_GC6_STEP_ID
|
|
@c.record
|
|
class struct_NV2080_CTRL_GC6_FLAVOR_INFO(c.Struct):
|
|
SIZE = 8
|
|
flavorId: Annotated[NV2080_CTRL_GC6_FLAVOR_ID, 0]
|
|
stepMask: Annotated[NvU32, 4]
|
|
NV2080_CTRL_GC6_FLAVOR_INFO: TypeAlias = struct_NV2080_CTRL_GC6_FLAVOR_INFO
|
|
@c.record
|
|
class struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(c.Struct):
|
|
SIZE = 32
|
|
hChannel: Annotated[NvHandle, 0]
|
|
virtAddress: Annotated[NvU64, 8]
|
|
bufferPtr: Annotated[NvP64, 16]
|
|
bufferSize: Annotated[NvU32, 24]
|
|
NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS: TypeAlias = struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
errorCount: Annotated[NvU32, 0]
|
|
NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS: TypeAlias = struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS(c.Struct):
|
|
SIZE = 8200
|
|
whichBuffer: Annotated[NvU32, 0]
|
|
outputRecordSize: Annotated[NvU32, 4]
|
|
recordBuffer: Annotated[c.Array[NvU8, Literal[8192]], 8]
|
|
NV2080_CTRL_RC_GET_ERROR_V2_PARAMS: TypeAlias = struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
watchdogStatusFlags: Annotated[NvU32, 0]
|
|
NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
rcEnable: Annotated[NvU32, 0]
|
|
NV2080_CTRL_CMD_RC_RECOVERY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS
|
|
NV2080_CTRL_SET_RC_RECOVERY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS
|
|
NV2080_CTRL_GET_RC_RECOVERY_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
cmd: Annotated[NvU32, 0]
|
|
status: Annotated[NvS32, 4]
|
|
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS: TypeAlias = struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_RC_INFO_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
rcMode: Annotated[NvU32, 0]
|
|
rcBreak: Annotated[NvU32, 4]
|
|
NV2080_CTRL_CMD_RC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS
|
|
NV2080_CTRL_SET_RC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS
|
|
NV2080_CTRL_GET_RC_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_CMD_CC_INIT(c.Struct):
|
|
SIZE = 1
|
|
cmdType: Annotated[NvU8, 0]
|
|
RM_GSP_SPDM_CMD_CC_INIT: TypeAlias = struct_RM_GSP_SPDM_CMD_CC_INIT
|
|
PRM_GSP_SPDM_CMD_CC_INIT: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_CMD_CC_INIT]
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_CMD_CC_DEINIT(c.Struct):
|
|
SIZE = 1
|
|
cmdType: Annotated[NvU8, 0]
|
|
RM_GSP_SPDM_CMD_CC_DEINIT: TypeAlias = struct_RM_GSP_SPDM_CMD_CC_DEINIT
|
|
PRM_GSP_SPDM_CMD_CC_DEINIT: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_CMD_CC_DEINIT]
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_CMD_CC_CTRL(c.Struct):
|
|
SIZE = 1
|
|
cmdType: Annotated[NvU8, 0]
|
|
RM_GSP_SPDM_CMD_CC_CTRL: TypeAlias = struct_RM_GSP_SPDM_CMD_CC_CTRL
|
|
PRM_GSP_SPDM_CMD_CC_CTRL: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_CMD_CC_CTRL]
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA(c.Struct):
|
|
SIZE = 68
|
|
cmdType: Annotated[NvU8, 0]
|
|
rsvd0: Annotated[c.Array[NvU32, Literal[2]], 4]
|
|
rsvd1: Annotated[NvU32, 12]
|
|
rsvd2: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[9]], 16]
|
|
rsvd3: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[5]], 25]
|
|
rsvd4: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[5]], 30]
|
|
rsvd5: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[5]], 35]
|
|
rsvd6: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[2]], 40]
|
|
rsvd7: Annotated[c.Array[Annotated[bytes, ctypes.c_char], Literal[16]], 42]
|
|
rsvd8: Annotated[c.Array[NvU32, Literal[2]], 60]
|
|
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA: TypeAlias = struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA
|
|
PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA]
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL(c.Struct):
|
|
SIZE = 2
|
|
cmdType: Annotated[NvU8, 0]
|
|
bEnable: Annotated[NvBool, 1]
|
|
RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL: TypeAlias = struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL
|
|
PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL]
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST(c.Struct):
|
|
SIZE = 160
|
|
cmdType: Annotated[NvU8, 0]
|
|
isEnc: Annotated[NvU8, 1]
|
|
kmb: Annotated[CC_KMB, 4]
|
|
text: Annotated[c.Array[NvU8, Literal[16]], 128]
|
|
authTag: Annotated[c.Array[NvU8, Literal[16]], 144]
|
|
@c.record
|
|
class struct_CC_KMB(c.Struct):
|
|
SIZE = 124
|
|
encryptBundle: Annotated[CC_AES_CRYPTOBUNDLE, 0]
|
|
hmacBundle: Annotated[CC_HMAC_CRYPTOBUNDLE, 56]
|
|
decryptBundle: Annotated[CC_AES_CRYPTOBUNDLE, 56]
|
|
bIsWorkLaunch: Annotated[NvBool, 120]
|
|
CC_KMB: TypeAlias = struct_CC_KMB
|
|
@c.record
|
|
class struct_CC_AES_CRYPTOBUNDLE(c.Struct):
|
|
SIZE = 56
|
|
iv: Annotated[c.Array[NvU32, Literal[3]], 0]
|
|
key: Annotated[c.Array[NvU32, Literal[8]], 12]
|
|
ivMask: Annotated[c.Array[NvU32, Literal[3]], 44]
|
|
CC_AES_CRYPTOBUNDLE: TypeAlias = struct_CC_AES_CRYPTOBUNDLE
|
|
@c.record
|
|
class struct_CC_HMAC_CRYPTOBUNDLE(c.Struct):
|
|
SIZE = 64
|
|
nonce: Annotated[c.Array[NvU32, Literal[8]], 0]
|
|
key: Annotated[c.Array[NvU32, Literal[8]], 32]
|
|
CC_HMAC_CRYPTOBUNDLE: TypeAlias = struct_CC_HMAC_CRYPTOBUNDLE
|
|
RM_GSP_SPDM_CMD_FIPS_SELFTEST: TypeAlias = struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST
|
|
PRM_GSP_SPDM_CMD_FIPS_SELFTEST: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST]
|
|
@c.record
|
|
class union_RM_GSP_SPDM_CMD(c.Struct):
|
|
SIZE = 160
|
|
cmdType: Annotated[NvU8, 0]
|
|
ccInit: Annotated[RM_GSP_SPDM_CMD_CC_INIT, 0]
|
|
ccDeinit: Annotated[RM_GSP_SPDM_CMD_CC_DEINIT, 0]
|
|
ccCtrl: Annotated[RM_GSP_SPDM_CMD_CC_CTRL, 0]
|
|
rmDataInitCmd: Annotated[RM_GSP_SPDM_CMD_CC_INIT_RM_DATA, 0]
|
|
ccHeartbeatCtrl: Annotated[RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL, 0]
|
|
ccFipsTest: Annotated[RM_GSP_SPDM_CMD_FIPS_SELFTEST, 0]
|
|
RM_GSP_SPDM_CMD: TypeAlias = union_RM_GSP_SPDM_CMD
|
|
PRM_GSP_SPDM_CMD: TypeAlias = c.POINTER[union_RM_GSP_SPDM_CMD]
|
|
@c.record
|
|
class struct_RM_GSP_SPDM_MSG(c.Struct):
|
|
SIZE = 28
|
|
msgType: Annotated[NvU8, 0]
|
|
status: Annotated[NvU32, 4]
|
|
rsvd1: Annotated[NvU32, 8]
|
|
rsvd2: Annotated[NvU32, 12]
|
|
rsvd3: Annotated[NvU32, 16]
|
|
rsvd4: Annotated[NvU32, 20]
|
|
rsvd5: Annotated[NvU32, 24]
|
|
RM_GSP_SPDM_MSG: TypeAlias = struct_RM_GSP_SPDM_MSG
|
|
PRM_GSP_SPDM_MSG: TypeAlias = c.POINTER[struct_RM_GSP_SPDM_MSG]
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS(c.Struct):
|
|
SIZE = 192
|
|
index: Annotated[NvU8, 0]
|
|
cmd: Annotated[RM_GSP_SPDM_CMD, 4]
|
|
msg: Annotated[RM_GSP_SPDM_MSG, 164]
|
|
NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS(c.Struct):
|
|
SIZE = 9220
|
|
transcript: Annotated[c.Array[NvU8, Literal[9216]], 0]
|
|
transcriptSize: Annotated[NvU32, 9216]
|
|
NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS: TypeAlias = struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS(c.Struct):
|
|
SIZE = 16
|
|
time_nsec: Annotated[NvU64, 0]
|
|
flags: Annotated[NvU32, 8]
|
|
NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
time_nsec: Annotated[NvU64, 0]
|
|
NV2080_CTRL_TIMER_GET_TIME_PARAMS: TypeAlias = struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
tmr_offset: Annotated[NvU32, 0]
|
|
NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS: TypeAlias = struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE(c.Struct):
|
|
SIZE = 16
|
|
cpuTime: Annotated[NvU64, 0]
|
|
gpuTime: Annotated[NvU64, 8]
|
|
NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE: TypeAlias = struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE
|
|
@c.record
|
|
class struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS(c.Struct):
|
|
SIZE = 264
|
|
cpuClkId: Annotated[NvU8, 0]
|
|
sampleCount: Annotated[NvU8, 1]
|
|
samples: Annotated[c.Array[NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE, Literal[16]], 8]
|
|
NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bSetMaxFreq: Annotated[NvBool, 0]
|
|
NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS: TypeAlias = struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
action: Annotated[NvU32, 0]
|
|
NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS: TypeAlias = struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
action: Annotated[NvU32, 0]
|
|
NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS: TypeAlias = struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bEnter: Annotated[NvBool, 0]
|
|
NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS: TypeAlias = struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hNotifierResource: Annotated[NvHandle, 0]
|
|
notifyDataSize: Annotated[NvU32, 4]
|
|
hNotifyDataMemory: Annotated[NvHandle, 8]
|
|
perfmonIdCount: Annotated[NvU32, 12]
|
|
snapshotBufferSize: Annotated[NvU32, 16]
|
|
hSnapshotMemory: Annotated[NvHandle, 20]
|
|
NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS: TypeAlias = struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bVidmemPersistent: Annotated[NvBool, 0]
|
|
NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bUpdateTGP: Annotated[NvBool, 0]
|
|
NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS(c.Struct):
|
|
SIZE = 6616
|
|
dbdf: Annotated[NvU32, 0]
|
|
gfid: Annotated[NvU32, 4]
|
|
vgpuType: Annotated[NvU32, 8]
|
|
vmPid: Annotated[NvU32, 12]
|
|
swizzId: Annotated[NvU32, 16]
|
|
numChannels: Annotated[NvU32, 20]
|
|
numPluginChannels: Annotated[NvU32, 24]
|
|
chidOffset: Annotated[c.Array[NvU32, Literal[84]], 28]
|
|
bDisableDefaultSmcExecPartRestore: Annotated[NvBool, 364]
|
|
numGuestFbSegments: Annotated[NvU32, 368]
|
|
guestFbPhysAddrList: Annotated[c.Array[NvU64, Literal[384]], 376]
|
|
guestFbLengthList: Annotated[c.Array[NvU64, Literal[384]], 3448]
|
|
pluginHeapMemoryPhysAddr: Annotated[NvU64, 6520]
|
|
pluginHeapMemoryLength: Annotated[NvU64, 6528]
|
|
ctrlBuffOffset: Annotated[NvU64, 6536]
|
|
initTaskLogBuffOffset: Annotated[NvU64, 6544]
|
|
initTaskLogBuffSize: Annotated[NvU64, 6552]
|
|
vgpuTaskLogBuffOffset: Annotated[NvU64, 6560]
|
|
vgpuTaskLogBuffSize: Annotated[NvU64, 6568]
|
|
kernelLogBuffOffset: Annotated[NvU64, 6576]
|
|
kernelLogBuffSize: Annotated[NvU64, 6584]
|
|
migRmHeapMemoryPhysAddr: Annotated[NvU64, 6592]
|
|
migRmHeapMemoryLength: Annotated[NvU64, 6600]
|
|
bDeviceProfilingEnabled: Annotated[NvBool, 6608]
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gfid: Annotated[NvU32, 0]
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS(c.Struct):
|
|
SIZE = 334344
|
|
discardVgpuTypes: Annotated[NvBool, 0]
|
|
vgpuInfoCount: Annotated[NvU32, 4]
|
|
vgpuInfo: Annotated[c.Array[NVA081_CTRL_VGPU_INFO, Literal[64]], 8]
|
|
@c.record
|
|
class struct_NVA081_CTRL_VGPU_INFO(c.Struct):
|
|
SIZE = 5224
|
|
vgpuType: Annotated[NvU32, 0]
|
|
vgpuName: Annotated[c.Array[NvU8, Literal[32]], 4]
|
|
vgpuClass: Annotated[c.Array[NvU8, Literal[32]], 36]
|
|
vgpuSignature: Annotated[c.Array[NvU8, Literal[128]], 68]
|
|
license: Annotated[c.Array[NvU8, Literal[128]], 196]
|
|
maxInstance: Annotated[NvU32, 324]
|
|
numHeads: Annotated[NvU32, 328]
|
|
maxResolutionX: Annotated[NvU32, 332]
|
|
maxResolutionY: Annotated[NvU32, 336]
|
|
maxPixels: Annotated[NvU32, 340]
|
|
frlConfig: Annotated[NvU32, 344]
|
|
cudaEnabled: Annotated[NvU32, 348]
|
|
eccSupported: Annotated[NvU32, 352]
|
|
gpuInstanceSize: Annotated[NvU32, 356]
|
|
multiVgpuSupported: Annotated[NvU32, 360]
|
|
vdevId: Annotated[NvU64, 368]
|
|
pdevId: Annotated[NvU64, 376]
|
|
profileSize: Annotated[NvU64, 384]
|
|
fbLength: Annotated[NvU64, 392]
|
|
gspHeapSize: Annotated[NvU64, 400]
|
|
fbReservation: Annotated[NvU64, 408]
|
|
mappableVideoSize: Annotated[NvU64, 416]
|
|
encoderCapacity: Annotated[NvU32, 424]
|
|
bar1Length: Annotated[NvU64, 432]
|
|
frlEnable: Annotated[NvU32, 440]
|
|
adapterName: Annotated[c.Array[NvU8, Literal[64]], 444]
|
|
adapterName_Unicode: Annotated[c.Array[NvU16, Literal[64]], 508]
|
|
shortGpuNameString: Annotated[c.Array[NvU8, Literal[64]], 636]
|
|
licensedProductName: Annotated[c.Array[NvU8, Literal[128]], 700]
|
|
vgpuExtraParams: Annotated[c.Array[NvU32, Literal[1024]], 828]
|
|
ftraceEnable: Annotated[NvU32, 4924]
|
|
gpuDirectSupported: Annotated[NvU32, 4928]
|
|
nvlinkP2PSupported: Annotated[NvU32, 4932]
|
|
multiVgpuExclusive: Annotated[NvU32, 4936]
|
|
exclusiveType: Annotated[NvU32, 4940]
|
|
exclusiveSize: Annotated[NvU32, 4944]
|
|
gpuInstanceProfileId: Annotated[NvU32, 4948]
|
|
placementSize: Annotated[NvU32, 4952]
|
|
homogeneousPlacementCount: Annotated[NvU32, 4956]
|
|
homogeneousPlacementIds: Annotated[c.Array[NvU32, Literal[32]], 4960]
|
|
heterogeneousPlacementCount: Annotated[NvU32, 5088]
|
|
heterogeneousPlacementIds: Annotated[c.Array[NvU32, Literal[32]], 5092]
|
|
NVA081_CTRL_VGPU_INFO: TypeAlias = struct_NVA081_CTRL_VGPU_INFO
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_GUEST_VM_INFO(c.Struct):
|
|
SIZE = 104
|
|
vmPid: Annotated[NvU32, 0]
|
|
guestOs: Annotated[NvU32, 4]
|
|
migrationProhibited: Annotated[NvU32, 8]
|
|
guestNegotiatedVgpuVersion: Annotated[NvU32, 12]
|
|
frameRateLimit: Annotated[NvU32, 16]
|
|
licensed: Annotated[NvBool, 20]
|
|
licenseState: Annotated[NvU32, 24]
|
|
licenseExpiryTimestamp: Annotated[NvU32, 28]
|
|
licenseExpiryStatus: Annotated[NvU8, 32]
|
|
guestDriverVersion: Annotated[c.Array[NvU8, Literal[32]], 33]
|
|
guestDriverBranch: Annotated[c.Array[NvU8, Literal[32]], 65]
|
|
guestVmInfoState: Annotated[GUEST_VM_INFO_STATE, 100]
|
|
class enum_GUEST_VM_INFO_STATE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
GUEST_VM_INFO_STATE_UNINITIALIZED = enum_GUEST_VM_INFO_STATE.define('GUEST_VM_INFO_STATE_UNINITIALIZED', 0)
|
|
GUEST_VM_INFO_STATE_INITIALIZED = enum_GUEST_VM_INFO_STATE.define('GUEST_VM_INFO_STATE_INITIALIZED', 1)
|
|
|
|
GUEST_VM_INFO_STATE: TypeAlias = enum_GUEST_VM_INFO_STATE
|
|
NV2080_GUEST_VM_INFO: TypeAlias = struct_NV2080_GUEST_VM_INFO
|
|
@c.record
|
|
class struct_NV2080_HOST_VGPU_DEVICE(c.Struct):
|
|
SIZE = 48
|
|
gfid: Annotated[NvU32, 0]
|
|
vgpuPciId: Annotated[NvU64, 8]
|
|
vgpuDeviceInstanceId: Annotated[NvU32, 16]
|
|
fbUsed: Annotated[NvU64, 24]
|
|
encoderCapacity: Annotated[NvU32, 32]
|
|
eccState: Annotated[NvU32, 36]
|
|
bDriverLoaded: Annotated[NvBool, 40]
|
|
NV2080_HOST_VGPU_DEVICE: TypeAlias = struct_NV2080_HOST_VGPU_DEVICE
|
|
@c.record
|
|
class struct_NV2080_VGPU_GUEST(c.Struct):
|
|
SIZE = 152
|
|
guestVmInfo: Annotated[NV2080_GUEST_VM_INFO, 0]
|
|
vgpuDevice: Annotated[NV2080_HOST_VGPU_DEVICE, 104]
|
|
NV2080_VGPU_GUEST: TypeAlias = struct_NV2080_VGPU_GUEST
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS(c.Struct):
|
|
SIZE = 4872
|
|
numVgpu: Annotated[NvU32, 0]
|
|
vgpuGuest: Annotated[c.Array[NV2080_VGPU_GUEST, Literal[32]], 8]
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gfid: Annotated[NvU32, 0]
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV2080_VGPU_FB_USAGE(c.Struct):
|
|
SIZE = 16
|
|
gfid: Annotated[NvU32, 0]
|
|
fbUsed: Annotated[NvU64, 8]
|
|
NV2080_VGPU_FB_USAGE: TypeAlias = struct_NV2080_VGPU_FB_USAGE
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS(c.Struct):
|
|
SIZE = 520
|
|
vgpuCount: Annotated[NvU32, 0]
|
|
vgpuFbUsage: Annotated[c.Array[NV2080_VGPU_FB_USAGE, Literal[32]], 8]
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gfid: Annotated[NvU32, 0]
|
|
encoderCapacity: Annotated[NvU32, 4]
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
gfid: Annotated[NvU32, 0]
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS(c.Struct):
|
|
SIZE = 260
|
|
pgpuString: Annotated[c.Array[NvU8, Literal[256]], 0]
|
|
pgpuStringSize: Annotated[NvU32, 256]
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bIsMigrationSupported: Annotated[NvBool, 0]
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bSupportHeterogeneousTimeSlicedVgpuTypes: Annotated[NvBool, 0]
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
gfid: Annotated[NvU32, 0]
|
|
flags: Annotated[NvU32, 4]
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bFlrDisabled: Annotated[NvBool, 0]
|
|
NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bHeterogeneousMode: Annotated[NvBool, 0]
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS: TypeAlias = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
action: Annotated[NvU32, 0]
|
|
NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
value: Annotated[NvU32, 0]
|
|
NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
exceptionMask: Annotated[NvU32, 0]
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_SM_ERROR_STATE_REGISTERS(c.Struct):
|
|
SIZE = 48
|
|
hwwGlobalEsr: Annotated[NvU32, 0]
|
|
hwwWarpEsr: Annotated[NvU32, 4]
|
|
hwwWarpEsrPc: Annotated[NvU32, 8]
|
|
hwwGlobalEsrReportMask: Annotated[NvU32, 12]
|
|
hwwWarpEsrReportMask: Annotated[NvU32, 16]
|
|
hwwEsrAddr: Annotated[NvU64, 24]
|
|
hwwWarpEsrPc64: Annotated[NvU64, 32]
|
|
hwwCgaEsr: Annotated[NvU32, 40]
|
|
hwwCgaEsrReportMask: Annotated[NvU32, 44]
|
|
NV83DE_SM_ERROR_STATE_REGISTERS: TypeAlias = struct_NV83DE_SM_ERROR_STATE_REGISTERS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
hTargetChannel: Annotated[NvHandle, 0]
|
|
smID: Annotated[NvU32, 4]
|
|
smErrorState: Annotated[NV83DE_SM_ERROR_STATE_REGISTERS, 8]
|
|
NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_MMU_FAULT_INFO(c.Struct):
|
|
SIZE = 8
|
|
valid: Annotated[NvBool, 0]
|
|
faultInfo: Annotated[NvU32, 4]
|
|
NV83DE_MMU_FAULT_INFO: TypeAlias = struct_NV83DE_MMU_FAULT_INFO
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS(c.Struct):
|
|
SIZE = 4824
|
|
hTargetChannel: Annotated[NvHandle, 0]
|
|
numSMsToRead: Annotated[NvU32, 4]
|
|
smErrorStateArray: Annotated[c.Array[NV83DE_SM_ERROR_STATE_REGISTERS, Literal[100]], 8]
|
|
mmuFaultInfo: Annotated[NvU32, 4808]
|
|
mmuFault: Annotated[NV83DE_MMU_FAULT_INFO, 4812]
|
|
startingSM: Annotated[NvU32, 4820]
|
|
NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hTargetChannel: Annotated[NvHandle, 0]
|
|
smID: Annotated[NvU32, 4]
|
|
NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hTargetChannel: Annotated[NvHandle, 0]
|
|
numSMsToClear: Annotated[NvU32, 4]
|
|
NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
waitForEvent: Annotated[NvU32, 0]
|
|
hResidentChannel: Annotated[NvHandle, 4]
|
|
NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS: TypeAlias = struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
stopTriggerType: Annotated[NvU32, 0]
|
|
NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
singleStepHandling: Annotated[NvU32, 0]
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hMemory: Annotated[NvU32, 0]
|
|
length: Annotated[NvU32, 4]
|
|
offset: Annotated[NvU64, 8]
|
|
buffer: Annotated[NvP64, 16]
|
|
NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 24
|
|
hMemory: Annotated[NvU32, 0]
|
|
length: Annotated[NvU32, 4]
|
|
offset: Annotated[NvU64, 8]
|
|
buffer: Annotated[NvP64, 16]
|
|
NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS
|
|
NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS: TypeAlias = struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
hChannel: Annotated[NvHandle, 0]
|
|
hSubdevice: Annotated[NvHandle, 4]
|
|
NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_ACCESS_OP(c.Struct):
|
|
SIZE = 24
|
|
gpuVA: Annotated[NvU64, 0]
|
|
pCpuVA: Annotated[NvP64, 8]
|
|
size: Annotated[NvU32, 16]
|
|
valid: Annotated[NvU32, 20]
|
|
NV83DE_CTRL_DEBUG_ACCESS_OP: TypeAlias = struct_NV83DE_CTRL_DEBUG_ACCESS_OP
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS(c.Struct):
|
|
SIZE = 1544
|
|
count: Annotated[NvU32, 0]
|
|
opsBuffer: Annotated[c.Array[NV83DE_CTRL_DEBUG_ACCESS_OP, Literal[64]], 8]
|
|
NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS: TypeAlias = struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP(c.Struct):
|
|
SIZE = 16
|
|
gpuVA: Annotated[NvU64, 0]
|
|
size: Annotated[NvU32, 8]
|
|
NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS(c.Struct):
|
|
SIZE = 1048
|
|
vaLo: Annotated[NvU64, 0]
|
|
vaHi: Annotated[NvU64, 8]
|
|
count: Annotated[NvU32, 16]
|
|
hasMore: Annotated[NvU32, 20]
|
|
opsBuffer: Annotated[c.Array[NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP, Literal[64]], 24]
|
|
NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS(c.Struct):
|
|
SIZE = 3208
|
|
bNonTransactional: Annotated[NvBool, 0]
|
|
regOpCount: Annotated[NvU32, 4]
|
|
regOps: Annotated[c.Array[NV2080_CTRL_GPU_REG_OP, Literal[100]], 8]
|
|
NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
action: Annotated[NvU32, 0]
|
|
NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
value: Annotated[NvU32, 0]
|
|
NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
smID: Annotated[NvU32, 0]
|
|
bSingleStep: Annotated[NvBool, 4]
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
smID: Annotated[NvU32, 0]
|
|
bStopTrigger: Annotated[NvBool, 4]
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
smID: Annotated[NvU32, 0]
|
|
bRunTrigger: Annotated[NvBool, 4]
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
smID: Annotated[NvU32, 0]
|
|
bSkipIdleWarpDetect: Annotated[NvBool, 4]
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS(c.Struct):
|
|
SIZE = 5
|
|
bInTrapMode: Annotated[NvBool, 0]
|
|
bCrsFlushDone: Annotated[NvBool, 1]
|
|
bRunTriggerInProgress: Annotated[NvBool, 2]
|
|
bComputeContext: Annotated[NvBool, 3]
|
|
bLockedDown: Annotated[NvBool, 4]
|
|
NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
smID: Annotated[NvU32, 0]
|
|
smDebuggerStatus: Annotated[NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS, 4]
|
|
NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY(c.Struct):
|
|
SIZE = 24
|
|
hMemory: Annotated[NvHandle, 0]
|
|
length: Annotated[NvU32, 4]
|
|
memOffset: Annotated[NvU64, 8]
|
|
dataOffset: Annotated[NvU32, 16]
|
|
status: Annotated[NV_STATUS, 20]
|
|
NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY: TypeAlias = struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS(c.Struct):
|
|
SIZE = 3616
|
|
pData: Annotated[NvP64, 0]
|
|
dataLength: Annotated[NvU32, 8]
|
|
count: Annotated[NvU32, 12]
|
|
entries: Annotated[c.Array[NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY, Literal[150]], 16]
|
|
NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY(c.Struct):
|
|
SIZE = 16
|
|
faultAddress: Annotated[NvU64, 0]
|
|
faultType: Annotated[NvU32, 8]
|
|
accessType: Annotated[NvU32, 12]
|
|
NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY: TypeAlias = struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS(c.Struct):
|
|
SIZE = 72
|
|
mmuFaultInfoList: Annotated[c.Array[NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY, Literal[4]], 0]
|
|
count: Annotated[NvU32, 64]
|
|
NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
bDropDeferredRc: Annotated[NvBool, 0]
|
|
NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
action: Annotated[NvU32, 0]
|
|
NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS
|
|
@c.record
|
|
class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
value: Annotated[NvU32, 0]
|
|
NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS: TypeAlias = struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
params: Annotated[NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS, 0]
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS(c.Struct):
|
|
SIZE = 56
|
|
hMemPmaBuffer: Annotated[NvHandle, 0]
|
|
pmaBufferOffset: Annotated[NvU64, 8]
|
|
pmaBufferSize: Annotated[NvU64, 16]
|
|
hMemPmaBytesAvailable: Annotated[NvHandle, 24]
|
|
pmaBytesAvailableOffset: Annotated[NvU64, 32]
|
|
ctxsw: Annotated[NvBool, 40]
|
|
pmaChannelIdx: Annotated[NvU32, 44]
|
|
pmaBufferVA: Annotated[NvU64, 48]
|
|
NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS: TypeAlias = struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS
|
|
NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS: TypeAlias = struct_NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
pmaChannelIdx: Annotated[NvU32, 0]
|
|
bMembytesPollingRequired: Annotated[NvBool, 4]
|
|
NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
pmaChannelIdx: Annotated[NvU32, 0]
|
|
pmaBufferVA: Annotated[NvU64, 8]
|
|
pmaBufferSize: Annotated[NvU64, 16]
|
|
membytesVA: Annotated[NvU64, 24]
|
|
hwpmIBPA: Annotated[NvU64, 32]
|
|
hwpmIBAperture: Annotated[NvU8, 40]
|
|
NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS(c.Struct):
|
|
SIZE = 5
|
|
bAdminProfilingPermitted: Annotated[NvBool, 0]
|
|
bDevProfilingPermitted: Annotated[NvBool, 1]
|
|
bCtxProfilingPermitted: Annotated[NvBool, 2]
|
|
bVideoMemoryProfilingPermitted: Annotated[NvBool, 3]
|
|
bSysMemoryProfilingPermitted: Annotated[NvBool, 4]
|
|
NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS(c.Struct):
|
|
SIZE = 64
|
|
hMemPmaBuffer: Annotated[NvHandle, 0]
|
|
pmaBufferOffset: Annotated[NvU64, 8]
|
|
pmaBufferSize: Annotated[NvU64, 16]
|
|
hMemPmaBytesAvailable: Annotated[NvHandle, 24]
|
|
pmaBytesAvailableOffset: Annotated[NvU64, 32]
|
|
ctxsw: Annotated[NvBool, 40]
|
|
pmaChannelIdx: Annotated[NvU32, 44]
|
|
pmaBufferVA: Annotated[NvU64, 48]
|
|
bInputPmaChIdx: Annotated[NvBool, 56]
|
|
NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
pmaChannelIdx: Annotated[NvU32, 0]
|
|
NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
maxPmaChannels: Annotated[NvU32, 0]
|
|
NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
ctxsw: Annotated[NvBool, 0]
|
|
NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS: TypeAlias = struct_NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS(c.Struct):
|
|
SIZE = 12
|
|
globalStatus: Annotated[NvU32, 0]
|
|
controlMask: Annotated[NvU32, 4]
|
|
statusMask: Annotated[NvU32, 8]
|
|
NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS: TypeAlias = struct_NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
controlMask: Annotated[NvU32, 0]
|
|
NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS: TypeAlias = struct_NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
ctxsw: Annotated[NvBool, 0]
|
|
NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
ctxsw: Annotated[NvBool, 0]
|
|
NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
pmaChannelIdx: Annotated[NvU32, 0]
|
|
NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS: TypeAlias = struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS(c.Struct):
|
|
SIZE = 48
|
|
bytesConsumed: Annotated[NvU64, 0]
|
|
bUpdateAvailableBytes: Annotated[NvBool, 8]
|
|
bWait: Annotated[NvBool, 9]
|
|
bytesAvailable: Annotated[NvU64, 16]
|
|
bReturnPut: Annotated[NvBool, 24]
|
|
putPtr: Annotated[NvU64, 32]
|
|
pmaChannelIdx: Annotated[NvU32, 40]
|
|
bOverflowStatus: Annotated[NvBool, 44]
|
|
NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS: TypeAlias = struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS
|
|
NVB0CC_GPU_REG_OP: TypeAlias = struct_NV2080_CTRL_GPU_REG_OP
|
|
class enum_NVB0CC_REGOPS_MODE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NVB0CC_REGOPS_MODE_ALL_OR_NONE = enum_NVB0CC_REGOPS_MODE.define('NVB0CC_REGOPS_MODE_ALL_OR_NONE', 0)
|
|
NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR = enum_NVB0CC_REGOPS_MODE.define('NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR', 1)
|
|
|
|
NVB0CC_REGOPS_MODE: TypeAlias = enum_NVB0CC_REGOPS_MODE
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS(c.Struct):
|
|
SIZE = 3980
|
|
regOpCount: Annotated[NvU32, 0]
|
|
mode: Annotated[NVB0CC_REGOPS_MODE, 4]
|
|
bPassed: Annotated[NvBool, 8]
|
|
bDirect: Annotated[NvBool, 9]
|
|
regOps: Annotated[c.Array[NVB0CC_GPU_REG_OP, Literal[124]], 12]
|
|
NVB0CC_CTRL_EXEC_REG_OPS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
numCredits: Annotated[NvU32, 0]
|
|
NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS
|
|
class enum_NVB0CC_CHIPLET_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NVB0CC_CHIPLET_TYPE_INVALID = enum_NVB0CC_CHIPLET_TYPE.define('NVB0CC_CHIPLET_TYPE_INVALID', 0)
|
|
NVB0CC_CHIPLET_TYPE_FBP = enum_NVB0CC_CHIPLET_TYPE.define('NVB0CC_CHIPLET_TYPE_FBP', 1)
|
|
NVB0CC_CHIPLET_TYPE_GPC = enum_NVB0CC_CHIPLET_TYPE.define('NVB0CC_CHIPLET_TYPE_GPC', 2)
|
|
NVB0CC_CHIPLET_TYPE_SYS = enum_NVB0CC_CHIPLET_TYPE.define('NVB0CC_CHIPLET_TYPE_SYS', 3)
|
|
|
|
NVB0CC_CHIPLET_TYPE: TypeAlias = enum_NVB0CC_CHIPLET_TYPE
|
|
class enum_NVB0CC_HS_CREDITS_CMD_STATUS(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NVB0CC_HS_CREDITS_CMD_STATUS_OK = enum_NVB0CC_HS_CREDITS_CMD_STATUS.define('NVB0CC_HS_CREDITS_CMD_STATUS_OK', 0)
|
|
NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CREDITS = enum_NVB0CC_HS_CREDITS_CMD_STATUS.define('NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CREDITS', 1)
|
|
NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET = enum_NVB0CC_HS_CREDITS_CMD_STATUS.define('NVB0CC_HS_CREDITS_CMD_STATUS_INVALID_CHIPLET', 2)
|
|
|
|
NVB0CC_HS_CREDITS_CMD_STATUS: TypeAlias = enum_NVB0CC_HS_CREDITS_CMD_STATUS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO(c.Struct):
|
|
SIZE = 4
|
|
chipletType: Annotated[NvU8, 0]
|
|
chipletIndex: Annotated[NvU8, 1]
|
|
numCredits: Annotated[NvU16, 2]
|
|
NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO: TypeAlias = struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS(c.Struct):
|
|
SIZE = 2
|
|
status: Annotated[NvU8, 0]
|
|
entryIndex: Annotated[NvU8, 1]
|
|
NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS: TypeAlias = struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_HS_CREDITS_PARAMS(c.Struct):
|
|
SIZE = 256
|
|
pmaChannelIdx: Annotated[NvU8, 0]
|
|
numEntries: Annotated[NvU8, 1]
|
|
statusInfo: Annotated[NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS, 2]
|
|
creditInfo: Annotated[c.Array[NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO, Literal[63]], 4]
|
|
NVB0CC_CTRL_HS_CREDITS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_HS_CREDITS_PARAMS
|
|
NVB0CC_CTRL_SET_HS_CREDITS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_HS_CREDITS_PARAMS
|
|
NVB0CC_CTRL_GET_HS_CREDITS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_HS_CREDITS_PARAMS
|
|
class enum_NVB0CC_CTRL_HES_TYPE(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NVB0CC_CTRL_HES_INVALID = enum_NVB0CC_CTRL_HES_TYPE.define('NVB0CC_CTRL_HES_INVALID', 0)
|
|
NVB0CC_CTRL_HES_CWD = enum_NVB0CC_CTRL_HES_TYPE.define('NVB0CC_CTRL_HES_CWD', 1)
|
|
|
|
NVB0CC_CTRL_HES_TYPE: TypeAlias = enum_NVB0CC_CTRL_HES_TYPE
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
ctxsw: Annotated[NvBool, 0]
|
|
NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS
|
|
@c.record
|
|
class union_NVB0CC_CTRL_HES_RESERVATION_UNION(c.Struct):
|
|
SIZE = 1
|
|
cwd: Annotated[NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS, 0]
|
|
NVB0CC_CTRL_HES_RESERVATION_UNION: TypeAlias = union_NVB0CC_CTRL_HES_RESERVATION_UNION
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RESERVE_HES_PARAMS(c.Struct):
|
|
SIZE = 8
|
|
type: Annotated[NvU32, 0]
|
|
reserveParams: Annotated[NVB0CC_CTRL_HES_RESERVATION_UNION, 4]
|
|
NVB0CC_CTRL_RESERVE_HES_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RESERVE_HES_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RELEASE_HES_PARAMS(c.Struct):
|
|
SIZE = 4
|
|
type: Annotated[NVB0CC_CTRL_HES_TYPE, 0]
|
|
NVB0CC_CTRL_RELEASE_HES_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RELEASE_HES_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_CREDIT_POOL_INFO(c.Struct):
|
|
SIZE = 4
|
|
numCredits: Annotated[NvU16, 0]
|
|
poolIndex: Annotated[NvU8, 2]
|
|
chipletType: Annotated[NvU8, 3]
|
|
NVB0CC_CTRL_CREDIT_POOL_INFO: TypeAlias = struct_NVB0CC_CTRL_CREDIT_POOL_INFO
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL(c.Struct):
|
|
SIZE = 124
|
|
poolInfos: Annotated[c.Array[NVB0CC_CTRL_CREDIT_POOL_INFO, Literal[30]], 0]
|
|
poolInfosCount: Annotated[NvU32, 120]
|
|
NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL: TypeAlias = struct_NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO(c.Struct):
|
|
SIZE = 3
|
|
chipletType: Annotated[NvU8, 0]
|
|
chipletIndex: Annotated[NvU8, 1]
|
|
poolIndex: Annotated[NvU8, 2]
|
|
NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO: TypeAlias = struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS(c.Struct):
|
|
SIZE = 194
|
|
numQueries: Annotated[NvU16, 0]
|
|
statusInfo: Annotated[NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS, 2]
|
|
queries: Annotated[c.Array[NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO, Literal[63]], 4]
|
|
NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS: TypeAlias = struct_NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
disable: Annotated[NvBool, 0]
|
|
NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS: TypeAlias = struct_NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
enabled: Annotated[NvBool, 0]
|
|
NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS: TypeAlias = struct_NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS
|
|
@c.record
|
|
class struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS(c.Struct):
|
|
SIZE = 1
|
|
ctxsw: Annotated[NvBool, 0]
|
|
NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS: TypeAlias = struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS
|
|
class nv_status_codes(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
|
NV_OK = nv_status_codes.define('NV_OK', 0)
|
|
NV_ERR_GENERIC = nv_status_codes.define('NV_ERR_GENERIC', 65535)
|
|
NV_ERR_BROKEN_FB = nv_status_codes.define('NV_ERR_BROKEN_FB', 1)
|
|
NV_ERR_BUFFER_TOO_SMALL = nv_status_codes.define('NV_ERR_BUFFER_TOO_SMALL', 2)
|
|
NV_ERR_BUSY_RETRY = nv_status_codes.define('NV_ERR_BUSY_RETRY', 3)
|
|
NV_ERR_CALLBACK_NOT_SCHEDULED = nv_status_codes.define('NV_ERR_CALLBACK_NOT_SCHEDULED', 4)
|
|
NV_ERR_CARD_NOT_PRESENT = nv_status_codes.define('NV_ERR_CARD_NOT_PRESENT', 5)
|
|
NV_ERR_CYCLE_DETECTED = nv_status_codes.define('NV_ERR_CYCLE_DETECTED', 6)
|
|
NV_ERR_DMA_IN_USE = nv_status_codes.define('NV_ERR_DMA_IN_USE', 7)
|
|
NV_ERR_DMA_MEM_NOT_LOCKED = nv_status_codes.define('NV_ERR_DMA_MEM_NOT_LOCKED', 8)
|
|
NV_ERR_DMA_MEM_NOT_UNLOCKED = nv_status_codes.define('NV_ERR_DMA_MEM_NOT_UNLOCKED', 9)
|
|
NV_ERR_DUAL_LINK_INUSE = nv_status_codes.define('NV_ERR_DUAL_LINK_INUSE', 10)
|
|
NV_ERR_ECC_ERROR = nv_status_codes.define('NV_ERR_ECC_ERROR', 11)
|
|
NV_ERR_FIFO_BAD_ACCESS = nv_status_codes.define('NV_ERR_FIFO_BAD_ACCESS', 12)
|
|
NV_ERR_FREQ_NOT_SUPPORTED = nv_status_codes.define('NV_ERR_FREQ_NOT_SUPPORTED', 13)
|
|
NV_ERR_GPU_DMA_NOT_INITIALIZED = nv_status_codes.define('NV_ERR_GPU_DMA_NOT_INITIALIZED', 14)
|
|
NV_ERR_GPU_IS_LOST = nv_status_codes.define('NV_ERR_GPU_IS_LOST', 15)
|
|
NV_ERR_GPU_IN_FULLCHIP_RESET = nv_status_codes.define('NV_ERR_GPU_IN_FULLCHIP_RESET', 16)
|
|
NV_ERR_GPU_NOT_FULL_POWER = nv_status_codes.define('NV_ERR_GPU_NOT_FULL_POWER', 17)
|
|
NV_ERR_GPU_UUID_NOT_FOUND = nv_status_codes.define('NV_ERR_GPU_UUID_NOT_FOUND', 18)
|
|
NV_ERR_HOT_SWITCH = nv_status_codes.define('NV_ERR_HOT_SWITCH', 19)
|
|
NV_ERR_I2C_ERROR = nv_status_codes.define('NV_ERR_I2C_ERROR', 20)
|
|
NV_ERR_I2C_SPEED_TOO_HIGH = nv_status_codes.define('NV_ERR_I2C_SPEED_TOO_HIGH', 21)
|
|
NV_ERR_ILLEGAL_ACTION = nv_status_codes.define('NV_ERR_ILLEGAL_ACTION', 22)
|
|
NV_ERR_IN_USE = nv_status_codes.define('NV_ERR_IN_USE', 23)
|
|
NV_ERR_INFLATE_COMPRESSED_DATA_FAILED = nv_status_codes.define('NV_ERR_INFLATE_COMPRESSED_DATA_FAILED', 24)
|
|
NV_ERR_INSERT_DUPLICATE_NAME = nv_status_codes.define('NV_ERR_INSERT_DUPLICATE_NAME', 25)
|
|
NV_ERR_INSUFFICIENT_RESOURCES = nv_status_codes.define('NV_ERR_INSUFFICIENT_RESOURCES', 26)
|
|
NV_ERR_INSUFFICIENT_PERMISSIONS = nv_status_codes.define('NV_ERR_INSUFFICIENT_PERMISSIONS', 27)
|
|
NV_ERR_INSUFFICIENT_POWER = nv_status_codes.define('NV_ERR_INSUFFICIENT_POWER', 28)
|
|
NV_ERR_INVALID_ACCESS_TYPE = nv_status_codes.define('NV_ERR_INVALID_ACCESS_TYPE', 29)
|
|
NV_ERR_INVALID_ADDRESS = nv_status_codes.define('NV_ERR_INVALID_ADDRESS', 30)
|
|
NV_ERR_INVALID_ARGUMENT = nv_status_codes.define('NV_ERR_INVALID_ARGUMENT', 31)
|
|
NV_ERR_INVALID_BASE = nv_status_codes.define('NV_ERR_INVALID_BASE', 32)
|
|
NV_ERR_INVALID_CHANNEL = nv_status_codes.define('NV_ERR_INVALID_CHANNEL', 33)
|
|
NV_ERR_INVALID_CLASS = nv_status_codes.define('NV_ERR_INVALID_CLASS', 34)
|
|
NV_ERR_INVALID_CLIENT = nv_status_codes.define('NV_ERR_INVALID_CLIENT', 35)
|
|
NV_ERR_INVALID_COMMAND = nv_status_codes.define('NV_ERR_INVALID_COMMAND', 36)
|
|
NV_ERR_INVALID_DATA = nv_status_codes.define('NV_ERR_INVALID_DATA', 37)
|
|
NV_ERR_INVALID_DEVICE = nv_status_codes.define('NV_ERR_INVALID_DEVICE', 38)
|
|
NV_ERR_INVALID_DMA_SPECIFIER = nv_status_codes.define('NV_ERR_INVALID_DMA_SPECIFIER', 39)
|
|
NV_ERR_INVALID_EVENT = nv_status_codes.define('NV_ERR_INVALID_EVENT', 40)
|
|
NV_ERR_INVALID_FLAGS = nv_status_codes.define('NV_ERR_INVALID_FLAGS', 41)
|
|
NV_ERR_INVALID_FUNCTION = nv_status_codes.define('NV_ERR_INVALID_FUNCTION', 42)
|
|
NV_ERR_INVALID_HEAP = nv_status_codes.define('NV_ERR_INVALID_HEAP', 43)
|
|
NV_ERR_INVALID_INDEX = nv_status_codes.define('NV_ERR_INVALID_INDEX', 44)
|
|
NV_ERR_INVALID_IRQ_LEVEL = nv_status_codes.define('NV_ERR_INVALID_IRQ_LEVEL', 45)
|
|
NV_ERR_INVALID_LIMIT = nv_status_codes.define('NV_ERR_INVALID_LIMIT', 46)
|
|
NV_ERR_INVALID_LOCK_STATE = nv_status_codes.define('NV_ERR_INVALID_LOCK_STATE', 47)
|
|
NV_ERR_INVALID_METHOD = nv_status_codes.define('NV_ERR_INVALID_METHOD', 48)
|
|
NV_ERR_INVALID_OBJECT = nv_status_codes.define('NV_ERR_INVALID_OBJECT', 49)
|
|
NV_ERR_INVALID_OBJECT_BUFFER = nv_status_codes.define('NV_ERR_INVALID_OBJECT_BUFFER', 50)
|
|
NV_ERR_INVALID_OBJECT_HANDLE = nv_status_codes.define('NV_ERR_INVALID_OBJECT_HANDLE', 51)
|
|
NV_ERR_INVALID_OBJECT_NEW = nv_status_codes.define('NV_ERR_INVALID_OBJECT_NEW', 52)
|
|
NV_ERR_INVALID_OBJECT_OLD = nv_status_codes.define('NV_ERR_INVALID_OBJECT_OLD', 53)
|
|
NV_ERR_INVALID_OBJECT_PARENT = nv_status_codes.define('NV_ERR_INVALID_OBJECT_PARENT', 54)
|
|
NV_ERR_INVALID_OFFSET = nv_status_codes.define('NV_ERR_INVALID_OFFSET', 55)
|
|
NV_ERR_INVALID_OPERATION = nv_status_codes.define('NV_ERR_INVALID_OPERATION', 56)
|
|
NV_ERR_INVALID_OWNER = nv_status_codes.define('NV_ERR_INVALID_OWNER', 57)
|
|
NV_ERR_INVALID_PARAM_STRUCT = nv_status_codes.define('NV_ERR_INVALID_PARAM_STRUCT', 58)
|
|
NV_ERR_INVALID_PARAMETER = nv_status_codes.define('NV_ERR_INVALID_PARAMETER', 59)
|
|
NV_ERR_INVALID_PATH = nv_status_codes.define('NV_ERR_INVALID_PATH', 60)
|
|
NV_ERR_INVALID_POINTER = nv_status_codes.define('NV_ERR_INVALID_POINTER', 61)
|
|
NV_ERR_INVALID_REGISTRY_KEY = nv_status_codes.define('NV_ERR_INVALID_REGISTRY_KEY', 62)
|
|
NV_ERR_INVALID_REQUEST = nv_status_codes.define('NV_ERR_INVALID_REQUEST', 63)
|
|
NV_ERR_INVALID_STATE = nv_status_codes.define('NV_ERR_INVALID_STATE', 64)
|
|
NV_ERR_INVALID_STRING_LENGTH = nv_status_codes.define('NV_ERR_INVALID_STRING_LENGTH', 65)
|
|
NV_ERR_INVALID_READ = nv_status_codes.define('NV_ERR_INVALID_READ', 66)
|
|
NV_ERR_INVALID_WRITE = nv_status_codes.define('NV_ERR_INVALID_WRITE', 67)
|
|
NV_ERR_INVALID_XLATE = nv_status_codes.define('NV_ERR_INVALID_XLATE', 68)
|
|
NV_ERR_IRQ_NOT_FIRING = nv_status_codes.define('NV_ERR_IRQ_NOT_FIRING', 69)
|
|
NV_ERR_IRQ_EDGE_TRIGGERED = nv_status_codes.define('NV_ERR_IRQ_EDGE_TRIGGERED', 70)
|
|
NV_ERR_MEMORY_TRAINING_FAILED = nv_status_codes.define('NV_ERR_MEMORY_TRAINING_FAILED', 71)
|
|
NV_ERR_MISMATCHED_SLAVE = nv_status_codes.define('NV_ERR_MISMATCHED_SLAVE', 72)
|
|
NV_ERR_MISMATCHED_TARGET = nv_status_codes.define('NV_ERR_MISMATCHED_TARGET', 73)
|
|
NV_ERR_MISSING_TABLE_ENTRY = nv_status_codes.define('NV_ERR_MISSING_TABLE_ENTRY', 74)
|
|
NV_ERR_MODULE_LOAD_FAILED = nv_status_codes.define('NV_ERR_MODULE_LOAD_FAILED', 75)
|
|
NV_ERR_MORE_DATA_AVAILABLE = nv_status_codes.define('NV_ERR_MORE_DATA_AVAILABLE', 76)
|
|
NV_ERR_MORE_PROCESSING_REQUIRED = nv_status_codes.define('NV_ERR_MORE_PROCESSING_REQUIRED', 77)
|
|
NV_ERR_MULTIPLE_MEMORY_TYPES = nv_status_codes.define('NV_ERR_MULTIPLE_MEMORY_TYPES', 78)
|
|
NV_ERR_NO_FREE_FIFOS = nv_status_codes.define('NV_ERR_NO_FREE_FIFOS', 79)
|
|
NV_ERR_NO_INTR_PENDING = nv_status_codes.define('NV_ERR_NO_INTR_PENDING', 80)
|
|
NV_ERR_NO_MEMORY = nv_status_codes.define('NV_ERR_NO_MEMORY', 81)
|
|
NV_ERR_NO_SUCH_DOMAIN = nv_status_codes.define('NV_ERR_NO_SUCH_DOMAIN', 82)
|
|
NV_ERR_NO_VALID_PATH = nv_status_codes.define('NV_ERR_NO_VALID_PATH', 83)
|
|
NV_ERR_NOT_COMPATIBLE = nv_status_codes.define('NV_ERR_NOT_COMPATIBLE', 84)
|
|
NV_ERR_NOT_READY = nv_status_codes.define('NV_ERR_NOT_READY', 85)
|
|
NV_ERR_NOT_SUPPORTED = nv_status_codes.define('NV_ERR_NOT_SUPPORTED', 86)
|
|
NV_ERR_OBJECT_NOT_FOUND = nv_status_codes.define('NV_ERR_OBJECT_NOT_FOUND', 87)
|
|
NV_ERR_OBJECT_TYPE_MISMATCH = nv_status_codes.define('NV_ERR_OBJECT_TYPE_MISMATCH', 88)
|
|
NV_ERR_OPERATING_SYSTEM = nv_status_codes.define('NV_ERR_OPERATING_SYSTEM', 89)
|
|
NV_ERR_OTHER_DEVICE_FOUND = nv_status_codes.define('NV_ERR_OTHER_DEVICE_FOUND', 90)
|
|
NV_ERR_OUT_OF_RANGE = nv_status_codes.define('NV_ERR_OUT_OF_RANGE', 91)
|
|
NV_ERR_OVERLAPPING_UVM_COMMIT = nv_status_codes.define('NV_ERR_OVERLAPPING_UVM_COMMIT', 92)
|
|
NV_ERR_PAGE_TABLE_NOT_AVAIL = nv_status_codes.define('NV_ERR_PAGE_TABLE_NOT_AVAIL', 93)
|
|
NV_ERR_PID_NOT_FOUND = nv_status_codes.define('NV_ERR_PID_NOT_FOUND', 94)
|
|
NV_ERR_PROTECTION_FAULT = nv_status_codes.define('NV_ERR_PROTECTION_FAULT', 95)
|
|
NV_ERR_RC_ERROR = nv_status_codes.define('NV_ERR_RC_ERROR', 96)
|
|
NV_ERR_REJECTED_VBIOS = nv_status_codes.define('NV_ERR_REJECTED_VBIOS', 97)
|
|
NV_ERR_RESET_REQUIRED = nv_status_codes.define('NV_ERR_RESET_REQUIRED', 98)
|
|
NV_ERR_STATE_IN_USE = nv_status_codes.define('NV_ERR_STATE_IN_USE', 99)
|
|
NV_ERR_SIGNAL_PENDING = nv_status_codes.define('NV_ERR_SIGNAL_PENDING', 100)
|
|
NV_ERR_TIMEOUT = nv_status_codes.define('NV_ERR_TIMEOUT', 101)
|
|
NV_ERR_TIMEOUT_RETRY = nv_status_codes.define('NV_ERR_TIMEOUT_RETRY', 102)
|
|
NV_ERR_TOO_MANY_PRIMARIES = nv_status_codes.define('NV_ERR_TOO_MANY_PRIMARIES', 103)
|
|
NV_ERR_UVM_ADDRESS_IN_USE = nv_status_codes.define('NV_ERR_UVM_ADDRESS_IN_USE', 104)
|
|
NV_ERR_MAX_SESSION_LIMIT_REACHED = nv_status_codes.define('NV_ERR_MAX_SESSION_LIMIT_REACHED', 105)
|
|
NV_ERR_LIB_RM_VERSION_MISMATCH = nv_status_codes.define('NV_ERR_LIB_RM_VERSION_MISMATCH', 106)
|
|
NV_ERR_PRIV_SEC_VIOLATION = nv_status_codes.define('NV_ERR_PRIV_SEC_VIOLATION', 107)
|
|
NV_ERR_GPU_IN_DEBUG_MODE = nv_status_codes.define('NV_ERR_GPU_IN_DEBUG_MODE', 108)
|
|
NV_ERR_FEATURE_NOT_ENABLED = nv_status_codes.define('NV_ERR_FEATURE_NOT_ENABLED', 109)
|
|
NV_ERR_RESOURCE_LOST = nv_status_codes.define('NV_ERR_RESOURCE_LOST', 110)
|
|
NV_ERR_PMU_NOT_READY = nv_status_codes.define('NV_ERR_PMU_NOT_READY', 111)
|
|
NV_ERR_FLCN_ERROR = nv_status_codes.define('NV_ERR_FLCN_ERROR', 112)
|
|
NV_ERR_FATAL_ERROR = nv_status_codes.define('NV_ERR_FATAL_ERROR', 113)
|
|
NV_ERR_MEMORY_ERROR = nv_status_codes.define('NV_ERR_MEMORY_ERROR', 114)
|
|
NV_ERR_INVALID_LICENSE = nv_status_codes.define('NV_ERR_INVALID_LICENSE', 115)
|
|
NV_ERR_NVLINK_INIT_ERROR = nv_status_codes.define('NV_ERR_NVLINK_INIT_ERROR', 116)
|
|
NV_ERR_NVLINK_MINION_ERROR = nv_status_codes.define('NV_ERR_NVLINK_MINION_ERROR', 117)
|
|
NV_ERR_NVLINK_CLOCK_ERROR = nv_status_codes.define('NV_ERR_NVLINK_CLOCK_ERROR', 118)
|
|
NV_ERR_NVLINK_TRAINING_ERROR = nv_status_codes.define('NV_ERR_NVLINK_TRAINING_ERROR', 119)
|
|
NV_ERR_NVLINK_CONFIGURATION_ERROR = nv_status_codes.define('NV_ERR_NVLINK_CONFIGURATION_ERROR', 120)
|
|
NV_ERR_RISCV_ERROR = nv_status_codes.define('NV_ERR_RISCV_ERROR', 121)
|
|
NV_ERR_FABRIC_MANAGER_NOT_PRESENT = nv_status_codes.define('NV_ERR_FABRIC_MANAGER_NOT_PRESENT', 122)
|
|
NV_ERR_ALREADY_SIGNALLED = nv_status_codes.define('NV_ERR_ALREADY_SIGNALLED', 123)
|
|
NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE = nv_status_codes.define('NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE', 124)
|
|
NV_ERR_KEY_ROTATION_IN_PROGRESS = nv_status_codes.define('NV_ERR_KEY_ROTATION_IN_PROGRESS', 125)
|
|
NV_ERR_TEST_ONLY_CODE_NOT_ENABLED = nv_status_codes.define('NV_ERR_TEST_ONLY_CODE_NOT_ENABLED', 126)
|
|
NV_ERR_SECURE_BOOT_FAILED = nv_status_codes.define('NV_ERR_SECURE_BOOT_FAILED', 127)
|
|
NV_ERR_INSUFFICIENT_ZBC_ENTRY = nv_status_codes.define('NV_ERR_INSUFFICIENT_ZBC_ENTRY', 128)
|
|
NV_ERR_NVLINK_FABRIC_NOT_READY = nv_status_codes.define('NV_ERR_NVLINK_FABRIC_NOT_READY', 129)
|
|
NV_ERR_NVLINK_FABRIC_FAILURE = nv_status_codes.define('NV_ERR_NVLINK_FABRIC_FAILURE', 130)
|
|
NV_ERR_GPU_MEMORY_ONLINING_FAILURE = nv_status_codes.define('NV_ERR_GPU_MEMORY_ONLINING_FAILURE', 131)
|
|
NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE = nv_status_codes.define('NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE', 132)
|
|
NV_WARN_HOT_SWITCH = nv_status_codes.define('NV_WARN_HOT_SWITCH', 65537)
|
|
NV_WARN_INCORRECT_PERFMON_DATA = nv_status_codes.define('NV_WARN_INCORRECT_PERFMON_DATA', 65538)
|
|
NV_WARN_MISMATCHED_SLAVE = nv_status_codes.define('NV_WARN_MISMATCHED_SLAVE', 65539)
|
|
NV_WARN_MISMATCHED_TARGET = nv_status_codes.define('NV_WARN_MISMATCHED_TARGET', 65540)
|
|
NV_WARN_MORE_PROCESSING_REQUIRED = nv_status_codes.define('NV_WARN_MORE_PROCESSING_REQUIRED', 65541)
|
|
NV_WARN_NOTHING_TO_DO = nv_status_codes.define('NV_WARN_NOTHING_TO_DO', 65542)
|
|
NV_WARN_NULL_OBJECT = nv_status_codes.define('NV_WARN_NULL_OBJECT', 65543)
|
|
NV_WARN_OUT_OF_RANGE = nv_status_codes.define('NV_WARN_OUT_OF_RANGE', 65544)
|
|
|
|
c.init_records()
|
|
NVC9B0_VIDEO_DECODER = (0x0000C9B0) # type: ignore
|
|
NVC9B0_NOP = (0x00000100) # type: ignore
|
|
NVC9B0_NOP_PARAMETER = (31, 0) # type: ignore
|
|
NVC9B0_PM_TRIGGER = (0x00000140) # type: ignore
|
|
NVC9B0_PM_TRIGGER_V = (31, 0) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID = (0x00000200) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID = (31, 0) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_MPEG12 = (0x00000001) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_VC1 = (0x00000002) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_H264 = (0x00000003) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_MPEG4 = (0x00000004) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_VP8 = (0x00000005) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_CTR64 = (0x00000006) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_HEVC = (0x00000007) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_NEW_H264 = (0x00000008) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_VP9 = (0x00000009) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_PASS1 = (0x0000000A) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_HEVC_PARSER = (0x0000000C) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_UCODE_TEST = (0x0000000D) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_HWDRM_PR_DECRYPTAUDIO = (0x0000000E) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_HWDRM_PR_DECRYPTAUDIOMULTIPLE = (0x0000000F) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_HWDRM_PR_PREPROCESSENCRYPTEDDATA = (0x00000010) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_VP9_WITH_PARSER = (0x00000011) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_AVD = (0x00000012) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_HW_DRM_PR4_DECRYPTCONTENTMULTIPLE = (0x00000013) # type: ignore
|
|
NVC9B0_SET_APPLICATION_ID_ID_DHKE = (0x00000020) # type: ignore
|
|
NVC9B0_SET_WATCHDOG_TIMER = (0x00000204) # type: ignore
|
|
NVC9B0_SET_WATCHDOG_TIMER_TIMER = (31, 0) # type: ignore
|
|
NVC9B0_SEMAPHORE_A = (0x00000240) # type: ignore
|
|
NVC9B0_SEMAPHORE_A_UPPER = (7, 0) # type: ignore
|
|
NVC9B0_SEMAPHORE_B = (0x00000244) # type: ignore
|
|
NVC9B0_SEMAPHORE_B_LOWER = (31, 0) # type: ignore
|
|
NVC9B0_SEMAPHORE_C = (0x00000248) # type: ignore
|
|
NVC9B0_SEMAPHORE_C_PAYLOAD = (31, 0) # type: ignore
|
|
NVC9B0_CTX_SAVE_AREA = (0x0000024C) # type: ignore
|
|
NVC9B0_CTX_SAVE_AREA_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_CTX_SWITCH = (0x00000250) # type: ignore
|
|
NVC9B0_CTX_SWITCH_OP = (1, 0) # type: ignore
|
|
NVC9B0_CTX_SWITCH_OP_CTX_UPDATE = (0x00000000) # type: ignore
|
|
NVC9B0_CTX_SWITCH_OP_CTX_SAVE = (0x00000001) # type: ignore
|
|
NVC9B0_CTX_SWITCH_OP_CTX_RESTORE = (0x00000002) # type: ignore
|
|
NVC9B0_CTX_SWITCH_OP_CTX_FORCERESTORE = (0x00000003) # type: ignore
|
|
NVC9B0_CTX_SWITCH_CTXID_VALID = (2, 2) # type: ignore
|
|
NVC9B0_CTX_SWITCH_CTXID_VALID_FALSE = (0x00000000) # type: ignore
|
|
NVC9B0_CTX_SWITCH_CTXID_VALID_TRUE = (0x00000001) # type: ignore
|
|
NVC9B0_CTX_SWITCH_RESERVED0 = (7, 3) # type: ignore
|
|
NVC9B0_CTX_SWITCH_CTX_ID = (23, 8) # type: ignore
|
|
NVC9B0_CTX_SWITCH_RESERVED1 = (31, 24) # type: ignore
|
|
NVC9B0_SET_SEMAPHORE_PAYLOAD_LOWER = (0x00000254) # type: ignore
|
|
NVC9B0_SET_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER = (31, 0) # type: ignore
|
|
NVC9B0_SET_SEMAPHORE_PAYLOAD_UPPER = (0x00000258) # type: ignore
|
|
NVC9B0_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER = (31, 0) # type: ignore
|
|
NVC9B0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_A = (0x0000025C) # type: ignore
|
|
NVC9B0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_A_LOWER = (31, 0) # type: ignore
|
|
NVC9B0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_B = (0x00000260) # type: ignore
|
|
NVC9B0_SET_MONITORED_FENCE_SIGNAL_ADDRESS_BASE_B_UPPER = (31, 0) # type: ignore
|
|
NVC9B0_EXECUTE = (0x00000300) # type: ignore
|
|
NVC9B0_EXECUTE_NOTIFY = (0, 0) # type: ignore
|
|
NVC9B0_EXECUTE_NOTIFY_DISABLE = (0x00000000) # type: ignore
|
|
NVC9B0_EXECUTE_NOTIFY_ENABLE = (0x00000001) # type: ignore
|
|
NVC9B0_EXECUTE_NOTIFY_ON = (1, 1) # type: ignore
|
|
NVC9B0_EXECUTE_NOTIFY_ON_END = (0x00000000) # type: ignore
|
|
NVC9B0_EXECUTE_NOTIFY_ON_BEGIN = (0x00000001) # type: ignore
|
|
NVC9B0_EXECUTE_PREDICATION = (2, 2) # type: ignore
|
|
NVC9B0_EXECUTE_PREDICATION_DISABLE = (0x00000000) # type: ignore
|
|
NVC9B0_EXECUTE_PREDICATION_ENABLE = (0x00000001) # type: ignore
|
|
NVC9B0_EXECUTE_PREDICATION_OP = (3, 3) # type: ignore
|
|
NVC9B0_EXECUTE_PREDICATION_OP_EQUAL_ZERO = (0x00000000) # type: ignore
|
|
NVC9B0_EXECUTE_PREDICATION_OP_NOT_EQUAL_ZERO = (0x00000001) # type: ignore
|
|
NVC9B0_EXECUTE_AWAKEN = (8, 8) # type: ignore
|
|
NVC9B0_EXECUTE_AWAKEN_DISABLE = (0x00000000) # type: ignore
|
|
NVC9B0_EXECUTE_AWAKEN_ENABLE = (0x00000001) # type: ignore
|
|
NVC9B0_SEMAPHORE_D = (0x00000304) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_STRUCTURE_SIZE = (1, 0) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_STRUCTURE_SIZE_ONE = (0x00000000) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_STRUCTURE_SIZE_FOUR = (0x00000001) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_STRUCTURE_SIZE_TWO = (0x00000002) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_AWAKEN_ENABLE = (8, 8) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_AWAKEN_ENABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_AWAKEN_ENABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_OPERATION = (17, 16) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_OPERATION_RELEASE = (0x00000000) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_OPERATION_RESERVED_0 = (0x00000001) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_OPERATION_RESERVED_1 = (0x00000002) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_OPERATION_TRAP = (0x00000003) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_FLUSH_DISABLE = (21, 21) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_FLUSH_DISABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_FLUSH_DISABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_TRAP_TYPE = (23, 22) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_TRAP_TYPE_UNCONDITIONAL = (0x00000000) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_TRAP_TYPE_CONDITIONAL = (0x00000001) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_TRAP_TYPE_CONDITIONAL_EXT = (0x00000002) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_PAYLOAD_SIZE = (24, 24) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_PAYLOAD_SIZE_32BIT = (0x00000000) # type: ignore
|
|
NVC9B0_SEMAPHORE_D_PAYLOAD_SIZE_64BIT = (0x00000001) # type: ignore
|
|
NVC9B0_SET_PREDICATION_OFFSET_UPPER = (0x00000308) # type: ignore
|
|
NVC9B0_SET_PREDICATION_OFFSET_UPPER_OFFSET = (7, 0) # type: ignore
|
|
NVC9B0_SET_PREDICATION_OFFSET_LOWER = (0x0000030C) # type: ignore
|
|
NVC9B0_SET_PREDICATION_OFFSET_LOWER_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_AUXILIARY_DATA_BUFFER = (0x00000310) # type: ignore
|
|
NVC9B0_SET_AUXILIARY_DATA_BUFFER_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS = (0x00000400) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE = (3, 0) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_MPEG1 = (0x00000000) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_MPEG2 = (0x00000001) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_VC1 = (0x00000002) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_H264 = (0x00000003) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_MPEG4 = (0x00000004) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_DIVX3 = (0x00000004) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_VP8 = (0x00000005) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_HEVC = (0x00000007) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_VP9 = (0x00000009) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_CODEC_TYPE_AV1 = (0x0000000A) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_GPTIMER_ON = (4, 4) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_RET_ERROR = (5, 5) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_ERR_CONCEAL_ON = (6, 6) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_ERROR_FRM_IDX = (12, 7) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_MBTIMER_ON = (13, 13) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_EC_INTRA_FRAME_USING_PSLC = (14, 14) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_IGNORE_SOME_FIELDS_CRC_CHECK = (15, 15) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_EVENT_TRACE_LOGGING_ON = (16, 16) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_ALL_INTRA_FRAME = (17, 17) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_TESTRUN_ENV = (19, 18) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_TESTRUN_ENV_TRACE3D_RUN = (0x00000000) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_TESTRUN_ENV_PROD_RUN = (0x00000001) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_HINT_DUMP_EN = (20, 20) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_RESERVED = (25, 21) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_NVDECSIM_SKIP_SCP = (26, 26) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_ENABLE_ENCRYPT = (27, 27) # type: ignore
|
|
NVC9B0_SET_CONTROL_PARAMS_ENCRYPTMODE = (31, 28) # type: ignore
|
|
NVC9B0_SET_DRV_PIC_SETUP_OFFSET = (0x00000404) # type: ignore
|
|
NVC9B0_SET_DRV_PIC_SETUP_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_IN_BUF_BASE_OFFSET = (0x00000408) # type: ignore
|
|
NVC9B0_SET_IN_BUF_BASE_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_INDEX = (0x0000040C) # type: ignore
|
|
NVC9B0_SET_PICTURE_INDEX_INDEX = (31, 0) # type: ignore
|
|
NVC9B0_SET_SLICE_OFFSETS_BUF_OFFSET = (0x00000410) # type: ignore
|
|
NVC9B0_SET_SLICE_OFFSETS_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_COLOC_DATA_OFFSET = (0x00000414) # type: ignore
|
|
NVC9B0_SET_COLOC_DATA_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_HISTORY_OFFSET = (0x00000418) # type: ignore
|
|
NVC9B0_SET_HISTORY_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_DISPLAY_BUF_SIZE = (0x0000041C) # type: ignore
|
|
NVC9B0_SET_DISPLAY_BUF_SIZE_SIZE = (31, 0) # type: ignore
|
|
NVC9B0_SET_HISTOGRAM_OFFSET = (0x00000420) # type: ignore
|
|
NVC9B0_SET_HISTOGRAM_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_NVDEC_STATUS_OFFSET = (0x00000424) # type: ignore
|
|
NVC9B0_SET_NVDEC_STATUS_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_DISPLAY_BUF_LUMA_OFFSET = (0x00000428) # type: ignore
|
|
NVC9B0_SET_DISPLAY_BUF_LUMA_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_DISPLAY_BUF_CHROMA_OFFSET = (0x0000042C) # type: ignore
|
|
NVC9B0_SET_DISPLAY_BUF_CHROMA_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET0 = (0x00000430) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET0_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET1 = (0x00000434) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET1_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET2 = (0x00000438) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET2_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET3 = (0x0000043C) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET3_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET4 = (0x00000440) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET4_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET5 = (0x00000444) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET5_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET6 = (0x00000448) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET6_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET7 = (0x0000044C) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET7_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET8 = (0x00000450) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET8_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET9 = (0x00000454) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET9_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET10 = (0x00000458) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET10_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET11 = (0x0000045C) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET11_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET12 = (0x00000460) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET12_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET13 = (0x00000464) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET13_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET14 = (0x00000468) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET14_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET15 = (0x0000046C) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET15_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET16 = (0x00000470) # type: ignore
|
|
NVC9B0_SET_PICTURE_LUMA_OFFSET16_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET0 = (0x00000474) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET0_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET1 = (0x00000478) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET1_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET2 = (0x0000047C) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET2_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET3 = (0x00000480) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET3_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET4 = (0x00000484) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET4_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET5 = (0x00000488) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET5_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET6 = (0x0000048C) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET6_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET7 = (0x00000490) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET7_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET8 = (0x00000494) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET8_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET9 = (0x00000498) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET9_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET10 = (0x0000049C) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET10_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET11 = (0x000004A0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET11_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET12 = (0x000004A4) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET12_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET13 = (0x000004A8) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET13_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET14 = (0x000004AC) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET14_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET15 = (0x000004B0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET15_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET16 = (0x000004B4) # type: ignore
|
|
NVC9B0_SET_PICTURE_CHROMA_OFFSET16_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PIC_SCRATCH_BUF_OFFSET = (0x000004B8) # type: ignore
|
|
NVC9B0_SET_PIC_SCRATCH_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_EXTERNAL_MVBUFFER_OFFSET = (0x000004BC) # type: ignore
|
|
NVC9B0_SET_EXTERNAL_MVBUFFER_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_SUB_SAMPLE_MAP_OFFSET = (0x000004C0) # type: ignore
|
|
NVC9B0_SET_SUB_SAMPLE_MAP_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_SUB_SAMPLE_MAP_IV_OFFSET = (0x000004C4) # type: ignore
|
|
NVC9B0_SET_SUB_SAMPLE_MAP_IV_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_INTRA_TOP_BUF_OFFSET = (0x000004C8) # type: ignore
|
|
NVC9B0_SET_INTRA_TOP_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_TILE_SIZE_BUF_OFFSET = (0x000004CC) # type: ignore
|
|
NVC9B0_SET_TILE_SIZE_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_FILTER_BUFFER_OFFSET = (0x000004D0) # type: ignore
|
|
NVC9B0_SET_FILTER_BUFFER_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_CRC_STRUCT_OFFSET = (0x000004D4) # type: ignore
|
|
NVC9B0_SET_CRC_STRUCT_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_PR_SSM_CONTENT_INFO_BUF_OFFSET = (0x000004D8) # type: ignore
|
|
NVC9B0_SET_PR_SSM_CONTENT_INFO_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_H264_SET_MBHIST_BUF_OFFSET = (0x00000500) # type: ignore
|
|
NVC9B0_H264_SET_MBHIST_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP8_SET_PROB_DATA_OFFSET = (0x00000540) # type: ignore
|
|
NVC9B0_VP8_SET_PROB_DATA_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP8_SET_HEADER_PARTITION_BUF_BASE_OFFSET = (0x00000544) # type: ignore
|
|
NVC9B0_VP8_SET_HEADER_PARTITION_BUF_BASE_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_HEVC_SET_SCALING_LIST_OFFSET = (0x00000580) # type: ignore
|
|
NVC9B0_HEVC_SET_SCALING_LIST_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_HEVC_SET_TILE_SIZES_OFFSET = (0x00000584) # type: ignore
|
|
NVC9B0_HEVC_SET_TILE_SIZES_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_HEVC_SET_FILTER_BUFFER_OFFSET = (0x00000588) # type: ignore
|
|
NVC9B0_HEVC_SET_FILTER_BUFFER_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_HEVC_SET_SAO_BUFFER_OFFSET = (0x0000058C) # type: ignore
|
|
NVC9B0_HEVC_SET_SAO_BUFFER_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_HEVC_SET_SLICE_INFO_BUFFER_OFFSET = (0x00000590) # type: ignore
|
|
NVC9B0_HEVC_SET_SLICE_INFO_BUFFER_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_HEVC_SET_SLICE_GROUP_INDEX = (0x00000594) # type: ignore
|
|
NVC9B0_HEVC_SET_SLICE_GROUP_INDEX_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP9_SET_PROB_TAB_BUF_OFFSET = (0x000005C0) # type: ignore
|
|
NVC9B0_VP9_SET_PROB_TAB_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP9_SET_CTX_COUNTER_BUF_OFFSET = (0x000005C4) # type: ignore
|
|
NVC9B0_VP9_SET_CTX_COUNTER_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP9_SET_SEGMENT_READ_BUF_OFFSET = (0x000005C8) # type: ignore
|
|
NVC9B0_VP9_SET_SEGMENT_READ_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP9_SET_SEGMENT_WRITE_BUF_OFFSET = (0x000005CC) # type: ignore
|
|
NVC9B0_VP9_SET_SEGMENT_WRITE_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP9_SET_TILE_SIZE_BUF_OFFSET = (0x000005D0) # type: ignore
|
|
NVC9B0_VP9_SET_TILE_SIZE_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP9_SET_COL_MVWRITE_BUF_OFFSET = (0x000005D4) # type: ignore
|
|
NVC9B0_VP9_SET_COL_MVWRITE_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP9_SET_COL_MVREAD_BUF_OFFSET = (0x000005D8) # type: ignore
|
|
NVC9B0_VP9_SET_COL_MVREAD_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP9_SET_FILTER_BUFFER_OFFSET = (0x000005DC) # type: ignore
|
|
NVC9B0_VP9_SET_FILTER_BUFFER_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP9_PARSER_SET_PIC_SETUP_OFFSET = (0x000005E0) # type: ignore
|
|
NVC9B0_VP9_PARSER_SET_PIC_SETUP_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP9_PARSER_SET_PREV_PIC_SETUP_OFFSET = (0x000005E4) # type: ignore
|
|
NVC9B0_VP9_PARSER_SET_PREV_PIC_SETUP_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP9_PARSER_SET_PROB_TAB_BUF_OFFSET = (0x000005E8) # type: ignore
|
|
NVC9B0_VP9_PARSER_SET_PROB_TAB_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_VP9_SET_HINT_DUMP_BUF_OFFSET = (0x000005EC) # type: ignore
|
|
NVC9B0_VP9_SET_HINT_DUMP_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_PASS1_SET_CLEAR_HEADER_OFFSET = (0x00000600) # type: ignore
|
|
NVC9B0_PASS1_SET_CLEAR_HEADER_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_PASS1_SET_RE_ENCRYPT_OFFSET = (0x00000604) # type: ignore
|
|
NVC9B0_PASS1_SET_RE_ENCRYPT_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_PASS1_SET_VP8_TOKEN_OFFSET = (0x00000608) # type: ignore
|
|
NVC9B0_PASS1_SET_VP8_TOKEN_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_PASS1_SET_INPUT_DATA_OFFSET = (0x0000060C) # type: ignore
|
|
NVC9B0_PASS1_SET_INPUT_DATA_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_PASS1_SET_OUTPUT_DATA_SIZE_OFFSET = (0x00000610) # type: ignore
|
|
NVC9B0_PASS1_SET_OUTPUT_DATA_SIZE_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_PROB_TAB_READ_BUF_OFFSET = (0x00000640) # type: ignore
|
|
NVC9B0_AV1_SET_PROB_TAB_READ_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_PROB_TAB_WRITE_BUF_OFFSET = (0x00000644) # type: ignore
|
|
NVC9B0_AV1_SET_PROB_TAB_WRITE_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_SEGMENT_READ_BUF_OFFSET = (0x00000648) # type: ignore
|
|
NVC9B0_AV1_SET_SEGMENT_READ_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_SEGMENT_WRITE_BUF_OFFSET = (0x0000064C) # type: ignore
|
|
NVC9B0_AV1_SET_SEGMENT_WRITE_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_COL_MV0_READ_BUF_OFFSET = (0x00000650) # type: ignore
|
|
NVC9B0_AV1_SET_COL_MV0_READ_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_COL_MV1_READ_BUF_OFFSET = (0x00000654) # type: ignore
|
|
NVC9B0_AV1_SET_COL_MV1_READ_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_COL_MV2_READ_BUF_OFFSET = (0x00000658) # type: ignore
|
|
NVC9B0_AV1_SET_COL_MV2_READ_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_COL_MVWRITE_BUF_OFFSET = (0x0000065C) # type: ignore
|
|
NVC9B0_AV1_SET_COL_MVWRITE_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_GLOBAL_MODEL_BUF_OFFSET = (0x00000660) # type: ignore
|
|
NVC9B0_AV1_SET_GLOBAL_MODEL_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_FILM_GRAIN_BUF_OFFSET = (0x00000664) # type: ignore
|
|
NVC9B0_AV1_SET_FILM_GRAIN_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_TILE_STREAM_INFO_BUF_OFFSET = (0x00000668) # type: ignore
|
|
NVC9B0_AV1_SET_TILE_STREAM_INFO_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_SUB_STREAM_ENTRY_BUF_OFFSET = (0x0000066C) # type: ignore
|
|
NVC9B0_AV1_SET_SUB_STREAM_ENTRY_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_AV1_SET_HINT_DUMP_BUF_OFFSET = (0x00000670) # type: ignore
|
|
NVC9B0_AV1_SET_HINT_DUMP_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_H264_SET_SCALING_LIST_OFFSET = (0x00000680) # type: ignore
|
|
NVC9B0_H264_SET_SCALING_LIST_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_H264_SET_VLDHIST_BUF_OFFSET = (0x00000684) # type: ignore
|
|
NVC9B0_H264_SET_VLDHIST_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_H264_SET_EDOBOFFSET0 = (0x00000688) # type: ignore
|
|
NVC9B0_H264_SET_EDOBOFFSET0_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_H264_SET_EDOBOFFSET1 = (0x0000068C) # type: ignore
|
|
NVC9B0_H264_SET_EDOBOFFSET1_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_H264_SET_EDOBOFFSET2 = (0x00000690) # type: ignore
|
|
NVC9B0_H264_SET_EDOBOFFSET2_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_H264_SET_EDOBOFFSET3 = (0x00000694) # type: ignore
|
|
NVC9B0_H264_SET_EDOBOFFSET3_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_CONTENT_INITIAL_VECTOR = lambda b: (0x00000C00 + (b)*0x00000004) # type: ignore
|
|
NVC9B0_SET_CONTENT_INITIAL_VECTOR_VALUE = (31, 0) # type: ignore
|
|
NVC9B0_SET_CTL_COUNT = (0x00000C10) # type: ignore
|
|
NVC9B0_SET_CTL_COUNT_VALUE = (31, 0) # type: ignore
|
|
NVC9B0_SET_UPPER_SRC = (0x00000C14) # type: ignore
|
|
NVC9B0_SET_UPPER_SRC_OFFSET = (7, 0) # type: ignore
|
|
NVC9B0_SET_LOWER_SRC = (0x00000C18) # type: ignore
|
|
NVC9B0_SET_LOWER_SRC_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_UPPER_DST = (0x00000C1C) # type: ignore
|
|
NVC9B0_SET_UPPER_DST_OFFSET = (7, 0) # type: ignore
|
|
NVC9B0_SET_LOWER_DST = (0x00000C20) # type: ignore
|
|
NVC9B0_SET_LOWER_DST_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_BLOCK_COUNT = (0x00000C24) # type: ignore
|
|
NVC9B0_SET_BLOCK_COUNT_VALUE = (31, 0) # type: ignore
|
|
NVC9B0_PR_SET_REQUEST_BUF_OFFSET = (0x00000D00) # type: ignore
|
|
NVC9B0_PR_SET_REQUEST_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_PR_SET_REQUEST_BUF_SIZE = (0x00000D04) # type: ignore
|
|
NVC9B0_PR_SET_REQUEST_BUF_SIZE_SIZE = (31, 0) # type: ignore
|
|
NVC9B0_PR_SET_RESPONSE_BUF_OFFSET = (0x00000D08) # type: ignore
|
|
NVC9B0_PR_SET_RESPONSE_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_PR_SET_RESPONSE_BUF_SIZE = (0x00000D0C) # type: ignore
|
|
NVC9B0_PR_SET_RESPONSE_BUF_SIZE_SIZE = (31, 0) # type: ignore
|
|
NVC9B0_PR_SET_REQUEST_MESSAGE_BUF_OFFSET = (0x00000D10) # type: ignore
|
|
NVC9B0_PR_SET_REQUEST_MESSAGE_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_PR_SET_RESPONSE_MESSAGE_BUF_OFFSET = (0x00000D14) # type: ignore
|
|
NVC9B0_PR_SET_RESPONSE_MESSAGE_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_PR_SET_LOCAL_DECRYPT_BUF_OFFSET = (0x00000D18) # type: ignore
|
|
NVC9B0_PR_SET_LOCAL_DECRYPT_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_PR_SET_LOCAL_DECRYPT_BUF_SIZE = (0x00000D1C) # type: ignore
|
|
NVC9B0_PR_SET_LOCAL_DECRYPT_BUF_SIZE_SIZE = (31, 0) # type: ignore
|
|
NVC9B0_PR_SET_CONTENT_DECRYPT_INFO_BUF_OFFSET = (0x00000D20) # type: ignore
|
|
NVC9B0_PR_SET_CONTENT_DECRYPT_INFO_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_PR_SET_REENCRYPTED_BITSTREAM_BUF_OFFSET = (0x00000D24) # type: ignore
|
|
NVC9B0_PR_SET_REENCRYPTED_BITSTREAM_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_DH_KE_SET_CHALLENGE_BUF_OFFSET = (0x00000E00) # type: ignore
|
|
NVC9B0_DH_KE_SET_CHALLENGE_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_DH_KE_SET_RESPONSE_BUF_OFFSET = (0x00000E04) # type: ignore
|
|
NVC9B0_DH_KE_SET_RESPONSE_BUF_OFFSET_OFFSET = (31, 0) # type: ignore
|
|
NVC9B0_SET_SESSION_KEY = lambda b: (0x00000F00 + (b)*0x00000004) # type: ignore
|
|
NVC9B0_SET_SESSION_KEY_VALUE = (31, 0) # type: ignore
|
|
NVC9B0_SET_CONTENT_KEY = lambda b: (0x00000F10 + (b)*0x00000004) # type: ignore
|
|
NVC9B0_SET_CONTENT_KEY_VALUE = (31, 0) # type: ignore
|
|
NVC9B0_PM_TRIGGER_END = (0x00001114) # type: ignore
|
|
NVC9B0_PM_TRIGGER_END_V = (31, 0) # type: ignore
|
|
NVC9B0_ERROR_NONE = (0x00000000) # type: ignore
|
|
NVC9B0_OS_ERROR_EXECUTE_INSUFFICIENT_DATA = (0x00000001) # type: ignore
|
|
NVC9B0_OS_ERROR_SEMAPHORE_INSUFFICIENT_DATA = (0x00000002) # type: ignore
|
|
NVC9B0_OS_ERROR_INVALID_METHOD = (0x00000003) # type: ignore
|
|
NVC9B0_OS_ERROR_INVALID_DMA_PAGE = (0x00000004) # type: ignore
|
|
NVC9B0_OS_ERROR_UNHANDLED_INTERRUPT = (0x00000005) # type: ignore
|
|
NVC9B0_OS_ERROR_EXCEPTION = (0x00000006) # type: ignore
|
|
NVC9B0_OS_ERROR_INVALID_CTXSW_REQUEST = (0x00000007) # type: ignore
|
|
NVC9B0_OS_ERROR_APPLICATION = (0x00000008) # type: ignore
|
|
NVC9B0_OS_ERROR_SW_BREAKPT = (0x00000009) # type: ignore
|
|
NVC9B0_OS_INTERRUPT_EXECUTE_AWAKEN = (0x00000100) # type: ignore
|
|
NVC9B0_OS_INTERRUPT_BACKEND_SEMAPHORE_AWAKEN = (0x00000200) # type: ignore
|
|
NVC9B0_OS_INTERRUPT_CTX_ERROR_FBIF = (0x00000300) # type: ignore
|
|
NVC9B0_OS_INTERRUPT_LIMIT_VIOLATION = (0x00000400) # type: ignore
|
|
NVC9B0_OS_INTERRUPT_LIMIT_AND_FBIF_CTX_ERROR = (0x00000500) # type: ignore
|
|
NVC9B0_OS_INTERRUPT_HALT_ENGINE = (0x00000600) # type: ignore
|
|
NVC9B0_OS_INTERRUPT_TRAP_NONSTALL = (0x00000700) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_SEQ_DATA_INCONSISTENT = (0x00004001) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_PIC_DATA_INCONSISTENT = (0x00004002) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_SLC_DATA_BUF_ADDR_OUT_OF_BOUNDS = (0x00004100) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_BITSTREAM_ERROR = (0x00004101) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID = (0x000041F8) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_SLC_HDR_OUT_SIZE_NOT_MULT256 = (0x00004200) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_SLC_DATA_OUT_SIZE_NOT_MULT256 = (0x00004201) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID = (0x00004203) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_CTX_DMA_ID_SLC_HDR_OUT_INVALID = (0x00004204) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_SLC_HDR_OUT_BUF_TOO_SMALL = (0x00004205) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_SLC_HDR_OUT_BUF_ALREADY_VALID = (0x00004206) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_SLC_DATA_OUT_BUF_TOO_SMALL = (0x00004207) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_DATA_BUF_CNT_TOO_SMALL = (0x00004208) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_BITSTREAM_EMPTY = (0x00004209) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_FRAME_WIDTH_TOO_LARGE = (0x0000420A) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_FRAME_HEIGHT_TOO_LARGE = (0x0000420B) # type: ignore
|
|
NVC9B0_H264_VLD_ERR_HIST_BUF_TOO_SMALL = (0x00004300) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_PIC_DATA_BUF_ADDR_OUT_OF_BOUND = (0x00005100) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_BITSTREAM_ERROR = (0x00005101) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_PIC_HDR_OUT_SIZE_NOT_MULT256 = (0x00005200) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_PIC_DATA_OUT_SIZE_NOT_MULT256 = (0x00005201) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID = (0x00005202) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID = (0x00005203) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_CTX_DMA_ID_PIC_HDR_OUT_INVALID = (0x00005204) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_SLC_HDR_OUT_BUF_TOO_SMALL = (0x00005205) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_PIC_HDR_OUT_BUF_ALREADY_VALID = (0x00005206) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_PIC_DATA_OUT_BUF_TOO_SMALL = (0x00005207) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_DATA_INFO_IN_BUF_TOO_SMALL = (0x00005208) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_BITSTREAM_EMPTY = (0x00005209) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_FRAME_WIDTH_TOO_LARGE = (0x0000520A) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_FRAME_HEIGHT_TOO_LARGE = (0x0000520B) # type: ignore
|
|
NVC9B0_VC1_VLD_ERR_PIC_DATA_OUT_BUF_FULL_TIME_OUT = (0x00005300) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_SLC_DATA_BUF_ADDR_OUT_OF_BOUNDS = (0x00006100) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_BITSTREAM_ERROR = (0x00006101) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_SLC_DATA_OUT_SIZE_NOT_MULT256 = (0x00006200) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID = (0x00006201) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID = (0x00006202) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_SLC_DATA_OUT_BUF_TOO_SMALL = (0x00006203) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_DATA_INFO_IN_BUF_TOO_SMALL = (0x00006204) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_BITSTREAM_EMPTY = (0x00006205) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_INVALID_PIC_STRUCTURE = (0x00006206) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_INVALID_PIC_CODING_TYPE = (0x00006207) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_FRAME_WIDTH_TOO_LARGE = (0x00006208) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_FRAME_HEIGHT_TOO_LARGE = (0x00006209) # type: ignore
|
|
NVC9B0_MPEG12_VLD_ERR_SLC_DATA_OUT_BUF_FULL_TIME_OUT = (0x00006300) # type: ignore
|
|
NVC9B0_CMN_VLD_ERR_PDEC_RETURNED_ERROR = (0x00007101) # type: ignore
|
|
NVC9B0_CMN_VLD_ERR_EDOB_FLUSH_TIME_OUT = (0x00007102) # type: ignore
|
|
NVC9B0_CMN_VLD_ERR_EDOB_REWIND_TIME_OUT = (0x00007103) # type: ignore
|
|
NVC9B0_CMN_VLD_ERR_VLD_WD_TIME_OUT = (0x00007104) # type: ignore
|
|
NVC9B0_CMN_VLD_ERR_NUM_SLICES_ZERO = (0x00007105) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_PIC_DATA_BUF_ADDR_OUT_OF_BOUND = (0x00008100) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_BITSTREAM_ERROR = (0x00008101) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_PIC_HDR_OUT_SIZE_NOT_MULT256 = (0x00008200) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_PIC_DATA_OUT_SIZE_NOT_MULT256 = (0x00008201) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_CTX_DMA_ID_CTRL_IN_INVALID = (0x00008202) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_CTX_DMA_ID_FLOW_CTRL_INVALID = (0x00008203) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_CTX_DMA_ID_PIC_HDR_OUT_INVALID = (0x00008204) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_SLC_HDR_OUT_BUF_TOO_SMALL = (0x00008205) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_PIC_HDR_OUT_BUF_ALREADY_VALID = (0x00008206) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_PIC_DATA_OUT_BUF_TOO_SMALL = (0x00008207) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_DATA_INFO_IN_BUF_TOO_SMALL = (0x00008208) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_BITSTREAM_EMPTY = (0x00008209) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_FRAME_WIDTH_TOO_LARGE = (0x0000820A) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_FRAME_HEIGHT_TOO_LARGE = (0x0000820B) # type: ignore
|
|
NVC9B0_MPEG4_VLD_ERR_PIC_DATA_OUT_BUF_FULL_TIME_OUT = (0x00051E01) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_APPTIMER_EXPIRED = (0xDEC10001) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_MVTIMER_EXPIRED = (0xDEC10002) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_TOKEN = (0xDEC10003) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_SLICEDATA_MISSING = (0xDEC10004) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_HWERR_INTERRUPT = (0xDEC10005) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_DETECTED_VLD_FAILURE = (0xDEC10006) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_PICTURE_INIT = (0xDEC10100) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_STATEMACHINE_FAILURE = (0xDEC10101) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_CTXID_PIC = (0xDEC10901) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_CTXID_UCODE = (0xDEC10902) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_CTXID_FC = (0xDEC10903) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_CTXID_SLH = (0xDEC10904) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_UCODE_SIZE = (0xDEC10905) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG12_INVALID_SLICE_COUNT = (0xDEC10906) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_APPTIMER_EXPIRED = (0xDEC20001) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_MVTIMER_EXPIRED = (0xDEC20002) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_INVALID_TOKEN = (0xDEC20003) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_SLICEDATA_MISSING = (0xDEC20004) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_HWERR_INTERRUPT = (0xDEC20005) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_DETECTED_VLD_FAILURE = (0xDEC20006) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_TIMEOUT_POLLING_FOR_DATA = (0xDEC20007) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_PDEC_PIC_END_UNALIGNED = (0xDEC20008) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_WDTIMER_EXPIRED = (0xDEC20009) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_ERRINTSTART = (0xDEC20010) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_IQT_ERRINT = (0xDEC20011) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_MC_ERRINT = (0xDEC20012) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_MC_IQT_ERRINT = (0xDEC20013) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_REC_ERRINT = (0xDEC20014) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_REC_IQT_ERRINT = (0xDEC20015) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_REC_MC_ERRINT = (0xDEC20016) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_REC_MC_IQT_ERRINT = (0xDEC20017) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_DBF_ERRINT = (0xDEC20018) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_DBF_IQT_ERRINT = (0xDEC20019) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_DBF_MC_ERRINT = (0xDEC2001A) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_DBF_MC_IQT_ERRINT = (0xDEC2001B) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_DBF_REC_ERRINT = (0xDEC2001C) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_DBF_REC_IQT_ERRINT = (0xDEC2001D) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_DBF_REC_MC_ERRINT = (0xDEC2001E) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_DBF_REC_MC_IQT_ERRINT = (0xDEC2001F) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_PICTURE_INIT = (0xDEC20100) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_STATEMACHINE_FAILURE = (0xDEC20101) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_INVALID_CTXID_PIC = (0xDEC20901) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_INVALID_CTXID_UCODE = (0xDEC20902) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_INVALID_CTXID_FC = (0xDEC20903) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_INVAILD_CTXID_SLH = (0xDEC20904) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_INVALID_UCODE_SIZE = (0xDEC20905) # type: ignore
|
|
NVC9B0_DEC_ERROR_VC1_INVALID_SLICE_COUNT = (0xDEC20906) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_APPTIMER_EXPIRED = (0xDEC30001) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_MVTIMER_EXPIRED = (0xDEC30002) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_INVALID_TOKEN = (0xDEC30003) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_SLICEDATA_MISSING = (0xDEC30004) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_HWERR_INTERRUPT = (0xDEC30005) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_DETECTED_VLD_FAILURE = (0xDEC30006) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_ERRINTSTART = (0xDEC30010) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_IQT_ERRINT = (0xDEC30011) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_MC_ERRINT = (0xDEC30012) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_MC_IQT_ERRINT = (0xDEC30013) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_REC_ERRINT = (0xDEC30014) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_REC_IQT_ERRINT = (0xDEC30015) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_REC_MC_ERRINT = (0xDEC30016) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_REC_MC_IQT_ERRINT = (0xDEC30017) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_DBF_ERRINT = (0xDEC30018) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_DBF_IQT_ERRINT = (0xDEC30019) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_DBF_MC_ERRINT = (0xDEC3001A) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_DBF_MC_IQT_ERRINT = (0xDEC3001B) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_DBF_REC_ERRINT = (0xDEC3001C) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_DBF_REC_IQT_ERRINT = (0xDEC3001D) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_DBF_REC_MC_ERRINT = (0xDEC3001E) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_DBF_REC_MC_IQT_ERRINT = (0xDEC3001F) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_PICTURE_INIT = (0xDEC30100) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_STATEMACHINE_FAILURE = (0xDEC30101) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_INVALID_CTXID_PIC = (0xDEC30901) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_INVALID_CTXID_UCODE = (0xDEC30902) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_INVALID_CTXID_FC = (0xDEC30903) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_INVALID_CTXID_SLH = (0xDEC30904) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_INVALID_UCODE_SIZE = (0xDEC30905) # type: ignore
|
|
NVC9B0_DEC_ERROR_H264_INVALID_SLICE_COUNT = (0xDEC30906) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_APPTIMER_EXPIRED = (0xDEC40001) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_MVTIMER_EXPIRED = (0xDEC40002) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_TOKEN = (0xDEC40003) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_SLICEDATA_MISSING = (0xDEC40004) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_HWERR_INTERRUPT = (0xDEC40005) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_DETECTED_VLD_FAILURE = (0xDEC40006) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_TIMEOUT_POLLING_FOR_DATA = (0xDEC40007) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_PDEC_PIC_END_UNALIGNED = (0xDEC40008) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_WDTIMER_EXPIRED = (0xDEC40009) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_ERRINTSTART = (0xDEC40010) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_IQT_ERRINT = (0xDEC40011) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_MC_ERRINT = (0xDEC40012) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_MC_IQT_ERRINT = (0xDEC40013) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_REC_ERRINT = (0xDEC40014) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_REC_IQT_ERRINT = (0xDEC40015) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_REC_MC_ERRINT = (0xDEC40016) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_REC_MC_IQT_ERRINT = (0xDEC40017) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_ERRINT = (0xDEC40018) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_IQT_ERRINT = (0xDEC40019) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_MC_ERRINT = (0xDEC4001A) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_MC_IQT_ERRINT = (0xDEC4001B) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_REC_ERRINT = (0xDEC4001C) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_REC_IQT_ERRINT = (0xDEC4001D) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_REC_MC_ERRINT = (0xDEC4001E) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_DBF_REC_MC_IQT_ERRINT = (0xDEC4001F) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_PICTURE_INIT = (0xDEC40100) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_STATEMACHINE_FAILURE = (0xDEC40101) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_CTXID_PIC = (0xDEC40901) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_CTXID_UCODE = (0xDEC40902) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_CTXID_FC = (0xDEC40903) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_CTXID_SLH = (0xDEC40904) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_UCODE_SIZE = (0xDEC40905) # type: ignore
|
|
NVC9B0_DEC_ERROR_MPEG4_INVALID_SLICE_COUNT = (0xDEC40906) # type: ignore
|
|
NVC6C0_QMDV02_03_OUTER_PUT = (30, 0) # type: ignore
|
|
NVC6C0_QMDV02_03_OUTER_OVERFLOW = (31, 31) # type: ignore
|
|
NVC6C0_QMDV02_03_OUTER_GET = (62, 32) # type: ignore
|
|
NVC6C0_QMDV02_03_OUTER_STICKY_OVERFLOW = (63, 63) # type: ignore
|
|
NVC6C0_QMDV02_03_INNER_GET = (94, 64) # type: ignore
|
|
NVC6C0_QMDV02_03_INNER_OVERFLOW = (95, 95) # type: ignore
|
|
NVC6C0_QMDV02_03_INNER_PUT = (126, 96) # type: ignore
|
|
NVC6C0_QMDV02_03_INNER_STICKY_OVERFLOW = (127, 127) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_GROUP_ID = (133, 128) # type: ignore
|
|
NVC6C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE = (134, 134) # type: ignore
|
|
NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION = (135, 135) # type: ignore
|
|
NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_IS_QUEUE = (136, 136) # type: ignore
|
|
NVC6C0_QMDV02_03_IS_QUEUE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_IS_QUEUE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137, 137) # type: ignore
|
|
NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 = (138, 138) # type: ignore
|
|
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 = (139, 139) # type: ignore
|
|
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS = (140, 140) # type: ignore
|
|
NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE = (141, 141) # type: ignore
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE = (142, 142) # type: ignore
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY = (143, 143) # type: ignore
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_B = (159, 144) # type: ignore
|
|
NVC6C0_QMDV02_03_CIRCULAR_QUEUE_SIZE = (184, 160) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_C = (185, 185) # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE = (186, 186) # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187, 187) # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE = (188, 188) # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE = (189, 189) # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE = (190, 190) # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE = (191, 191) # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME = (223, 192) # type: ignore
|
|
NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME = (239, 224) # type: ignore
|
|
NVC6C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME = (255, 240) # type: ignore
|
|
NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287, 256) # type: ignore
|
|
NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER = (319, 288) # type: ignore
|
|
NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER = (327, 320) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_D = (335, 328) # type: ignore
|
|
NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE = (351, 336) # type: ignore
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_ID = (357, 352) # type: ignore
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365, 358) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE = (366, 366) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE = (367, 367) # type: ignore
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE = (369, 368) # type: ignore
|
|
NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS = (370, 370) # type: ignore
|
|
NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE = (371, 371) # type: ignore
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT = (378, 378) # type: ignore
|
|
NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_SAMPLER_INDEX = (382, 382) # type: ignore
|
|
NVC6C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_CTA_RASTER_WIDTH = (415, 384) # type: ignore
|
|
NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT = (431, 416) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED13A = (447, 432) # type: ignore
|
|
NVC6C0_QMDV02_03_CTA_RASTER_DEPTH = (463, 448) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED14A = (479, 464) # type: ignore
|
|
NVC6C0_QMDV02_03_DEPENDENT_QMD_POINTER = (511, 480) # type: ignore
|
|
NVC6C0_QMDV02_03_COALESCE_WAITING_PERIOD = (529, 522) # type: ignore
|
|
NVC6C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 = (534, 530) # type: ignore
|
|
NVC6C0_QMDV02_03_SHARED_MEMORY_SIZE = (561, 544) # type: ignore
|
|
NVC6C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE = (568, 562) # type: ignore
|
|
NVC6C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE = (575, 569) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_VERSION = (579, 576) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_MAJOR_VERSION = (583, 580) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_H = (591, 584) # type: ignore
|
|
NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION0 = (607, 592) # type: ignore
|
|
NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION1 = (623, 608) # type: ignore
|
|
NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION2 = (639, 624) # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID = lambda i: ((640+(i)*1), (640+(i)*1)) # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_REGISTER_COUNT_V = (656, 648) # type: ignore
|
|
NVC6C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (663, 657) # type: ignore
|
|
NVC6C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM = (671, 664) # type: ignore
|
|
NVC6C0_QMDV02_03_SM_DISABLE_MASK_LOWER = (703, 672) # type: ignore
|
|
NVC6C0_QMDV02_03_SM_DISABLE_MASK_UPPER = (735, 704) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_ADDRESS_LOWER = (767, 736) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_ADDRESS_UPPER = (775, 768) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_J = (783, 776) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP = (790, 788) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007 # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_K = (791, 791) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT = (793, 792) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE = (794, 794) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE = (799, 799) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE0_PAYLOAD = (831, 800) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_ADDRESS_LOWER = (863, 832) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_ADDRESS_UPPER = (871, 864) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_L = (879, 872) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP = (886, 884) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007 # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_M = (887, 887) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT = (889, 888) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE = (890, 890) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE = (895, 895) # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_RELEASE1_PAYLOAD = (927, 896) # type: ignore
|
|
NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE = (951, 928) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_N = (954, 952) # type: ignore
|
|
NVC6C0_QMDV02_03_BARRIER_COUNT = (959, 955) # type: ignore
|
|
NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE = (983, 960) # type: ignore
|
|
NVC6C0_QMDV02_03_REGISTER_COUNT = (991, 984) # type: ignore
|
|
NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1000, 992) # type: ignore
|
|
NVC6C0_QMDV02_03_PROGRAM_PREFETCH_SIZE = (1009, 1001) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_A = (1015, 1010) # type: ignore
|
|
NVC6C0_QMDV02_03_SASS_VERSION = (1023, 1016) # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER = lambda i: ((1055+(i)*64), (1024+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER = lambda i: ((1072+(i)*64), (1056+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST = lambda i: ((1073+(i)*64), (1073+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1074+(i)*64), (1074+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1087+(i)*64), (1075+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_03_PROGRAM_ADDRESS_LOWER = (1567, 1536) # type: ignore
|
|
NVC6C0_QMDV02_03_PROGRAM_ADDRESS_UPPER = (1584, 1568) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_S = (1599, 1585) # type: ignore
|
|
NVC6C0_QMDV02_03_HW_ONLY_INNER_GET = (1630, 1600) # type: ignore
|
|
NVC6C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1631, 1631) # type: ignore
|
|
NVC6C0_QMDV02_03_HW_ONLY_INNER_PUT = (1662, 1632) # type: ignore
|
|
NVC6C0_QMDV02_03_HW_ONLY_SCG_TYPE = (1663, 1663) # type: ignore
|
|
NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1693, 1664) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_RESERVED_Q = (1694, 1694) # type: ignore
|
|
NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1695, 1695) # type: ignore
|
|
NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER = (1727, 1696) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_SPARE_G = (1759, 1728) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_SPARE_H = (1791, 1760) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_SPARE_I = (1823, 1792) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_SPARE_J = (1855, 1824) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_SPARE_K = (1887, 1856) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_SPARE_L = (1919, 1888) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_SPARE_M = (1951, 1920) # type: ignore
|
|
NVC6C0_QMDV02_03_QMD_SPARE_N = (1983, 1952) # type: ignore
|
|
NVC6C0_QMDV02_03_DEBUG_ID_UPPER = (2015, 1984) # type: ignore
|
|
NVC6C0_QMDV02_03_DEBUG_ID_LOWER = (2047, 2016) # type: ignore
|
|
NVC6C0_QMDV02_04_OUTER_PUT = (30, 0) # type: ignore
|
|
NVC6C0_QMDV02_04_OUTER_OVERFLOW = (31, 31) # type: ignore
|
|
NVC6C0_QMDV02_04_OUTER_GET = (62, 32) # type: ignore
|
|
NVC6C0_QMDV02_04_OUTER_STICKY_OVERFLOW = (63, 63) # type: ignore
|
|
NVC6C0_QMDV02_04_INNER_GET = (94, 64) # type: ignore
|
|
NVC6C0_QMDV02_04_INNER_OVERFLOW = (95, 95) # type: ignore
|
|
NVC6C0_QMDV02_04_INNER_PUT = (126, 96) # type: ignore
|
|
NVC6C0_QMDV02_04_INNER_STICKY_OVERFLOW = (127, 127) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_GROUP_ID = (133, 128) # type: ignore
|
|
NVC6C0_QMDV02_04_SM_GLOBAL_CACHING_ENABLE = (134, 134) # type: ignore
|
|
NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION = (135, 135) # type: ignore
|
|
NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_IS_QUEUE = (136, 136) # type: ignore
|
|
NVC6C0_QMDV02_04_IS_QUEUE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_IS_QUEUE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137, 137) # type: ignore
|
|
NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0 = (138, 138) # type: ignore
|
|
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1 = (139, 139) # type: ignore
|
|
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS = (140, 140) # type: ignore
|
|
NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE = (141, 141) # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION = (144, 142) # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH = (145, 145) # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE = (146, 146) # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION = (149, 147) # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH = (150, 150) # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENCE_COUNTER = (157, 151) # type: ignore
|
|
NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION = (158, 158) # type: ignore
|
|
NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_B = (159, 159) # type: ignore
|
|
NVC6C0_QMDV02_04_CIRCULAR_QUEUE_SIZE = (184, 160) # type: ignore
|
|
NVC6C0_QMDV02_04_DEMOTE_L2_EVICT_LAST = (185, 185) # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE = (186, 186) # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187, 187) # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE = (188, 188) # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE = (189, 189) # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE = (190, 190) # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE = (191, 191) # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_CTA_RASTER_WIDTH_RESUME = (223, 192) # type: ignore
|
|
NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT_RESUME = (239, 224) # type: ignore
|
|
NVC6C0_QMDV02_04_CTA_RASTER_DEPTH_RESUME = (255, 240) # type: ignore
|
|
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287, 256) # type: ignore
|
|
NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_LOWER = (319, 288) # type: ignore
|
|
NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_UPPER = (327, 320) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_D = (335, 328) # type: ignore
|
|
NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ENTRY_SIZE = (351, 336) # type: ignore
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_ID = (357, 352) # type: ignore
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365, 358) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE = (366, 366) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE = (367, 367) # type: ignore
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE = (369, 368) # type: ignore
|
|
NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS = (370, 370) # type: ignore
|
|
NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE = (371, 371) # type: ignore
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT = (378, 378) # type: ignore
|
|
NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_SAMPLER_INDEX = (382, 382) # type: ignore
|
|
NVC6C0_QMDV02_04_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE = (383, 383) # type: ignore
|
|
NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_CTA_RASTER_WIDTH = (415, 384) # type: ignore
|
|
NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT = (431, 416) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED13A = (447, 432) # type: ignore
|
|
NVC6C0_QMDV02_04_CTA_RASTER_DEPTH = (463, 448) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED14A = (479, 464) # type: ignore
|
|
NVC6C0_QMDV02_04_DEPENDENT_QMD0_POINTER = (511, 480) # type: ignore
|
|
NVC6C0_QMDV02_04_COALESCE_WAITING_PERIOD = (529, 522) # type: ignore
|
|
NVC6C0_QMDV02_04_QUEUE_ENTRIES_PER_CTA_LOG2 = (534, 530) # type: ignore
|
|
NVC6C0_QMDV02_04_SHARED_MEMORY_SIZE = (561, 544) # type: ignore
|
|
NVC6C0_QMDV02_04_MIN_SM_CONFIG_SHARED_MEM_SIZE = (568, 562) # type: ignore
|
|
NVC6C0_QMDV02_04_MAX_SM_CONFIG_SHARED_MEM_SIZE = (575, 569) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_VERSION = (579, 576) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_MAJOR_VERSION = (583, 580) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_H = (591, 584) # type: ignore
|
|
NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION0 = (607, 592) # type: ignore
|
|
NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION1 = (623, 608) # type: ignore
|
|
NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION2 = (639, 624) # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID = lambda i: ((640+(i)*1), (640+(i)*1)) # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_REGISTER_COUNT_V = (656, 648) # type: ignore
|
|
NVC6C0_QMDV02_04_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (663, 657) # type: ignore
|
|
NVC6C0_QMDV02_04_FREE_CTA_SLOTS_EMPTY_SM = (671, 664) # type: ignore
|
|
NVC6C0_QMDV02_04_SM_DISABLE_MASK_LOWER = (703, 672) # type: ignore
|
|
NVC6C0_QMDV02_04_SM_DISABLE_MASK_UPPER = (735, 704) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_ADDRESS_LOWER = (767, 736) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_ADDRESS_UPPER = (775, 768) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_J = (783, 776) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP = (790, 788) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007 # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_K = (791, 791) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT = (793, 792) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE = (794, 794) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE = (799, 799) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE0_PAYLOAD = (831, 800) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_ADDRESS_LOWER = (863, 832) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_ADDRESS_UPPER = (871, 864) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_L = (879, 872) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP = (886, 884) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007 # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_M = (887, 887) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT = (889, 888) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE = (890, 890) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE = (895, 895) # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_RELEASE1_PAYLOAD = (927, 896) # type: ignore
|
|
NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_LOW_SIZE = (951, 928) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_N = (954, 952) # type: ignore
|
|
NVC6C0_QMDV02_04_BARRIER_COUNT = (959, 955) # type: ignore
|
|
NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_HIGH_SIZE = (983, 960) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_G = (991, 984) # type: ignore
|
|
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1000, 992) # type: ignore
|
|
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_SIZE = (1009, 1001) # type: ignore
|
|
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE = (1011, 1010) # type: ignore
|
|
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_A = (1015, 1012) # type: ignore
|
|
NVC6C0_QMDV02_04_SASS_VERSION = (1023, 1016) # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_LOWER = lambda i: ((1055+(i)*64), (1024+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_UPPER = lambda i: ((1072+(i)*64), (1056+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST = lambda i: ((1073+(i)*64), (1073+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1074+(i)*64), (1074+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1087+(i)*64), (1075+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV02_04_PROGRAM_ADDRESS_LOWER = (1567, 1536) # type: ignore
|
|
NVC6C0_QMDV02_04_PROGRAM_ADDRESS_UPPER = (1584, 1568) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_S = (1599, 1585) # type: ignore
|
|
NVC6C0_QMDV02_04_HW_ONLY_INNER_GET = (1630, 1600) # type: ignore
|
|
NVC6C0_QMDV02_04_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1631, 1631) # type: ignore
|
|
NVC6C0_QMDV02_04_HW_ONLY_INNER_PUT = (1662, 1632) # type: ignore
|
|
NVC6C0_QMDV02_04_HW_ONLY_SCG_TYPE = (1663, 1663) # type: ignore
|
|
NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1693, 1664) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_Q = (1694, 1694) # type: ignore
|
|
NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1695, 1695) # type: ignore
|
|
NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV02_04_HW_ONLY_SKED_NEXT_QMD_POINTER = (1727, 1696) # type: ignore
|
|
NVC6C0_QMDV02_04_HW_ONLY_DEPENDENCE_COUNTER = (1734, 1728) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_RESERVED_I = (1759, 1735) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_SPARE_H = (1791, 1760) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_SPARE_I = (1823, 1792) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_SPARE_J = (1855, 1824) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_SPARE_K = (1887, 1856) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_SPARE_L = (1919, 1888) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_SPARE_M = (1951, 1920) # type: ignore
|
|
NVC6C0_QMDV02_04_QMD_SPARE_N = (1983, 1952) # type: ignore
|
|
NVC6C0_QMDV02_04_DEBUG_ID_UPPER = (2015, 1984) # type: ignore
|
|
NVC6C0_QMDV02_04_DEBUG_ID_LOWER = (2047, 2016) # type: ignore
|
|
NVC6C0_QMDV03_00_OUTER_PUT = (30, 0) # type: ignore
|
|
NVC6C0_QMDV03_00_OUTER_OVERFLOW = (31, 31) # type: ignore
|
|
NVC6C0_QMDV03_00_OUTER_GET = (62, 32) # type: ignore
|
|
NVC6C0_QMDV03_00_OUTER_STICKY_OVERFLOW = (63, 63) # type: ignore
|
|
NVC6C0_QMDV03_00_INNER_GET = (94, 64) # type: ignore
|
|
NVC6C0_QMDV03_00_INNER_OVERFLOW = (95, 95) # type: ignore
|
|
NVC6C0_QMDV03_00_INNER_PUT = (126, 96) # type: ignore
|
|
NVC6C0_QMDV03_00_INNER_STICKY_OVERFLOW = (127, 127) # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_GROUP_ID = (133, 128) # type: ignore
|
|
NVC6C0_QMDV03_00_SM_GLOBAL_CACHING_ENABLE = (134, 134) # type: ignore
|
|
NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION = (135, 135) # type: ignore
|
|
NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_IS_QUEUE = (136, 136) # type: ignore
|
|
NVC6C0_QMDV03_00_IS_QUEUE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_IS_QUEUE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137, 137) # type: ignore
|
|
NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_RESERVED04A = (139, 138) # type: ignore
|
|
NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS = (140, 140) # type: ignore
|
|
NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_RESERVED04B = (141, 141) # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENCE_COUNTER = (157, 142) # type: ignore
|
|
NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION = (158, 158) # type: ignore
|
|
NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_RESERVED04C = (159, 159) # type: ignore
|
|
NVC6C0_QMDV03_00_CIRCULAR_QUEUE_SIZE = (184, 160) # type: ignore
|
|
NVC6C0_QMDV03_00_DEMOTE_L2_EVICT_LAST = (185, 185) # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE = (186, 186) # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187, 187) # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE = (188, 188) # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE = (189, 189) # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE = (190, 190) # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE = (191, 191) # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_CTA_RASTER_WIDTH_RESUME = (223, 192) # type: ignore
|
|
NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT_RESUME = (239, 224) # type: ignore
|
|
NVC6C0_QMDV03_00_CTA_RASTER_DEPTH_RESUME = (255, 240) # type: ignore
|
|
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287, 256) # type: ignore
|
|
NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_LOWER = (319, 288) # type: ignore
|
|
NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_UPPER = (327, 320) # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_RESERVED_D = (335, 328) # type: ignore
|
|
NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ENTRY_SIZE = (351, 336) # type: ignore
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_ID = (357, 352) # type: ignore
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365, 358) # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_RESERVED11A = (366, 366) # type: ignore
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE = (367, 367) # type: ignore
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE = (369, 368) # type: ignore
|
|
NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS = (370, 370) # type: ignore
|
|
NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE = (371, 371) # type: ignore
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_RESERVED11B = (377, 372) # type: ignore
|
|
NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT = (378, 378) # type: ignore
|
|
NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_RESERVED11C = (381, 379) # type: ignore
|
|
NVC6C0_QMDV03_00_SAMPLER_INDEX = (382, 382) # type: ignore
|
|
NVC6C0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE = (383, 383) # type: ignore
|
|
NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_CTA_RASTER_WIDTH = (415, 384) # type: ignore
|
|
NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT = (431, 416) # type: ignore
|
|
NVC6C0_QMDV03_00_CTA_RASTER_DEPTH = (463, 448) # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_POINTER = (511, 480) # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE = (512, 512) # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION = (515, 513) # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH = (516, 516) # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE = (517, 517) # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION = (520, 518) # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH = (521, 521) # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_COALESCE_WAITING_PERIOD = (529, 522) # type: ignore
|
|
NVC6C0_QMDV03_00_QUEUE_ENTRIES_PER_CTA_LOG2 = (534, 530) # type: ignore
|
|
NVC6C0_QMDV03_00_SHARED_MEMORY_SIZE = (561, 544) # type: ignore
|
|
NVC6C0_QMDV03_00_MIN_SM_CONFIG_SHARED_MEM_SIZE = (567, 562) # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_RESERVED17A = (568, 568) # type: ignore
|
|
NVC6C0_QMDV03_00_MAX_SM_CONFIG_SHARED_MEM_SIZE = (574, 569) # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_RESERVED17B = (575, 575) # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_VERSION = (579, 576) # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_MAJOR_VERSION = (583, 580) # type: ignore
|
|
NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION0 = (607, 592) # type: ignore
|
|
NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION1 = (623, 608) # type: ignore
|
|
NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION2 = (639, 624) # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID = lambda i: ((640+(i)*1), (640+(i)*1)) # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_REGISTER_COUNT_V = (656, 648) # type: ignore
|
|
NVC6C0_QMDV03_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (662, 657) # type: ignore
|
|
NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE = (663, 663) # type: ignore
|
|
NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_FREE_CTA_SLOTS_EMPTY_SM = (671, 664) # type: ignore
|
|
NVC6C0_QMDV03_00_SM_DISABLE_MASK_LOWER = (703, 672) # type: ignore
|
|
NVC6C0_QMDV03_00_SM_DISABLE_MASK_UPPER = (735, 704) # type: ignore
|
|
NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_LOW_SIZE = (759, 736) # type: ignore
|
|
NVC6C0_QMDV03_00_BARRIER_COUNT = (767, 763) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_ADDRESS_LOWER = (799, 768) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_ADDRESS_UPPER = (807, 800) # type: ignore
|
|
NVC6C0_QMDV03_00_SEMAPHORE_RESERVED25A = (818, 808) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE = (819, 819) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP = (822, 820) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_ENABLE = (823, 823) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT = (825, 824) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE = (826, 826) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE = (828, 827) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B = (829, 829) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE = (831, 830) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_LOWER = (863, 832) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_UPPER = (895, 864) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_ADDRESS_LOWER = (927, 896) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_ADDRESS_UPPER = (935, 928) # type: ignore
|
|
NVC6C0_QMDV03_00_SEMAPHORE_RESERVED29A = (946, 936) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE = (947, 947) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP = (950, 948) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_ENABLE = (951, 951) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT = (953, 952) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE = (954, 954) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE = (956, 955) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B = (957, 957) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE = (959, 958) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_LOWER = (991, 960) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_UPPER = (1023, 992) # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_LOWER = lambda i: ((1055+(i)*64), (1024+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_UPPER = lambda i: ((1072+(i)*64), (1056+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST = lambda i: ((1073+(i)*64), (1073+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1074+(i)*64), (1074+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1087+(i)*64), (1075+(i)*64)) # type: ignore
|
|
NVC6C0_QMDV03_00_PROGRAM_ADDRESS_LOWER = (1567, 1536) # type: ignore
|
|
NVC6C0_QMDV03_00_PROGRAM_ADDRESS_UPPER = (1584, 1568) # type: ignore
|
|
NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_HIGH_SIZE = (1623, 1600) # type: ignore
|
|
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1640, 1632) # type: ignore
|
|
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_SIZE = (1649, 1641) # type: ignore
|
|
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE = (1651, 1650) # type: ignore
|
|
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_SASS_VERSION = (1663, 1656) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_ADDRESS_LOWER = (1695, 1664) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_ADDRESS_UPPER = (1703, 1696) # type: ignore
|
|
NVC6C0_QMDV03_00_SEMAPHORE_RESERVED53A = (1714, 1704) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE = (1715, 1715) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP = (1718, 1716) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC = 0x00000003 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC = 0x00000004 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND = 0x00000005 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR = 0x00000006 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR = 0x00000007 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_ENABLE = (1719, 1719) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT = (1721, 1720) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE = (1722, 1722) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE = (1724, 1723) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B = (1725, 1725) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE = (1727, 1726) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_LOWER = (1759, 1728) # type: ignore
|
|
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_UPPER = (1791, 1760) # type: ignore
|
|
NVC6C0_QMDV03_00_QMD_SPARE_I = (1823, 1792) # type: ignore
|
|
NVC6C0_QMDV03_00_HW_ONLY_INNER_GET = (1854, 1824) # type: ignore
|
|
NVC6C0_QMDV03_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1855, 1855) # type: ignore
|
|
NVC6C0_QMDV03_00_HW_ONLY_INNER_PUT = (1886, 1856) # type: ignore
|
|
NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1917, 1888) # type: ignore
|
|
NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1919, 1919) # type: ignore
|
|
NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_QMDV03_00_HW_ONLY_SKED_NEXT_QMD_POINTER = (1951, 1920) # type: ignore
|
|
NVC6C0_QMDV03_00_HW_ONLY_DEPENDENCE_COUNTER = (1958, 1952) # type: ignore
|
|
NVC6C0_QMDV03_00_DEBUG_ID_UPPER = (2015, 1984) # type: ignore
|
|
NVC6C0_QMDV03_00_DEBUG_ID_LOWER = (2047, 2016) # type: ignore
|
|
NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX = (29, 0) # type: ignore
|
|
NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (30, 30) # type: ignore
|
|
NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (31, 31) # type: ignore
|
|
NVCEC0_QMDV05_00_HW_ONLY_SKED_NEXT_QMD_POINTER = (63, 32) # type: ignore
|
|
NVCEC0_QMDV05_00_INNER_GET = (94, 64) # type: ignore
|
|
NVCEC0_QMDV05_00_INNER_OVERFLOW = (95, 95) # type: ignore
|
|
NVCEC0_QMDV05_00_INNER_PUT = (126, 96) # type: ignore
|
|
NVCEC0_QMDV05_00_INNER_STICKY_OVERFLOW = (127, 127) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENCE_COUNTER = (143, 128) # type: ignore
|
|
NVCEC0_QMDV05_00_QMD_GROUP_ID = (149, 144) # type: ignore
|
|
NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (150, 150) # type: ignore
|
|
NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_QMD_TYPE = (153, 151) # type: ignore
|
|
NVCEC0_QMDV05_00_QMD_TYPE_QUEUE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_QMD_TYPE_GRID_NULL = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_QMD_TYPE_GRID_CTA = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPC_CGA = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_CGA = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005 # type: ignore
|
|
NVCEC0_QMDV05_00_NUM_SUB_TASKS_PER_TASK = (157, 154) # type: ignore
|
|
NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS = (158, 158) # type: ignore
|
|
NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID = (159, 159) # type: ignore
|
|
NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_CIRCULAR_QUEUE_SIZE = (184, 160) # type: ignore
|
|
NVCEC0_QMDV05_00_HW_ONLY_DEPENDENCE_COUNTER = (207, 192) # type: ignore
|
|
NVCEC0_QMDV05_00_RESUME_SUB_TASK_ID = (210, 208) # type: ignore
|
|
NVCEC0_QMDV05_00_COMPLETED_SUB_TASK_MASK = (218, 211) # type: ignore
|
|
NVCEC0_QMDV05_00_GRID_WIDTH_RESUME = (255, 224) # type: ignore
|
|
NVCEC0_QMDV05_00_GRID_HEIGHT_RESUME = (271, 256) # type: ignore
|
|
NVCEC0_QMDV05_00_GRID_DEPTH_RESUME = (287, 272) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_ENABLE = lambda i: ((288+(i)*16), (288+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE0_ENABLE = NVCEC0_QMDV05_00_RELEASE_ENABLE(0) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE1_ENABLE = NVCEC0_QMDV05_00_RELEASE_ENABLE(1) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE = lambda i: ((290+(i)*16), (289+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE = lambda i: ((291+(i)*16), (291+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE = lambda i: ((292+(i)*16), (292+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP = lambda i: ((295+(i)*16), (293+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_INC = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_AND = 0x00000005 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_OR = 0x00000006 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT = lambda i: ((297+(i)*16), (296+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE = lambda i: ((299+(i)*16), (298+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B = lambda i: ((300+(i)*16), (300+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_RESERVED_INFO = lambda i: ((303+(i)*16), (301+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE = (336, 336) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION = (339, 337) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH = (340, 340) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION = (341, 341) # type: ignore
|
|
NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST = (342, 342) # type: ignore
|
|
NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE = (343, 343) # type: ignore
|
|
NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE = (344, 344) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION = (347, 345) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH = (348, 348) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL = (349, 349) # type: ignore
|
|
NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE = (350, 350) # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE = (351, 351) # type: ignore
|
|
NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_CORRELATION_ID = (383, 352) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD0_POINTER = (415, 384) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD1_POINTER = (447, 416) # type: ignore
|
|
NVCEC0_QMDV05_00_SASS_VERSION = (455, 448) # type: ignore
|
|
NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT = (456, 456) # type: ignore
|
|
NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_SAMPLER_INDEX = (457, 457) # type: ignore
|
|
NVCEC0_QMDV05_00_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (463, 458) # type: ignore
|
|
NVCEC0_QMDV05_00_QMD_MINOR_VERSION = (467, 464) # type: ignore
|
|
NVCEC0_QMDV05_00_QMD_MAJOR_VERSION = (471, 468) # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE = (472, 472) # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE = (473, 473) # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE = (474, 474) # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE = (475, 475) # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE = (476, 476) # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE = (477, 477) # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (478, 478) # type: ignore
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (479, 479) # type: ignore
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_LOWER = (511, 480) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_UPPER = (536, 512) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (575, 544) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (607, 576) # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (615, 608) # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_ID = (621, 616) # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE = (622, 622) # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE = (623, 623) # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE = (625, 624) # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE = (626, 626) # type: ignore
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_CTA_LAUNCH_QUEUE = (627, 627) # type: ignore
|
|
NVCEC0_QMDV05_00_FREE_CTA_SLOTS_EMPTY_SM = (635, 628) # type: ignore
|
|
NVCEC0_QMDV05_00_SYNC_DOMAIN_ID = (637, 636) # type: ignore
|
|
NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH = (638, 638) # type: ignore
|
|
NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT = (639, 639) # type: ignore
|
|
NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_ID = (671, 640) # type: ignore
|
|
NVCEC0_QMDV05_00_WAIT_ON_LATCH_ID = (703, 672) # type: ignore
|
|
NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_SHARED_MEM = (721, 714) # type: ignore
|
|
NVCEC0_QMDV05_00_OCCUPANCY_MAX_SHARED_MEM = (729, 722) # type: ignore
|
|
NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID = (730, 730) # type: ignore
|
|
NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID = (731, 731) # type: ignore
|
|
NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE = (732, 732) # type: ignore
|
|
NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE = (733, 733) # type: ignore
|
|
NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE = (734, 734) # type: ignore
|
|
NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE = (735, 735) # type: ignore
|
|
NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_WARP = (743, 736) # type: ignore
|
|
NVCEC0_QMDV05_00_OCCUPANCY_MAX_WARP = (751, 744) # type: ignore
|
|
NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_REGISTER = (759, 752) # type: ignore
|
|
NVCEC0_QMDV05_00_OCCUPANCY_MAX_REGISTER = (767, 760) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_LOWER = (799, 768) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_UPPER = (824, 800) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_LOWER = (863, 832) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_UPPER = (895, 864) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_LOWER = (927, 896) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_UPPER = (952, 928) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_LOWER = (991, 960) # type: ignore
|
|
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_UPPER = (1023, 992) # type: ignore
|
|
NVCEC0_QMDV05_00_PROGRAM_ADDRESS_LOWER_SHIFTED4 = (1055, 1024) # type: ignore
|
|
NVCEC0_QMDV05_00_PROGRAM_ADDRESS_UPPER_SHIFTED4 = (1076, 1056) # type: ignore
|
|
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_SIZE = (1085, 1077) # type: ignore
|
|
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE = (1087, 1086) # type: ignore
|
|
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION0 = (1103, 1088) # type: ignore
|
|
NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION1 = (1119, 1104) # type: ignore
|
|
NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION2 = (1127, 1120) # type: ignore
|
|
NVCEC0_QMDV05_00_REGISTER_COUNT = (1136, 1128) # type: ignore
|
|
NVCEC0_QMDV05_00_BARRIER_COUNT = (1141, 1137) # type: ignore
|
|
NVCEC0_QMDV05_00_ICC_PREFETCH_SIZE = (1147, 1142) # type: ignore
|
|
NVCEC0_QMDV05_00_SHARED_MEMORY_SIZE_SHIFTED7 = (1162, 1152) # type: ignore
|
|
NVCEC0_QMDV05_00_MIN_SM_CONFIG_SHARED_MEM_SIZE = (1168, 1163) # type: ignore
|
|
NVCEC0_QMDV05_00_MAX_SM_CONFIG_SHARED_MEM_SIZE = (1174, 1169) # type: ignore
|
|
NVCEC0_QMDV05_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (1180, 1175) # type: ignore
|
|
NVCEC0_QMDV05_00_SHARED_MEM_BARRIER_INIT_ENABLE = (1181, 1181) # type: ignore
|
|
NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4 = (1199, 1184) # type: ignore
|
|
NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4 = (1215, 1200) # type: ignore
|
|
NVCEC0_QMDV05_00_VIRTUAL_RESOURCE_COUNT = (1223, 1216) # type: ignore
|
|
NVCEC0_QMDV05_00_GRID_WIDTH = (1279, 1248) # type: ignore
|
|
NVCEC0_QMDV05_00_GRID_HEIGHT = (1295, 1280) # type: ignore
|
|
NVCEC0_QMDV05_00_GRID_DEPTH = (1327, 1312) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6 = lambda i: ((1375+(i)*64), (1344+(i)*64)) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6 = lambda i: ((1394+(i)*64), (1376+(i)*64)) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1407+(i)*64), (1395+(i)*64)) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID = lambda i: ((1856+(i)*4), (1856+(i)*4)) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH = lambda i: ((1858+(i)*4), (1857+(i)*4)) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1859+(i)*4), (1859+(i)*4)) # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (1919, 1888) # type: ignore
|
|
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1936, 1920) # type: ignore
|
|
NVCEC0_QMDV05_00_GPC_CGA_WIDTH = (2053, 2048) # type: ignore
|
|
NVCEC0_QMDV05_00_GPC_CGA_HEIGHT = (2061, 2056) # type: ignore
|
|
NVCEC0_QMDV05_00_GPC_CGA_DEPTH = (2069, 2064) # type: ignore
|
|
NVCEC0_QMDV05_00_LARGE_GPC_CGA_WIDTH_MINUS_ONE = (2075, 2072) # type: ignore
|
|
NVCEC0_QMDV05_00_LARGE_GPC_CGA_HEIGHT_MINUS_ONE = (2079, 2076) # type: ignore
|
|
NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE = (2111, 2111) # type: ignore
|
|
NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_GPU_CGA_WIDTH = (2127, 2112) # type: ignore
|
|
NVCEC0_QMDV05_00_GPU_CGA_HEIGHT = (2143, 2128) # type: ignore
|
|
NVCEC0_QMDV05_00_GPU_CGA_DEPTH = (2159, 2144) # type: ignore
|
|
NVCEC0_QMDV05_00_DEBUG_ID_LOWER = (2207, 2176) # type: ignore
|
|
NVCEC0_QMDV05_00_DEBUG_ID_UPPER = (2239, 2208) # type: ignore
|
|
NVCEC0_QMDV05_00_TPC_DISABLE_MASK = lambda i: ((2271+(i)*32), (2240+(i)*32)) # type: ignore
|
|
NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_WIDTH_RESUME = (2527, 2496) # type: ignore
|
|
NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_HEIGHT_RESUME = (2543, 2528) # type: ignore
|
|
NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_DEPTH_RESUME = (2559, 2544) # type: ignore
|
|
NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME = (2563, 2560) # type: ignore
|
|
NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME = (2567, 2564) # type: ignore
|
|
NVCEC0_QMDV05_00_QUEUE_ENTRIES_PER_CTA_LOG2 = (2596, 2592) # type: ignore
|
|
NVCEC0_QMDV05_00_HW_ONLY_INNER_GET = (2654, 2624) # type: ignore
|
|
NVCEC0_QMDV05_00_HW_ONLY_INNER_PUT = (2686, 2656) # type: ignore
|
|
NVCEC0_QMDV05_00_OUTER_PUT = (3038, 3008) # type: ignore
|
|
NVCEC0_QMDV05_00_OUTER_OVERFLOW = (3039, 3039) # type: ignore
|
|
NVCEC0_QMDV05_00_OUTER_GET = (3070, 3040) # type: ignore
|
|
NVCEC0_QMDV05_00_OUTER_STICKY_OVERFLOW = (3071, 3071) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE = lambda i: ((336+(i)*8), (336+(i)*8)) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION = lambda i: ((339+(i)*8), (337+(i)*8)) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH = lambda i: ((340+(i)*8), (340+(i)*8)) # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_00_DEPENDENT_QMD_POINTER = lambda i: ((415+(i)*32), (384+(i)*32)) # type: ignore
|
|
NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX = (29, 0) # type: ignore
|
|
NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (30, 30) # type: ignore
|
|
NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (31, 31) # type: ignore
|
|
NVCEC0_QMDV05_01_HW_ONLY_SKED_NEXT_QMD_POINTER = (63, 32) # type: ignore
|
|
NVCEC0_QMDV05_01_INNER_GET = (94, 64) # type: ignore
|
|
NVCEC0_QMDV05_01_INNER_OVERFLOW = (95, 95) # type: ignore
|
|
NVCEC0_QMDV05_01_INNER_PUT = (126, 96) # type: ignore
|
|
NVCEC0_QMDV05_01_INNER_STICKY_OVERFLOW = (127, 127) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENCE_COUNTER = (143, 128) # type: ignore
|
|
NVCEC0_QMDV05_01_QMD_GROUP_ID = (149, 144) # type: ignore
|
|
NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (150, 150) # type: ignore
|
|
NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_QMD_TYPE = (153, 151) # type: ignore
|
|
NVCEC0_QMDV05_01_QMD_TYPE_QUEUE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_QMD_TYPE_GRID_NULL = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_QMD_TYPE_GRID_CTA = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPC_CGA = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_CGA = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005 # type: ignore
|
|
NVCEC0_QMDV05_01_NUM_SUB_TASKS_PER_TASK = (157, 154) # type: ignore
|
|
NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS = (158, 158) # type: ignore
|
|
NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID = (159, 159) # type: ignore
|
|
NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_CIRCULAR_QUEUE_SIZE = (184, 160) # type: ignore
|
|
NVCEC0_QMDV05_01_HW_ONLY_DEPENDENCE_COUNTER = (207, 192) # type: ignore
|
|
NVCEC0_QMDV05_01_RESUME_SUB_TASK_ID = (210, 208) # type: ignore
|
|
NVCEC0_QMDV05_01_COMPLETED_SUB_TASK_MASK = (218, 211) # type: ignore
|
|
NVCEC0_QMDV05_01_GRID_WIDTH_RESUME = (255, 224) # type: ignore
|
|
NVCEC0_QMDV05_01_GRID_HEIGHT_RESUME = (271, 256) # type: ignore
|
|
NVCEC0_QMDV05_01_GRID_DEPTH_RESUME = (287, 272) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_ENABLE = lambda i: ((288+(i)*16), (288+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE = lambda i: ((290+(i)*16), (289+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE = lambda i: ((291+(i)*16), (291+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE = lambda i: ((292+(i)*16), (292+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP = lambda i: ((295+(i)*16), (293+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_INC = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_AND = 0x00000005 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_OR = 0x00000006 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT = lambda i: ((297+(i)*16), (296+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE = lambda i: ((299+(i)*16), (298+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B = lambda i: ((300+(i)*16), (300+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_RESERVED_INFO = lambda i: ((303+(i)*16), (301+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE = (336, 336) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION = (339, 337) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH = (340, 340) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION = (341, 341) # type: ignore
|
|
NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST = (342, 342) # type: ignore
|
|
NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE = (343, 343) # type: ignore
|
|
NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE = (344, 344) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION = (347, 345) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH = (348, 348) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL = (349, 349) # type: ignore
|
|
NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE = (350, 350) # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE = (351, 351) # type: ignore
|
|
NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_CORRELATION_ID = (383, 352) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD0_POINTER = (415, 384) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD1_POINTER = (447, 416) # type: ignore
|
|
NVCEC0_QMDV05_01_SASS_VERSION = (455, 448) # type: ignore
|
|
NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT = (456, 456) # type: ignore
|
|
NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SAMPLER_INDEX = (457, 457) # type: ignore
|
|
NVCEC0_QMDV05_01_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (463, 458) # type: ignore
|
|
NVCEC0_QMDV05_01_QMD_MINOR_VERSION = (467, 464) # type: ignore
|
|
NVCEC0_QMDV05_01_QMD_MAJOR_VERSION = (471, 468) # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE = (472, 472) # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE = (473, 473) # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE = (474, 474) # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE = (475, 475) # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE = (476, 476) # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE = (477, 477) # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (478, 478) # type: ignore
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (479, 479) # type: ignore
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_LOWER = (511, 480) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_UPPER = (536, 512) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (575, 544) # type: ignore
|
|
NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (607, 576) # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (615, 608) # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_ID = (621, 616) # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE = (622, 622) # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE = (623, 623) # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE = (625, 624) # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE = (626, 626) # type: ignore
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_CTA_LAUNCH_QUEUE = (627, 627) # type: ignore
|
|
NVCEC0_QMDV05_01_FREE_CTA_SLOTS_EMPTY_SM = (635, 628) # type: ignore
|
|
NVCEC0_QMDV05_01_SYNC_DOMAIN_ID = (637, 636) # type: ignore
|
|
NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH = (638, 638) # type: ignore
|
|
NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT = (639, 639) # type: ignore
|
|
NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_ID = (671, 640) # type: ignore
|
|
NVCEC0_QMDV05_01_WAIT_ON_LATCH_ID = (703, 672) # type: ignore
|
|
NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_SHARED_MEM = (721, 714) # type: ignore
|
|
NVCEC0_QMDV05_01_OCCUPANCY_MAX_SHARED_MEM = (729, 722) # type: ignore
|
|
NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID = (730, 730) # type: ignore
|
|
NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID = (731, 731) # type: ignore
|
|
NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE = (732, 732) # type: ignore
|
|
NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE = (733, 733) # type: ignore
|
|
NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE = (734, 734) # type: ignore
|
|
NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE = (735, 735) # type: ignore
|
|
NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_WARP = (743, 736) # type: ignore
|
|
NVCEC0_QMDV05_01_OCCUPANCY_MAX_WARP = (751, 744) # type: ignore
|
|
NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_REGISTER = (759, 752) # type: ignore
|
|
NVCEC0_QMDV05_01_OCCUPANCY_MAX_REGISTER = (767, 760) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_LOWER_SHIFTED4 = lambda i: ((799+(i)*416), (768+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_UPPER_SHIFTED4 = lambda i: ((820+(i)*416), (800+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_SIZE = lambda i: ((829+(i)*416), (821+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE = lambda i: ((831+(i)*416), (830+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION0 = lambda i: ((847+(i)*416), (832+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION1 = lambda i: ((863+(i)*416), (848+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION2 = lambda i: ((871+(i)*416), (864+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_REGISTER_COUNT = lambda i: ((880+(i)*416), (872+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_BARRIER_COUNT = lambda i: ((885+(i)*416), (881+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID = lambda i: ((886+(i)*416), (886+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH = lambda i: ((888+(i)*416), (887+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_PRE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_POST = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE = lambda i: ((889+(i)*416), (889+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_ICC_PREFETCH_SIZE = lambda i: ((895+(i)*416), (890+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEMORY_SIZE_SHIFTED7 = lambda i: ((906+(i)*416), (896+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_MIN_SM_CONFIG_SHARED_MEM_SIZE = lambda i: ((912+(i)*416), (907+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_MAX_SM_CONFIG_SHARED_MEM_SIZE = lambda i: ((918+(i)*416), (913+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_TARGET_SM_CONFIG_SHARED_MEM_SIZE = lambda i: ((924+(i)*416), (919+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEM_BARRIER_INIT_ENABLE = lambda i: ((925+(i)*416), (925+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4 = lambda i: ((943+(i)*416), (928+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4 = lambda i: ((959+(i)*416), (944+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_LOWER_SHIFTED6 = lambda i: ((991+(i)*416), (960+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_UPPER_SHIFTED6 = lambda i: ((1010+(i)*416), (992+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_SIZE_SHIFTED4 = lambda i: ((1023+(i)*416), (1011+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_LOWER_SHIFTED6 = lambda i: ((1055+(i)*416), (1024+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_UPPER_SHIFTED6 = lambda i: ((1074+(i)*416), (1056+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_SIZE_SHIFTED4 = lambda i: ((1087+(i)*416), (1075+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID = lambda i: ((1088+(i)*416), (1088+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH = lambda i: ((1090+(i)*416), (1089+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_PRE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_POST = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE = lambda i: ((1091+(i)*416), (1091+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_VIRTUAL_RESOURCE_COUNT = lambda i: ((1099+(i)*416), (1092+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_GRID_WIDTH = lambda i: ((1151+(i)*416), (1120+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_GRID_HEIGHT = lambda i: ((1167+(i)*416), (1152+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_GRID_DEPTH = lambda i: ((1183+(i)*416), (1168+(i)*416)) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE = lambda i: ((336+(i)*8), (336+(i)*8)) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION = lambda i: ((339+(i)*8), (337+(i)*8)) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH = lambda i: ((340+(i)*8), (340+(i)*8)) # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_DEPENDENT_QMD_POINTER = lambda i: ((415+(i)*32), (384+(i)*32)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID = lambda i,j: ((886+(i)*416+(j)*202), (886+(i)*416+(j)*202)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH = lambda i,j: ((888+(i)*416+(j)*202), (887+(i)*416+(j)*202)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_PRE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_POST = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE = lambda i,j: ((889+(i)*416+(j)*202), (889+(i)*416+(j)*202)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_LOWER_SHIFTED6 = lambda i,j: ((991+(i)*416+(j)*64), (960+(i)*416+(j)*64)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_UPPER_SHIFTED6 = lambda i,j: ((1010+(i)*416+(j)*64), (992+(i)*416+(j)*64)) # type: ignore
|
|
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_SIZE_SHIFTED4 = lambda i,j: ((1023+(i)*416+(j)*64), (1011+(i)*416+(j)*64)) # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENCE_COUNTER = (15, 0) # type: ignore
|
|
NVCEC0_QMDV04_01_QMD_GROUP_ID = (21, 16) # type: ignore
|
|
NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (22, 22) # type: ignore
|
|
NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_QMD_TYPE = (25, 23) # type: ignore
|
|
NVCEC0_QMDV04_01_QMD_TYPE_QUEUE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_QMD_TYPE_GRID_NULL = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_QMD_TYPE_GRID_CTA = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPC_CGA = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_CGA = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005 # type: ignore
|
|
NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_VALID = (28, 28) # type: ignore
|
|
NVCEC0_QMDV04_01_WAIT_ON_LATCH_VALID = (29, 29) # type: ignore
|
|
NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS = (30, 30) # type: ignore
|
|
NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID = (31, 31) # type: ignore
|
|
NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_CIRCULAR_QUEUE_SIZE = (56, 32) # type: ignore
|
|
NVCEC0_QMDV04_01_INNER_GET = (94, 64) # type: ignore
|
|
NVCEC0_QMDV04_01_INNER_OVERFLOW = (95, 95) # type: ignore
|
|
NVCEC0_QMDV04_01_INNER_PUT = (126, 96) # type: ignore
|
|
NVCEC0_QMDV04_01_INNER_STICKY_OVERFLOW = (127, 127) # type: ignore
|
|
NVCEC0_QMDV04_01_HW_ONLY_INNER_GET = (190, 160) # type: ignore
|
|
NVCEC0_QMDV04_01_HW_ONLY_INNER_PUT = (222, 192) # type: ignore
|
|
NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX = (253, 224) # type: ignore
|
|
NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (254, 254) # type: ignore
|
|
NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_HW_ONLY_SKED_NEXT_QMD_POINTER = (287, 256) # type: ignore
|
|
NVCEC0_QMDV04_01_HW_ONLY_DEPENDENCE_COUNTER = (303, 288) # type: ignore
|
|
NVCEC0_QMDV04_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (304, 304) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_ENABLE = lambda i: ((320+(i)*16), (320+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE = lambda i: ((322+(i)*16), (321+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE = lambda i: ((323+(i)*16), (323+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE = lambda i: ((324+(i)*16), (324+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP = lambda i: ((327+(i)*16), (325+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_INC = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_AND = 0x00000005 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_OR = 0x00000006 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT = lambda i: ((329+(i)*16), (328+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE = lambda i: ((331+(i)*16), (330+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B = lambda i: ((332+(i)*16), (332+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_RESERVED_INFO = lambda i: ((335+(i)*16), (333+(i)*16)) # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE = lambda i: ((368+(i)*5), (368+(i)*5)) # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION = lambda i: ((371+(i)*5), (369+(i)*5)) # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH = lambda i: ((372+(i)*5), (372+(i)*5)) # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION = (378, 378) # type: ignore
|
|
NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST = (379, 379) # type: ignore
|
|
NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE = (380, 380) # type: ignore
|
|
NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL = (381, 381) # type: ignore
|
|
NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE = (382, 382) # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_CORRELATION_ID = (415, 384) # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID = lambda i: ((416+(i)*4), (416+(i)*4)) # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH = lambda i: ((418+(i)*4), (417+(i)*4)) # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST = 0x00000002 # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE = lambda i: ((419+(i)*4), (419+(i)*4)) # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD0_POINTER = (479, 448) # type: ignore
|
|
NVCEC0_QMDV04_01_DEPENDENT_QMD1_POINTER = (511, 480) # type: ignore
|
|
NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_LOW_SIZE = (535, 512) # type: ignore
|
|
NVCEC0_QMDV04_01_SASS_VERSION = (543, 536) # type: ignore
|
|
NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_HIGH_SIZE = (567, 544) # type: ignore
|
|
NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT = (568, 568) # type: ignore
|
|
NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_SAMPLER_INDEX = (569, 569) # type: ignore
|
|
NVCEC0_QMDV04_01_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (575, 570) # type: ignore
|
|
NVCEC0_QMDV04_01_QMD_MINOR_VERSION = (579, 576) # type: ignore
|
|
NVCEC0_QMDV04_01_QMD_MAJOR_VERSION = (583, 580) # type: ignore
|
|
NVCEC0_QMDV04_01_SHARED_MEMORY_SIZE = (601, 584) # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE = (602, 602) # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE = (603, 603) # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE = (604, 604) # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE = (605, 605) # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE = (606, 606) # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE = (607, 607) # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_MIN_SM_CONFIG_SHARED_MEM_SIZE = (613, 608) # type: ignore
|
|
NVCEC0_QMDV04_01_MAX_SM_CONFIG_SHARED_MEM_SIZE = (619, 614) # type: ignore
|
|
NVCEC0_QMDV04_01_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (625, 620) # type: ignore
|
|
NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE = (626, 626) # type: ignore
|
|
NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_LOWER = (671, 640) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_UPPER = (696, 672) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (735, 704) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (767, 736) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_LOWER = (799, 768) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_UPPER = (824, 800) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_LOWER = (863, 832) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_UPPER = (895, 864) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_LOWER = (927, 896) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_UPPER = (952, 928) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_LOWER = (991, 960) # type: ignore
|
|
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_UPPER = (1023, 992) # type: ignore
|
|
NVCEC0_QMDV04_01_GRID_WIDTH = (1055, 1024) # type: ignore
|
|
NVCEC0_QMDV04_01_GRID_HEIGHT = (1071, 1056) # type: ignore
|
|
NVCEC0_QMDV04_01_GRID_DEPTH = (1103, 1088) # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (1127, 1120) # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_ID = (1133, 1128) # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE = (1134, 1134) # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE = (1135, 1135) # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE = (1137, 1136) # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # type: ignore
|
|
NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS = (1138, 1138) # type: ignore
|
|
NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_CTA_LAUNCH_QUEUE = (1139, 1139) # type: ignore
|
|
NVCEC0_QMDV04_01_FREE_CTA_SLOTS_EMPTY_SM = (1147, 1140) # type: ignore
|
|
NVCEC0_QMDV04_01_SYNC_DOMAIN_ID = (1149, 1148) # type: ignore
|
|
NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH = (1150, 1150) # type: ignore
|
|
NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT = (1151, 1151) # type: ignore
|
|
NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION0 = (1167, 1152) # type: ignore
|
|
NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION1 = (1183, 1168) # type: ignore
|
|
NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION2 = (1191, 1184) # type: ignore
|
|
NVCEC0_QMDV04_01_VIRTUAL_RESOURCE_COUNT = (1199, 1192) # type: ignore
|
|
NVCEC0_QMDV04_01_REGISTER_COUNT = (1208, 1200) # type: ignore
|
|
NVCEC0_QMDV04_01_SHARED_MEM_BARRIER_INIT_ENABLE = (1210, 1210) # type: ignore
|
|
NVCEC0_QMDV04_01_BARRIER_COUNT = (1215, 1211) # type: ignore
|
|
NVCEC0_QMDV04_01_PROGRAM_ADDRESS_LOWER = (1247, 1216) # type: ignore
|
|
NVCEC0_QMDV04_01_PROGRAM_ADDRESS_UPPER = (1272, 1248) # type: ignore
|
|
NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_WARP = (1287, 1280) # type: ignore
|
|
NVCEC0_QMDV04_01_OCCUPANCY_MAX_WARP = (1295, 1288) # type: ignore
|
|
NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_REGISTER = (1303, 1296) # type: ignore
|
|
NVCEC0_QMDV04_01_OCCUPANCY_MAX_REGISTER = (1311, 1304) # type: ignore
|
|
NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_SHARED_MEM = (1319, 1312) # type: ignore
|
|
NVCEC0_QMDV04_01_OCCUPANCY_MAX_SHARED_MEM = (1327, 1320) # type: ignore
|
|
NVCEC0_QMDV04_01_ICC_PREFETCH_SIZE = (1333, 1328) # type: ignore
|
|
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (1375, 1344) # type: ignore
|
|
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1392, 1376) # type: ignore
|
|
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_SIZE = (1401, 1393) # type: ignore
|
|
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE = (1403, 1402) # type: ignore
|
|
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (1406, 1406) # type: ignore
|
|
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (1407, 1407) # type: ignore
|
|
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_GRID_WIDTH_RESUME = (1439, 1408) # type: ignore
|
|
NVCEC0_QMDV04_01_GRID_HEIGHT_RESUME = (1455, 1440) # type: ignore
|
|
NVCEC0_QMDV04_01_GRID_DEPTH_RESUME = (1471, 1456) # type: ignore
|
|
NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_ID = (1503, 1472) # type: ignore
|
|
NVCEC0_QMDV04_01_WAIT_ON_LATCH_ID = (1535, 1504) # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6 = lambda i: ((1567+(i)*64), (1536+(i)*64)) # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6 = lambda i: ((1586+(i)*64), (1568+(i)*64)) # type: ignore
|
|
NVCEC0_QMDV04_01_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1599+(i)*64), (1587+(i)*64)) # type: ignore
|
|
NVCEC0_QMDV04_01_COALESCE_WAITING_PERIOD = (2135, 2128) # type: ignore
|
|
NVCEC0_QMDV04_01_QUEUE_ENTRIES_PER_CTA_LOG2 = (2140, 2136) # type: ignore
|
|
NVCEC0_QMDV04_01_GPC_CGA_WIDTH = (2149, 2144) # type: ignore
|
|
NVCEC0_QMDV04_01_GPC_CGA_HEIGHT = (2157, 2152) # type: ignore
|
|
NVCEC0_QMDV04_01_GPC_CGA_DEPTH = (2165, 2160) # type: ignore
|
|
NVCEC0_QMDV04_01_LARGE_GPC_CGA_WIDTH_MINUS_ONE = (2171, 2168) # type: ignore
|
|
NVCEC0_QMDV04_01_LARGE_GPC_CGA_HEIGHT_MINUS_ONE = (2175, 2172) # type: ignore
|
|
NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE = (2207, 2207) # type: ignore
|
|
NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING = 0x00000000 # type: ignore
|
|
NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST = 0x00000001 # type: ignore
|
|
NVCEC0_QMDV04_01_GPU_CGA_WIDTH = (2223, 2208) # type: ignore
|
|
NVCEC0_QMDV04_01_GPU_CGA_HEIGHT = (2239, 2224) # type: ignore
|
|
NVCEC0_QMDV04_01_GPU_CGA_DEPTH = (2255, 2240) # type: ignore
|
|
NVCEC0_QMDV04_01_DEBUG_ID_LOWER = (2399, 2368) # type: ignore
|
|
NVCEC0_QMDV04_01_DEBUG_ID_UPPER = (2431, 2400) # type: ignore
|
|
NVCEC0_QMDV04_01_TPC_DISABLE_MASK = lambda i: ((2463+(i)*32), (2432+(i)*32)) # type: ignore
|
|
NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_WIDTH_RESUME = (2591, 2560) # type: ignore
|
|
NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_HEIGHT_RESUME = (2607, 2592) # type: ignore
|
|
NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_DEPTH_RESUME = (2623, 2608) # type: ignore
|
|
NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME = (2627, 2624) # type: ignore
|
|
NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME = (2631, 2628) # type: ignore
|
|
NVCEC0_QMDV04_01_TPC_DISABLE_MASK_UPPER = lambda i: ((2719+(i)*32), (2688+(i)*32)) # type: ignore
|
|
NVCEC0_QMDV04_01_OUTER_PUT = (3038, 3008) # type: ignore
|
|
NVCEC0_QMDV04_01_OUTER_OVERFLOW = (3039, 3039) # type: ignore
|
|
NVCEC0_QMDV04_01_OUTER_GET = (3070, 3040) # type: ignore
|
|
NVCEC0_QMDV04_01_OUTER_STICKY_OVERFLOW = (3071, 3071) # type: ignore
|
|
ALIGN_UP = lambda v,n: (((v) + ((n)-1)) &~ ((n)-1)) # type: ignore
|
|
NVDEC_ALIGN = lambda value: ALIGN_UP(value,256) # type: ignore
|
|
NVDEC_MAX_MPEG2_SLICE = 65536 # type: ignore
|
|
NVDEC_CODEC_MPEG1 = 0 # type: ignore
|
|
NVDEC_CODEC_MPEG2 = 1 # type: ignore
|
|
NVDEC_CODEC_VC1 = 2 # type: ignore
|
|
NVDEC_CODEC_H264 = 3 # type: ignore
|
|
NVDEC_CODEC_MPEG4 = 4 # type: ignore
|
|
NVDEC_CODEC_DIVX = NVDEC_CODEC_MPEG4 # type: ignore
|
|
NVDEC_CODEC_VP8 = 5 # type: ignore
|
|
NVDEC_CODEC_HEVC = 7 # type: ignore
|
|
NVDEC_CODEC_VP9 = 9 # type: ignore
|
|
NVDEC_CODEC_HEVC_PARSER = 12 # type: ignore
|
|
NVDEC_CODEC_AV1 = 10 # type: ignore
|
|
AES_MODE_MASK = 0x7 # type: ignore
|
|
AES_CTS_MASK = 0x1 # type: ignore
|
|
AES_PADDING_TYPE_MASK = 0x7 # type: ignore
|
|
AES_UNWRAP_KEY_MASK = 0x1 # type: ignore
|
|
AES_MODE_SHIFT = 0 # type: ignore
|
|
AES_CTS_SHIFT = 3 # type: ignore
|
|
AES_PADDING_TYPE_SHIFT = 4 # type: ignore
|
|
AES_UNWRAP_KEY_SHIFT = 7 # type: ignore
|
|
AES_SET_FLAG = lambda M,C,P: ((M & AES_MODE_MASK) << AES_MODE_SHIFT) | ((C & AES_CTS_MASK) << AES_CTS_SHIFT) | ((P & AES_PADDING_TYPE_MASK) << AES_PADDING_TYPE_SHIFT) # type: ignore
|
|
DRM_MODE_MASK = 0x7f # type: ignore
|
|
AES_GET_DRM_MODE = lambda V: (V & DRM_MODE_MASK) # type: ignore
|
|
GIP_ASIC_VERT_FILTER_RAM_SIZE = 16 # type: ignore
|
|
GIP_ASIC_BSD_CTRL_RAM_SIZE = 4 # type: ignore
|
|
GIP_ASIC_SCALING_LIST_SIZE = (16*64) # type: ignore
|
|
GIP_ASIC_VERT_SAO_RAM_SIZE = 16 # type: ignore
|
|
GIP_ASIC_TILE_SIZE = ((20*22*2*2+16+15) & ~0xF) # type: ignore
|
|
GIP_ASIC_VP9_CTB_SEG_SIZE = 32 # type: ignore
|
|
HEVC_DBLK_TOP_SIZE_IN_SB16 = ALIGN_UP(632, 128) # type: ignore
|
|
HEVC_DBLK_TOP_BUF_SIZE = lambda w: NVDEC_ALIGN( (ALIGN_UP(w,16)/16 + 2) * HEVC_DBLK_TOP_SIZE_IN_SB16) # type: ignore
|
|
HEVC_DBLK_LEFT_SIZE_IN_SB16 = ALIGN_UP(506, 128) # type: ignore
|
|
HEVC_DBLK_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,16)/16 + 2) * HEVC_DBLK_LEFT_SIZE_IN_SB16) # type: ignore
|
|
HEVC_SAO_LEFT_SIZE_IN_SB16 = ALIGN_UP(713, 128) # type: ignore
|
|
HEVC_SAO_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,16)/16 + 2) * HEVC_SAO_LEFT_SIZE_IN_SB16) # type: ignore
|
|
VP9_DBLK_TOP_SIZE_IN_SB64 = ALIGN_UP(2000, 128) # type: ignore
|
|
VP9_DBLK_TOP_BUF_SIZE = lambda w: NVDEC_ALIGN( (ALIGN_UP(w,64)/64 + 2) * VP9_DBLK_TOP_SIZE_IN_SB64) # type: ignore
|
|
VP9_DBLK_LEFT_SIZE_IN_SB64 = ALIGN_UP(1600, 128) # type: ignore
|
|
VP9_DBLK_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * VP9_DBLK_LEFT_SIZE_IN_SB64) # type: ignore
|
|
VP9_HINT_DUMP_SIZE_IN_SB64 = ((64*64)/(4*4)*8) # type: ignore
|
|
VP9_HINT_DUMP_SIZE = lambda w,h: NVDEC_ALIGN(VP9_HINT_DUMP_SIZE_IN_SB64*((w+63)/64)*((h+63)/64)) # type: ignore
|
|
NUM_SUBSAMPLES = 32 # type: ignore
|
|
VP8_MAX_TOKEN_PARTITIONS = 8 # type: ignore
|
|
VP9_MAX_FRAMES_IN_SUPERFRAME = 8 # type: ignore
|
|
AV1_MAX_TILES = 256 # type: ignore
|
|
MAX_SUBSTREAM_ENTRY_SIZE = 32 # type: ignore
|
|
AV1_TEMPORAL_MV_SIZE_IN_64x64 = 256 # type: ignore
|
|
AV1_TEMPORAL_MV_BUF_SIZE = lambda w,h: ALIGN_UP( ALIGN_UP(w,128) * ALIGN_UP(h,128) / (64*64) * AV1_TEMPORAL_MV_SIZE_IN_64x64, 4096) # type: ignore
|
|
AV1_SEGMENT_ID_SIZE_IN_64x64 = 128 # type: ignore
|
|
AV1_SEGMENT_ID_BUF_SIZE = lambda w,h: ALIGN_UP( ALIGN_UP(w,128) * ALIGN_UP(h,128) / (64*64) * AV1_SEGMENT_ID_SIZE_IN_64x64, 4096) # type: ignore
|
|
AV1_GLOBAL_MOTION_BUF_SIZE = NVDEC_ALIGN(7*32) # type: ignore
|
|
AV1_INTRA_TOP_BUF_SIZE = NVDEC_ALIGN(8*8192) # type: ignore
|
|
AV1_HISTOGRAM_BUF_SIZE = NVDEC_ALIGN(1024) # type: ignore
|
|
AV1_DBLK_TOP_SIZE_IN_SB64 = ALIGN_UP(1920, 128) # type: ignore
|
|
AV1_DBLK_TOP_BUF_SIZE = lambda w: NVDEC_ALIGN( (ALIGN_UP(w,64)/64 + 2) * AV1_DBLK_TOP_SIZE_IN_SB64) # type: ignore
|
|
AV1_DBLK_LEFT_SIZE_IN_SB64 = ALIGN_UP(1536, 128) # type: ignore
|
|
AV1_DBLK_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_DBLK_LEFT_SIZE_IN_SB64) # type: ignore
|
|
AV1_CDEF_LEFT_SIZE_IN_SB64 = ALIGN_UP(1792, 128) # type: ignore
|
|
AV1_CDEF_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_CDEF_LEFT_SIZE_IN_SB64) # type: ignore
|
|
AV1_HUS_LEFT_SIZE_IN_SB64 = ALIGN_UP(12544, 128) # type: ignore
|
|
AV1_ASIC_HUS_LEFT_BUFFER_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_HUS_LEFT_SIZE_IN_SB64) # type: ignore
|
|
AV1_HUS_LEFT_BUF_SIZE = lambda h: 2*AV1_ASIC_HUS_LEFT_BUFFER_SIZE(h) # type: ignore
|
|
AV1_LR_LEFT_SIZE_IN_SB64 = ALIGN_UP(1920, 128) # type: ignore
|
|
AV1_LR_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_LR_LEFT_SIZE_IN_SB64) # type: ignore
|
|
AV1_FGS_LEFT_SIZE_IN_SB64 = ALIGN_UP(320, 128) # type: ignore
|
|
AV1_FGS_LEFT_BUF_SIZE = lambda h: NVDEC_ALIGN( (ALIGN_UP(h,64)/64 + 2) * AV1_FGS_LEFT_SIZE_IN_SB64) # type: ignore
|
|
AV1_HINT_DUMP_SIZE_IN_SB64 = ((64*64)/(4*4)*8) # type: ignore
|
|
AV1_HINT_DUMP_SIZE_IN_SB128 = ((128*128)/(4*4)*8) # type: ignore
|
|
AV1_HINT_DUMP_SIZE = lambda w,h: NVDEC_ALIGN(AV1_HINT_DUMP_SIZE_IN_SB128*((w+127)/128)*((h+127)/128)) # type: ignore
|
|
NVBIT = lambda b: (1<<(b)) # type: ignore
|
|
NVBIT32 = lambda b: NVBIT_TYPE(b, NvU32) # type: ignore
|
|
NVBIT64 = lambda b: NVBIT_TYPE(b, NvU64) # type: ignore
|
|
NV_BITMASK32_IDX = lambda chId: (((chId) & ~(0x1F)) >> 5) # type: ignore
|
|
NV_BITMASK32_OFFSET = lambda chId: ((chId) & (0x1F)) # type: ignore
|
|
NV_BITMASK32_GET = lambda pChannelMask,chId: ((pChannelMask)[NV_BITMASK32_IDX(chId)] & NVBIT(NV_BITMASK32_OFFSET(chId))) # type: ignore
|
|
DRF_SHIFT = lambda drf: ((DRF_ISBIT(0,drf)) % 32) # type: ignore
|
|
DRF_SHIFT_RT = lambda drf: ((DRF_ISBIT(1,drf)) % 32) # type: ignore
|
|
DRF_SIZE = lambda drf: (DRF_EXTENT(drf)-DRF_BASE(drf)+1) # type: ignore
|
|
DRF_MASK = lambda drf: (0xFFFFFFFF>>(31-((DRF_ISBIT(1,drf)) % 32)+((DRF_ISBIT(0,drf)) % 32))) # type: ignore
|
|
DRF_SHIFTMASK = lambda drf: (DRF_MASK(drf)<<(DRF_SHIFT(drf))) # type: ignore
|
|
DRF_SHIFT64 = lambda drf: ((DRF_ISBIT(0,drf)) % 64) # type: ignore
|
|
DRF_MASK64 = lambda drf: (NV_U64_MAX>>(63-((DRF_ISBIT(1,drf)) % 64)+((DRF_ISBIT(0,drf)) % 64))) # type: ignore
|
|
DRF_SHIFTMASK64 = lambda drf: (DRF_MASK64(drf)<<(DRF_SHIFT64(drf))) # type: ignore
|
|
FLD_TEST_DRF_NUM64 = lambda d,r,f,n,v: (DRF_VAL64(d, r, f, (v)) == (n)) # type: ignore
|
|
REF_VAL64 = lambda drf,v: (((NvU64)(v)>>DRF_SHIFT64(drf))&DRF_MASK64(drf)) # type: ignore
|
|
REF_NUM64 = lambda drf,n: (((NvU64)(n)&DRF_MASK64(drf))<<DRF_SHIFT64(drf)) # type: ignore
|
|
FLD_SET_REF_NUM64 = lambda drf,n,v: (((NvU64)(v) & ~DRF_SHIFTMASK64(drf)) | REF_NUM64(drf,n)) # type: ignore
|
|
FLD_TEST_DRF_NUM = lambda d,r,f,n,v: ((DRF_VAL(d, r, f, (v)) == (n))) # type: ignore
|
|
REF_VAL = lambda drf,v: (((v)>>DRF_SHIFT(drf))&DRF_MASK(drf)) # type: ignore
|
|
REF_NUM = lambda drf,n: (((n)&DRF_MASK(drf))<<DRF_SHIFT(drf)) # type: ignore
|
|
FLD_SET_REF_NUM = lambda drf,n,v: (((v) & ~DRF_SHIFTMASK(drf)) | REF_NUM(drf,n)) # type: ignore
|
|
DRF_EXPAND_MW = lambda drf: drf # type: ignore
|
|
DRF_WORD_MW = lambda drf: (DRF_PICK_MW(drf,0)/32) # type: ignore
|
|
DRF_BASE_MW = lambda drf: (DRF_PICK_MW(drf,0)%32) # type: ignore
|
|
DRF_EXTENT_MW = lambda drf: (DRF_PICK_MW(drf,1)%32) # type: ignore
|
|
DRF_SHIFT_MW = lambda drf: (DRF_PICK_MW(drf,0)%32) # type: ignore
|
|
DRF_MASK_MW = lambda drf: (0xFFFFFFFF>>((31-(DRF_EXTENT_MW(drf))+(DRF_BASE_MW(drf)))%32)) # type: ignore
|
|
DRF_SHIFTMASK_MW = lambda drf: ((DRF_MASK_MW(drf))<<(DRF_SHIFT_MW(drf))) # type: ignore
|
|
DRF_SIZE_MW = lambda drf: (DRF_EXTENT_MW(drf)-DRF_BASE_MW(drf)+1) # type: ignore
|
|
DRF_WORD_MW_LOW = lambda drf: (DRF_PICK_MW(drf,0)/32) # type: ignore
|
|
DRF_WORD_MW_HIGH = lambda drf: (DRF_PICK_MW(drf,1)/32) # type: ignore
|
|
DRF_MASK_MW_LOW = lambda drf: (0xFFFFFFFF) # type: ignore
|
|
DRF_MASK_MW_HIGH = lambda drf: (0xFFFFFFFF>>(31-(DRF_EXTENT_MW(drf)))) # type: ignore
|
|
DRF_SHIFT_MW_LOW = lambda drf: (DRF_PICK_MW(drf,0)%32) # type: ignore
|
|
DRF_SHIFT_MW_HIGH = lambda drf: (0) # type: ignore
|
|
DRF_MERGE_SHIFT = lambda drf: ((32-((DRF_PICK_MW(drf,0)%32)))%32) # type: ignore
|
|
FLD_MERGE_MW = lambda drf,n,v: (((v)[DRF_WORD_MW(drf)] & ~DRF_SHIFTMASK_MW(drf)) | n) # type: ignore
|
|
FLD_IDX_MERGE_MW = lambda drf,i,n,v: (((v)[DRF_WORD_MW(drf(i))] & ~DRF_SHIFTMASK_MW(drf(i))) | n) # type: ignore
|
|
FLD_TEST_DRF_NUM_MW = lambda d,r,f,n,v: ((DRF_VAL_MW(d, r, f, (v)) == n)) # type: ignore
|
|
NV_TWO_N_MINUS_ONE = lambda n: (((1<<(n/2))<<((n+1)/2))-1) # type: ignore
|
|
LOWESTBIT = lambda x: ( (x) & (((x) - 1) ^ (x)) ) # type: ignore
|
|
NV_ANYSIZE_ARRAY = 1 # type: ignore
|
|
NV_CEIL = lambda a,b: (((a)+(b)-1)/(b)) # type: ignore
|
|
NV_DIV_AND_CEIL = lambda a,b: NV_CEIL(a,b) # type: ignore
|
|
NV_SIGN = lambda s: ((NvS8)(((s) > 0) - ((s) < 0))) # type: ignore
|
|
NV_ZERO_SIGN = lambda s: ((NvS8)((((s) >= 0) * 2) - 1)) # type: ignore
|
|
NV_UNSIGNED_ROUNDED_DIV = lambda a,b: (((a) + ((b) / 2)) / (b)) # type: ignore
|
|
NV_UNSIGNED_DIV_CEIL = lambda a,b: (((a) + (b - 1)) / (b)) # type: ignore
|
|
NV_ALIGN_DOWN = lambda v,gran: ((v) & ~((v) - (v) + (gran) - 1)) # type: ignore
|
|
NV_ALIGN_UP = lambda v,gran: (((v) + ((gran) - 1)) & ~((v) - (v) + (gran) - 1)) # type: ignore
|
|
NV_IS_ALIGNED = lambda v,gran: (0 == ((v) & ((gran) - 1))) # type: ignore
|
|
NV_BIT_GET = lambda k,x: (((x) >> (k)) & 1) # type: ignore
|
|
NV_ARRAY_ELEMENTS = lambda x: ((sizeof(x)/sizeof((x)[0]))) # type: ignore
|
|
BIT = lambda b: (1<<(b)) # type: ignore
|
|
NV01_NULL_OBJECT = (0x0) # type: ignore
|
|
NV1_NULL_OBJECT = NV01_NULL_OBJECT # type: ignore
|
|
NV01_ROOT = (0x0) # type: ignore
|
|
NV0000_ALLOC_PARAMETERS_MESSAGE_ID = (0x0000) # type: ignore
|
|
NV01_MEMORY_VIRTUAL = (0x70) # type: ignore
|
|
NV01_MEMORY_SYSTEM_DYNAMIC = (0x70) # type: ignore
|
|
NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID = (0x0070) # type: ignore
|
|
NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE = 0xffffffff # type: ignore
|
|
NV01_DEVICE_0 = (0x80) # type: ignore
|
|
NV0080_ALLOC_PARAMETERS_MESSAGE_ID = (0x0080) # type: ignore
|
|
NV20_SUBDEVICE_0 = (0x2080) # type: ignore
|
|
NV2080_ALLOC_PARAMETERS_MESSAGE_ID = (0x2080) # type: ignore
|
|
NV2080_NOTIFIERS_SW = (0) # type: ignore
|
|
NV2080_NOTIFIERS_HOTPLUG = (1) # type: ignore
|
|
NV2080_NOTIFIERS_POWER_CONNECTOR = (2) # type: ignore
|
|
NV2080_NOTIFIERS_THERMAL_SW = (3) # type: ignore
|
|
NV2080_NOTIFIERS_THERMAL_HW = (4) # type: ignore
|
|
NV2080_NOTIFIERS_FULL_SCREEN_CHANGE = (5) # type: ignore
|
|
NV2080_NOTIFIERS_EVENTBUFFER = (6) # type: ignore
|
|
NV2080_NOTIFIERS_DP_IRQ = (7) # type: ignore
|
|
NV2080_NOTIFIERS_GR_DEBUG_INTR = (8) # type: ignore
|
|
NV2080_NOTIFIERS_PMU_EVENT = (9) # type: ignore
|
|
NV2080_NOTIFIERS_PMU_COMMAND = (10) # type: ignore
|
|
NV2080_NOTIFIERS_TIMER = (11) # type: ignore
|
|
NV2080_NOTIFIERS_GRAPHICS = (12) # type: ignore
|
|
NV2080_NOTIFIERS_PPP = (13) # type: ignore
|
|
NV2080_NOTIFIERS_VLD = (14) # type: ignore
|
|
NV2080_NOTIFIERS_NVDEC0 = NV2080_NOTIFIERS_VLD # type: ignore
|
|
NV2080_NOTIFIERS_NVDEC1 = (15) # type: ignore
|
|
NV2080_NOTIFIERS_NVDEC2 = (16) # type: ignore
|
|
NV2080_NOTIFIERS_NVDEC3 = (17) # type: ignore
|
|
NV2080_NOTIFIERS_NVDEC4 = (18) # type: ignore
|
|
NV2080_NOTIFIERS_NVDEC5 = (19) # type: ignore
|
|
NV2080_NOTIFIERS_NVDEC6 = (20) # type: ignore
|
|
NV2080_NOTIFIERS_NVDEC7 = (21) # type: ignore
|
|
NV2080_NOTIFIERS_PDEC = (22) # type: ignore
|
|
NV2080_NOTIFIERS_CE0 = (23) # type: ignore
|
|
NV2080_NOTIFIERS_CE1 = (24) # type: ignore
|
|
NV2080_NOTIFIERS_CE2 = (25) # type: ignore
|
|
NV2080_NOTIFIERS_CE3 = (26) # type: ignore
|
|
NV2080_NOTIFIERS_CE4 = (27) # type: ignore
|
|
NV2080_NOTIFIERS_CE5 = (28) # type: ignore
|
|
NV2080_NOTIFIERS_CE6 = (29) # type: ignore
|
|
NV2080_NOTIFIERS_CE7 = (30) # type: ignore
|
|
NV2080_NOTIFIERS_CE8 = (31) # type: ignore
|
|
NV2080_NOTIFIERS_CE9 = (32) # type: ignore
|
|
NV2080_NOTIFIERS_PSTATE_CHANGE = (33) # type: ignore
|
|
NV2080_NOTIFIERS_HDCP_STATUS_CHANGE = (34) # type: ignore
|
|
NV2080_NOTIFIERS_FIFO_EVENT_MTHD = (35) # type: ignore
|
|
NV2080_NOTIFIERS_PRIV_RING_HANG = (36) # type: ignore
|
|
NV2080_NOTIFIERS_RC_ERROR = (37) # type: ignore
|
|
NV2080_NOTIFIERS_MSENC = (38) # type: ignore
|
|
NV2080_NOTIFIERS_NVENC0 = NV2080_NOTIFIERS_MSENC # type: ignore
|
|
NV2080_NOTIFIERS_NVENC1 = (39) # type: ignore
|
|
NV2080_NOTIFIERS_NVENC2 = (40) # type: ignore
|
|
NV2080_NOTIFIERS_UNUSED_0 = (41) # type: ignore
|
|
NV2080_NOTIFIERS_ACPI_NOTIFY = (42) # type: ignore
|
|
NV2080_NOTIFIERS_COOLER_DIAG_ZONE = (43) # type: ignore
|
|
NV2080_NOTIFIERS_THERMAL_DIAG_ZONE = (44) # type: ignore
|
|
NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST = (45) # type: ignore
|
|
NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE = (46) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT = (47) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT = (48) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT = (49) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT = (50) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT = (51) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT = (52) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT = (53) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT = (54) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT = (55) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT = (56) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT = (57) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT = (58) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT = (59) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT = (60) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT = (61) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT = (62) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT = (63) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT = (64) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT = (65) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT = (66) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT = (67) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT = (68) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT = (69) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT = (70) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT = (71) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT = (72) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT = (73) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT = (74) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT = (75) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT = (76) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT = (77) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT = (78) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT = (79) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT = (80) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT = (81) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT = (82) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT = (83) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT = (84) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT = (85) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT = (86) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT = (87) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT = (88) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT = (89) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT = (90) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT = (91) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT = (92) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT = (93) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT = (94) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT = (95) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT = (96) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT = (97) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT = (98) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT = (99) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT = (100) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT = (101) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT = (102) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT = (103) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT = (104) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT = (105) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT = (106) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT = (107) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT = (108) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT = (109) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT = (110) # type: ignore
|
|
NV2080_NOTIFIERS_ECC_SBE = (111) # type: ignore
|
|
NV2080_NOTIFIERS_ECC_DBE = (112) # type: ignore
|
|
NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION = (113) # type: ignore
|
|
NV2080_NOTIFIERS_GC5_GPU_READY = (114) # type: ignore
|
|
NV2080_NOTIFIERS_SEC2 = (115) # type: ignore
|
|
NV2080_NOTIFIERS_GC6_REFCOUNT_INC = (116) # type: ignore
|
|
NV2080_NOTIFIERS_GC6_REFCOUNT_DEC = (117) # type: ignore
|
|
NV2080_NOTIFIERS_POWER_EVENT = (118) # type: ignore
|
|
NV2080_NOTIFIERS_CLOCKS_CHANGE = (119) # type: ignore
|
|
NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE = (120) # type: ignore
|
|
NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT = (121) # type: ignore
|
|
NV2080_NOTIFIERS_RESERVED122 = (122) # type: ignore
|
|
NV2080_NOTIFIERS_NVLINK_ERROR_FATAL = (123) # type: ignore
|
|
NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT = (124) # type: ignore
|
|
NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED = (125) # type: ignore
|
|
NV2080_NOTIFIERS_NVJPG = (126) # type: ignore
|
|
NV2080_NOTIFIERS_NVJPEG0 = NV2080_NOTIFIERS_NVJPG # type: ignore
|
|
NV2080_NOTIFIERS_NVJPEG1 = (127) # type: ignore
|
|
NV2080_NOTIFIERS_NVJPEG2 = (128) # type: ignore
|
|
NV2080_NOTIFIERS_NVJPEG3 = (129) # type: ignore
|
|
NV2080_NOTIFIERS_NVJPEG4 = (130) # type: ignore
|
|
NV2080_NOTIFIERS_NVJPEG5 = (131) # type: ignore
|
|
NV2080_NOTIFIERS_NVJPEG6 = (132) # type: ignore
|
|
NV2080_NOTIFIERS_NVJPEG7 = (133) # type: ignore
|
|
NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE = (134) # type: ignore
|
|
NV2080_NOTIFIERS_RUNLIST_ACQUIRE = (135) # type: ignore
|
|
NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE = (136) # type: ignore
|
|
NV2080_NOTIFIERS_RUNLIST_IDLE = (137) # type: ignore
|
|
NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE = (138) # type: ignore
|
|
NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE = (139) # type: ignore
|
|
NV2080_NOTIFIERS_CTXSW_TIMEOUT = (140) # type: ignore
|
|
NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED = (141) # type: ignore
|
|
NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT = (142) # type: ignore
|
|
NV2080_NOTIFIERS_DSTATE_XUSB_PPC = (143) # type: ignore
|
|
NV2080_NOTIFIERS_FECS_CTX_SWITCH = (144) # type: ignore
|
|
NV2080_NOTIFIERS_XUSB_PPC_CONNECTED = (145) # type: ignore
|
|
NV2080_NOTIFIERS_GR0 = NV2080_NOTIFIERS_GRAPHICS # type: ignore
|
|
NV2080_NOTIFIERS_GR1 = (146) # type: ignore
|
|
NV2080_NOTIFIERS_GR2 = (147) # type: ignore
|
|
NV2080_NOTIFIERS_GR3 = (148) # type: ignore
|
|
NV2080_NOTIFIERS_GR4 = (149) # type: ignore
|
|
NV2080_NOTIFIERS_GR5 = (150) # type: ignore
|
|
NV2080_NOTIFIERS_GR6 = (151) # type: ignore
|
|
NV2080_NOTIFIERS_GR7 = (152) # type: ignore
|
|
NV2080_NOTIFIERS_OFA = (153) # type: ignore
|
|
NV2080_NOTIFIERS_OFA0 = NV2080_NOTIFIERS_OFA # type: ignore
|
|
NV2080_NOTIFIERS_DSTATE_HDA = (154) # type: ignore
|
|
NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL = (155) # type: ignore
|
|
NV2080_NOTIFIERS_POISON_ERROR_FATAL = (156) # type: ignore
|
|
NV2080_NOTIFIERS_UCODE_RESET = (157) # type: ignore
|
|
NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE = (158) # type: ignore
|
|
NV2080_NOTIFIERS_SMC_CONFIG_UPDATE = (159) # type: ignore
|
|
NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED = (160) # type: ignore
|
|
NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED = (161) # type: ignore
|
|
NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST = (162) # type: ignore
|
|
NV2080_NOTIFIERS_SEC_FAULT_ERROR = (163) # type: ignore
|
|
NV2080_NOTIFIERS_UNUSED_1 = (164) # type: ignore
|
|
NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP = (165) # type: ignore
|
|
NV2080_NOTIFIERS_CE10 = (166) # type: ignore
|
|
NV2080_NOTIFIERS_CE11 = (167) # type: ignore
|
|
NV2080_NOTIFIERS_CE12 = (168) # type: ignore
|
|
NV2080_NOTIFIERS_CE13 = (169) # type: ignore
|
|
NV2080_NOTIFIERS_CE14 = (170) # type: ignore
|
|
NV2080_NOTIFIERS_CE15 = (171) # type: ignore
|
|
NV2080_NOTIFIERS_CE16 = (172) # type: ignore
|
|
NV2080_NOTIFIERS_CE17 = (173) # type: ignore
|
|
NV2080_NOTIFIERS_CE18 = (174) # type: ignore
|
|
NV2080_NOTIFIERS_CE19 = (175) # type: ignore
|
|
NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN = (176) # type: ignore
|
|
NV2080_NOTIFIERS_NVPCF_EVENTS = (177) # type: ignore
|
|
NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST = (178) # type: ignore
|
|
NV2080_NOTIFIERS_VRR_SET_TIMEOUT = (179) # type: ignore
|
|
NV2080_NOTIFIERS_OFA1 = (180) # type: ignore
|
|
NV2080_NOTIFIERS_AUX_POWER_EVENT = (181) # type: ignore
|
|
NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE = (182) # type: ignore
|
|
NV2080_NOTIFIERS_NVENC3 = (183) # type: ignore
|
|
NV2080_NOTIFIERS_GSP_PERF_TRACE = (184) # type: ignore
|
|
NV2080_NOTIFIERS_INBAND_RESPONSE = (185) # type: ignore
|
|
NV2080_NOTIFIERS_RESERVED_186 = (186) # type: ignore
|
|
NV2080_NOTIFIERS_ECC_SBE_STORM = (187) # type: ignore
|
|
NV2080_NOTIFIERS_DRAM_RETIREMENT_EVENT = (188) # type: ignore
|
|
NV2080_NOTIFIERS_DRAM_RETIREMENT_FAILURE = (189) # type: ignore
|
|
NV2080_NOTIFIERS_NVLINK_UNCONTAINED_ERROR = (190) # type: ignore
|
|
NV2080_NOTIFIERS_GPU_UNAVAILABLE = (191) # type: ignore
|
|
NV2080_NOTIFIERS_GPU_RECOVERY_ACTION = (192) # type: ignore
|
|
NV2080_NOTIFIERS_POWER_SUSPEND = (193) # type: ignore
|
|
NV2080_NOTIFIERS_POWER_RESUME = (194) # type: ignore
|
|
NV2080_NOTIFIERS_CTXSW_UCODE_ERROR = (195) # type: ignore
|
|
NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD = (196) # type: ignore
|
|
NV2080_NOTIFIERS_MAXCOUNT = (197) # type: ignore
|
|
NV2080_NOTIFIERS_GR_IDX = lambda x: ((x) - NV2080_NOTIFIERS_GR0) # type: ignore
|
|
NV2080_NOTIFIER_TYPE_IS_GR = lambda x: (((x) == NV2080_NOTIFIERS_GR0) or (((x) >= NV2080_NOTIFIERS_GR1) and ((x) <= NV2080_NOTIFIERS_GR7))) # type: ignore
|
|
NV2080_NOTIFIER_TYPE_IS_CE = lambda x: ((((x) >= NV2080_NOTIFIERS_CE0) and ((x) <= NV2080_NOTIFIERS_CE9)) or (((x) >= NV2080_NOTIFIERS_CE10) and ((x) <= NV2080_NOTIFIERS_CE19))) # type: ignore
|
|
NV2080_NOTIFIER_TYPE_IS_NVENC = lambda x: ((((x) >= NV2080_NOTIFIERS_NVENC0) and ((x) <= NV2080_NOTIFIERS_NVENC2)) or (((x) == NV2080_NOTIFIERS_NVENC3))) # type: ignore
|
|
NV2080_NOTIFIERS_NVDEC = lambda x: (NV2080_NOTIFIERS_NVDEC0 + (x)) # type: ignore
|
|
NV2080_NOTIFIERS_NVDEC_IDX = lambda x: ((x) - NV2080_NOTIFIERS_NVDEC0) # type: ignore
|
|
NV2080_NOTIFIER_TYPE_IS_NVDEC = lambda x: (((x) >= NV2080_NOTIFIERS_NVDEC0) and ((x) <= NV2080_NOTIFIERS_NVDEC7)) # type: ignore
|
|
NV2080_NOTIFIERS_NVJPEG = lambda x: (NV2080_NOTIFIERS_NVJPEG0 + (x)) # type: ignore
|
|
NV2080_NOTIFIERS_NVJPEG_IDX = lambda x: ((x) - NV2080_NOTIFIERS_NVJPEG0) # type: ignore
|
|
NV2080_NOTIFIER_TYPE_IS_NVJPEG = lambda x: (((x) >= NV2080_NOTIFIERS_NVJPEG0) and ((x) <= NV2080_NOTIFIERS_NVJPEG7)) # type: ignore
|
|
NV2080_NOTIFIER_TYPE_IS_OFA = lambda x: (((x) == NV2080_NOTIFIERS_OFA0) or ((x) == NV2080_NOTIFIERS_OFA1)) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT = lambda pin: (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT + (pin)) # type: ignore
|
|
NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT = lambda pin: (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT + (pin)) # type: ignore
|
|
NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS = (0x8000) # type: ignore
|
|
NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT = (0x4000) # type: ignore
|
|
NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE = (0x2000) # type: ignore
|
|
NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE = (0x1000) # type: ignore
|
|
NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS = (0x0000) # type: ignore
|
|
NV2080_ENGINE_TYPE_NULL = (0x00000000) # type: ignore
|
|
NV2080_ENGINE_TYPE_GRAPHICS = (0x00000001) # type: ignore
|
|
NV2080_ENGINE_TYPE_GR0 = NV2080_ENGINE_TYPE_GRAPHICS # type: ignore
|
|
NV2080_ENGINE_TYPE_GR1 = (0x00000002) # type: ignore
|
|
NV2080_ENGINE_TYPE_GR2 = (0x00000003) # type: ignore
|
|
NV2080_ENGINE_TYPE_GR3 = (0x00000004) # type: ignore
|
|
NV2080_ENGINE_TYPE_GR4 = (0x00000005) # type: ignore
|
|
NV2080_ENGINE_TYPE_GR5 = (0x00000006) # type: ignore
|
|
NV2080_ENGINE_TYPE_GR6 = (0x00000007) # type: ignore
|
|
NV2080_ENGINE_TYPE_GR7 = (0x00000008) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY0 = (0x00000009) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY1 = (0x0000000a) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY2 = (0x0000000b) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY3 = (0x0000000c) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY4 = (0x0000000d) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY5 = (0x0000000e) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY6 = (0x0000000f) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY7 = (0x00000010) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY8 = (0x00000011) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY9 = (0x00000012) # type: ignore
|
|
NV2080_ENGINE_TYPE_BSP = (0x00000013) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC0 = NV2080_ENGINE_TYPE_BSP # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC1 = (0x00000014) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC2 = (0x00000015) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC3 = (0x00000016) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC4 = (0x00000017) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC5 = (0x00000018) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC6 = (0x00000019) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC7 = (0x0000001a) # type: ignore
|
|
NV2080_ENGINE_TYPE_MSENC = (0x0000001b) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVENC0 = NV2080_ENGINE_TYPE_MSENC # type: ignore
|
|
NV2080_ENGINE_TYPE_NVENC1 = (0x0000001c) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVENC2 = (0x0000001d) # type: ignore
|
|
NV2080_ENGINE_TYPE_VP = (0x0000001e) # type: ignore
|
|
NV2080_ENGINE_TYPE_ME = (0x0000001f) # type: ignore
|
|
NV2080_ENGINE_TYPE_PPP = (0x00000020) # type: ignore
|
|
NV2080_ENGINE_TYPE_MPEG = (0x00000021) # type: ignore
|
|
NV2080_ENGINE_TYPE_SW = (0x00000022) # type: ignore
|
|
NV2080_ENGINE_TYPE_CIPHER = (0x00000023) # type: ignore
|
|
NV2080_ENGINE_TYPE_TSEC = NV2080_ENGINE_TYPE_CIPHER # type: ignore
|
|
NV2080_ENGINE_TYPE_VIC = (0x00000024) # type: ignore
|
|
NV2080_ENGINE_TYPE_MP = (0x00000025) # type: ignore
|
|
NV2080_ENGINE_TYPE_SEC2 = (0x00000026) # type: ignore
|
|
NV2080_ENGINE_TYPE_HOST = (0x00000027) # type: ignore
|
|
NV2080_ENGINE_TYPE_DPU = (0x00000028) # type: ignore
|
|
NV2080_ENGINE_TYPE_PMU = (0x00000029) # type: ignore
|
|
NV2080_ENGINE_TYPE_FBFLCN = (0x0000002a) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPG = (0x0000002b) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG0 = NV2080_ENGINE_TYPE_NVJPG # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG1 = (0x0000002c) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG2 = (0x0000002d) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG3 = (0x0000002e) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG4 = (0x0000002f) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG5 = (0x00000030) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG6 = (0x00000031) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG7 = (0x00000032) # type: ignore
|
|
NV2080_ENGINE_TYPE_OFA = (0x00000033) # type: ignore
|
|
NV2080_ENGINE_TYPE_OFA0 = NV2080_ENGINE_TYPE_OFA # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY10 = (0x00000034) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY11 = (0x00000035) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY12 = (0x00000036) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY13 = (0x00000037) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY14 = (0x00000038) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY15 = (0x00000039) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY16 = (0x0000003a) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY17 = (0x0000003b) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY18 = (0x0000003c) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY19 = (0x0000003d) # type: ignore
|
|
NV2080_ENGINE_TYPE_OFA1 = (0x0000003e) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVENC3 = (0x0000003f) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 = (0x00000040) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY1 = (0x00000041) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY2 = (0x00000042) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY3 = (0x00000043) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY4 = (0x00000044) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY5 = (0x00000045) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY6 = (0x00000046) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY7 = (0x00000047) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY8 = (0x00000048) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY9 = (0x00000049) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY10 = (0x0000004a) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY11 = (0x0000004b) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY12 = (0x0000004c) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY13 = (0x0000004d) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY14 = (0x0000004e) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY15 = (0x0000004f) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY16 = (0x00000050) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY17 = (0x00000051) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY18 = (0x00000052) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19 = (0x00000053) # type: ignore
|
|
NV2080_ENGINE_TYPE_LAST = (0x00000054) # type: ignore
|
|
NV2080_ENGINE_TYPE_ALLENGINES = (0xffffffff) # type: ignore
|
|
NV2080_ENGINE_TYPE_COPY_SIZE = 64 # type: ignore
|
|
NV2080_ENGINE_TYPE_NVENC_SIZE = 4 # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG_SIZE = 8 # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC_SIZE = 8 # type: ignore
|
|
NV2080_ENGINE_TYPE_GR_SIZE = 8 # type: ignore
|
|
NV2080_ENGINE_TYPE_OFA_SIZE = 2 # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY = lambda i: (NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 + (i)) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_COMP_DECOMP_COPY = lambda i: (((i) >= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0) and ((i) <= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19)) # type: ignore
|
|
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_COPY = lambda i: ((((i) >= NV2080_ENGINE_TYPE_COPY0) and ((i) <= NV2080_ENGINE_TYPE_COPY9)) or (((i) >= NV2080_ENGINE_TYPE_COPY10) and ((i) <= NV2080_ENGINE_TYPE_COPY19))) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_NVENC = lambda i: ((((i) >= NV2080_ENGINE_TYPE_NVENC0) and ((i) <= NV2080_ENGINE_TYPE_NVENC2)) or (((i) == NV2080_ENGINE_TYPE_NVENC3))) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC = lambda i: (NV2080_ENGINE_TYPE_NVDEC0+(i)) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_NVDEC = lambda i: (((i) >= NV2080_ENGINE_TYPE_NVDEC0) and ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE))) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVDEC_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_NVDEC0) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG = lambda i: (NV2080_ENGINE_TYPE_NVJPEG0+(i)) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_NVJPEG = lambda i: (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) and ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE))) # type: ignore
|
|
NV2080_ENGINE_TYPE_NVJPEG_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_NVJPEG0) # type: ignore
|
|
NV2080_ENGINE_TYPE_GR = lambda i: (NV2080_ENGINE_TYPE_GR0 + (i)) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_GR = lambda i: (((i) >= NV2080_ENGINE_TYPE_GR0) and ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE))) # type: ignore
|
|
NV2080_ENGINE_TYPE_GR_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_GR0) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_OFA = lambda i: (((i) == NV2080_ENGINE_TYPE_OFA0) or ((i) == NV2080_ENGINE_TYPE_OFA1)) # type: ignore
|
|
NV2080_ENGINE_TYPE_IS_VALID = lambda i: (((i) > (NV2080_ENGINE_TYPE_NULL)) and ((i) < (NV2080_ENGINE_TYPE_LAST))) # type: ignore
|
|
NV2080_CLIENT_TYPE_TEX = (0x00000001) # type: ignore
|
|
NV2080_CLIENT_TYPE_COLOR = (0x00000002) # type: ignore
|
|
NV2080_CLIENT_TYPE_DEPTH = (0x00000003) # type: ignore
|
|
NV2080_CLIENT_TYPE_DA = (0x00000004) # type: ignore
|
|
NV2080_CLIENT_TYPE_FE = (0x00000005) # type: ignore
|
|
NV2080_CLIENT_TYPE_SCC = (0x00000006) # type: ignore
|
|
NV2080_CLIENT_TYPE_WID = (0x00000007) # type: ignore
|
|
NV2080_CLIENT_TYPE_MSVLD = (0x00000008) # type: ignore
|
|
NV2080_CLIENT_TYPE_MSPDEC = (0x00000009) # type: ignore
|
|
NV2080_CLIENT_TYPE_MSPPP = (0x0000000a) # type: ignore
|
|
NV2080_CLIENT_TYPE_VIC = (0x0000000b) # type: ignore
|
|
NV2080_CLIENT_TYPE_ALLCLIENTS = (0xffffffff) # type: ignore
|
|
NV2080_GC5_EXIT_COMPLETE = (0x00000001) # type: ignore
|
|
NV2080_GC5_ENTRY_ABORTED = (0x00000002) # type: ignore
|
|
NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION = (0x00000000) # type: ignore
|
|
NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION = (0x00000001) # type: ignore
|
|
NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT = (0x4000) # type: ignore
|
|
NV2080_TYPEDEF = Nv20Subdevice0 # type: ignore
|
|
NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX = (7, 0) # type: ignore
|
|
NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK = (15, 8) # type: ignore
|
|
NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON = (23, 16) # type: ignore
|
|
AMPERE_CHANNEL_GPFIFO_A = (0x0000C56F) # type: ignore
|
|
NVC56F_NUMBER_OF_SUBCHANNELS = (8) # type: ignore
|
|
NVC56F_SET_OBJECT = (0x00000000) # type: ignore
|
|
NVC56F_SET_OBJECT_NVCLASS = (15, 0) # type: ignore
|
|
NVC56F_SET_OBJECT_ENGINE = (20, 16) # type: ignore
|
|
NVC56F_SET_OBJECT_ENGINE_SW = 0x0000001f # type: ignore
|
|
NVC56F_ILLEGAL = (0x00000004) # type: ignore
|
|
NVC56F_ILLEGAL_HANDLE = (31, 0) # type: ignore
|
|
NVC56F_NOP = (0x00000008) # type: ignore
|
|
NVC56F_NOP_HANDLE = (31, 0) # type: ignore
|
|
NVC56F_SEMAPHOREA = (0x00000010) # type: ignore
|
|
NVC56F_SEMAPHOREA_OFFSET_UPPER = (7, 0) # type: ignore
|
|
NVC56F_SEMAPHOREB = (0x00000014) # type: ignore
|
|
NVC56F_SEMAPHOREB_OFFSET_LOWER = (31, 2) # type: ignore
|
|
NVC56F_SEMAPHOREC = (0x00000018) # type: ignore
|
|
NVC56F_SEMAPHOREC_PAYLOAD = (31, 0) # type: ignore
|
|
NVC56F_SEMAPHORED = (0x0000001C) # type: ignore
|
|
NVC56F_SEMAPHORED_OPERATION = (4, 0) # type: ignore
|
|
NVC56F_SEMAPHORED_OPERATION_ACQUIRE = 0x00000001 # type: ignore
|
|
NVC56F_SEMAPHORED_OPERATION_RELEASE = 0x00000002 # type: ignore
|
|
NVC56F_SEMAPHORED_OPERATION_ACQ_GEQ = 0x00000004 # type: ignore
|
|
NVC56F_SEMAPHORED_OPERATION_ACQ_AND = 0x00000008 # type: ignore
|
|
NVC56F_SEMAPHORED_OPERATION_REDUCTION = 0x00000010 # type: ignore
|
|
NVC56F_SEMAPHORED_ACQUIRE_SWITCH = (12, 12) # type: ignore
|
|
NVC56F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED = 0x00000000 # type: ignore
|
|
NVC56F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED = 0x00000001 # type: ignore
|
|
NVC56F_SEMAPHORED_RELEASE_WFI = (20, 20) # type: ignore
|
|
NVC56F_SEMAPHORED_RELEASE_WFI_EN = 0x00000000 # type: ignore
|
|
NVC56F_SEMAPHORED_RELEASE_WFI_DIS = 0x00000001 # type: ignore
|
|
NVC56F_SEMAPHORED_RELEASE_SIZE = (24, 24) # type: ignore
|
|
NVC56F_SEMAPHORED_RELEASE_SIZE_16BYTE = 0x00000000 # type: ignore
|
|
NVC56F_SEMAPHORED_RELEASE_SIZE_4BYTE = 0x00000001 # type: ignore
|
|
NVC56F_SEMAPHORED_REDUCTION = (30, 27) # type: ignore
|
|
NVC56F_SEMAPHORED_REDUCTION_MIN = 0x00000000 # type: ignore
|
|
NVC56F_SEMAPHORED_REDUCTION_MAX = 0x00000001 # type: ignore
|
|
NVC56F_SEMAPHORED_REDUCTION_XOR = 0x00000002 # type: ignore
|
|
NVC56F_SEMAPHORED_REDUCTION_AND = 0x00000003 # type: ignore
|
|
NVC56F_SEMAPHORED_REDUCTION_OR = 0x00000004 # type: ignore
|
|
NVC56F_SEMAPHORED_REDUCTION_ADD = 0x00000005 # type: ignore
|
|
NVC56F_SEMAPHORED_REDUCTION_INC = 0x00000006 # type: ignore
|
|
NVC56F_SEMAPHORED_REDUCTION_DEC = 0x00000007 # type: ignore
|
|
NVC56F_SEMAPHORED_FORMAT = (31, 31) # type: ignore
|
|
NVC56F_SEMAPHORED_FORMAT_SIGNED = 0x00000000 # type: ignore
|
|
NVC56F_SEMAPHORED_FORMAT_UNSIGNED = 0x00000001 # type: ignore
|
|
NVC56F_NON_STALL_INTERRUPT = (0x00000020) # type: ignore
|
|
NVC56F_NON_STALL_INTERRUPT_HANDLE = (31, 0) # type: ignore
|
|
NVC56F_FB_FLUSH = (0x00000024) # type: ignore
|
|
NVC56F_FB_FLUSH_HANDLE = (31, 0) # type: ignore
|
|
NVC56F_MEM_OP_A = (0x00000028) # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID = (5, 0) # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE = (5, 0) # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID = (10, 6) # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE = (7, 6) # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS = 0 # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS = 1 # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2 # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD = 3 # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID = (6, 0) # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR = (11, 11) # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001 # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000 # type: ignore
|
|
NVC56F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO = (31, 12) # type: ignore
|
|
NVC56F_MEM_OP_B = (0x0000002c) # type: ignore
|
|
NVC56F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI = (31, 0) # type: ignore
|
|
NVC56F_MEM_OP_C = (0x00000030) # type: ignore
|
|
NVC56F_MEM_OP_C_MEMBAR_TYPE = (2, 0) # type: ignore
|
|
NVC56F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR = 0x00000000 # type: ignore
|
|
NVC56F_MEM_OP_C_MEMBAR_TYPE_MEMBAR = 0x00000001 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB = (0, 0) # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC = (1, 1) # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY = (4, 2) # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START = 0x00000001 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL = 0x00000002 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED = 0x00000003 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL = 0x00000004 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL = 0x00000005 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE = (6, 5) # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE = 0x00000002 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE = (9, 7) # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ = 0 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE = 1 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 2 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD = 3 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 4 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL = 5 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC = 6 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL = 7 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL = (9, 7) # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 = 0x00000002 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 = 0x00000003 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 = 0x00000004 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 = 0x00000005 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 = 0x00000007 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE = (11, 10) # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT = 0x00000003 # type: ignore
|
|
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO = (31, 12) # type: ignore
|
|
NVC56F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG = (19, 0) # type: ignore
|
|
NVC56F_MEM_OP_D = (0x00000034) # type: ignore
|
|
NVC56F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI = (26, 0) # type: ignore
|
|
NVC56F_MEM_OP_D_OPERATION = (31, 27) # type: ignore
|
|
NVC56F_MEM_OP_D_OPERATION_MEMBAR = 0x00000005 # type: ignore
|
|
NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009 # type: ignore
|
|
NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a # type: ignore
|
|
NVC56F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE = 0x0000000d # type: ignore
|
|
NVC56F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE = 0x0000000e # type: ignore
|
|
NVC56F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES = 0x0000000e # type: ignore
|
|
NVC56F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS = 0x0000000f # type: ignore
|
|
NVC56F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010 # type: ignore
|
|
NVC56F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS = 0x00000015 # type: ignore
|
|
NVC56F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR = 0x00000016 # type: ignore
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE = (1, 0) # type: ignore
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC = 0x00000000 # type: ignore
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC = 0x00000001 # type: ignore
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL = 0x00000002 # type: ignore
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED = 0x00000003 # type: ignore
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE = (2, 2) # type: ignore
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC = 0x00000000 # type: ignore
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC = 0x00000001 # type: ignore
|
|
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK = (6, 3) # type: ignore
|
|
NVC56F_SET_REFERENCE = (0x00000050) # type: ignore
|
|
NVC56F_SET_REFERENCE_COUNT = (31, 0) # type: ignore
|
|
NVC56F_SEM_ADDR_LO = (0x0000005c) # type: ignore
|
|
NVC56F_SEM_ADDR_LO_OFFSET = (31, 2) # type: ignore
|
|
NVC56F_SEM_ADDR_HI = (0x00000060) # type: ignore
|
|
NVC56F_SEM_ADDR_HI_OFFSET = (7, 0) # type: ignore
|
|
NVC56F_SEM_PAYLOAD_LO = (0x00000064) # type: ignore
|
|
NVC56F_SEM_PAYLOAD_LO_PAYLOAD = (31, 0) # type: ignore
|
|
NVC56F_SEM_PAYLOAD_HI = (0x00000068) # type: ignore
|
|
NVC56F_SEM_PAYLOAD_HI_PAYLOAD = (31, 0) # type: ignore
|
|
NVC56F_SEM_EXECUTE = (0x0000006c) # type: ignore
|
|
NVC56F_SEM_EXECUTE_OPERATION = (2, 0) # type: ignore
|
|
NVC56F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000 # type: ignore
|
|
NVC56F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001 # type: ignore
|
|
NVC56F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ = 0x00000002 # type: ignore
|
|
NVC56F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ = 0x00000003 # type: ignore
|
|
NVC56F_SEM_EXECUTE_OPERATION_ACQ_AND = 0x00000004 # type: ignore
|
|
NVC56F_SEM_EXECUTE_OPERATION_ACQ_NOR = 0x00000005 # type: ignore
|
|
NVC56F_SEM_EXECUTE_OPERATION_REDUCTION = 0x00000006 # type: ignore
|
|
NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG = (12, 12) # type: ignore
|
|
NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS = 0x00000000 # type: ignore
|
|
NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN = 0x00000001 # type: ignore
|
|
NVC56F_SEM_EXECUTE_RELEASE_WFI = (20, 20) # type: ignore
|
|
NVC56F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000 # type: ignore
|
|
NVC56F_SEM_EXECUTE_RELEASE_WFI_EN = 0x00000001 # type: ignore
|
|
NVC56F_SEM_EXECUTE_PAYLOAD_SIZE = (24, 24) # type: ignore
|
|
NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000 # type: ignore
|
|
NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT = 0x00000001 # type: ignore
|
|
NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP = (25, 25) # type: ignore
|
|
NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS = 0x00000000 # type: ignore
|
|
NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN = 0x00000001 # type: ignore
|
|
NVC56F_SEM_EXECUTE_REDUCTION = (30, 27) # type: ignore
|
|
NVC56F_SEM_EXECUTE_REDUCTION_IMIN = 0x00000000 # type: ignore
|
|
NVC56F_SEM_EXECUTE_REDUCTION_IMAX = 0x00000001 # type: ignore
|
|
NVC56F_SEM_EXECUTE_REDUCTION_IXOR = 0x00000002 # type: ignore
|
|
NVC56F_SEM_EXECUTE_REDUCTION_IAND = 0x00000003 # type: ignore
|
|
NVC56F_SEM_EXECUTE_REDUCTION_IOR = 0x00000004 # type: ignore
|
|
NVC56F_SEM_EXECUTE_REDUCTION_IADD = 0x00000005 # type: ignore
|
|
NVC56F_SEM_EXECUTE_REDUCTION_INC = 0x00000006 # type: ignore
|
|
NVC56F_SEM_EXECUTE_REDUCTION_DEC = 0x00000007 # type: ignore
|
|
NVC56F_SEM_EXECUTE_REDUCTION_FORMAT = (31, 31) # type: ignore
|
|
NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED = 0x00000000 # type: ignore
|
|
NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED = 0x00000001 # type: ignore
|
|
NVC56F_WFI = (0x00000078) # type: ignore
|
|
NVC56F_WFI_SCOPE = (0, 0) # type: ignore
|
|
NVC56F_WFI_SCOPE_CURRENT_SCG_TYPE = 0x00000000 # type: ignore
|
|
NVC56F_WFI_SCOPE_CURRENT_VEID = 0x00000000 # type: ignore
|
|
NVC56F_WFI_SCOPE_ALL = 0x00000001 # type: ignore
|
|
NVC56F_YIELD = (0x00000080) # type: ignore
|
|
NVC56F_YIELD_OP = (1, 0) # type: ignore
|
|
NVC56F_YIELD_OP_NOP = 0x00000000 # type: ignore
|
|
NVC56F_YIELD_OP_TSG = 0x00000003 # type: ignore
|
|
NVC56F_CLEAR_FAULTED = (0x00000084) # type: ignore
|
|
NVC56F_CLEAR_FAULTED_HANDLE = (30, 0) # type: ignore
|
|
NVC56F_CLEAR_FAULTED_TYPE = (31, 31) # type: ignore
|
|
NVC56F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED = 0x00000000 # type: ignore
|
|
NVC56F_CLEAR_FAULTED_TYPE_ENG_FAULTED = 0x00000001 # type: ignore
|
|
NVC56F_GP_ENTRY__SIZE = 8 # type: ignore
|
|
NVC56F_GP_ENTRY0_FETCH = (0, 0) # type: ignore
|
|
NVC56F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000 # type: ignore
|
|
NVC56F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001 # type: ignore
|
|
NVC56F_GP_ENTRY0_GET = (31, 2) # type: ignore
|
|
NVC56F_GP_ENTRY0_OPERAND = (31, 0) # type: ignore
|
|
NVC56F_GP_ENTRY1_GET_HI = (7, 0) # type: ignore
|
|
NVC56F_GP_ENTRY1_LEVEL = (9, 9) # type: ignore
|
|
NVC56F_GP_ENTRY1_LEVEL_MAIN = 0x00000000 # type: ignore
|
|
NVC56F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001 # type: ignore
|
|
NVC56F_GP_ENTRY1_LENGTH = (30, 10) # type: ignore
|
|
NVC56F_GP_ENTRY1_SYNC = (31, 31) # type: ignore
|
|
NVC56F_GP_ENTRY1_SYNC_PROCEED = 0x00000000 # type: ignore
|
|
NVC56F_GP_ENTRY1_SYNC_WAIT = 0x00000001 # type: ignore
|
|
NVC56F_GP_ENTRY1_OPCODE = (7, 0) # type: ignore
|
|
NVC56F_GP_ENTRY1_OPCODE_NOP = 0x00000000 # type: ignore
|
|
NVC56F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001 # type: ignore
|
|
NVC56F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002 # type: ignore
|
|
NVC56F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003 # type: ignore
|
|
NVC56F_DMA_METHOD_ADDRESS_OLD = (12, 2) # type: ignore
|
|
NVC56F_DMA_METHOD_ADDRESS = (11, 0) # type: ignore
|
|
NVC56F_DMA_SUBDEVICE_MASK = (15, 4) # type: ignore
|
|
NVC56F_DMA_METHOD_SUBCHANNEL = (15, 13) # type: ignore
|
|
NVC56F_DMA_TERT_OP = (17, 16) # type: ignore
|
|
NVC56F_DMA_TERT_OP_GRP0_INC_METHOD = (0x00000000) # type: ignore
|
|
NVC56F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK = (0x00000001) # type: ignore
|
|
NVC56F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK = (0x00000002) # type: ignore
|
|
NVC56F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK = (0x00000003) # type: ignore
|
|
NVC56F_DMA_TERT_OP_GRP2_NON_INC_METHOD = (0x00000000) # type: ignore
|
|
NVC56F_DMA_METHOD_COUNT_OLD = (28, 18) # type: ignore
|
|
NVC56F_DMA_METHOD_COUNT = (28, 16) # type: ignore
|
|
NVC56F_DMA_IMMD_DATA = (28, 16) # type: ignore
|
|
NVC56F_DMA_SEC_OP = (31, 29) # type: ignore
|
|
NVC56F_DMA_SEC_OP_GRP0_USE_TERT = (0x00000000) # type: ignore
|
|
NVC56F_DMA_SEC_OP_INC_METHOD = (0x00000001) # type: ignore
|
|
NVC56F_DMA_SEC_OP_GRP2_USE_TERT = (0x00000002) # type: ignore
|
|
NVC56F_DMA_SEC_OP_NON_INC_METHOD = (0x00000003) # type: ignore
|
|
NVC56F_DMA_SEC_OP_IMMD_DATA_METHOD = (0x00000004) # type: ignore
|
|
NVC56F_DMA_SEC_OP_ONE_INC = (0x00000005) # type: ignore
|
|
NVC56F_DMA_SEC_OP_RESERVED6 = (0x00000006) # type: ignore
|
|
NVC56F_DMA_SEC_OP_END_PB_SEGMENT = (0x00000007) # type: ignore
|
|
NVC56F_DMA_INCR_ADDRESS = (11, 0) # type: ignore
|
|
NVC56F_DMA_INCR_SUBCHANNEL = (15, 13) # type: ignore
|
|
NVC56F_DMA_INCR_COUNT = (28, 16) # type: ignore
|
|
NVC56F_DMA_INCR_OPCODE = (31, 29) # type: ignore
|
|
NVC56F_DMA_INCR_OPCODE_VALUE = (0x00000001) # type: ignore
|
|
NVC56F_DMA_INCR_DATA = (31, 0) # type: ignore
|
|
NVC56F_DMA_NONINCR_ADDRESS = (11, 0) # type: ignore
|
|
NVC56F_DMA_NONINCR_SUBCHANNEL = (15, 13) # type: ignore
|
|
NVC56F_DMA_NONINCR_COUNT = (28, 16) # type: ignore
|
|
NVC56F_DMA_NONINCR_OPCODE = (31, 29) # type: ignore
|
|
NVC56F_DMA_NONINCR_OPCODE_VALUE = (0x00000003) # type: ignore
|
|
NVC56F_DMA_NONINCR_DATA = (31, 0) # type: ignore
|
|
NVC56F_DMA_ONEINCR_ADDRESS = (11, 0) # type: ignore
|
|
NVC56F_DMA_ONEINCR_SUBCHANNEL = (15, 13) # type: ignore
|
|
NVC56F_DMA_ONEINCR_COUNT = (28, 16) # type: ignore
|
|
NVC56F_DMA_ONEINCR_OPCODE = (31, 29) # type: ignore
|
|
NVC56F_DMA_ONEINCR_OPCODE_VALUE = (0x00000005) # type: ignore
|
|
NVC56F_DMA_ONEINCR_DATA = (31, 0) # type: ignore
|
|
NVC56F_DMA_NOP = (0x00000000) # type: ignore
|
|
NVC56F_DMA_IMMD_ADDRESS = (11, 0) # type: ignore
|
|
NVC56F_DMA_IMMD_SUBCHANNEL = (15, 13) # type: ignore
|
|
NVC56F_DMA_IMMD_DATA = (28, 16) # type: ignore
|
|
NVC56F_DMA_IMMD_OPCODE = (31, 29) # type: ignore
|
|
NVC56F_DMA_IMMD_OPCODE_VALUE = (0x00000004) # type: ignore
|
|
NVC56F_DMA_SET_SUBDEVICE_MASK_VALUE = (15, 4) # type: ignore
|
|
NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE = (31, 16) # type: ignore
|
|
NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000001) # type: ignore
|
|
NVC56F_DMA_STORE_SUBDEVICE_MASK_VALUE = (15, 4) # type: ignore
|
|
NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE = (31, 16) # type: ignore
|
|
NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000002) # type: ignore
|
|
NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE = (31, 16) # type: ignore
|
|
NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000003) # type: ignore
|
|
NVC56F_DMA_ENDSEG_OPCODE = (31, 29) # type: ignore
|
|
NVC56F_DMA_ENDSEG_OPCODE_VALUE = (0x00000007) # type: ignore
|
|
NVC56F_DMA_ADDRESS = (12, 2) # type: ignore
|
|
NVC56F_DMA_SUBCH = (15, 13) # type: ignore
|
|
NVC56F_DMA_OPCODE3 = (17, 16) # type: ignore
|
|
NVC56F_DMA_OPCODE3_NONE = (0x00000000) # type: ignore
|
|
NVC56F_DMA_COUNT = (28, 18) # type: ignore
|
|
NVC56F_DMA_OPCODE = (31, 29) # type: ignore
|
|
NVC56F_DMA_OPCODE_METHOD = (0x00000000) # type: ignore
|
|
NVC56F_DMA_OPCODE_NONINC_METHOD = (0x00000002) # type: ignore
|
|
NVC56F_DMA_DATA = (31, 0) # type: ignore
|
|
HOPPER_CHANNEL_GPFIFO_A = (0x0000C86F) # type: ignore
|
|
NVC86F_SET_OBJECT = (0x00000000) # type: ignore
|
|
NVC86F_SEM_ADDR_LO = (0x0000005c) # type: ignore
|
|
NVC86F_SEM_ADDR_LO_OFFSET = (31, 2) # type: ignore
|
|
NVC86F_SEM_ADDR_HI = (0x00000060) # type: ignore
|
|
NVC86F_SEM_ADDR_HI_OFFSET = (24, 0) # type: ignore
|
|
NVC86F_SEM_PAYLOAD_LO = (0x00000064) # type: ignore
|
|
NVC86F_SEM_PAYLOAD_HI = (0x00000068) # type: ignore
|
|
NVC86F_SEM_EXECUTE = (0x0000006c) # type: ignore
|
|
NVC86F_SEM_EXECUTE_OPERATION = (2, 0) # type: ignore
|
|
NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000 # type: ignore
|
|
NVC86F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001 # type: ignore
|
|
NVC86F_SEM_EXECUTE_RELEASE_WFI = (20, 20) # type: ignore
|
|
NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000 # type: ignore
|
|
NVC86F_SEM_EXECUTE_PAYLOAD_SIZE = (24, 24) # type: ignore
|
|
NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000 # type: ignore
|
|
NVC86F_GP_ENTRY__SIZE = 8 # type: ignore
|
|
NVC86F_GP_ENTRY0_FETCH = (0, 0) # type: ignore
|
|
NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000 # type: ignore
|
|
NVC86F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001 # type: ignore
|
|
NVC86F_GP_ENTRY0_GET = (31, 2) # type: ignore
|
|
NVC86F_GP_ENTRY0_OPERAND = (31, 0) # type: ignore
|
|
NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND = (24, 8) # type: ignore
|
|
NVC86F_GP_ENTRY1_GET_HI = (7, 0) # type: ignore
|
|
NVC86F_GP_ENTRY1_LEVEL = (9, 9) # type: ignore
|
|
NVC86F_GP_ENTRY1_LEVEL_MAIN = 0x00000000 # type: ignore
|
|
NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001 # type: ignore
|
|
NVC86F_GP_ENTRY1_LENGTH = (30, 10) # type: ignore
|
|
NVC86F_GP_ENTRY1_SYNC = (31, 31) # type: ignore
|
|
NVC86F_GP_ENTRY1_SYNC_PROCEED = 0x00000000 # type: ignore
|
|
NVC86F_GP_ENTRY1_SYNC_WAIT = 0x00000001 # type: ignore
|
|
NVC86F_GP_ENTRY1_OPCODE = (7, 0) # type: ignore
|
|
NVC86F_GP_ENTRY1_OPCODE_NOP = 0x00000000 # type: ignore
|
|
NVC86F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001 # type: ignore
|
|
NVC86F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002 # type: ignore
|
|
NVC86F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003 # type: ignore
|
|
NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE = 0x00000004 # type: ignore
|
|
NVC86F_WFI = (0x00000078) # type: ignore
|
|
NVC86F_WFI_SCOPE = (0, 0) # type: ignore
|
|
NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE = 0x00000000 # type: ignore
|
|
NVC86F_WFI_SCOPE_CURRENT_VEID = 0x00000000 # type: ignore
|
|
NVC86F_WFI_SCOPE_ALL = 0x00000001 # type: ignore
|
|
NVC86F_MEM_OP_A = (0x00000028) # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID = (5, 0) # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE = (5, 0) # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID = (10, 6) # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE = (7, 6) # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS = 0 # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS = 1 # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2 # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD = 3 # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID = (8, 0) # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR = (11, 11) # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001 # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000 # type: ignore
|
|
NVC86F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO = (31, 12) # type: ignore
|
|
NVC86F_MEM_OP_B = (0x0000002c) # type: ignore
|
|
NVC86F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI = (31, 0) # type: ignore
|
|
NVC86F_MEM_OP_C = (0x00000030) # type: ignore
|
|
NVC86F_MEM_OP_C_MEMBAR_TYPE = (2, 0) # type: ignore
|
|
NVC86F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR = 0x00000000 # type: ignore
|
|
NVC86F_MEM_OP_C_MEMBAR_TYPE_MEMBAR = 0x00000001 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB = (0, 0) # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC = (1, 1) # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY = (4, 2) # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START = 0x00000001 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL = 0x00000002 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED = 0x00000003 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL = 0x00000004 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL = 0x00000005 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE = (6, 5) # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE = 0x00000002 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE = (9, 7) # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ = 0 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE = 1 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 2 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD = 3 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 4 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL = 5 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC = 6 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL = 7 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL = (9, 7) # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 = 0x00000002 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 = 0x00000003 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 = 0x00000004 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 = 0x00000005 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 = 0x00000007 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE = (11, 10) # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT = 0x00000003 # type: ignore
|
|
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO = (31, 12) # type: ignore
|
|
NVC86F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG = (19, 0) # type: ignore
|
|
NVC86F_MEM_OP_D = (0x00000034) # type: ignore
|
|
NVC86F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI = (26, 0) # type: ignore
|
|
NVC86F_MEM_OP_D_OPERATION = (31, 27) # type: ignore
|
|
NVC86F_MEM_OP_D_OPERATION_MEMBAR = 0x00000005 # type: ignore
|
|
NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009 # type: ignore
|
|
NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a # type: ignore
|
|
NVC86F_MEM_OP_D_OPERATION_MMU_OPERATION = 0x0000000b # type: ignore
|
|
NVC86F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE = 0x0000000d # type: ignore
|
|
NVC86F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE = 0x0000000e # type: ignore
|
|
NVC86F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES = 0x0000000e # type: ignore
|
|
NVC86F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS = 0x0000000f # type: ignore
|
|
NVC86F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010 # type: ignore
|
|
NVC86F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS = 0x00000015 # type: ignore
|
|
NVC86F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR = 0x00000016 # type: ignore
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE = (1, 0) # type: ignore
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC = 0x00000000 # type: ignore
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC = 0x00000001 # type: ignore
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL = 0x00000002 # type: ignore
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED = 0x00000003 # type: ignore
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE = (2, 2) # type: ignore
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC = 0x00000000 # type: ignore
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC = 0x00000001 # type: ignore
|
|
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK = (6, 3) # type: ignore
|
|
NVC86F_MEM_OP_D_MMU_OPERATION_TYPE = (23, 20) # type: ignore
|
|
NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED = 0x00000000 # type: ignore
|
|
NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP = 0x00000001 # type: ignore
|
|
BLACKWELL_CHANNEL_GPFIFO_A = (0x0000C96F) # type: ignore
|
|
NVC96F_SET_OBJECT = (0x00000000) # type: ignore
|
|
NVC96F_SEM_ADDR_LO = (0x0000005c) # type: ignore
|
|
NVC96F_SEM_ADDR_LO_OFFSET = (31, 2) # type: ignore
|
|
NVC96F_SEM_ADDR_HI = (0x00000060) # type: ignore
|
|
NVC96F_SEM_ADDR_HI_OFFSET = (24, 0) # type: ignore
|
|
NVC96F_SEM_PAYLOAD_LO = (0x00000064) # type: ignore
|
|
NVC96F_SEM_PAYLOAD_HI = (0x00000068) # type: ignore
|
|
NVC96F_SEM_EXECUTE = (0x0000006c) # type: ignore
|
|
NVC96F_SEM_EXECUTE_OPERATION = (2, 0) # type: ignore
|
|
NVC96F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000 # type: ignore
|
|
NVC96F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001 # type: ignore
|
|
NVC96F_SEM_EXECUTE_RELEASE_WFI = (20, 20) # type: ignore
|
|
NVC96F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000 # type: ignore
|
|
NVC96F_SEM_EXECUTE_PAYLOAD_SIZE = (24, 24) # type: ignore
|
|
NVC96F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000 # type: ignore
|
|
NVC96F_GP_ENTRY__SIZE = 8 # type: ignore
|
|
NVC96F_GP_ENTRY0_FETCH = (0, 0) # type: ignore
|
|
NVC96F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000 # type: ignore
|
|
NVC96F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001 # type: ignore
|
|
NVC96F_GP_ENTRY0_GET = (31, 2) # type: ignore
|
|
NVC96F_GP_ENTRY0_OPERAND = (31, 0) # type: ignore
|
|
NVC96F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND = (24, 8) # type: ignore
|
|
NVC96F_GP_ENTRY1_GET_HI = (7, 0) # type: ignore
|
|
NVC96F_GP_ENTRY1_LEVEL = (9, 9) # type: ignore
|
|
NVC96F_GP_ENTRY1_LEVEL_MAIN = 0x00000000 # type: ignore
|
|
NVC96F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001 # type: ignore
|
|
NVC96F_GP_ENTRY1_LENGTH = (30, 10) # type: ignore
|
|
NVC96F_GP_ENTRY1_SYNC = (31, 31) # type: ignore
|
|
NVC96F_GP_ENTRY1_SYNC_PROCEED = 0x00000000 # type: ignore
|
|
NVC96F_GP_ENTRY1_SYNC_WAIT = 0x00000001 # type: ignore
|
|
NVC96F_GP_ENTRY1_OPCODE = (7, 0) # type: ignore
|
|
NVC96F_GP_ENTRY1_OPCODE_NOP = 0x00000000 # type: ignore
|
|
NVC96F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001 # type: ignore
|
|
NVC96F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002 # type: ignore
|
|
NVC96F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003 # type: ignore
|
|
NVC96F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE = 0x00000004 # type: ignore
|
|
BLACKWELL_USERMODE_A = (0xc761) # type: ignore
|
|
GT200_DEBUGGER = (0x83de) # type: ignore
|
|
NV83DE_ALLOC_PARAMETERS_MESSAGE_ID = (0x83de) # type: ignore
|
|
MAXWELL_PROFILER_DEVICE = (0xb2cc) # type: ignore
|
|
NVB2CC_ALLOC_PARAMETERS_MESSAGE_ID = (0xb2cc) # type: ignore
|
|
AMPERE_COMPUTE_A = 0xC6C0 # type: ignore
|
|
NVC6C0_SET_OBJECT = 0x0000 # type: ignore
|
|
NVC6C0_SET_OBJECT_CLASS_ID = (15, 0) # type: ignore
|
|
NVC6C0_SET_OBJECT_ENGINE_ID = (20, 16) # type: ignore
|
|
NVC6C0_NO_OPERATION = 0x0100 # type: ignore
|
|
NVC6C0_NO_OPERATION_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_NOTIFY_A = 0x0104 # type: ignore
|
|
NVC6C0_SET_NOTIFY_A_ADDRESS_UPPER = (7, 0) # type: ignore
|
|
NVC6C0_SET_NOTIFY_B = 0x0108 # type: ignore
|
|
NVC6C0_SET_NOTIFY_B_ADDRESS_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_NOTIFY = 0x010c # type: ignore
|
|
NVC6C0_NOTIFY_TYPE = (31, 0) # type: ignore
|
|
NVC6C0_NOTIFY_TYPE_WRITE_ONLY = 0x00000000 # type: ignore
|
|
NVC6C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN = 0x00000001 # type: ignore
|
|
NVC6C0_WAIT_FOR_IDLE = 0x0110 # type: ignore
|
|
NVC6C0_WAIT_FOR_IDLE_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_A = 0x0130 # type: ignore
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER = (7, 0) # type: ignore
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_B = 0x0134 # type: ignore
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C = 0x0138 # type: ignore
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE = (2, 0) # type: ignore
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002 # type: ignore
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003 # type: ignore
|
|
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004 # type: ignore
|
|
NVC6C0_SEND_GO_IDLE = 0x013c # type: ignore
|
|
NVC6C0_SEND_GO_IDLE_V = (31, 0) # type: ignore
|
|
NVC6C0_PM_TRIGGER = 0x0140 # type: ignore
|
|
NVC6C0_PM_TRIGGER_V = (31, 0) # type: ignore
|
|
NVC6C0_PM_TRIGGER_WFI = 0x0144 # type: ignore
|
|
NVC6C0_PM_TRIGGER_WFI_V = (31, 0) # type: ignore
|
|
NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN = 0x0148 # type: ignore
|
|
NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN_V = (31, 0) # type: ignore
|
|
NVC6C0_FE_ATOMIC_SEQUENCE_END = 0x014c # type: ignore
|
|
NVC6C0_FE_ATOMIC_SEQUENCE_END_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER = 0x0150 # type: ignore
|
|
NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_INSTRUMENTATION_METHOD_DATA = 0x0154 # type: ignore
|
|
NVC6C0_SET_INSTRUMENTATION_METHOD_DATA_V = (31, 0) # type: ignore
|
|
NVC6C0_LINE_LENGTH_IN = 0x0180 # type: ignore
|
|
NVC6C0_LINE_LENGTH_IN_VALUE = (31, 0) # type: ignore
|
|
NVC6C0_LINE_COUNT = 0x0184 # type: ignore
|
|
NVC6C0_LINE_COUNT_VALUE = (31, 0) # type: ignore
|
|
NVC6C0_OFFSET_OUT_UPPER = 0x0188 # type: ignore
|
|
NVC6C0_OFFSET_OUT_UPPER_VALUE = (16, 0) # type: ignore
|
|
NVC6C0_OFFSET_OUT = 0x018c # type: ignore
|
|
NVC6C0_OFFSET_OUT_VALUE = (31, 0) # type: ignore
|
|
NVC6C0_PITCH_OUT = 0x0190 # type: ignore
|
|
NVC6C0_PITCH_OUT_VALUE = (31, 0) # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE = 0x0194 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_WIDTH = (3, 0) # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = 0x00000000 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT = (7, 4) # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = 0x00000000 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = 0x00000001 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = 0x00000002 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = 0x00000003 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = 0x00000004 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = 0x00000005 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH = (11, 8) # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = 0x00000000 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = 0x00000001 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = 0x00000002 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = 0x00000003 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = 0x00000004 # type: ignore
|
|
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = 0x00000005 # type: ignore
|
|
NVC6C0_SET_DST_WIDTH = 0x0198 # type: ignore
|
|
NVC6C0_SET_DST_WIDTH_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_DST_HEIGHT = 0x019c # type: ignore
|
|
NVC6C0_SET_DST_HEIGHT_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_DST_DEPTH = 0x01a0 # type: ignore
|
|
NVC6C0_SET_DST_DEPTH_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_DST_LAYER = 0x01a4 # type: ignore
|
|
NVC6C0_SET_DST_LAYER_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_DST_ORIGIN_BYTES_X = 0x01a8 # type: ignore
|
|
NVC6C0_SET_DST_ORIGIN_BYTES_X_V = (20, 0) # type: ignore
|
|
NVC6C0_SET_DST_ORIGIN_SAMPLES_Y = 0x01ac # type: ignore
|
|
NVC6C0_SET_DST_ORIGIN_SAMPLES_Y_V = (16, 0) # type: ignore
|
|
NVC6C0_LAUNCH_DMA = 0x01b0 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT = (0, 0) # type: ignore
|
|
NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = 0x00000000 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = 0x00000001 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_COMPLETION_TYPE = (5, 4) # type: ignore
|
|
NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE = 0x00000000 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY = 0x00000001 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE = 0x00000002 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE = (9, 8) # type: ignore
|
|
NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE = 0x00000000 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT = 0x00000001 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE = (12, 12) # type: ignore
|
|
NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS = 0x00000000 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD = 0x00000001 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE = (1, 1) # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP = (15, 13) # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD = 0x00000000 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN = 0x00000001 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX = 0x00000002 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_INC = 0x00000003 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC = 0x00000004 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_AND = 0x00000005 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_OR = 0x00000006 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR = 0x00000007 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT = (3, 2) # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE = (6, 6) # type: ignore
|
|
NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_LOAD_INLINE_DATA = 0x01b4 # type: ignore
|
|
NVC6C0_LOAD_INLINE_DATA_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_I2M_SEMAPHORE_A = 0x01dc # type: ignore
|
|
NVC6C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER = (7, 0) # type: ignore
|
|
NVC6C0_SET_I2M_SEMAPHORE_B = 0x01e0 # type: ignore
|
|
NVC6C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_SET_I2M_SEMAPHORE_C = 0x01e4 # type: ignore
|
|
NVC6C0_SET_I2M_SEMAPHORE_C_PAYLOAD = (31, 0) # type: ignore
|
|
NVC6C0_SET_SM_SCG_CONTROL = 0x01e8 # type: ignore
|
|
NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS = (0, 0) # type: ignore
|
|
NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_I2M_SPARE_NOOP00 = 0x01f0 # type: ignore
|
|
NVC6C0_SET_I2M_SPARE_NOOP00_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_I2M_SPARE_NOOP01 = 0x01f4 # type: ignore
|
|
NVC6C0_SET_I2M_SPARE_NOOP01_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_I2M_SPARE_NOOP02 = 0x01f8 # type: ignore
|
|
NVC6C0_SET_I2M_SPARE_NOOP02_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_I2M_SPARE_NOOP03 = 0x01fc # type: ignore
|
|
NVC6C0_SET_I2M_SPARE_NOOP03_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A = 0x0200 # type: ignore
|
|
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER = (7, 0) # type: ignore
|
|
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B = 0x0204 # type: ignore
|
|
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C = 0x0208 # type: ignore
|
|
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE = (31, 0) # type: ignore
|
|
NVC6C0_PERFMON_TRANSFER = 0x0210 # type: ignore
|
|
NVC6C0_PERFMON_TRANSFER_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A = 0x0214 # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER = (7, 0) # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B = 0x0218 # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES = 0x021c # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION = (0, 0) # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_DATA = (4, 4) # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_DATA_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_DATA_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT = (12, 12) # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS = (1, 1) # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA = (2, 2) # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD00 = 0x0220 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD00_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD01 = 0x0224 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD01_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD02 = 0x0228 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD02_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD03 = 0x022c # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD03_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD04 = 0x0230 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD04_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD05 = 0x0234 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD05_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD06 = 0x0238 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD06_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD07 = 0x023c # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD07_V = (31, 0) # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI = 0x0244 # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES = (0, 0) # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG = (25, 4) # type: ignore
|
|
NVC6C0_SET_CWD_REF_COUNTER = 0x0248 # type: ignore
|
|
NVC6C0_SET_CWD_REF_COUNTER_SELECT = (5, 0) # type: ignore
|
|
NVC6C0_SET_CWD_REF_COUNTER_VALUE = (23, 8) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD08 = 0x024c # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD08_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD09 = 0x0250 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD09_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD10 = 0x0254 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD10_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD11 = 0x0258 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD11_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD12 = 0x025c # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD12_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD13 = 0x0260 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD13_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD14 = 0x0264 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD14_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD15 = 0x0268 # type: ignore
|
|
NVC6C0_SET_RESERVED_SW_METHOD15_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_SCG_CONTROL = 0x0270 # type: ignore
|
|
NVC6C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT = (8, 0) # type: ignore
|
|
NVC6C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT = (20, 12) # type: ignore
|
|
NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE = (24, 24) # type: ignore
|
|
NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_COMPUTE_CLASS_VERSION = 0x0280 # type: ignore
|
|
NVC6C0_SET_COMPUTE_CLASS_VERSION_CURRENT = (15, 0) # type: ignore
|
|
NVC6C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED = (31, 16) # type: ignore
|
|
NVC6C0_CHECK_COMPUTE_CLASS_VERSION = 0x0284 # type: ignore
|
|
NVC6C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT = (15, 0) # type: ignore
|
|
NVC6C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED = (31, 16) # type: ignore
|
|
NVC6C0_SET_QMD_VERSION = 0x0288 # type: ignore
|
|
NVC6C0_SET_QMD_VERSION_CURRENT = (15, 0) # type: ignore
|
|
NVC6C0_SET_QMD_VERSION_OLDEST_SUPPORTED = (31, 16) # type: ignore
|
|
NVC6C0_CHECK_QMD_VERSION = 0x0290 # type: ignore
|
|
NVC6C0_CHECK_QMD_VERSION_CURRENT = (15, 0) # type: ignore
|
|
NVC6C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED = (31, 16) # type: ignore
|
|
NVC6C0_INVALIDATE_SKED_CACHES = 0x0298 # type: ignore
|
|
NVC6C0_INVALIDATE_SKED_CACHES_V = (0, 0) # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL = 0x029c # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK = (7, 0) # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE = (8, 8) # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE = (12, 12) # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE = (16, 16) # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE = (20, 20) # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE = (24, 24) # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A = 0x02a0 # type: ignore
|
|
NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER = (16, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B = 0x02a4 # type: ignore
|
|
NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS = (31, 0) # type: ignore
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL = 0x02a8 # type: ignore
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE = (0, 0) # type: ignore
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE = (1, 1) # type: ignore
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_CWD_SLOT_COUNT = 0x02b0 # type: ignore
|
|
NVC6C0_SET_CWD_SLOT_COUNT_V = (7, 0) # type: ignore
|
|
NVC6C0_SEND_PCAS_A = 0x02b4 # type: ignore
|
|
NVC6C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 = (31, 0) # type: ignore
|
|
NVC6C0_SEND_PCAS_B = 0x02b8 # type: ignore
|
|
NVC6C0_SEND_PCAS_B_FROM = (23, 0) # type: ignore
|
|
NVC6C0_SEND_PCAS_B_DELTA = (31, 24) # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS_B = 0x02bc # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE = (0, 0) # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE = (1, 1) # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B = 0x02c0 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION = (3, 0) # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP = 0x00000000 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE = 0x00000001 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE = 0x00000002 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE = 0x00000003 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT = 0x00000006 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE = 0x00000007 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH = 0x00000008 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE = 0x00000009 # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE = 0x0000000A # type: ignore
|
|
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING = 0x0000000B # type: ignore
|
|
NVC6C0_SET_SKED_CACHE_CONTROL = 0x02cc # type: ignore
|
|
NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID = (0, 0) # type: ignore
|
|
NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A = 0x02e4 # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER = (7, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B = 0x02e8 # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C = 0x02ec # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT = (8, 0) # type: ignore
|
|
NVC6C0_SET_SPA_VERSION = 0x0310 # type: ignore
|
|
NVC6C0_SET_SPA_VERSION_MINOR = (7, 0) # type: ignore
|
|
NVC6C0_SET_SPA_VERSION_MAJOR = (15, 8) # type: ignore
|
|
NVC6C0_SET_INLINE_QMD_ADDRESS_A = 0x0318 # type: ignore
|
|
NVC6C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER = (31, 0) # type: ignore
|
|
NVC6C0_SET_INLINE_QMD_ADDRESS_B = 0x031c # type: ignore
|
|
NVC6C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_LOAD_INLINE_QMD_DATA = lambda i: (0x0320+(i)*4) # type: ignore
|
|
NVC6C0_LOAD_INLINE_QMD_DATA_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON00 = 0x0500 # type: ignore
|
|
NVC6C0_SET_FALCON00_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON01 = 0x0504 # type: ignore
|
|
NVC6C0_SET_FALCON01_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON02 = 0x0508 # type: ignore
|
|
NVC6C0_SET_FALCON02_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON03 = 0x050c # type: ignore
|
|
NVC6C0_SET_FALCON03_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON04 = 0x0510 # type: ignore
|
|
NVC6C0_SET_FALCON04_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON05 = 0x0514 # type: ignore
|
|
NVC6C0_SET_FALCON05_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON06 = 0x0518 # type: ignore
|
|
NVC6C0_SET_FALCON06_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON07 = 0x051c # type: ignore
|
|
NVC6C0_SET_FALCON07_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON08 = 0x0520 # type: ignore
|
|
NVC6C0_SET_FALCON08_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON09 = 0x0524 # type: ignore
|
|
NVC6C0_SET_FALCON09_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON10 = 0x0528 # type: ignore
|
|
NVC6C0_SET_FALCON10_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON11 = 0x052c # type: ignore
|
|
NVC6C0_SET_FALCON11_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON12 = 0x0530 # type: ignore
|
|
NVC6C0_SET_FALCON12_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON13 = 0x0534 # type: ignore
|
|
NVC6C0_SET_FALCON13_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON14 = 0x0538 # type: ignore
|
|
NVC6C0_SET_FALCON14_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_FALCON15 = 0x053c # type: ignore
|
|
NVC6C0_SET_FALCON15_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_A = 0x0790 # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER = (16, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_B = 0x0794 # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A = 0x07b0 # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER = (16, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B = 0x07b4 # type: ignore
|
|
NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS = (31, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_CACHE_CONTROL = 0x0d94 # type: ignore
|
|
NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE = (0, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS = lambda i: (0x0da0+(i)*4) # type: ignore
|
|
NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_SM_TIMEOUT_INTERVAL = 0x0de4 # type: ignore
|
|
NVC6C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT = (5, 0) # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI = 0x1288 # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES = (0, 0) # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG = (25, 4) # type: ignore
|
|
NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT = 0x12a8 # type: ignore
|
|
NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL = (0, 0) # type: ignore
|
|
NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE = 0x1330 # type: ignore
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES = (0, 0) # type: ignore
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_TAG = (25, 4) # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE = 0x1334 # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES = (0, 0) # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG = (25, 4) # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE = 0x1338 # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES = (0, 0) # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG = (25, 4) # type: ignore
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI = 0x1424 # type: ignore
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES = (0, 0) # type: ignore
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG = (25, 4) # type: ignore
|
|
NVC6C0_SET_SHADER_EXCEPTIONS = 0x1528 # type: ignore
|
|
NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE = (0, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_A = 0x1550 # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_A_OFFSET_UPPER = (7, 0) # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_B = 0x1554 # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_B_OFFSET_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_C = 0x1558 # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_C_MODE = (2, 0) # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_C_MODE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_C_MODE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002 # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003 # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004 # type: ignore
|
|
NVC6C0_SET_TEX_SAMPLER_POOL_A = 0x155c # type: ignore
|
|
NVC6C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER = (16, 0) # type: ignore
|
|
NVC6C0_SET_TEX_SAMPLER_POOL_B = 0x1560 # type: ignore
|
|
NVC6C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_SET_TEX_SAMPLER_POOL_C = 0x1564 # type: ignore
|
|
NVC6C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX = (19, 0) # type: ignore
|
|
NVC6C0_SET_TEX_HEADER_POOL_A = 0x1574 # type: ignore
|
|
NVC6C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER = (16, 0) # type: ignore
|
|
NVC6C0_SET_TEX_HEADER_POOL_B = 0x1578 # type: ignore
|
|
NVC6C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_SET_TEX_HEADER_POOL_C = 0x157c # type: ignore
|
|
NVC6C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX = (21, 0) # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI = 0x1698 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION = (0, 0) # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA = (4, 4) # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT = (12, 12) # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_OVERRIDE = 0x1944 # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE = (1, 0) # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER = 0x00000001 # type: ignore
|
|
NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER = 0x00000002 # type: ignore
|
|
NVC6C0_PIPE_NOP = 0x1a2c # type: ignore
|
|
NVC6C0_PIPE_NOP_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_SPARE00 = 0x1a30 # type: ignore
|
|
NVC6C0_SET_SPARE00_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_SPARE01 = 0x1a34 # type: ignore
|
|
NVC6C0_SET_SPARE01_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_SPARE02 = 0x1a38 # type: ignore
|
|
NVC6C0_SET_SPARE02_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_SPARE03 = 0x1a3c # type: ignore
|
|
NVC6C0_SET_SPARE03_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_A = 0x1b00 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER = (7, 0) # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_B = 0x1b04 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_C = 0x1b08 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_C_PAYLOAD = (31, 0) # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D = 0x1b0c # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION = (1, 0) # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP = 0x00000003 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE = (20, 20) # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE = (28, 28) # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE = (2, 2) # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE = (3, 3) # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP = (11, 9) # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD = 0x00000000 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN = 0x00000001 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX = 0x00000002 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC = 0x00000003 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC = 0x00000004 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND = 0x00000005 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR = 0x00000006 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR = 0x00000007 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT = (18, 17) # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP = (19, 19) # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE = 0x00000000 # type: ignore
|
|
NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE = 0x00000001 # type: ignore
|
|
NVC6C0_SET_TRAP_HANDLER_A = 0x25f8 # type: ignore
|
|
NVC6C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER = (16, 0) # type: ignore
|
|
NVC6C0_SET_TRAP_HANDLER_B = 0x25fc # type: ignore
|
|
NVC6C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER = (31, 0) # type: ignore
|
|
NVC6C0_SET_BINDLESS_TEXTURE = 0x2608 # type: ignore
|
|
NVC6C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT = (2, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE = lambda i: (0x32f4+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER = lambda i: (0x3314+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V = (31, 0) # type: ignore
|
|
NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3334 # type: ignore
|
|
NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V = (0, 0) # type: ignore
|
|
NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3338 # type: ignore
|
|
NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V = (0, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER = lambda i: (0x333c+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE = lambda i: (0x335c+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT = lambda i: (0x337c+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT = (7, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A = lambda i: (0x339c+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 = (1, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 = (4, 2) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 = (6, 5) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 = (9, 7) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 = (11, 10) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 = (14, 12) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 = (16, 15) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 = (19, 17) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 = (21, 20) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 = (24, 22) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 = (26, 25) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 = (29, 27) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE = (31, 30) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B = lambda i: (0x33bc+(i)*4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE = (0, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE = (2, 1) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED = (3, 3) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC = (19, 4) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL = 0x33dc # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK = (7, 0) # type: ignore
|
|
NVC6C0_START_SHADER_PERFORMANCE_COUNTER = 0x33e0 # type: ignore
|
|
NVC6C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK = (7, 0) # type: ignore
|
|
NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER = 0x33e4 # type: ignore
|
|
NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK = (7, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER = 0x33e8 # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER = 0x33ec # type: ignore
|
|
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V = (31, 0) # type: ignore
|
|
NVC6C0_SET_MME_SHADOW_SCRATCH = lambda i: (0x3400+(i)*4) # type: ignore
|
|
NVC6C0_SET_MME_SHADOW_SCRATCH_V = (31, 0) # type: ignore
|
|
BLACKWELL_COMPUTE_A = 0xCDC0 # type: ignore
|
|
AMPERE_DMA_COPY_A = (0x0000C6B5) # type: ignore
|
|
NVC6B5_NOP = (0x00000100) # type: ignore
|
|
NVC6B5_NOP_PARAMETER = (31, 0) # type: ignore
|
|
NVC6B5_PM_TRIGGER = (0x00000140) # type: ignore
|
|
NVC6B5_PM_TRIGGER_V = (31, 0) # type: ignore
|
|
NVC6B5_SET_SEMAPHORE_A = (0x00000240) # type: ignore
|
|
NVC6B5_SET_SEMAPHORE_A_UPPER = (16, 0) # type: ignore
|
|
NVC6B5_SET_SEMAPHORE_B = (0x00000244) # type: ignore
|
|
NVC6B5_SET_SEMAPHORE_B_LOWER = (31, 0) # type: ignore
|
|
NVC6B5_SET_SEMAPHORE_PAYLOAD = (0x00000248) # type: ignore
|
|
NVC6B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD = (31, 0) # type: ignore
|
|
NVC6B5_SET_RENDER_ENABLE_A = (0x00000254) # type: ignore
|
|
NVC6B5_SET_RENDER_ENABLE_A_UPPER = (7, 0) # type: ignore
|
|
NVC6B5_SET_RENDER_ENABLE_B = (0x00000258) # type: ignore
|
|
NVC6B5_SET_RENDER_ENABLE_B_LOWER = (31, 0) # type: ignore
|
|
NVC6B5_SET_RENDER_ENABLE_C = (0x0000025C) # type: ignore
|
|
NVC6B5_SET_RENDER_ENABLE_C_MODE = (2, 0) # type: ignore
|
|
NVC6B5_SET_RENDER_ENABLE_C_MODE_FALSE = (0x00000000) # type: ignore
|
|
NVC6B5_SET_RENDER_ENABLE_C_MODE_TRUE = (0x00000001) # type: ignore
|
|
NVC6B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = (0x00000002) # type: ignore
|
|
NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = (0x00000003) # type: ignore
|
|
NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = (0x00000004) # type: ignore
|
|
NVC6B5_SET_SRC_PHYS_MODE = (0x00000260) # type: ignore
|
|
NVC6B5_SET_SRC_PHYS_MODE_TARGET = (1, 0) # type: ignore
|
|
NVC6B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) # type: ignore
|
|
NVC6B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) # type: ignore
|
|
NVC6B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # type: ignore
|
|
NVC6B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM = (0x00000003) # type: ignore
|
|
NVC6B5_SET_SRC_PHYS_MODE_BASIC_KIND = (5, 2) # type: ignore
|
|
NVC6B5_SET_SRC_PHYS_MODE_PEER_ID = (8, 6) # type: ignore
|
|
NVC6B5_SET_SRC_PHYS_MODE_FLA = (9, 9) # type: ignore
|
|
NVC6B5_SET_DST_PHYS_MODE = (0x00000264) # type: ignore
|
|
NVC6B5_SET_DST_PHYS_MODE_TARGET = (1, 0) # type: ignore
|
|
NVC6B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) # type: ignore
|
|
NVC6B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) # type: ignore
|
|
NVC6B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # type: ignore
|
|
NVC6B5_SET_DST_PHYS_MODE_TARGET_PEERMEM = (0x00000003) # type: ignore
|
|
NVC6B5_SET_DST_PHYS_MODE_BASIC_KIND = (5, 2) # type: ignore
|
|
NVC6B5_SET_DST_PHYS_MODE_PEER_ID = (8, 6) # type: ignore
|
|
NVC6B5_SET_DST_PHYS_MODE_FLA = (9, 9) # type: ignore
|
|
NVC6B5_LAUNCH_DMA = (0x00000300) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE = (1, 0) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED = (0x00000002) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_FLUSH_ENABLE = (2, 2) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_FLUSH_TYPE = (25, 25) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_FLUSH_TYPE_SYS = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_FLUSH_TYPE_GL = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE = (4, 3) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE = (0x00000002) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE = (0x00000003) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE = (6, 5) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING = (0x00000002) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT = (7, 7) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT = (8, 8) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE = (9, 9) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_REMAP_ENABLE = (10, 10) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_REMAP_ENABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_REMAP_ENABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE = (11, 11) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SRC_TYPE = (12, 12) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DST_TYPE = (13, 13) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DST_TYPE_VIRTUAL = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DST_TYPE_PHYSICAL = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION = (17, 14) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR = (0x00000002) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND = (0x00000003) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR = (0x00000004) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD = (0x00000005) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC = (0x00000006) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC = (0x00000007) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD = (0x0000000A) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN = (18, 18) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE = (19, 19) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_VPRMODE = (23, 22) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_VPRMODE_VPR_NONE = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_RESERVED_START_OF_COPY = (24, 24) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DISABLE_PLC = (26, 26) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DISABLE_PLC_FALSE = (0x00000000) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_DISABLE_PLC_TRUE = (0x00000001) # type: ignore
|
|
NVC6B5_LAUNCH_DMA_RESERVED_ERR_CODE = (31, 28) # type: ignore
|
|
NVC6B5_OFFSET_IN_UPPER = (0x00000400) # type: ignore
|
|
NVC6B5_OFFSET_IN_UPPER_UPPER = (16, 0) # type: ignore
|
|
NVC6B5_OFFSET_IN_LOWER = (0x00000404) # type: ignore
|
|
NVC6B5_OFFSET_IN_LOWER_VALUE = (31, 0) # type: ignore
|
|
NVC6B5_OFFSET_OUT_UPPER = (0x00000408) # type: ignore
|
|
NVC6B5_OFFSET_OUT_UPPER_UPPER = (16, 0) # type: ignore
|
|
NVC6B5_OFFSET_OUT_LOWER = (0x0000040C) # type: ignore
|
|
NVC6B5_OFFSET_OUT_LOWER_VALUE = (31, 0) # type: ignore
|
|
NVC6B5_PITCH_IN = (0x00000410) # type: ignore
|
|
NVC6B5_PITCH_IN_VALUE = (31, 0) # type: ignore
|
|
NVC6B5_PITCH_OUT = (0x00000414) # type: ignore
|
|
NVC6B5_PITCH_OUT_VALUE = (31, 0) # type: ignore
|
|
NVC6B5_LINE_LENGTH_IN = (0x00000418) # type: ignore
|
|
NVC6B5_LINE_LENGTH_IN_VALUE = (31, 0) # type: ignore
|
|
NVC6B5_LINE_COUNT = (0x0000041C) # type: ignore
|
|
NVC6B5_LINE_COUNT_VALUE = (31, 0) # type: ignore
|
|
NVC6B5_SET_REMAP_CONST_A = (0x00000700) # type: ignore
|
|
NVC6B5_SET_REMAP_CONST_A_V = (31, 0) # type: ignore
|
|
NVC6B5_SET_REMAP_CONST_B = (0x00000704) # type: ignore
|
|
NVC6B5_SET_REMAP_CONST_B_V = (31, 0) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS = (0x00000708) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X = (2, 0) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_X = (0x00000000) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y = (0x00000001) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z = (0x00000002) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_W = (0x00000003) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_A = (0x00000004) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_B = (0x00000005) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE = (0x00000006) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y = (6, 4) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X = (0x00000000) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y = (0x00000001) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z = (0x00000002) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W = (0x00000003) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A = (0x00000004) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B = (0x00000005) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE = (0x00000006) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z = (10, 8) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X = (0x00000000) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y = (0x00000001) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z = (0x00000002) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W = (0x00000003) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A = (0x00000004) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B = (0x00000005) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE = (0x00000006) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W = (14, 12) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_X = (0x00000000) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y = (0x00000001) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z = (0x00000002) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_W = (0x00000003) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_A = (0x00000004) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_B = (0x00000005) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE = (0x00000006) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE = (17, 16) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE = (0x00000000) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO = (0x00000001) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE = (0x00000002) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR = (0x00000003) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS = (21, 20) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE = (0x00000000) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO = (0x00000001) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE = (0x00000002) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR = (0x00000003) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS = (25, 24) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE = (0x00000000) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO = (0x00000001) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE = (0x00000002) # type: ignore
|
|
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR = (0x00000003) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE = (0x0000070C) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_WIDTH = (3, 0) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT = (7, 4) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH = (11, 8) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT = (15, 12) # type: ignore
|
|
NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) # type: ignore
|
|
NVC6B5_SET_DST_WIDTH = (0x00000710) # type: ignore
|
|
NVC6B5_SET_DST_WIDTH_V = (31, 0) # type: ignore
|
|
NVC6B5_SET_DST_HEIGHT = (0x00000714) # type: ignore
|
|
NVC6B5_SET_DST_HEIGHT_V = (31, 0) # type: ignore
|
|
NVC6B5_SET_DST_DEPTH = (0x00000718) # type: ignore
|
|
NVC6B5_SET_DST_DEPTH_V = (31, 0) # type: ignore
|
|
NVC6B5_SET_DST_LAYER = (0x0000071C) # type: ignore
|
|
NVC6B5_SET_DST_LAYER_V = (31, 0) # type: ignore
|
|
NVC6B5_SET_DST_ORIGIN = (0x00000720) # type: ignore
|
|
NVC6B5_SET_DST_ORIGIN_X = (15, 0) # type: ignore
|
|
NVC6B5_SET_DST_ORIGIN_Y = (31, 16) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE = (0x00000728) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH = (3, 0) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT = (7, 4) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH = (11, 8) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT = (15, 12) # type: ignore
|
|
NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) # type: ignore
|
|
NVC6B5_SET_SRC_WIDTH = (0x0000072C) # type: ignore
|
|
NVC6B5_SET_SRC_WIDTH_V = (31, 0) # type: ignore
|
|
NVC6B5_SET_SRC_HEIGHT = (0x00000730) # type: ignore
|
|
NVC6B5_SET_SRC_HEIGHT_V = (31, 0) # type: ignore
|
|
NVC6B5_SET_SRC_DEPTH = (0x00000734) # type: ignore
|
|
NVC6B5_SET_SRC_DEPTH_V = (31, 0) # type: ignore
|
|
NVC6B5_SET_SRC_LAYER = (0x00000738) # type: ignore
|
|
NVC6B5_SET_SRC_LAYER_V = (31, 0) # type: ignore
|
|
NVC6B5_SET_SRC_ORIGIN = (0x0000073C) # type: ignore
|
|
NVC6B5_SET_SRC_ORIGIN_X = (15, 0) # type: ignore
|
|
NVC6B5_SET_SRC_ORIGIN_Y = (31, 16) # type: ignore
|
|
NVC6B5_SRC_ORIGIN_X = (0x00000744) # type: ignore
|
|
NVC6B5_SRC_ORIGIN_X_VALUE = (31, 0) # type: ignore
|
|
NVC6B5_SRC_ORIGIN_Y = (0x00000748) # type: ignore
|
|
NVC6B5_SRC_ORIGIN_Y_VALUE = (31, 0) # type: ignore
|
|
NVC6B5_DST_ORIGIN_X = (0x0000074C) # type: ignore
|
|
NVC6B5_DST_ORIGIN_X_VALUE = (31, 0) # type: ignore
|
|
NVC6B5_DST_ORIGIN_Y = (0x00000750) # type: ignore
|
|
NVC6B5_DST_ORIGIN_Y_VALUE = (31, 0) # type: ignore
|
|
NVC6B5_PM_TRIGGER_END = (0x00001114) # type: ignore
|
|
NVC6B5_PM_TRIGGER_END_V = (31, 0) # type: ignore
|
|
BLACKWELL_DMA_COPY_A = (0x0000C9B5) # type: ignore
|
|
NVC9B5_NOP = (0x00000100) # type: ignore
|
|
NVC9B5_NOP_PARAMETER = (31, 0) # type: ignore
|
|
NVC9B5_PM_TRIGGER = (0x00000140) # type: ignore
|
|
NVC9B5_PM_TRIGGER_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_MONITORED_FENCE_TYPE = (0x0000021C) # type: ignore
|
|
NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE = (0, 0) # type: ignore
|
|
NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE = (0x00000000) # type: ignore
|
|
NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT = (0x00000001) # type: ignore
|
|
NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER = (0x00000220) # type: ignore
|
|
NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER = (24, 0) # type: ignore
|
|
NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER = (0x00000224) # type: ignore
|
|
NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER = (31, 0) # type: ignore
|
|
NVC9B5_SET_SEMAPHORE_A = (0x00000240) # type: ignore
|
|
NVC9B5_SET_SEMAPHORE_A_UPPER = (24, 0) # type: ignore
|
|
NVC9B5_SET_SEMAPHORE_B = (0x00000244) # type: ignore
|
|
NVC9B5_SET_SEMAPHORE_B_LOWER = (31, 0) # type: ignore
|
|
NVC9B5_SET_SEMAPHORE_PAYLOAD = (0x00000248) # type: ignore
|
|
NVC9B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD = (31, 0) # type: ignore
|
|
NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER = (0x0000024C) # type: ignore
|
|
NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD = (31, 0) # type: ignore
|
|
NVC9B5_SET_RENDER_ENABLE_A = (0x00000254) # type: ignore
|
|
NVC9B5_SET_RENDER_ENABLE_A_UPPER = (24, 0) # type: ignore
|
|
NVC9B5_SET_RENDER_ENABLE_B = (0x00000258) # type: ignore
|
|
NVC9B5_SET_RENDER_ENABLE_B_LOWER = (31, 0) # type: ignore
|
|
NVC9B5_SET_RENDER_ENABLE_C = (0x0000025C) # type: ignore
|
|
NVC9B5_SET_RENDER_ENABLE_C_MODE = (2, 0) # type: ignore
|
|
NVC9B5_SET_RENDER_ENABLE_C_MODE_FALSE = (0x00000000) # type: ignore
|
|
NVC9B5_SET_RENDER_ENABLE_C_MODE_TRUE = (0x00000001) # type: ignore
|
|
NVC9B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = (0x00000002) # type: ignore
|
|
NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = (0x00000003) # type: ignore
|
|
NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = (0x00000004) # type: ignore
|
|
NVC9B5_SET_SRC_PHYS_MODE = (0x00000260) # type: ignore
|
|
NVC9B5_SET_SRC_PHYS_MODE_TARGET = (1, 0) # type: ignore
|
|
NVC9B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) # type: ignore
|
|
NVC9B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) # type: ignore
|
|
NVC9B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # type: ignore
|
|
NVC9B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM = (0x00000003) # type: ignore
|
|
NVC9B5_SET_SRC_PHYS_MODE_BASIC_KIND = (5, 2) # type: ignore
|
|
NVC9B5_SET_SRC_PHYS_MODE_PEER_ID = (8, 6) # type: ignore
|
|
NVC9B5_SET_SRC_PHYS_MODE_FLA = (9, 9) # type: ignore
|
|
NVC9B5_SET_DST_PHYS_MODE = (0x00000264) # type: ignore
|
|
NVC9B5_SET_DST_PHYS_MODE_TARGET = (1, 0) # type: ignore
|
|
NVC9B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) # type: ignore
|
|
NVC9B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) # type: ignore
|
|
NVC9B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # type: ignore
|
|
NVC9B5_SET_DST_PHYS_MODE_TARGET_PEERMEM = (0x00000003) # type: ignore
|
|
NVC9B5_SET_DST_PHYS_MODE_BASIC_KIND = (5, 2) # type: ignore
|
|
NVC9B5_SET_DST_PHYS_MODE_PEER_ID = (8, 6) # type: ignore
|
|
NVC9B5_SET_DST_PHYS_MODE_FLA = (9, 9) # type: ignore
|
|
NVC9B5_LAUNCH_DMA = (0x00000300) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE = (1, 0) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED = (0x00000002) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_FLUSH_ENABLE = (2, 2) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_FLUSH_TYPE = (25, 25) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_FLUSH_TYPE_SYS = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_FLUSH_TYPE_GL = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE = (4, 3) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP = (0x00000002) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE = (0x00000002) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE = (0x00000003) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE = (6, 5) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING = (0x00000002) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT = (7, 7) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT = (8, 8) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE = (9, 9) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_REMAP_ENABLE = (10, 10) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_REMAP_ENABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_REMAP_ENABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE = (11, 11) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SRC_TYPE = (12, 12) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DST_TYPE = (13, 13) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DST_TYPE_VIRTUAL = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DST_TYPE_PHYSICAL = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION = (17, 14) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR = (0x00000002) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND = (0x00000003) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR = (0x00000004) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD = (0x00000005) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC = (0x00000006) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC = (0x00000007) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA = (0x00000008) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB = (0x00000009) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD = (0x0000000A) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN = (0x0000000B) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX = (0x0000000C) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC = (0x0000000D) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD = (0x0000000E) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE = (0x0000000F) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN = (18, 18) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE = (19, 19) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_COPY_TYPE = (21, 20) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_COPY_TYPE_DEFAULT = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_COPY_TYPE_SECURE = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT = (0x00000002) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_COPY_TYPE_RESERVED = (0x00000003) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_VPRMODE = (22, 22) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_VPRMODE_VPR_NONE = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE = (23, 23) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_RESERVED_START_OF_COPY = (24, 24) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DISABLE_PLC = (26, 26) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DISABLE_PLC_FALSE = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_DISABLE_PLC_TRUE = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE = (27, 27) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD = (0x00000000) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD = (0x00000001) # type: ignore
|
|
NVC9B5_LAUNCH_DMA_RESERVED_ERR_CODE = (31, 28) # type: ignore
|
|
NVC9B5_OFFSET_IN_UPPER = (0x00000400) # type: ignore
|
|
NVC9B5_OFFSET_IN_UPPER_UPPER = (24, 0) # type: ignore
|
|
NVC9B5_OFFSET_IN_LOWER = (0x00000404) # type: ignore
|
|
NVC9B5_OFFSET_IN_LOWER_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_OFFSET_OUT_UPPER = (0x00000408) # type: ignore
|
|
NVC9B5_OFFSET_OUT_UPPER_UPPER = (24, 0) # type: ignore
|
|
NVC9B5_OFFSET_OUT_LOWER = (0x0000040C) # type: ignore
|
|
NVC9B5_OFFSET_OUT_LOWER_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_PITCH_IN = (0x00000410) # type: ignore
|
|
NVC9B5_PITCH_IN_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_PITCH_OUT = (0x00000414) # type: ignore
|
|
NVC9B5_PITCH_OUT_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_LINE_LENGTH_IN = (0x00000418) # type: ignore
|
|
NVC9B5_LINE_LENGTH_IN_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_LINE_COUNT = (0x0000041C) # type: ignore
|
|
NVC9B5_LINE_COUNT_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE = (0x00000500) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_MODE = (0, 0) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT = (0x00000000) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_MODE_DECRYPT = (0x00000001) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET = (20, 19) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_LOCAL_FB = (0x00000000) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_COHERENT_SYSMEM = (0x00000001) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_PEERMEM = (0x00000003) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_PEER_ID = (23, 21) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_FLA = (24, 24) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET = (26, 25) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_LOCAL_FB = (0x00000000) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_COHERENT_SYSMEM = (0x00000001) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_PEERMEM = (0x00000003) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_PEER_ID = (29, 27) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_FLA = (30, 30) # type: ignore
|
|
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_END_OF_COPY = (31, 31) # type: ignore
|
|
NVC9B5_SET_DECRYPT_IV0 = (0x00000504) # type: ignore
|
|
NVC9B5_SET_DECRYPT_IV0_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_SET_DECRYPT_IV1 = (0x00000508) # type: ignore
|
|
NVC9B5_SET_DECRYPT_IV1_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_SET_DECRYPT_IV2 = (0x0000050C) # type: ignore
|
|
NVC9B5_SET_DECRYPT_IV2_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_RESERVED_SET_AESCOUNTER = (0x00000510) # type: ignore
|
|
NVC9B5_RESERVED_SET_AESCOUNTER_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER = (0x00000514) # type: ignore
|
|
NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER = (24, 0) # type: ignore
|
|
NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER = (0x00000518) # type: ignore
|
|
NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER_LOWER = (31, 0) # type: ignore
|
|
NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER = (0x00000530) # type: ignore
|
|
NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER_UPPER = (24, 0) # type: ignore
|
|
NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER = (0x00000534) # type: ignore
|
|
NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER_LOWER = (31, 0) # type: ignore
|
|
NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER = (0x00000538) # type: ignore
|
|
NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER_UPPER = (24, 0) # type: ignore
|
|
NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER = (0x0000053C) # type: ignore
|
|
NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER_LOWER = (31, 0) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS = (0x00000580) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION = (0, 0) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_DECOMPRESS = (0x00000000) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_COMPRESS = (0x00000001) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO = (3, 1) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY = (0x00000000) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_DATA_ONLY = (0x00000001) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK = (0x00000002) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK_CHECKSUM = (0x00000003) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_DEFLATE = (0x00000004) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY_WITH_LONG_FETCH = (0x00000005) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM = (29, 28) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_NONE = (0x00000000) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_ADLER32 = (0x00000001) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_CRC32 = (0x00000002) # type: ignore
|
|
NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_SNAPPY_CRC = (0x00000003) # type: ignore
|
|
NVC9B5_SET_DECOMPRESS_OUT_LENGTH = (0x00000584) # type: ignore
|
|
NVC9B5_SET_DECOMPRESS_OUT_LENGTH_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_UPPER = (0x00000588) # type: ignore
|
|
NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_UPPER_UPPER = (24, 0) # type: ignore
|
|
NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_LOWER = (0x0000058C) # type: ignore
|
|
NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_LOWER_LOWER = (31, 0) # type: ignore
|
|
NVC9B5_SET_DECOMPRESS_CHECKSUM = (0x00000590) # type: ignore
|
|
NVC9B5_SET_DECOMPRESS_CHECKSUM_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_MEMORY_SCRUB_PARAMETERS = (0x000006FC) # type: ignore
|
|
NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE = (0, 0) # type: ignore
|
|
NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE = (0x00000000) # type: ignore
|
|
NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE = (0x00000001) # type: ignore
|
|
NVC9B5_SET_REMAP_CONST_A = (0x00000700) # type: ignore
|
|
NVC9B5_SET_REMAP_CONST_A_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_REMAP_CONST_B = (0x00000704) # type: ignore
|
|
NVC9B5_SET_REMAP_CONST_B_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS = (0x00000708) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_X = (2, 0) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_X = (0x00000000) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y = (0x00000001) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z = (0x00000002) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_W = (0x00000003) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_A = (0x00000004) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_B = (0x00000005) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE = (0x00000006) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Y = (6, 4) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X = (0x00000000) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y = (0x00000001) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z = (0x00000002) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W = (0x00000003) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A = (0x00000004) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B = (0x00000005) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE = (0x00000006) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Z = (10, 8) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X = (0x00000000) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y = (0x00000001) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z = (0x00000002) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W = (0x00000003) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A = (0x00000004) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B = (0x00000005) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE = (0x00000006) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_W = (14, 12) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_X = (0x00000000) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y = (0x00000001) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z = (0x00000002) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_W = (0x00000003) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_A = (0x00000004) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_B = (0x00000005) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE = (0x00000006) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE = (17, 16) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE = (0x00000000) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO = (0x00000001) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE = (0x00000002) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR = (0x00000003) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS = (21, 20) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE = (0x00000000) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO = (0x00000001) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE = (0x00000002) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR = (0x00000003) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS = (25, 24) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE = (0x00000000) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO = (0x00000001) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE = (0x00000002) # type: ignore
|
|
NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR = (0x00000003) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE = (0x0000070C) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_WIDTH = (3, 0) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT = (7, 4) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH = (11, 8) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT = (15, 12) # type: ignore
|
|
NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) # type: ignore
|
|
NVC9B5_SET_DST_WIDTH = (0x00000710) # type: ignore
|
|
NVC9B5_SET_DST_WIDTH_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_DST_HEIGHT = (0x00000714) # type: ignore
|
|
NVC9B5_SET_DST_HEIGHT_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_DST_DEPTH = (0x00000718) # type: ignore
|
|
NVC9B5_SET_DST_DEPTH_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_DST_LAYER = (0x0000071C) # type: ignore
|
|
NVC9B5_SET_DST_LAYER_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_DST_ORIGIN = (0x00000720) # type: ignore
|
|
NVC9B5_SET_DST_ORIGIN_X = (15, 0) # type: ignore
|
|
NVC9B5_SET_DST_ORIGIN_Y = (31, 16) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE = (0x00000728) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_WIDTH = (3, 0) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT = (7, 4) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH = (11, 8) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT = (15, 12) # type: ignore
|
|
NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) # type: ignore
|
|
NVC9B5_SET_SRC_WIDTH = (0x0000072C) # type: ignore
|
|
NVC9B5_SET_SRC_WIDTH_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_SRC_HEIGHT = (0x00000730) # type: ignore
|
|
NVC9B5_SET_SRC_HEIGHT_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_SRC_DEPTH = (0x00000734) # type: ignore
|
|
NVC9B5_SET_SRC_DEPTH_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_SRC_LAYER = (0x00000738) # type: ignore
|
|
NVC9B5_SET_SRC_LAYER_V = (31, 0) # type: ignore
|
|
NVC9B5_SET_SRC_ORIGIN = (0x0000073C) # type: ignore
|
|
NVC9B5_SET_SRC_ORIGIN_X = (15, 0) # type: ignore
|
|
NVC9B5_SET_SRC_ORIGIN_Y = (31, 16) # type: ignore
|
|
NVC9B5_SRC_ORIGIN_X = (0x00000744) # type: ignore
|
|
NVC9B5_SRC_ORIGIN_X_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_SRC_ORIGIN_Y = (0x00000748) # type: ignore
|
|
NVC9B5_SRC_ORIGIN_Y_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_DST_ORIGIN_X = (0x0000074C) # type: ignore
|
|
NVC9B5_DST_ORIGIN_X_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_DST_ORIGIN_Y = (0x00000750) # type: ignore
|
|
NVC9B5_DST_ORIGIN_Y_VALUE = (31, 0) # type: ignore
|
|
NVC9B5_PM_TRIGGER_END = (0x00001114) # type: ignore
|
|
NVC9B5_PM_TRIGGER_END_V = (31, 0) # type: ignore
|
|
UVM_IOCTL_BASE = lambda i: i # type: ignore
|
|
UVM_RESERVE_VA = UVM_IOCTL_BASE(1) # type: ignore
|
|
UVM_RELEASE_VA = UVM_IOCTL_BASE(2) # type: ignore
|
|
UVM_REGION_COMMIT = UVM_IOCTL_BASE(3) # type: ignore
|
|
UVM_REGION_DECOMMIT = UVM_IOCTL_BASE(4) # type: ignore
|
|
UVM_REGION_SET_STREAM = UVM_IOCTL_BASE(5) # type: ignore
|
|
UVM_SET_STREAM_RUNNING = UVM_IOCTL_BASE(6) # type: ignore
|
|
UVM_MAX_STREAMS_PER_IOCTL_CALL = 32 # type: ignore
|
|
UVM_SET_STREAM_STOPPED = UVM_IOCTL_BASE(7) # type: ignore
|
|
UVM_RUN_TEST = UVM_IOCTL_BASE(9) # type: ignore
|
|
UVM_EVENTS_OFFSET_BASE = (1 << 63) # type: ignore
|
|
UVM_COUNTERS_OFFSET_BASE = (1 << 62) # type: ignore
|
|
UVM_ADD_SESSION = UVM_IOCTL_BASE(10) # type: ignore
|
|
UVM_REMOVE_SESSION = UVM_IOCTL_BASE(11) # type: ignore
|
|
UVM_MAX_COUNTERS_PER_IOCTL_CALL = 32 # type: ignore
|
|
UVM_ENABLE_COUNTERS = UVM_IOCTL_BASE(12) # type: ignore
|
|
UVM_MAP_COUNTER = UVM_IOCTL_BASE(13) # type: ignore
|
|
UVM_CREATE_EVENT_QUEUE = UVM_IOCTL_BASE(14) # type: ignore
|
|
UVM_REMOVE_EVENT_QUEUE = UVM_IOCTL_BASE(15) # type: ignore
|
|
UVM_MAP_EVENT_QUEUE = UVM_IOCTL_BASE(16) # type: ignore
|
|
UVM_EVENT_CTRL = UVM_IOCTL_BASE(17) # type: ignore
|
|
UVM_REGISTER_MPS_SERVER = UVM_IOCTL_BASE(18) # type: ignore
|
|
UVM_REGISTER_MPS_CLIENT = UVM_IOCTL_BASE(19) # type: ignore
|
|
UVM_GET_GPU_UUID_TABLE = UVM_IOCTL_BASE(20) # type: ignore
|
|
UVM_CREATE_RANGE_GROUP = UVM_IOCTL_BASE(23) # type: ignore
|
|
UVM_DESTROY_RANGE_GROUP = UVM_IOCTL_BASE(24) # type: ignore
|
|
UVM_REGISTER_GPU_VASPACE = UVM_IOCTL_BASE(25) # type: ignore
|
|
UVM_UNREGISTER_GPU_VASPACE = UVM_IOCTL_BASE(26) # type: ignore
|
|
UVM_REGISTER_CHANNEL = UVM_IOCTL_BASE(27) # type: ignore
|
|
UVM_UNREGISTER_CHANNEL = UVM_IOCTL_BASE(28) # type: ignore
|
|
UVM_ENABLE_PEER_ACCESS = UVM_IOCTL_BASE(29) # type: ignore
|
|
UVM_DISABLE_PEER_ACCESS = UVM_IOCTL_BASE(30) # type: ignore
|
|
UVM_SET_RANGE_GROUP = UVM_IOCTL_BASE(31) # type: ignore
|
|
UVM_MAP_EXTERNAL_ALLOCATION = UVM_IOCTL_BASE(33) # type: ignore
|
|
UVM_FREE = UVM_IOCTL_BASE(34) # type: ignore
|
|
UVM_MEM_MAP = UVM_IOCTL_BASE(35) # type: ignore
|
|
UVM_DEBUG_ACCESS_MEMORY = UVM_IOCTL_BASE(36) # type: ignore
|
|
UVM_REGISTER_GPU = UVM_IOCTL_BASE(37) # type: ignore
|
|
UVM_UNREGISTER_GPU = UVM_IOCTL_BASE(38) # type: ignore
|
|
UVM_PAGEABLE_MEM_ACCESS = UVM_IOCTL_BASE(39) # type: ignore
|
|
UVM_MAX_RANGE_GROUPS_PER_IOCTL_CALL = 32 # type: ignore
|
|
UVM_PREVENT_MIGRATION_RANGE_GROUPS = UVM_IOCTL_BASE(40) # type: ignore
|
|
UVM_ALLOW_MIGRATION_RANGE_GROUPS = UVM_IOCTL_BASE(41) # type: ignore
|
|
UVM_SET_PREFERRED_LOCATION = UVM_IOCTL_BASE(42) # type: ignore
|
|
UVM_UNSET_PREFERRED_LOCATION = UVM_IOCTL_BASE(43) # type: ignore
|
|
UVM_ENABLE_READ_DUPLICATION = UVM_IOCTL_BASE(44) # type: ignore
|
|
UVM_DISABLE_READ_DUPLICATION = UVM_IOCTL_BASE(45) # type: ignore
|
|
UVM_SET_ACCESSED_BY = UVM_IOCTL_BASE(46) # type: ignore
|
|
UVM_UNSET_ACCESSED_BY = UVM_IOCTL_BASE(47) # type: ignore
|
|
UVM_MIGRATE_FLAG_ASYNC = 0x00000001 # type: ignore
|
|
UVM_MIGRATE_FLAG_SKIP_CPU_MAP = 0x00000002 # type: ignore
|
|
UVM_MIGRATE_FLAG_NO_GPU_VA_SPACE = 0x00000004 # type: ignore
|
|
UVM_MIGRATE_FLAGS_TEST_ALL = (UVM_MIGRATE_FLAG_SKIP_CPU_MAP | UVM_MIGRATE_FLAG_NO_GPU_VA_SPACE) # type: ignore
|
|
UVM_MIGRATE_FLAGS_ALL = (UVM_MIGRATE_FLAG_ASYNC | UVM_MIGRATE_FLAGS_TEST_ALL) # type: ignore
|
|
UVM_MIGRATE = UVM_IOCTL_BASE(51) # type: ignore
|
|
UVM_MIGRATE_RANGE_GROUP = UVM_IOCTL_BASE(53) # type: ignore
|
|
UVM_ENABLE_SYSTEM_WIDE_ATOMICS = UVM_IOCTL_BASE(54) # type: ignore
|
|
UVM_DISABLE_SYSTEM_WIDE_ATOMICS = UVM_IOCTL_BASE(55) # type: ignore
|
|
UVM_TOOLS_INIT_EVENT_TRACKER = UVM_IOCTL_BASE(56) # type: ignore
|
|
UVM_TOOLS_SET_NOTIFICATION_THRESHOLD = UVM_IOCTL_BASE(57) # type: ignore
|
|
UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS = UVM_IOCTL_BASE(58) # type: ignore
|
|
UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS = UVM_IOCTL_BASE(59) # type: ignore
|
|
UVM_TOOLS_ENABLE_COUNTERS = UVM_IOCTL_BASE(60) # type: ignore
|
|
UVM_TOOLS_DISABLE_COUNTERS = UVM_IOCTL_BASE(61) # type: ignore
|
|
UVM_TOOLS_READ_PROCESS_MEMORY = UVM_IOCTL_BASE(62) # type: ignore
|
|
UVM_TOOLS_WRITE_PROCESS_MEMORY = UVM_IOCTL_BASE(63) # type: ignore
|
|
UVM_TOOLS_GET_PROCESSOR_UUID_TABLE = UVM_IOCTL_BASE(64) # type: ignore
|
|
UVM_MAP_DYNAMIC_PARALLELISM_REGION = UVM_IOCTL_BASE(65) # type: ignore
|
|
UVM_UNMAP_EXTERNAL = UVM_IOCTL_BASE(66) # type: ignore
|
|
UVM_TOOLS_FLUSH_EVENTS = UVM_IOCTL_BASE(67) # type: ignore
|
|
UVM_ALLOC_SEMAPHORE_POOL = UVM_IOCTL_BASE(68) # type: ignore
|
|
UVM_CLEAN_UP_ZOMBIE_RESOURCES = UVM_IOCTL_BASE(69) # type: ignore
|
|
UVM_PAGEABLE_MEM_ACCESS_ON_GPU = UVM_IOCTL_BASE(70) # type: ignore
|
|
UVM_POPULATE_PAGEABLE = UVM_IOCTL_BASE(71) # type: ignore
|
|
UVM_POPULATE_PAGEABLE_FLAG_ALLOW_MANAGED = 0x00000001 # type: ignore
|
|
UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK = 0x00000002 # type: ignore
|
|
UVM_POPULATE_PAGEABLE_FLAGS_TEST_ALL = (UVM_POPULATE_PAGEABLE_FLAG_ALLOW_MANAGED | UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK) # type: ignore
|
|
UVM_POPULATE_PAGEABLE_FLAGS_ALL = UVM_POPULATE_PAGEABLE_FLAGS_TEST_ALL # type: ignore
|
|
UVM_VALIDATE_VA_RANGE = UVM_IOCTL_BASE(72) # type: ignore
|
|
UVM_CREATE_EXTERNAL_RANGE = UVM_IOCTL_BASE(73) # type: ignore
|
|
UVM_MAP_EXTERNAL_SPARSE = UVM_IOCTL_BASE(74) # type: ignore
|
|
UVM_MM_INITIALIZE = UVM_IOCTL_BASE(75) # type: ignore
|
|
UVM_TOOLS_INIT_EVENT_TRACKER_V2 = UVM_IOCTL_BASE(76) # type: ignore
|
|
UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2 = UVM_IOCTL_BASE(77) # type: ignore
|
|
UVM_ALLOC_DEVICE_P2P = UVM_IOCTL_BASE(78) # type: ignore
|
|
UVM_CLEAR_ALL_ACCESS_COUNTERS = UVM_IOCTL_BASE(79) # type: ignore
|
|
UVM_IS_8_SUPPORTED = UVM_IOCTL_BASE(2047) # type: ignore
|
|
UVM_INITIALIZE = 0x30000001 # type: ignore
|
|
UVM_DEINITIALIZE = 0x30000002 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_GRAPHICS = 64 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_DISPLAY = 1 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_GSP = 2 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_IFB = 9 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_FLA = 4 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1 = 128 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2 = 192 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_SEC = 14 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_PERF = 8 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_NVDEC = 25 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_NVDEC0 = 25 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_NVDEC1 = 26 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_NVDEC2 = 27 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_NVDEC3 = 28 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_NVDEC4 = 29 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_NVJPG0 = 30 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_GRCOPY = 15 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_CE0 = 15 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_CE1 = 16 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_CE2 = 17 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_CE3 = 18 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_CE4 = 19 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_CE5 = 20 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_CE6 = 21 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_CE7 = 22 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_CE8 = 23 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_CE9 = 24 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_PWR_PMU = 6 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_PTP = 3 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_NVENC0 = 11 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_NVENC1 = 12 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_NVENC2 = 13 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_OFA0 = 10 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_PHYSICAL = 31 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST0 = 32 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST1 = 33 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST2 = 34 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST3 = 35 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST4 = 36 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST5 = 37 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST6 = 38 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST7 = 39 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST8 = 40 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST9 = 41 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST10 = 42 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST11 = 43 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST12 = 44 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST13 = 45 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST14 = 46 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST15 = 47 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST16 = 48 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST17 = 49 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST18 = 50 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST19 = 51 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST20 = 52 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST21 = 53 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST22 = 54 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST23 = 55 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST24 = 56 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST25 = 57 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST26 = 58 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST27 = 59 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST28 = 60 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST29 = 61 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST30 = 62 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_HOST31 = 63 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN0 = 128 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN1 = 129 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN2 = 130 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN3 = 131 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN4 = 132 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN5 = 133 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN6 = 134 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN7 = 135 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN8 = 136 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN9 = 137 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN10 = 138 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN11 = 139 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN12 = 140 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN13 = 141 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN14 = 142 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN15 = 143 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN16 = 144 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN17 = 145 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN18 = 146 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN19 = 147 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN20 = 148 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN21 = 149 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN22 = 150 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN23 = 151 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN24 = 152 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN25 = 153 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN26 = 154 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN27 = 155 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN28 = 156 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN29 = 157 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN30 = 158 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN31 = 159 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN32 = 160 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN33 = 161 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN34 = 162 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN35 = 163 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN36 = 164 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN37 = 165 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN38 = 166 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN39 = 167 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN40 = 168 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN41 = 169 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN42 = 170 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN43 = 171 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN44 = 172 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN45 = 173 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN46 = 174 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN47 = 175 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN48 = 176 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN49 = 177 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN50 = 178 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN51 = 179 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN52 = 180 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN53 = 181 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN54 = 182 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN55 = 183 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN56 = 184 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN57 = 185 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN58 = 186 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN59 = 187 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN60 = 188 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN61 = 189 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN62 = 190 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR1_FN63 = 191 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN0 = 192 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN1 = 193 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN2 = 194 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN3 = 195 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN4 = 196 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN5 = 197 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN6 = 198 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN7 = 199 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN8 = 200 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN9 = 201 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN10 = 202 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN11 = 203 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN12 = 204 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN13 = 205 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN14 = 206 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN15 = 207 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN16 = 208 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN17 = 209 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN18 = 210 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN19 = 211 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN20 = 212 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN21 = 213 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN22 = 214 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN23 = 215 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN24 = 216 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN25 = 217 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN26 = 218 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN27 = 219 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN28 = 220 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN29 = 221 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN30 = 222 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN31 = 223 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN32 = 224 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN33 = 225 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN34 = 226 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN35 = 227 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN36 = 228 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN37 = 229 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN38 = 230 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN39 = 231 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN40 = 232 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN41 = 233 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN42 = 234 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN43 = 235 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN44 = 236 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN45 = 237 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN46 = 238 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN47 = 239 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN48 = 240 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN49 = 241 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN50 = 242 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN51 = 243 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN52 = 244 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN53 = 245 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN54 = 246 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN55 = 247 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN56 = 248 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN57 = 249 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN58 = 250 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN59 = 251 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN60 = 252 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN61 = 253 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN62 = 254 # type: ignore
|
|
NV_PFAULT_MMU_ENG_ID_BAR2_FN63 = 255 # type: ignore
|
|
NV_PFAULT_FAULT_TYPE = (4, 0) # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_PDE = 0x00000000 # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_PDE_SIZE = 0x00000001 # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_PTE = 0x00000002 # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION = 0x00000003 # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK = 0x00000004 # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION = 0x00000005 # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_RO_VIOLATION = 0x00000006 # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_WO_VIOLATION = 0x00000007 # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION = 0x00000008 # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_WORK_CREATION = 0x00000009 # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE = 0x0000000a # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE = 0x0000000b # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND = 0x0000000c # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_REGION_VIOLATION = 0x0000000d # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_POISONED = 0x0000000e # type: ignore
|
|
NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION = 0x0000000f # type: ignore
|
|
NV_PFAULT_CLIENT = (14, 8) # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_0 = 0x00000000 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_1 = 0x00000001 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_2 = 0x00000002 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_3 = 0x00000003 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_4 = 0x00000004 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_5 = 0x00000005 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_6 = 0x00000006 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_7 = 0x00000007 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_0 = 0x00000008 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_1 = 0x00000009 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_2 = 0x0000000A # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_3 = 0x0000000B # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_4 = 0x0000000C # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_5 = 0x0000000D # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_6 = 0x0000000E # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_7 = 0x0000000F # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_RAST = 0x00000010 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_GCC = 0x00000011 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_GPCCS = 0x00000012 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PROP_0 = 0x00000013 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PROP_1 = 0x00000014 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PROP_2 = 0x00000015 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PROP_3 = 0x00000016 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_8 = 0x00000021 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_9 = 0x00000022 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_10 = 0x00000023 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_11 = 0x00000024 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_12 = 0x00000025 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_13 = 0x00000026 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_14 = 0x00000027 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_15 = 0x00000028 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_0 = 0x00000029 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_1 = 0x0000002A # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_2 = 0x0000002B # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_3 = 0x0000002C # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_4 = 0x0000002D # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_5 = 0x0000002E # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_6 = 0x0000002F # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_7 = 0x00000030 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_8 = 0x00000031 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_9 = 0x00000032 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_8 = 0x00000033 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_9 = 0x00000034 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_16 = 0x00000035 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_17 = 0x00000036 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_18 = 0x00000037 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_19 = 0x00000038 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_10 = 0x00000039 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_11 = 0x0000003A # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_10 = 0x0000003B # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_11 = 0x0000003C # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_20 = 0x0000003D # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_21 = 0x0000003E # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_22 = 0x0000003F # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_23 = 0x00000040 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_12 = 0x00000041 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_13 = 0x00000042 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_12 = 0x00000043 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_13 = 0x00000044 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_24 = 0x00000045 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_25 = 0x00000046 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_26 = 0x00000047 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_27 = 0x00000048 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_14 = 0x00000049 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_15 = 0x0000004A # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_14 = 0x0000004B # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_15 = 0x0000004C # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_28 = 0x0000004D # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_29 = 0x0000004E # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_30 = 0x0000004F # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_31 = 0x00000050 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_16 = 0x00000051 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_17 = 0x00000052 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_16 = 0x00000053 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_17 = 0x00000054 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_32 = 0x00000055 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_33 = 0x00000056 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_34 = 0x00000057 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_35 = 0x00000058 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_18 = 0x00000059 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_PE_19 = 0x0000005A # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_18 = 0x0000005B # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_TPCCS_19 = 0x0000005C # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_36 = 0x0000005D # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_37 = 0x0000005E # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_38 = 0x0000005F # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_T1_39 = 0x00000060 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_ROP_0 = 0x00000070 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_ROP_1 = 0x00000071 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_ROP_2 = 0x00000072 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_ROP_3 = 0x00000073 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_GPM = 0x00000017 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_0 = 0x00000018 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_1 = 0x00000019 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_2 = 0x0000001A # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_3 = 0x0000001B # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_4 = 0x0000001C # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_5 = 0x0000001D # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_6 = 0x0000001E # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_7 = 0x0000001F # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_RGG_UTLB = 0x00000020 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_8 = 0x00000031 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_9 = 0x00000032 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_10 = 0x00000033 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_11 = 0x00000034 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_12 = 0x00000035 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_13 = 0x00000036 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_14 = 0x00000037 # type: ignore
|
|
NV_PFAULT_CLIENT_GPC_LTP_UTLB_15 = 0x00000038 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_VIP = 0x00000000 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_CE0 = 0x00000001 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_CE1 = 0x00000002 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_DNISO = 0x00000003 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_DISPNISO = 0x00000003 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FE0 = 0x00000004 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FE = 0x00000004 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FECS0 = 0x00000005 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FECS = 0x00000005 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HOST = 0x00000006 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HOST_CPU = 0x00000007 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HOST_CPU_NB = 0x00000008 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_ISO = 0x00000009 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_MMU = 0x0000000A # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_NVDEC0 = 0x0000000B # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_NVDEC = 0x0000000B # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_NVENC1 = 0x0000000D # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_NISO = 0x0000000E # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_ACTRS = 0x0000000E # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_P2P = 0x0000000F # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PD = 0x00000010 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PERF0 = 0x00000011 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PERF = 0x00000011 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PMU = 0x00000012 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_RASTERTWOD = 0x00000013 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SCC = 0x00000014 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SCC_NB = 0x00000015 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SEC = 0x00000016 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SSYNC = 0x00000017 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_GRCOPY = 0x00000018 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_CE2 = 0x00000018 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_XV = 0x00000019 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_MMU_NB = 0x0000001A # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_NVENC0 = 0x0000001B # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_NVENC = 0x0000001B # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_DFALCON = 0x0000001C # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SKED0 = 0x0000001D # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SKED = 0x0000001D # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_AFALCON = 0x0000001E # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_DONT_CARE = 0x0000001F # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE0 = 0x00000020 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE1 = 0x00000021 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE2 = 0x00000022 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE3 = 0x00000023 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE4 = 0x00000024 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE5 = 0x00000025 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE6 = 0x00000026 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE7 = 0x00000027 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE8 = 0x00000028 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE9 = 0x00000029 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSHUB = 0x0000002A # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X0 = 0x0000002B # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X1 = 0x0000002C # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X2 = 0x0000002D # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X3 = 0x0000002E # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X4 = 0x0000002F # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X5 = 0x00000030 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X6 = 0x00000031 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X7 = 0x00000032 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_NVENC2 = 0x00000033 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 = 0x00000034 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 = 0x00000035 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_DWBIF = 0x00000036 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FBFALCON = 0x00000037 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_CE_SHIM = 0x00000038 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_GSP = 0x00000039 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_NVDEC1 = 0x0000003A # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_NVDEC2 = 0x0000003B # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_NVJPG0 = 0x0000003C # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_NVDEC3 = 0x0000003D # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_NVDEC4 = 0x0000003E # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_OFA0 = 0x0000003F # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE10 = 0x00000040 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE11 = 0x00000041 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE12 = 0x00000042 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE13 = 0x00000043 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE14 = 0x00000044 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_HSCE15 = 0x00000045 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X8 = 0x00000046 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X9 = 0x00000047 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X10 = 0x00000048 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X11 = 0x00000049 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X12 = 0x0000004A # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X13 = 0x0000004B # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X14 = 0x0000004C # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_PTP_X15 = 0x0000004D # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FE1 = 0x0000004E # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FE2 = 0x0000004F # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FE3 = 0x00000050 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FE4 = 0x00000051 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FE5 = 0x00000052 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FE6 = 0x00000053 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FE7 = 0x00000054 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FECS1 = 0x00000055 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FECS2 = 0x00000056 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FECS3 = 0x00000057 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FECS4 = 0x00000058 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FECS5 = 0x00000059 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FECS6 = 0x0000005A # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_FECS7 = 0x0000005B # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SKED1 = 0x0000005C # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SKED2 = 0x0000005D # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SKED3 = 0x0000005E # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SKED4 = 0x0000005F # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SKED5 = 0x00000060 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SKED6 = 0x00000061 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_SKED7 = 0x00000062 # type: ignore
|
|
NV_PFAULT_CLIENT_HUB_ESC = 0x00000063 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE = (19, 16) # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_READ = 0x00000000 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_WRITE = 0x00000001 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_ATOMIC = 0x00000002 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_PREFETCH = 0x00000003 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_VIRT_READ = 0x00000000 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_VIRT_WRITE = 0x00000001 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC = 0x00000002 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 0x00000002 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH = 0x00000003 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 0x00000004 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_PHYS_READ = 0x00000008 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_PHYS_WRITE = 0x00000009 # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC = 0x0000000a # type: ignore
|
|
NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH = 0x0000000b # type: ignore
|
|
NV_PFAULT_MMU_CLIENT_TYPE = (20, 20) # type: ignore
|
|
NV_PFAULT_MMU_CLIENT_TYPE_GPC = 0x00000000 # type: ignore
|
|
NV_PFAULT_MMU_CLIENT_TYPE_HUB = 0x00000001 # type: ignore
|
|
NV_PFAULT_GPC_ID = (28, 24) # type: ignore
|
|
NV_PFAULT_PROTECTED_MODE = (29, 29) # type: ignore
|
|
NV_PFAULT_REPLAYABLE_FAULT_EN = (30, 30) # type: ignore
|
|
NV_PFAULT_VALID = (31, 31) # type: ignore
|
|
NV_ESC_RM_ALLOC_MEMORY = 0x27 # type: ignore
|
|
NV_ESC_RM_ALLOC_OBJECT = 0x28 # type: ignore
|
|
NV_ESC_RM_FREE = 0x29 # type: ignore
|
|
NV_ESC_RM_CONTROL = 0x2A # type: ignore
|
|
NV_ESC_RM_ALLOC = 0x2B # type: ignore
|
|
NV_ESC_RM_CONFIG_GET = 0x32 # type: ignore
|
|
NV_ESC_RM_CONFIG_SET = 0x33 # type: ignore
|
|
NV_ESC_RM_DUP_OBJECT = 0x34 # type: ignore
|
|
NV_ESC_RM_SHARE = 0x35 # type: ignore
|
|
NV_ESC_RM_CONFIG_GET_EX = 0x37 # type: ignore
|
|
NV_ESC_RM_CONFIG_SET_EX = 0x38 # type: ignore
|
|
NV_ESC_RM_I2C_ACCESS = 0x39 # type: ignore
|
|
NV_ESC_RM_IDLE_CHANNELS = 0x41 # type: ignore
|
|
NV_ESC_RM_VID_HEAP_CONTROL = 0x4A # type: ignore
|
|
NV_ESC_RM_ACCESS_REGISTRY = 0x4D # type: ignore
|
|
NV_ESC_RM_MAP_MEMORY = 0x4E # type: ignore
|
|
NV_ESC_RM_UNMAP_MEMORY = 0x4F # type: ignore
|
|
NV_ESC_RM_GET_EVENT_DATA = 0x52 # type: ignore
|
|
NV_ESC_RM_ALLOC_CONTEXT_DMA2 = 0x54 # type: ignore
|
|
NV_ESC_RM_ADD_VBLANK_CALLBACK = 0x56 # type: ignore
|
|
NV_ESC_RM_MAP_MEMORY_DMA = 0x57 # type: ignore
|
|
NV_ESC_RM_UNMAP_MEMORY_DMA = 0x58 # type: ignore
|
|
NV_ESC_RM_BIND_CONTEXT_DMA = 0x59 # type: ignore
|
|
NV_ESC_RM_EXPORT_OBJECT_TO_FD = 0x5C # type: ignore
|
|
NV_ESC_RM_IMPORT_OBJECT_FROM_FD = 0x5D # type: ignore
|
|
NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO = 0x5E # type: ignore
|
|
NV_ESC_RM_LOCKLESS_DIAGNOSTIC = 0x5F # type: ignore
|
|
NV_RM_API_VERSION_STRING_LENGTH = 64 # type: ignore
|
|
NV_RM_API_VERSION_CMD_STRICT = 0 # type: ignore
|
|
NV_RM_API_VERSION_CMD_RELAXED = '1' # type: ignore
|
|
NV_RM_API_VERSION_CMD_QUERY = '2' # type: ignore
|
|
NV_RM_API_VERSION_REPLY_UNRECOGNIZED = 0 # type: ignore
|
|
NV_RM_API_VERSION_REPLY_RECOGNIZED = 1 # type: ignore
|
|
NV_DMABUF_EXPORT_MAX_HANDLES = 128 # type: ignore
|
|
NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT = 0 # type: ignore
|
|
NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE = 1 # type: ignore
|
|
NV_IOCTL_MAGIC = 'F' # type: ignore
|
|
NV_IOCTL_BASE = 200 # type: ignore
|
|
NV_ESC_CARD_INFO = (NV_IOCTL_BASE + 0) # type: ignore
|
|
NV_ESC_REGISTER_FD = (NV_IOCTL_BASE + 1) # type: ignore
|
|
NV_ESC_ALLOC_OS_EVENT = (NV_IOCTL_BASE + 6) # type: ignore
|
|
NV_ESC_FREE_OS_EVENT = (NV_IOCTL_BASE + 7) # type: ignore
|
|
NV_ESC_STATUS_CODE = (NV_IOCTL_BASE + 9) # type: ignore
|
|
NV_ESC_CHECK_VERSION_STR = (NV_IOCTL_BASE + 10) # type: ignore
|
|
NV_ESC_IOCTL_XFER_CMD = (NV_IOCTL_BASE + 11) # type: ignore
|
|
NV_ESC_ATTACH_GPUS_TO_FD = (NV_IOCTL_BASE + 12) # type: ignore
|
|
NV_ESC_QUERY_DEVICE_INTR = (NV_IOCTL_BASE + 13) # type: ignore
|
|
NV_ESC_SYS_PARAMS = (NV_IOCTL_BASE + 14) # type: ignore
|
|
NV_ESC_EXPORT_TO_DMABUF_FD = (NV_IOCTL_BASE + 17) # type: ignore
|
|
NV_ESC_WAIT_OPEN_COMPLETE = (NV_IOCTL_BASE + 18) # type: ignore
|
|
__aligned = lambda n: __attribute__((aligned(n))) # type: ignore
|
|
NV_ESC_NUMA_INFO = (NV_IOCTL_BASE + 15) # type: ignore
|
|
NV_ESC_SET_NUMA_STATUS = (NV_IOCTL_BASE + 16) # type: ignore
|
|
NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES = 64 # type: ignore
|
|
NV_IOCTL_NUMA_STATUS_DISABLED = 0 # type: ignore
|
|
NV_IOCTL_NUMA_STATUS_OFFLINE = 1 # type: ignore
|
|
NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS = 2 # type: ignore
|
|
NV_IOCTL_NUMA_STATUS_ONLINE = 3 # type: ignore
|
|
NV_IOCTL_NUMA_STATUS_ONLINE_FAILED = 4 # type: ignore
|
|
NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS = 5 # type: ignore
|
|
NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED = 6 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_TYPE = (1, 0) # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL = 0x00000002 # type: ignore
|
|
NVOS04_FLAGS_VPR = (2, 2) # type: ignore
|
|
NVOS04_FLAGS_VPR_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_VPR_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_CC_SECURE = (2, 2) # type: ignore
|
|
NVOS04_FLAGS_CC_SECURE_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_CC_SECURE_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING = (3, 3) # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE = (4, 4) # type: ignore
|
|
NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_PRIVILEGED_CHANNEL = (5, 5) # type: ignore
|
|
NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING = (6, 6) # type: ignore
|
|
NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE = (7, 7) # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE = (10, 8) # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED = (11, 11) # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE = (20, 12) # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED = (21, 21) # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV = (22, 22) # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER = (23, 23) # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO = (24, 24) # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL = (25, 25) # type: ignore
|
|
NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT = (26, 26) # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT = (27, 27) # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_GROUP_CHANNEL_THREAD = (29, 28) # type: ignore
|
|
NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO = 0x00000002 # type: ignore
|
|
NVOS04_FLAGS_MAP_CHANNEL = (30, 30) # type: ignore
|
|
NVOS04_FLAGS_MAP_CHANNEL_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_MAP_CHANNEL_TRUE = 0x00000001 # type: ignore
|
|
NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC = (31, 31) # type: ignore
|
|
NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE = 0x00000000 # type: ignore
|
|
NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE = 0x00000001 # type: ignore
|
|
CC_CHAN_ALLOC_IV_SIZE_DWORD = 3 # type: ignore
|
|
CC_CHAN_ALLOC_NONCE_SIZE_DWORD = 8 # type: ignore
|
|
NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID = (0x906f) # type: ignore
|
|
FILE_DEVICE_NV = 0x00008000 # type: ignore
|
|
NV_IOCTL_FCT_BASE = 0x00000800 # type: ignore
|
|
NVOS_MAX_SUBDEVICES = 8 # type: ignore
|
|
UNIFIED_NV_STATUS = 1 # type: ignore
|
|
NVOS_STATUS = NV_STATUS # type: ignore
|
|
NVOS_STATUS_SUCCESS = NV_OK # type: ignore
|
|
NVOS_STATUS_ERROR_CARD_NOT_PRESENT = NV_ERR_CARD_NOT_PRESENT # type: ignore
|
|
NVOS_STATUS_ERROR_DUAL_LINK_INUSE = NV_ERR_DUAL_LINK_INUSE # type: ignore
|
|
NVOS_STATUS_ERROR_GENERIC = NV_ERR_GENERIC # type: ignore
|
|
NVOS_STATUS_ERROR_GPU_NOT_FULL_POWER = NV_ERR_GPU_NOT_FULL_POWER # type: ignore
|
|
NVOS_STATUS_ERROR_ILLEGAL_ACTION = NV_ERR_ILLEGAL_ACTION # type: ignore
|
|
NVOS_STATUS_ERROR_IN_USE = NV_ERR_STATE_IN_USE # type: ignore
|
|
NVOS_STATUS_ERROR_INSUFFICIENT_RESOURCES = NV_ERR_INSUFFICIENT_RESOURCES # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_ACCESS_TYPE = NV_ERR_INVALID_ACCESS_TYPE # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_ARGUMENT = NV_ERR_INVALID_ARGUMENT # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_BASE = NV_ERR_INVALID_BASE # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_CHANNEL = NV_ERR_INVALID_CHANNEL # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_CLASS = NV_ERR_INVALID_CLASS # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_CLIENT = NV_ERR_INVALID_CLIENT # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_COMMAND = NV_ERR_INVALID_COMMAND # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_DATA = NV_ERR_INVALID_DATA # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_DEVICE = NV_ERR_INVALID_DEVICE # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_DMA_SPECIFIER = NV_ERR_INVALID_DMA_SPECIFIER # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_EVENT = NV_ERR_INVALID_EVENT # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_FLAGS = NV_ERR_INVALID_FLAGS # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_FUNCTION = NV_ERR_INVALID_FUNCTION # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_HEAP = NV_ERR_INVALID_HEAP # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_INDEX = NV_ERR_INVALID_INDEX # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_LIMIT = NV_ERR_INVALID_LIMIT # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_METHOD = NV_ERR_INVALID_METHOD # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_OBJECT_BUFFER = NV_ERR_BUFFER_TOO_SMALL # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR = NV_ERR_INVALID_OBJECT # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE = NV_ERR_INVALID_OBJECT_HANDLE # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_OBJECT_NEW = NV_ERR_INVALID_OBJECT_NEW # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_OBJECT_OLD = NV_ERR_INVALID_OBJECT_OLD # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_OBJECT_PARENT = NV_ERR_INVALID_OBJECT_PARENT # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_OFFSET = NV_ERR_INVALID_OFFSET # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_OWNER = NV_ERR_INVALID_OWNER # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_PARAM_STRUCT = NV_ERR_INVALID_PARAM_STRUCT # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_PARAMETER = NV_ERR_INVALID_PARAMETER # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_POINTER = NV_ERR_INVALID_POINTER # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_REGISTRY_KEY = NV_ERR_INVALID_REGISTRY_KEY # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_STATE = NV_ERR_INVALID_STATE # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_STRING_LENGTH = NV_ERR_INVALID_STRING_LENGTH # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_XLATE = NV_ERR_INVALID_XLATE # type: ignore
|
|
NVOS_STATUS_ERROR_IRQ_NOT_FIRING = NV_ERR_IRQ_NOT_FIRING # type: ignore
|
|
NVOS_STATUS_ERROR_MULTIPLE_MEMORY_TYPES = NV_ERR_MULTIPLE_MEMORY_TYPES # type: ignore
|
|
NVOS_STATUS_ERROR_NOT_SUPPORTED = NV_ERR_NOT_SUPPORTED # type: ignore
|
|
NVOS_STATUS_ERROR_OPERATING_SYSTEM = NV_ERR_OPERATING_SYSTEM # type: ignore
|
|
NVOS_STATUS_ERROR_LIB_RM_VERSION_MISMATCH = NV_ERR_LIB_RM_VERSION_MISMATCH # type: ignore
|
|
NVOS_STATUS_ERROR_PROTECTION_FAULT = NV_ERR_PROTECTION_FAULT # type: ignore
|
|
NVOS_STATUS_ERROR_TIMEOUT = NV_ERR_TIMEOUT # type: ignore
|
|
NVOS_STATUS_ERROR_TOO_MANY_PRIMARIES = NV_ERR_TOO_MANY_PRIMARIES # type: ignore
|
|
NVOS_STATUS_ERROR_IRQ_EDGE_TRIGGERED = NV_ERR_IRQ_EDGE_TRIGGERED # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_OPERATION = NV_ERR_INVALID_OPERATION # type: ignore
|
|
NVOS_STATUS_ERROR_NOT_COMPATIBLE = NV_ERR_NOT_COMPATIBLE # type: ignore
|
|
NVOS_STATUS_ERROR_MORE_PROCESSING_REQUIRED = NV_WARN_MORE_PROCESSING_REQUIRED # type: ignore
|
|
NVOS_STATUS_ERROR_INSUFFICIENT_PERMISSIONS = NV_ERR_INSUFFICIENT_PERMISSIONS # type: ignore
|
|
NVOS_STATUS_ERROR_TIMEOUT_RETRY = NV_ERR_TIMEOUT_RETRY # type: ignore
|
|
NVOS_STATUS_ERROR_NOT_READY = NV_ERR_NOT_READY # type: ignore
|
|
NVOS_STATUS_ERROR_GPU_IS_LOST = NV_ERR_GPU_IS_LOST # type: ignore
|
|
NVOS_STATUS_ERROR_IN_FULLCHIP_RESET = NV_ERR_GPU_IN_FULLCHIP_RESET # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_LOCK_STATE = NV_ERR_INVALID_LOCK_STATE # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_ADDRESS = NV_ERR_INVALID_ADDRESS # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_IRQ_LEVEL = NV_ERR_INVALID_IRQ_LEVEL # type: ignore
|
|
NVOS_STATUS_ERROR_MEMORY_TRAINING_FAILED = NV_ERR_MEMORY_TRAINING_FAILED # type: ignore
|
|
NVOS_STATUS_ERROR_BUSY_RETRY = NV_ERR_BUSY_RETRY # type: ignore
|
|
NVOS_STATUS_ERROR_INSUFFICIENT_POWER = NV_ERR_INSUFFICIENT_POWER # type: ignore
|
|
NVOS_STATUS_ERROR_OBJECT_NOT_FOUND = NV_ERR_OBJECT_NOT_FOUND # type: ignore
|
|
NVOS_STATUS_ERROR_RESOURCE_LOST = NV_ERR_RESOURCE_LOST # type: ignore
|
|
NVOS_STATUS_ERROR_BUFFER_TOO_SMALL = NV_ERR_BUFFER_TOO_SMALL # type: ignore
|
|
NVOS_STATUS_ERROR_RESET_REQUIRED = NV_ERR_RESET_REQUIRED # type: ignore
|
|
NVOS_STATUS_ERROR_INVALID_REQUEST = NV_ERR_INVALID_REQUEST # type: ignore
|
|
NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION = NV_ERR_PRIV_SEC_VIOLATION # type: ignore
|
|
NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE = NV_ERR_GPU_IN_DEBUG_MODE # type: ignore
|
|
NVOS_STATUS_ERROR_ALREADY_SIGNALLED = NV_ERR_ALREADY_SIGNALLED # type: ignore
|
|
NV01_FREE = (0x00000000) # type: ignore
|
|
NV01_ROOT = (0x0) # type: ignore
|
|
NV01_ROOT_NON_PRIV = (0x00000001) # type: ignore
|
|
NV01_ROOT_CLIENT = (0x00000041) # type: ignore
|
|
NV01_ALLOC_MEMORY = (0x00000002) # type: ignore
|
|
NVOS02_FLAGS_PHYSICALITY = (7, 4) # type: ignore
|
|
NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS = (0x00000000) # type: ignore
|
|
NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_LOCATION = (11, 8) # type: ignore
|
|
NVOS02_FLAGS_LOCATION_PCI = (0x00000000) # type: ignore
|
|
NVOS02_FLAGS_LOCATION_VIDMEM = (0x00000002) # type: ignore
|
|
NVOS02_FLAGS_COHERENCY = (15, 12) # type: ignore
|
|
NVOS02_FLAGS_COHERENCY_UNCACHED = (0x00000000) # type: ignore
|
|
NVOS02_FLAGS_COHERENCY_CACHED = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_COHERENCY_WRITE_COMBINE = (0x00000002) # type: ignore
|
|
NVOS02_FLAGS_COHERENCY_WRITE_THROUGH = (0x00000003) # type: ignore
|
|
NVOS02_FLAGS_COHERENCY_WRITE_PROTECT = (0x00000004) # type: ignore
|
|
NVOS02_FLAGS_COHERENCY_WRITE_BACK = (0x00000005) # type: ignore
|
|
NVOS02_FLAGS_ALLOC = (17, 16) # type: ignore
|
|
NVOS02_FLAGS_ALLOC_NONE = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_GPU_CACHEABLE = (18, 18) # type: ignore
|
|
NVOS02_FLAGS_GPU_CACHEABLE_NO = (0x00000000) # type: ignore
|
|
NVOS02_FLAGS_GPU_CACHEABLE_YES = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_KERNEL_MAPPING = (19, 19) # type: ignore
|
|
NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP = (0x00000000) # type: ignore
|
|
NVOS02_FLAGS_KERNEL_MAPPING_MAP = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_ALLOC_NISO_DISPLAY = (20, 20) # type: ignore
|
|
NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO = (0x00000000) # type: ignore
|
|
NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_ALLOC_USER_READ_ONLY = (21, 21) # type: ignore
|
|
NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO = (0x00000000) # type: ignore
|
|
NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY = (22, 22) # type: ignore
|
|
NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO = (0x00000000) # type: ignore
|
|
NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_PEER_MAP_OVERRIDE = (23, 23) # type: ignore
|
|
NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT = (0x00000000) # type: ignore
|
|
NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT = (24, 24) # type: ignore
|
|
NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_MEMORY_PROTECTION = (26, 25) # type: ignore
|
|
NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT = (0x00000000) # type: ignore
|
|
NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED = (0x00000002) # type: ignore
|
|
NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM = (27, 27) # type: ignore
|
|
NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_FALSE = (0x00000000) # type: ignore
|
|
NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_TRUE = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_MAPPING = (31, 30) # type: ignore
|
|
NVOS02_FLAGS_MAPPING_DEFAULT = (0x00000000) # type: ignore
|
|
NVOS02_FLAGS_MAPPING_NO_MAP = (0x00000001) # type: ignore
|
|
NVOS02_FLAGS_MAPPING_NEVER_MAP = (0x00000002) # type: ignore
|
|
NVOS03_FLAGS_ACCESS = (1, 0) # type: ignore
|
|
NVOS03_FLAGS_ACCESS_READ_WRITE = (0x00000000) # type: ignore
|
|
NVOS03_FLAGS_ACCESS_READ_ONLY = (0x00000001) # type: ignore
|
|
NVOS03_FLAGS_ACCESS_WRITE_ONLY = (0x00000002) # type: ignore
|
|
NVOS03_FLAGS_PREALLOCATE = (2, 2) # type: ignore
|
|
NVOS03_FLAGS_PREALLOCATE_DISABLE = (0x00000000) # type: ignore
|
|
NVOS03_FLAGS_PREALLOCATE_ENABLE = (0x00000001) # type: ignore
|
|
NVOS03_FLAGS_GPU_MAPPABLE = (15, 15) # type: ignore
|
|
NVOS03_FLAGS_GPU_MAPPABLE_DISABLE = (0x00000000) # type: ignore
|
|
NVOS03_FLAGS_GPU_MAPPABLE_ENABLE = (0x00000001) # type: ignore
|
|
NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE = (16, 16) # type: ignore
|
|
NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_FALSE = (0x00000000) # type: ignore
|
|
NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_TRUE = (0x00000001) # type: ignore
|
|
NVOS03_FLAGS_PTE_KIND = (17, 16) # type: ignore
|
|
NVOS03_FLAGS_PTE_KIND_NONE = (0x00000000) # type: ignore
|
|
NVOS03_FLAGS_PTE_KIND_BL = (0x00000001) # type: ignore
|
|
NVOS03_FLAGS_PTE_KIND_PITCH = (0x00000002) # type: ignore
|
|
NVOS03_FLAGS_TYPE = (23, 20) # type: ignore
|
|
NVOS03_FLAGS_TYPE_NOTIFIER = (0x00000001) # type: ignore
|
|
NVOS03_FLAGS_MAPPING = (20, 20) # type: ignore
|
|
NVOS03_FLAGS_MAPPING_NONE = (0x00000000) # type: ignore
|
|
NVOS03_FLAGS_MAPPING_KERNEL = (0x00000001) # type: ignore
|
|
NVOS03_FLAGS_CACHE_SNOOP = (28, 28) # type: ignore
|
|
NVOS03_FLAGS_CACHE_SNOOP_ENABLE = (0x00000000) # type: ignore
|
|
NVOS03_FLAGS_CACHE_SNOOP_DISABLE = (0x00000001) # type: ignore
|
|
NVOS03_FLAGS_HASH_TABLE = (29, 29) # type: ignore
|
|
NVOS03_FLAGS_HASH_TABLE_ENABLE = (0x00000000) # type: ignore
|
|
NVOS03_FLAGS_HASH_TABLE_DISABLE = (0x00000001) # type: ignore
|
|
NV01_ALLOC_OBJECT = (0x00000005) # type: ignore
|
|
NV01_EVENT_KERNEL_CALLBACK = (0x00000078) # type: ignore
|
|
NV01_EVENT_OS_EVENT = (0x00000079) # type: ignore
|
|
NV01_EVENT_WIN32_EVENT = NV01_EVENT_OS_EVENT # type: ignore
|
|
NV01_EVENT_KERNEL_CALLBACK_EX = (0x0000007E) # type: ignore
|
|
NV01_EVENT_BROADCAST = (0x80000000) # type: ignore
|
|
NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION = (0x40000000) # type: ignore
|
|
NV01_EVENT_SUBDEVICE_SPECIFIC = (0x20000000) # type: ignore
|
|
NV01_EVENT_WITHOUT_EVENT_DATA = (0x10000000) # type: ignore
|
|
NV01_EVENT_NONSTALL_INTR = (0x08000000) # type: ignore
|
|
NV01_EVENT_CLIENT_RM = (0x04000000) # type: ignore
|
|
NV04_I2C_ACCESS = (0x00000013) # type: ignore
|
|
NVOS_I2C_ACCESS_MAX_BUFFER_SIZE = 2048 # type: ignore
|
|
NVOS20_COMMAND_unused0001 = 0x0001 # type: ignore
|
|
NVOS20_COMMAND_unused0002 = 0x0002 # type: ignore
|
|
NVOS20_COMMAND_STRING_PRINT = 0x0003 # type: ignore
|
|
NV04_ALLOC = (0x00000015) # type: ignore
|
|
NVOS64_FLAGS_NONE = (0x00000000) # type: ignore
|
|
NVOS64_FLAGS_FINN_SERIALIZED = (0x00000001) # type: ignore
|
|
NVOS65_PARAMETERS_VERSION_MAGIC = 0x77FEF81E # type: ignore
|
|
NV04_IDLE_CHANNELS = (0x0000001E) # type: ignore
|
|
NVOS30_FLAGS_BEHAVIOR = (3, 0) # type: ignore
|
|
NVOS30_FLAGS_BEHAVIOR_SPIN = (0x00000000) # type: ignore
|
|
NVOS30_FLAGS_BEHAVIOR_SLEEP = (0x00000001) # type: ignore
|
|
NVOS30_FLAGS_BEHAVIOR_QUERY = (0x00000002) # type: ignore
|
|
NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK = (0x00000003) # type: ignore
|
|
NVOS30_FLAGS_CHANNEL = (7, 4) # type: ignore
|
|
NVOS30_FLAGS_CHANNEL_LIST = (0x00000000) # type: ignore
|
|
NVOS30_FLAGS_CHANNEL_SINGLE = (0x00000001) # type: ignore
|
|
NVOS30_FLAGS_IDLE = (30, 8) # type: ignore
|
|
NVOS30_FLAGS_IDLE_PUSH_BUFFER = (0x00000001) # type: ignore
|
|
NVOS30_FLAGS_IDLE_CACHE1 = (0x00000002) # type: ignore
|
|
NVOS30_FLAGS_IDLE_GRAPHICS = (0x00000004) # type: ignore
|
|
NVOS30_FLAGS_IDLE_MPEG = (0x00000008) # type: ignore
|
|
NVOS30_FLAGS_IDLE_MOTION_ESTIMATION = (0x00000010) # type: ignore
|
|
NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR = (0x00000020) # type: ignore
|
|
NVOS30_FLAGS_IDLE_MSPDEC = (0x00000020) # type: ignore
|
|
NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR = (0x00000040) # type: ignore
|
|
NVOS30_FLAGS_IDLE_MSVLD = (0x00000040) # type: ignore
|
|
NVOS30_FLAGS_IDLE_NVDEC0 = NVOS30_FLAGS_IDLE_MSVLD # type: ignore
|
|
NVOS30_FLAGS_IDLE_CIPHER_DMA = (0x00000080) # type: ignore
|
|
NVOS30_FLAGS_IDLE_SEC = (0x00000080) # type: ignore
|
|
NVOS30_FLAGS_IDLE_CALLBACKS = (0x00000100) # type: ignore
|
|
NVOS30_FLAGS_IDLE_MSPPP = (0x00000200) # type: ignore
|
|
NVOS30_FLAGS_IDLE_CE0 = (0x00000400) # type: ignore
|
|
NVOS30_FLAGS_IDLE_CE1 = (0x00000800) # type: ignore
|
|
NVOS30_FLAGS_IDLE_CE2 = (0x00001000) # type: ignore
|
|
NVOS30_FLAGS_IDLE_CE3 = (0x00002000) # type: ignore
|
|
NVOS30_FLAGS_IDLE_CE4 = (0x00004000) # type: ignore
|
|
NVOS30_FLAGS_IDLE_CE5 = (0x00008000) # type: ignore
|
|
NVOS30_FLAGS_IDLE_VIC = (0x00010000) # type: ignore
|
|
NVOS30_FLAGS_IDLE_MSENC = (0x00020000) # type: ignore
|
|
NVOS30_FLAGS_IDLE_NVENC0 = NVOS30_FLAGS_IDLE_MSENC # type: ignore
|
|
NVOS30_FLAGS_IDLE_NVENC1 = (0x00040000) # type: ignore
|
|
NVOS30_FLAGS_IDLE_NVENC2 = (0x00080000) # type: ignore
|
|
NVOS30_FLAGS_IDLE_NVJPG = (0x00100000) # type: ignore
|
|
NVOS30_FLAGS_IDLE_NVDEC1 = (0x00200000) # type: ignore
|
|
NVOS30_FLAGS_IDLE_NVDEC2 = (0x00400000) # type: ignore
|
|
NVOS30_FLAGS_IDLE_ACTIVECHANNELS = (0x00800000) # type: ignore
|
|
NVOS30_FLAGS_IDLE_ALL_ENGINES = (NVOS30_FLAGS_IDLE_GRAPHICS | NVOS30_FLAGS_IDLE_MPEG | NVOS30_FLAGS_IDLE_MOTION_ESTIMATION | NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR | NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR | NVOS30_FLAGS_IDLE_CIPHER_DMA | NVOS30_FLAGS_IDLE_MSPDEC | NVOS30_FLAGS_IDLE_NVDEC0 | NVOS30_FLAGS_IDLE_SEC | NVOS30_FLAGS_IDLE_MSPPP | NVOS30_FLAGS_IDLE_CE0 | NVOS30_FLAGS_IDLE_CE1 | NVOS30_FLAGS_IDLE_CE2 | NVOS30_FLAGS_IDLE_CE3 | NVOS30_FLAGS_IDLE_CE4 | NVOS30_FLAGS_IDLE_CE5 | NVOS30_FLAGS_IDLE_NVENC0 | NVOS30_FLAGS_IDLE_NVENC1 | NVOS30_FLAGS_IDLE_NVENC2 | NVOS30_FLAGS_IDLE_VIC | NVOS30_FLAGS_IDLE_NVJPG | NVOS30_FLAGS_IDLE_NVDEC1 | NVOS30_FLAGS_IDLE_NVDEC2) # type: ignore
|
|
NVOS30_FLAGS_WAIT_FOR_ELPG_ON = (31, 31) # type: ignore
|
|
NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO = (0x00000000) # type: ignore
|
|
NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES = (0x00000001) # type: ignore
|
|
NV04_VID_HEAP_CONTROL = (0x00000020) # type: ignore
|
|
NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS = 0 # type: ignore
|
|
NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY = 1 # type: ignore
|
|
NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY = 2 # type: ignore
|
|
NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR = 3 # type: ignore
|
|
NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE = 4 # type: ignore
|
|
NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR = 5 # type: ignore
|
|
NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR = 6 # type: ignore
|
|
NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS = 7 # type: ignore
|
|
NVOS32_FUNCTION_ALLOC_SIZE = 2 # type: ignore
|
|
NVOS32_FUNCTION_FREE = 3 # type: ignore
|
|
NVOS32_FUNCTION_INFO = 5 # type: ignore
|
|
NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT = 6 # type: ignore
|
|
NVOS32_FUNCTION_DUMP = 11 # type: ignore
|
|
NVOS32_FUNCTION_ALLOC_SIZE_RANGE = 14 # type: ignore
|
|
NVOS32_FUNCTION_REACQUIRE_COMPR = 15 # type: ignore
|
|
NVOS32_FUNCTION_RELEASE_COMPR = 16 # type: ignore
|
|
NVOS32_FUNCTION_GET_MEM_ALIGNMENT = 18 # type: ignore
|
|
NVOS32_FUNCTION_HW_ALLOC = 19 # type: ignore
|
|
NVOS32_FUNCTION_HW_FREE = 20 # type: ignore
|
|
NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR = 27 # type: ignore
|
|
NVOS32_FLAGS_BLOCKINFO_VISIBILITY_CPU = (0x00000001) # type: ignore
|
|
NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP = 0 # type: ignore
|
|
NVAL_MAX_BANKS = (4) # type: ignore
|
|
NVAL_MAP_DIRECTION = (0, 0) # type: ignore
|
|
NVAL_MAP_DIRECTION_DOWN = 0x00000000 # type: ignore
|
|
NVAL_MAP_DIRECTION_UP = 0x00000001 # type: ignore
|
|
NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR = 1 # type: ignore
|
|
NVOS32_DELETE_RESOURCES_ALL = 0 # type: ignore
|
|
NVOS32_TYPE_IMAGE = 0 # type: ignore
|
|
NVOS32_TYPE_DEPTH = 1 # type: ignore
|
|
NVOS32_TYPE_TEXTURE = 2 # type: ignore
|
|
NVOS32_TYPE_VIDEO = 3 # type: ignore
|
|
NVOS32_TYPE_FONT = 4 # type: ignore
|
|
NVOS32_TYPE_CURSOR = 5 # type: ignore
|
|
NVOS32_TYPE_DMA = 6 # type: ignore
|
|
NVOS32_TYPE_INSTANCE = 7 # type: ignore
|
|
NVOS32_TYPE_PRIMARY = 8 # type: ignore
|
|
NVOS32_TYPE_ZCULL = 9 # type: ignore
|
|
NVOS32_TYPE_UNUSED = 10 # type: ignore
|
|
NVOS32_TYPE_SHADER_PROGRAM = 11 # type: ignore
|
|
NVOS32_TYPE_OWNER_RM = 12 # type: ignore
|
|
NVOS32_TYPE_NOTIFIER = 13 # type: ignore
|
|
NVOS32_TYPE_RESERVED = 14 # type: ignore
|
|
NVOS32_TYPE_PMA = 15 # type: ignore
|
|
NVOS32_TYPE_STENCIL = 16 # type: ignore
|
|
NVOS32_NUM_MEM_TYPES = 17 # type: ignore
|
|
NVOS32_ATTR_NONE = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_DEPTH = (2, 0) # type: ignore
|
|
NVOS32_ATTR_DEPTH_UNKNOWN = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_DEPTH_8 = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_DEPTH_16 = 0x00000002 # type: ignore
|
|
NVOS32_ATTR_DEPTH_24 = 0x00000003 # type: ignore
|
|
NVOS32_ATTR_DEPTH_32 = 0x00000004 # type: ignore
|
|
NVOS32_ATTR_DEPTH_64 = 0x00000005 # type: ignore
|
|
NVOS32_ATTR_DEPTH_128 = 0x00000006 # type: ignore
|
|
NVOS32_ATTR_COMPR_COVG = (3, 3) # type: ignore
|
|
NVOS32_ATTR_COMPR_COVG_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_COMPR_COVG_PROVIDED = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_AA_SAMPLES = (7, 4) # type: ignore
|
|
NVOS32_ATTR_AA_SAMPLES_1 = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_AA_SAMPLES_2 = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_AA_SAMPLES_4 = 0x00000002 # type: ignore
|
|
NVOS32_ATTR_AA_SAMPLES_4_ROTATED = 0x00000003 # type: ignore
|
|
NVOS32_ATTR_AA_SAMPLES_6 = 0x00000004 # type: ignore
|
|
NVOS32_ATTR_AA_SAMPLES_8 = 0x00000005 # type: ignore
|
|
NVOS32_ATTR_AA_SAMPLES_16 = 0x00000006 # type: ignore
|
|
NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8 = 0x00000007 # type: ignore
|
|
NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 = 0x00000008 # type: ignore
|
|
NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 = 0x00000009 # type: ignore
|
|
NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 = 0x0000000A # type: ignore
|
|
NVOS32_ATTR_ZCULL = (11, 10) # type: ignore
|
|
NVOS32_ATTR_ZCULL_NONE = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_ZCULL_REQUIRED = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_ZCULL_ANY = 0x00000002 # type: ignore
|
|
NVOS32_ATTR_ZCULL_SHARED = 0x00000003 # type: ignore
|
|
NVOS32_ATTR_COMPR = (13, 12) # type: ignore
|
|
NVOS32_ATTR_COMPR_NONE = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_COMPR_REQUIRED = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_COMPR_ANY = 0x00000002 # type: ignore
|
|
NVOS32_ATTR_COMPR_PLC_REQUIRED = NVOS32_ATTR_COMPR_REQUIRED # type: ignore
|
|
NVOS32_ATTR_COMPR_PLC_ANY = NVOS32_ATTR_COMPR_ANY # type: ignore
|
|
NVOS32_ATTR_COMPR_DISABLE_PLC_ANY = 0x00000003 # type: ignore
|
|
NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP = (14, 14) # type: ignore
|
|
NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_NO = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_YES = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_FORMAT = (17, 16) # type: ignore
|
|
NVOS32_ATTR_FORMAT_LOW_FIELD = 16 # type: ignore
|
|
NVOS32_ATTR_FORMAT_HIGH_FIELD = 17 # type: ignore
|
|
NVOS32_ATTR_FORMAT_PITCH = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_FORMAT_SWIZZLED = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_FORMAT_BLOCK_LINEAR = 0x00000002 # type: ignore
|
|
NVOS32_ATTR_Z_TYPE = (18, 18) # type: ignore
|
|
NVOS32_ATTR_Z_TYPE_FIXED = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_Z_TYPE_FLOAT = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_ZS_PACKING = (21, 19) # type: ignore
|
|
NVOS32_ATTR_ZS_PACKING_S8 = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_ZS_PACKING_Z24S8 = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_ZS_PACKING_S8Z24 = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_ZS_PACKING_Z32 = 0x00000002 # type: ignore
|
|
NVOS32_ATTR_ZS_PACKING_Z24X8 = 0x00000003 # type: ignore
|
|
NVOS32_ATTR_ZS_PACKING_X8Z24 = 0x00000004 # type: ignore
|
|
NVOS32_ATTR_ZS_PACKING_Z32_X24S8 = 0x00000005 # type: ignore
|
|
NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8 = 0x00000006 # type: ignore
|
|
NVOS32_ATTR_ZS_PACKING_Z16 = 0x00000007 # type: ignore
|
|
NVOS32_ATTR_COLOR_PACKING = NVOS32_ATTR_ZS_PACKING # type: ignore
|
|
NVOS32_ATTR_COLOR_PACKING_A8R8G8B8 = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_COLOR_PACKING_X8R8G8B8 = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_PAGE_SIZE = (24, 23) # type: ignore
|
|
NVOS32_ATTR_PAGE_SIZE_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_PAGE_SIZE_4KB = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_PAGE_SIZE_BIG = 0x00000002 # type: ignore
|
|
NVOS32_ATTR_PAGE_SIZE_HUGE = 0x00000003 # type: ignore
|
|
NVOS32_ATTR_LOCATION = (26, 25) # type: ignore
|
|
NVOS32_ATTR_LOCATION_VIDMEM = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_LOCATION_PCI = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_LOCATION_ANY = 0x00000003 # type: ignore
|
|
NVOS32_ATTR_PHYSICALITY = (28, 27) # type: ignore
|
|
NVOS32_ATTR_PHYSICALITY_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_PHYSICALITY_CONTIGUOUS = 0x00000002 # type: ignore
|
|
NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS = 0x00000003 # type: ignore
|
|
NVOS32_ATTR_COHERENCY = (31, 29) # type: ignore
|
|
NVOS32_ATTR_COHERENCY_UNCACHED = 0x00000000 # type: ignore
|
|
NVOS32_ATTR_COHERENCY_CACHED = 0x00000001 # type: ignore
|
|
NVOS32_ATTR_COHERENCY_WRITE_COMBINE = 0x00000002 # type: ignore
|
|
NVOS32_ATTR_COHERENCY_WRITE_THROUGH = 0x00000003 # type: ignore
|
|
NVOS32_ATTR_COHERENCY_WRITE_PROTECT = 0x00000004 # type: ignore
|
|
NVOS32_ATTR_COHERENCY_WRITE_BACK = 0x00000005 # type: ignore
|
|
NVOS32_ATTR2_NONE = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_ZBC = (1, 0) # type: ignore
|
|
NVOS32_ATTR2_ZBC_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_ZBC_PREFER_NO_ZBC = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_ZBC_PREFER_ZBC = 0x00000002 # type: ignore
|
|
NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC = 0x00000003 # type: ignore
|
|
NVOS32_ATTR2_ZBC_INVALID = 0x00000003 # type: ignore
|
|
NVOS32_ATTR2_GPU_CACHEABLE = (3, 2) # type: ignore
|
|
NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_GPU_CACHEABLE_YES = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_GPU_CACHEABLE_NO = 0x00000002 # type: ignore
|
|
NVOS32_ATTR2_GPU_CACHEABLE_INVALID = 0x00000003 # type: ignore
|
|
NVOS32_ATTR2_P2P_GPU_CACHEABLE = (5, 4) # type: ignore
|
|
NVOS32_ATTR2_P2P_GPU_CACHEABLE_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_P2P_GPU_CACHEABLE_YES = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_P2P_GPU_CACHEABLE_NO = 0x00000002 # type: ignore
|
|
NVOS32_ATTR2_32BIT_POINTER = (6, 6) # type: ignore
|
|
NVOS32_ATTR2_32BIT_POINTER_DISABLE = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_32BIT_POINTER_ENABLE = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_FIXED_NUMA_NODE_ID = (7, 7) # type: ignore
|
|
NVOS32_ATTR2_FIXED_NUMA_NODE_ID_NO = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_FIXED_NUMA_NODE_ID_YES = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_SMMU_ON_GPU = (9, 8) # type: ignore
|
|
NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_SMMU_ON_GPU_DISABLE = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_SMMU_ON_GPU_ENABLE = 0x00000002 # type: ignore
|
|
NVOS32_ATTR2_USE_SCANOUT_CARVEOUT = (10, 10) # type: ignore
|
|
NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_FALSE = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_TRUE = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN = (11, 11) # type: ignore
|
|
NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF = 0x0 # type: ignore
|
|
NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_ON = 0x1 # type: ignore
|
|
NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_DEFAULT = NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF # type: ignore
|
|
NVOS32_ATTR2_PRIORITY = (13, 12) # type: ignore
|
|
NVOS32_ATTR2_PRIORITY_DEFAULT = 0x0 # type: ignore
|
|
NVOS32_ATTR2_PRIORITY_HIGH = 0x1 # type: ignore
|
|
NVOS32_ATTR2_PRIORITY_LOW = 0x2 # type: ignore
|
|
NVOS32_ATTR2_INTERNAL = (14, 14) # type: ignore
|
|
NVOS32_ATTR2_INTERNAL_NO = 0x0 # type: ignore
|
|
NVOS32_ATTR2_INTERNAL_YES = 0x1 # type: ignore
|
|
NVOS32_ATTR2_PREFER_2C = (15, 15) # type: ignore
|
|
NVOS32_ATTR2_PREFER_2C_NO = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_PREFER_2C_YES = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_NISO_DISPLAY = (16, 16) # type: ignore
|
|
NVOS32_ATTR2_NISO_DISPLAY_NO = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_NISO_DISPLAY_YES = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT = (17, 17) # type: ignore
|
|
NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_ISO = (18, 18) # type: ignore
|
|
NVOS32_ATTR2_ISO_NO = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_ISO_YES = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_BLACKLIST = (19, 19) # type: ignore
|
|
NVOS32_ATTR2_BLACKLIST_ON = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_BLACKLIST_OFF = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_PAGE_OFFLINING = (19, 19) # type: ignore
|
|
NVOS32_ATTR2_PAGE_OFFLINING_ON = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_PAGE_OFFLINING_OFF = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_PAGE_SIZE_HUGE = (21, 20) # type: ignore
|
|
NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB = 0x00000002 # type: ignore
|
|
NVOS32_ATTR2_PAGE_SIZE_HUGE_256GB = 0x00000003 # type: ignore
|
|
NVOS32_ATTR2_PROTECTION_USER = (22, 22) # type: ignore
|
|
NVOS32_ATTR2_PROTECTION_USER_READ_WRITE = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_PROTECTION_USER_READ_ONLY = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_PROTECTION_DEVICE = (23, 23) # type: ignore
|
|
NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_USE_EGM = (24, 24) # type: ignore
|
|
NVOS32_ATTR2_USE_EGM_FALSE = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_USE_EGM_TRUE = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_MEMORY_PROTECTION = (26, 25) # type: ignore
|
|
NVOS32_ATTR2_MEMORY_PROTECTION_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_MEMORY_PROTECTION_PROTECTED = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_MEMORY_PROTECTION_UNPROTECTED = 0x00000002 # type: ignore
|
|
NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP = (27, 27) # type: ignore
|
|
NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES = 0x00000001 # type: ignore
|
|
NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM = (31, 31) # type: ignore
|
|
NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_FALSE = 0x00000000 # type: ignore
|
|
NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_TRUE = 0x00000001 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT = 0x00000001 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP = 0x00000002 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN = 0x00000004 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE = 0x00000008 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE = 0x00000010 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_BANK_HINT = 0x00000020 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_BANK_FORCE = 0x00000040 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT = 0x00000080 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE = 0x00000100 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_BANK_GROW_UP = 0x00000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN = 0x00000200 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_LAZY = 0x00000400 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_FORCE_REVERSE_ALLOC = 0x00000800 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_NO_SCANOUT = 0x00001000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_PITCH_FORCE = 0x00002000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED = 0x00004000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED = 0x00008000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM = 0x00010000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_USE_BEGIN_END = 0x00020000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED = 0x00040000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_VIRTUAL = 0x00080000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX = 0x00100000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED = 0x00200000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED = 0x00400000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE = 0x00800000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_PROTECTED = 0x01000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP = 0x02000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE = 0x02000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_SPARSE = 0x04000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_USER_READ_ONLY = 0x04000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY = 0x08000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED = 0x08000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC = 0x10000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY = 0x20000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD = 0x40000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_WPR1 = 0x40000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X = 0x80000000 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_WPR2 = 0x80000000 # type: ignore
|
|
NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC = 0x00000001 # type: ignore
|
|
NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB = 0x00000004 # type: ignore
|
|
NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE = NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE # type: ignore
|
|
NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY = ( NVOS32_ALLOC_FLAGS_VIRTUAL | NVOS32_ALLOC_FLAGS_LAZY | NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED | NVOS32_ALLOC_FLAGS_SPARSE | NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE | NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY ) # type: ignore
|
|
NVOS32_ALLOC_COMPR_COVG_SCALE = 10 # type: ignore
|
|
NVOS32_ALLOC_COMPR_COVG_BITS = (1, 0) # type: ignore
|
|
NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS32_ALLOC_COMPR_COVG_BITS_1 = 0x00000001 # type: ignore
|
|
NVOS32_ALLOC_COMPR_COVG_BITS_2 = 0x00000002 # type: ignore
|
|
NVOS32_ALLOC_COMPR_COVG_BITS_4 = 0x00000003 # type: ignore
|
|
NVOS32_ALLOC_COMPR_COVG_MAX = (11, 2) # type: ignore
|
|
NVOS32_ALLOC_COMPR_COVG_MIN = (21, 12) # type: ignore
|
|
NVOS32_ALLOC_COMPR_COVG_START = (31, 22) # type: ignore
|
|
NVOS32_ALLOC_ZCULL_COVG_FORMAT = (3, 0) # type: ignore
|
|
NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z = 0x00000000 # type: ignore
|
|
NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z = 0x00000002 # type: ignore
|
|
NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS = 0x00000003 # type: ignore
|
|
NVOS32_ALLOC_ZCULL_COVG_FALLBACK = (4, 4) # type: ignore
|
|
NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW = 0x00000000 # type: ignore
|
|
NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW = 0x00000001 # type: ignore
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_START = (19, 0) # type: ignore
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE = (31, 30) # type: ignore
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT = 0x00000000 # type: ignore
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF = 0x00000000 # type: ignore
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED = 0x00000001 # type: ignore
|
|
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN = 0x00000002 # type: ignore
|
|
NVOS32_REALLOC_FLAGS_GROW_ALLOCATION = 0x00000000 # type: ignore
|
|
NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION = 0x00000001 # type: ignore
|
|
NVOS32_REALLOC_FLAGS_REALLOC_UP = 0x00000000 # type: ignore
|
|
NVOS32_REALLOC_FLAGS_REALLOC_DOWN = 0x00000002 # type: ignore
|
|
NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED = 0x000000001 # type: ignore
|
|
NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED = 0x000000001 # type: ignore
|
|
NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED = 0x00000001 # type: ignore
|
|
NVOS32_DUMP_FLAGS_TYPE = (1, 0) # type: ignore
|
|
NVOS32_DUMP_FLAGS_TYPE_FB = 0x00000000 # type: ignore
|
|
NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD = 0x00000001 # type: ignore
|
|
NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA = 0x00000002 # type: ignore
|
|
NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE = 0x00000003 # type: ignore
|
|
NVOS32_BLOCK_TYPE_FREE = 0xFFFFFFFF # type: ignore
|
|
NVOS32_INVALID_BLOCK_FREE_OFFSET = 0xFFFFFFFF # type: ignore
|
|
NVOS32_MEM_TAG_NONE = 0x00000000 # type: ignore
|
|
NV04_MAP_MEMORY = (0x00000021) # type: ignore
|
|
NV04_MAP_MEMORY_FLAGS_NONE = (0x00000000) # type: ignore
|
|
NV04_MAP_MEMORY_FLAGS_USER = (0x00004000) # type: ignore
|
|
NVOS33_FLAGS_ACCESS = (1, 0) # type: ignore
|
|
NVOS33_FLAGS_ACCESS_READ_WRITE = (0x00000000) # type: ignore
|
|
NVOS33_FLAGS_ACCESS_READ_ONLY = (0x00000001) # type: ignore
|
|
NVOS33_FLAGS_ACCESS_WRITE_ONLY = (0x00000002) # type: ignore
|
|
NVOS33_FLAGS_PERSISTENT = (4, 4) # type: ignore
|
|
NVOS33_FLAGS_PERSISTENT_DISABLE = (0x00000000) # type: ignore
|
|
NVOS33_FLAGS_PERSISTENT_ENABLE = (0x00000001) # type: ignore
|
|
NVOS33_FLAGS_SKIP_SIZE_CHECK = (8, 8) # type: ignore
|
|
NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE = (0x00000000) # type: ignore
|
|
NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE = (0x00000001) # type: ignore
|
|
NVOS33_FLAGS_MEM_SPACE = (14, 14) # type: ignore
|
|
NVOS33_FLAGS_MEM_SPACE_CLIENT = (0x00000000) # type: ignore
|
|
NVOS33_FLAGS_MEM_SPACE_USER = (0x00000001) # type: ignore
|
|
NVOS33_FLAGS_MAPPING = (16, 15) # type: ignore
|
|
NVOS33_FLAGS_MAPPING_DEFAULT = (0x00000000) # type: ignore
|
|
NVOS33_FLAGS_MAPPING_DIRECT = (0x00000001) # type: ignore
|
|
NVOS33_FLAGS_MAPPING_REFLECTED = (0x00000002) # type: ignore
|
|
NVOS33_FLAGS_FIFO_MAPPING = (17, 17) # type: ignore
|
|
NVOS33_FLAGS_FIFO_MAPPING_DEFAULT = (0x00000000) # type: ignore
|
|
NVOS33_FLAGS_FIFO_MAPPING_ENABLE = (0x00000001) # type: ignore
|
|
NVOS33_FLAGS_MAP_FIXED = (18, 18) # type: ignore
|
|
NVOS33_FLAGS_MAP_FIXED_DISABLE = (0x00000000) # type: ignore
|
|
NVOS33_FLAGS_MAP_FIXED_ENABLE = (0x00000001) # type: ignore
|
|
NVOS33_FLAGS_RESERVE_ON_UNMAP = (19, 19) # type: ignore
|
|
NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE = (0x00000000) # type: ignore
|
|
NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE = (0x00000001) # type: ignore
|
|
NVOS33_FLAGS_OS_DESCRIPTOR = (22, 22) # type: ignore
|
|
NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE = (0x00000000) # type: ignore
|
|
NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE = (0x00000001) # type: ignore
|
|
NVOS33_FLAGS_CACHING_TYPE = (25, 23) # type: ignore
|
|
NVOS33_FLAGS_CACHING_TYPE_CACHED = 0 # type: ignore
|
|
NVOS33_FLAGS_CACHING_TYPE_UNCACHED = 1 # type: ignore
|
|
NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED = 2 # type: ignore
|
|
NVOS33_FLAGS_CACHING_TYPE_WRITEBACK = 5 # type: ignore
|
|
NVOS33_FLAGS_CACHING_TYPE_DEFAULT = 6 # type: ignore
|
|
NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK = 7 # type: ignore
|
|
NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC = (26, 26) # type: ignore
|
|
NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_NO = (0x00000000) # type: ignore
|
|
NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_YES = (0x00000001) # type: ignore
|
|
NV04_UNMAP_MEMORY = (0x00000022) # type: ignore
|
|
NV04_ACCESS_REGISTRY = (0x00000026) # type: ignore
|
|
NVOS38_ACCESS_TYPE_READ_DWORD = 1 # type: ignore
|
|
NVOS38_ACCESS_TYPE_WRITE_DWORD = 2 # type: ignore
|
|
NVOS38_ACCESS_TYPE_READ_BINARY = 6 # type: ignore
|
|
NVOS38_ACCESS_TYPE_WRITE_BINARY = 7 # type: ignore
|
|
NVOS38_MAX_REGISTRY_STRING_LENGTH = 256 # type: ignore
|
|
NVOS38_MAX_REGISTRY_BINARY_LENGTH = 256 # type: ignore
|
|
NV04_ALLOC_CONTEXT_DMA = (0x00000027) # type: ignore
|
|
NV04_GET_EVENT_DATA = (0x00000028) # type: ignore
|
|
NVSIM01_BUS_XACT = (0x0000002C) # type: ignore
|
|
NV04_MAP_MEMORY_DMA = (0x0000002E) # type: ignore
|
|
NVOS46_FLAGS_ACCESS = (1, 0) # type: ignore
|
|
NVOS46_FLAGS_ACCESS_READ_WRITE = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_ACCESS_READ_ONLY = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_ACCESS_WRITE_ONLY = (0x00000002) # type: ignore
|
|
NVOS46_FLAGS_32BIT_POINTER = (2, 2) # type: ignore
|
|
NVOS46_FLAGS_32BIT_POINTER_DISABLE = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_32BIT_POINTER_ENABLE = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_PAGE_KIND = (3, 3) # type: ignore
|
|
NVOS46_FLAGS_PAGE_KIND_PHYSICAL = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_PAGE_KIND_VIRTUAL = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_CACHE_SNOOP = (4, 4) # type: ignore
|
|
NVOS46_FLAGS_CACHE_SNOOP_DISABLE = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_CACHE_SNOOP_ENABLE = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_KERNEL_MAPPING = (5, 5) # type: ignore
|
|
NVOS46_FLAGS_KERNEL_MAPPING_NONE = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_KERNEL_MAPPING_ENABLE = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_SHADER_ACCESS = (7, 6) # type: ignore
|
|
NVOS46_FLAGS_SHADER_ACCESS_DEFAULT = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY = (0x00000002) # type: ignore
|
|
NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE = (0x00000003) # type: ignore
|
|
NVOS46_FLAGS_PAGE_SIZE = (11, 8) # type: ignore
|
|
NVOS46_FLAGS_PAGE_SIZE_DEFAULT = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_PAGE_SIZE_4KB = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_PAGE_SIZE_BIG = (0x00000002) # type: ignore
|
|
NVOS46_FLAGS_PAGE_SIZE_BOTH = (0x00000003) # type: ignore
|
|
NVOS46_FLAGS_PAGE_SIZE_HUGE = (0x00000004) # type: ignore
|
|
NVOS46_FLAGS_PAGE_SIZE_512M = (0x00000005) # type: ignore
|
|
NVOS46_FLAGS_SYSTEM_L3_ALLOC = (13, 13) # type: ignore
|
|
NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_DMA_OFFSET_GROWS = (14, 14) # type: ignore
|
|
NVOS46_FLAGS_DMA_OFFSET_GROWS_UP = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_DMA_OFFSET_FIXED = (15, 15) # type: ignore
|
|
NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_DISABLE_ENCRYPTION = (16, 16) # type: ignore
|
|
NVOS46_FLAGS_DISABLE_ENCRYPTION_FALSE = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_DISABLE_ENCRYPTION_TRUE = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_P2P = (27, 20) # type: ignore
|
|
NVOS46_FLAGS_P2P_ENABLE = (21, 20) # type: ignore
|
|
NVOS46_FLAGS_P2P_ENABLE_NO = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_P2P_ENABLE_YES = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_P2P_ENABLE_NONE = NVOS46_FLAGS_P2P_ENABLE_NO # type: ignore
|
|
NVOS46_FLAGS_P2P_ENABLE_SLI = NVOS46_FLAGS_P2P_ENABLE_YES # type: ignore
|
|
NVOS46_FLAGS_P2P_ENABLE_NOSLI = (0x00000002) # type: ignore
|
|
NVOS46_FLAGS_P2P_SUBDEVICE_ID = (24, 22) # type: ignore
|
|
NVOS46_FLAGS_P2P_SUBDEV_ID_SRC = NVOS46_FLAGS_P2P_SUBDEVICE_ID # type: ignore
|
|
NVOS46_FLAGS_P2P_SUBDEV_ID_TGT = (27, 25) # type: ignore
|
|
NVOS46_FLAGS_TLB_LOCK = (28, 28) # type: ignore
|
|
NVOS46_FLAGS_TLB_LOCK_DISABLE = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_TLB_LOCK_ENABLE = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC = (29, 29) # type: ignore
|
|
NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP = (30, 30) # type: ignore
|
|
NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_FALSE = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_TRUE = (0x00000001) # type: ignore
|
|
NVOS46_FLAGS_DEFER_TLB_INVALIDATION = (31, 31) # type: ignore
|
|
NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE = (0x00000000) # type: ignore
|
|
NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE = (0x00000001) # type: ignore
|
|
NV04_UNMAP_MEMORY_DMA = (0x0000002F) # type: ignore
|
|
NVOS47_FLAGS_DEFER_TLB_INVALIDATION = (0, 0) # type: ignore
|
|
NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE = (0x00000000) # type: ignore
|
|
NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE = (0x00000001) # type: ignore
|
|
NV04_BIND_CONTEXT_DMA = (0x00000031) # type: ignore
|
|
NV04_CONTROL = (0x00000036) # type: ignore
|
|
NVOS54_FLAGS_NONE = (0x00000000) # type: ignore
|
|
NVOS54_FLAGS_IRQL_RAISED = (0x00000001) # type: ignore
|
|
NVOS54_FLAGS_LOCK_BYPASS = (0x00000002) # type: ignore
|
|
NVOS54_FLAGS_FINN_SERIALIZED = (0x00000004) # type: ignore
|
|
NV04_DUP_OBJECT = (0x00000037) # type: ignore
|
|
NV04_DUP_HANDLE_FLAGS_NONE = (0x00000000) # type: ignore
|
|
NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE = (0x00000001) # type: ignore
|
|
NV04_UPDATE_DEVICE_MAPPING_INFO = (0x00000038) # type: ignore
|
|
NV04_SHARE = (0x0000003E) # type: ignore
|
|
NV_DEVICE_ALLOCATION_SZNAME_MAXLEN = 128 # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_NONE = (0x00000000) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY = (0x00000001) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE = (0x00000002) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS = (0x00000004) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE = (0x00000008) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE = (0x00000010) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET = (0x00000020) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT = (0x00000100) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k = (0x00000200) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k = (0x00000400) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS = (0x00000800) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_MIRRORED = (0x00000040) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED = (0x00001000) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE = (0x00002000) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT = (0x00004000) # type: ignore
|
|
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET = (0x00008000) # type: ignore
|
|
NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES = (0x00000000) # type: ignore
|
|
NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE = (0x00000001) # type: ignore
|
|
NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES = (0x00000002) # type: ignore
|
|
NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR = 0x00000000 # type: ignore
|
|
NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN = 0x00000001 # type: ignore
|
|
NV_CHANNELGPFIFO_NOTIFICATION_TYPE_KEY_ROTATION_STATUS = 0x00000002 # type: ignore
|
|
NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 = 3 # type: ignore
|
|
NV_CHANNELGPFIFO_NOTIFICATION_STATUS_VALUE = (14, 0) # type: ignore
|
|
NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS = (15, 15) # type: ignore
|
|
NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE = 0x1 # type: ignore
|
|
NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE = 0x0 # type: ignore
|
|
NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB = (1, 1) # type: ignore
|
|
NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES = 0x00000000 # type: ignore
|
|
NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO = 0x00000001 # type: ignore
|
|
NV_SWRUNLIST_QOS_INTR_NONE = 0x00000000 # type: ignore
|
|
NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE = (0x00000000) # type: ignore
|
|
NV_VP_ALLOCATION_FLAGS_STATIC_UCODE = (0x00000001) # type: ignore
|
|
NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE = (0x00000002) # type: ignore
|
|
NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO = (0x00000000) # type: ignore
|
|
NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO = (0x00000001) # type: ignore
|
|
NV04_ADD_VBLANK_CALLBACK = (0x0000003D) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_NONE = (0x00000000) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE = BIT(0) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS = BIT(1) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT = BIT(2) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED = BIT(3) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS = BIT(4) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_IS_MIRRORED = BIT(5) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_ENABLE_PAGE_FAULTING = BIT(6) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT = BIT(7) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_ALLOW_ZERO_ADDRESS = BIT(8) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_IS_FLA = BIT(9) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL = BIT(10) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE = BIT(11) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET = BIT(12) # type: ignore
|
|
NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED = BIT(13) # type: ignore
|
|
NV_VASPACE_ALLOCATION_INDEX_GPU_NEW = 0x00 # type: ignore
|
|
NV_VASPACE_ALLOCATION_INDEX_GPU_HOST = 0x01 # type: ignore
|
|
NV_VASPACE_ALLOCATION_INDEX_GPU_GLOBAL = 0x02 # type: ignore
|
|
NV_VASPACE_ALLOCATION_INDEX_GPU_DEVICE = 0x03 # type: ignore
|
|
NV_VASPACE_ALLOCATION_INDEX_GPU_FLA = 0x04 # type: ignore
|
|
NV_VASPACE_ALLOCATION_INDEX_GPU_MAX = 0x05 # type: ignore
|
|
NV_VASPACE_BIG_PAGE_SIZE_64K = (64 * 1024) # type: ignore
|
|
NV_VASPACE_BIG_PAGE_SIZE_128K = (128 * 1024) # type: ignore
|
|
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT = (1, 0) # type: ignore
|
|
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SYNC = (0x00000000) # type: ignore
|
|
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC = (0x00000001) # type: ignore
|
|
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SPECIFIED = (0x00000002) # type: ignore
|
|
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER = (0x00000003) # type: ignore
|
|
NV_CTXSHARE_ALLOCATION_SUBCTXID_SUBCTXID = (30, 0) # type: ignore
|
|
NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION = (31, 31) # type: ignore
|
|
NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_SUCCESS = (0x00000001) # type: ignore
|
|
NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_FAIL = (0x00000000) # type: ignore
|
|
NV_TIMEOUT_CONTROL_CMD_SET_DEVICE_TIMEOUT = (0x00000002) # type: ignore
|
|
NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT = (0x00000003) # type: ignore
|
|
NVC36F_CTRL_RESERVED = (0x00) # type: ignore
|
|
NVC36F_CTRL_GPFIFO = (0x01) # type: ignore
|
|
NVC36F_CTRL_EVENT = (0x02) # type: ignore
|
|
NVC36F_CTRL_INTERNAL = (0x03) # type: ignore
|
|
NVC36F_CTRL_CMD_NULL = (0xc36f0000) # type: ignore
|
|
NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = (0xc36f0108) # type: ignore
|
|
NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES = 0x2 # type: ignore
|
|
NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER = (0xc36f0109) # type: ignore
|
|
NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX = (0xc36f010a) # type: ignore
|
|
NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID = (0xA) # type: ignore
|
|
NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION = (0xc36f0205) # type: ignore
|
|
NVC36F_CTRL_CMD_EVENT_SET_TRIGGER = (0xc36f0206) # type: ignore
|
|
NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN = (0xc36f0301) # type: ignore
|
|
NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NVCB33_CTRL_RESERVED = (0x00) # type: ignore
|
|
NVCB33_CTRL_CONF_COMPUTE = (0x01) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_NULL = (0xcb330000) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = (0xcb330101) # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE = 0 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV = 1 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX = 2 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV_SNP = 3 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SNP_VTOM = 4 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE = 0 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM = 1 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC = 2 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE = 0 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM = 1 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD = 2 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED = 0 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED = 1 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED = 2 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED = 0 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED = 1 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE = 0 # type: ignore
|
|
NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE = 1 # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE = (0xcb330104) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE = (0xcb330105) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE = (0xcb330106) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE = (0xcb330107) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS = (0xcb330108) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE = (0xcb330109) # type: ignore
|
|
NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE = 0x1000 # type: ignore
|
|
NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE = 0x1400 # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT = (0xcb33010a) # type: ignore
|
|
NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE = 0x2000 # type: ignore
|
|
NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE = 0x1000 # type: ignore
|
|
NV_CONF_COMPUTE_NONCE_SIZE = 0x20 # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID = (0xA) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS = (0xcb33010b) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0xB) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE = (0xcb33010c) # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED = 0 # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED = 1 # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED = 2 # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED = 3 # type: ignore
|
|
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID = (0xC) # type: ignore
|
|
NVA06C_CTRL_RESERVED = (0x00) # type: ignore
|
|
NVA06C_CTRL_GPFIFO = (0x01) # type: ignore
|
|
NVA06C_CTRL_INTERNAL = (0x02) # type: ignore
|
|
NVA06C_CTRL_CMD_NULL = (0xa06c0000) # type: ignore
|
|
NVA06C_CTRL_CMD_GPFIFO_SCHEDULE = (0xa06c0101) # type: ignore
|
|
NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NVA06C_CTRL_CMD_BIND = (0xa06c0102) # type: ignore
|
|
NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NVA06C_CTRL_CMD_SET_TIMESLICE = (0xa06c0103) # type: ignore
|
|
NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NVA06C_CTRL_CMD_GET_TIMESLICE = (0xa06c0104) # type: ignore
|
|
NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NVA06C_CTRL_CMD_PREEMPT = (0xa06c0105) # type: ignore
|
|
NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US = (1000000) # type: ignore
|
|
NVA06C_CTRL_CMD_GET_INFO = (0xa06c0106) # type: ignore
|
|
NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL = (0xa06c0107) # type: ignore
|
|
NVA06C_CTRL_INTERLEAVE_LEVEL_LOW = (0x00000000) # type: ignore
|
|
NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM = (0x00000001) # type: ignore
|
|
NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH = (0x00000002) # type: ignore
|
|
NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL = (0xa06c0108) # type: ignore
|
|
NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE = (0xa06c0109) # type: ignore
|
|
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS = (0xa06c010a) # type: ignore
|
|
NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES = (NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES) # type: ignore
|
|
NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID = (0xa) # type: ignore
|
|
NVA06C_CTRL_CMD_MAKE_REALTIME = (0xa06c0110) # type: ignore
|
|
NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID = (0x10) # type: ignore
|
|
NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE = (0xa06c0201) # type: ignore
|
|
NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE = (0xa06c0202) # type: ignore
|
|
NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
GMMU_FMT_MAX_LEVELS = 6 # type: ignore
|
|
NV90F1_CTRL_RESERVED = (0x00) # type: ignore
|
|
NV90F1_CTRL_VASPACE = (0x01) # type: ignore
|
|
NV90F1_CTRL_CMD_NULL = (0x90f10000) # type: ignore
|
|
NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT = (0x90f10101) # type: ignore
|
|
NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO = (0x90f10102) # type: ignore
|
|
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE = 0x0 # type: ignore
|
|
NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES = (0x90f10103) # type: ignore
|
|
NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES = (0x90f10104) # type: ignore
|
|
NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF = (0x90f10105) # type: ignore
|
|
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES = (0x90f10106) # type: ignore
|
|
NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE = (0x90f10107) # type: ignore
|
|
NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO = (0x90f10108) # type: ignore
|
|
NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NVA06F_CTRL_CMD_GPFIFO_SCHEDULE = (0xa06f0103) # type: ignore
|
|
NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NVA06F_CTRL_CMD_BIND = (0xa06f0104) # type: ignore
|
|
NVA06F_CTRL_BIND_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NVA06F_CTRL_CMD_SET_ERROR_NOTIFIER = (0xa06f0108) # type: ignore
|
|
NVA06F_CTRL_SET_ERROR_NOTIFIER_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL = (0xa06f0109) # type: ignore
|
|
NVA06F_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NVA06F_CTRL_CMD_GET_INTERLEAVE_LEVEL = (0xa06f0110) # type: ignore
|
|
NVA06F_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x10) # type: ignore
|
|
NVA06F_CTRL_CMD_RESTART_RUNLIST = (0xa06f0111) # type: ignore
|
|
NVA06F_CTRL_RESTART_RUNLIST_PARAMS_MESSAGE_ID = (0x11) # type: ignore
|
|
NVA06F_CTRL_CMD_STOP_CHANNEL = (0xa06f0112) # type: ignore
|
|
NVA06F_CTRL_STOP_CHANNEL_PARAMS_MESSAGE_ID = (0x12) # type: ignore
|
|
NVA06F_CTRL_CMD_GET_CONTEXT_ID = (0xa06f0113) # type: ignore
|
|
NVA06F_CTRL_GET_CONTEXT_ID_PARAMS_MESSAGE_ID = (0x13) # type: ignore
|
|
NV0000_CTRL_RESERVED = (0x00) # type: ignore
|
|
NV0000_CTRL_SYSTEM = (0x01) # type: ignore
|
|
NV0000_CTRL_GPU = (0x02) # type: ignore
|
|
NV0000_CTRL_GSYNC = (0x03) # type: ignore
|
|
NV0000_CTRL_DIAG = (0x04) # type: ignore
|
|
NV0000_CTRL_EVENT = (0x05) # type: ignore
|
|
NV0000_CTRL_NVD = (0x06) # type: ignore
|
|
NV0000_CTRL_SWINSTR = (0x07) # type: ignore
|
|
NV0000_CTRL_PROC = (0x09) # type: ignore
|
|
NV0000_CTRL_SYNC_GPU_BOOST = (0x0A) # type: ignore
|
|
NV0000_CTRL_GPUACCT = (0x0B) # type: ignore
|
|
NV0000_CTRL_VGPU = (0x0C) # type: ignore
|
|
NV0000_CTRL_CLIENT = (0x0D) # type: ignore
|
|
NV0000_CTRL_OS_WINDOWS = (0x3F) # type: ignore
|
|
NV0000_CTRL_OS_MACOS = (0x3E) # type: ignore
|
|
NV0000_CTRL_OS_UNIX = (0x3D) # type: ignore
|
|
NV0000_CTRL_CMD_NULL = (0x0) # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE = (0xd01) # type: ignore
|
|
NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID = 0x00000000 # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM = 0x00000001 # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM = 0x00000002 # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM = 0x00000003 # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC = 0x00000004 # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO = (0xd02) # type: ignore
|
|
NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID = 0x00000000 # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT = 0x00000001 # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID = 0x00000002 # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS = (0xd03) # type: ignore
|
|
NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY = (0xd04) # type: ignore
|
|
NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE = (0xd05) # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT = (0xd06) # type: ignore
|
|
NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES = (0xd07) # type: ignore
|
|
NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL = (0xd08) # type: ignore
|
|
NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE = (0x480) # type: ignore
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID = (0x80) # type: ignore
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED = (0x00000000) # type: ignore
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED = (0x00000001) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES = (0x20000) # type: ignore
|
|
NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE = (0x481) # type: ignore
|
|
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID = (0x81) # type: ignore
|
|
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET = (0x00000002) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH = (0xc) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA = (0x00000001) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED = (0x00000002) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND = (0x00000003) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA = (0x00000004) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API = (0x00000010) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API = (0x00000011) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS = (0x00000020) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS = (0x00000021) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA = (0x00000100) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL = (0x00001000) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET = (0x00002000) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET = (0x00002001) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX = (0x00002002) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX = (0x00002003) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP = (0x00003000) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM = (0x00003001) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM = (0x00003002) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA = (0x00003003) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA = (0x00003004) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC = (0x00004000) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM = (0x00004001) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT = (0x00004010) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT = (0x00005000) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE = (0x00005001) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE = (0x00005002) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG = (0x00005003) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP = (0x00005004) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN = (0x00005005) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL = (0x00005006) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG = (0x00005007) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP = (0x00005008) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY = (0x00005009) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM = (0x0000500A) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT = (0x0000500B) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT = (0x0000500C) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS = (0x00006000) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA = (0x00007000) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA = (0x00007001) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR = (0x0000F000) # type: ignore
|
|
NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC = (0x0000F00F) # type: ignore
|
|
NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES = (0x485) # type: ignore
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX = (0x40) # type: ignore
|
|
NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID = (0x85) # type: ignore
|
|
NV0000_CTRL_CMD_DIAG_PROFILE_RPC = (0x488) # type: ignore
|
|
NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID = (0x88) # type: ignore
|
|
NV0000_CTRL_PROFILE_RPC_CMD_DISABLE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PROFILE_RPC_CMD_ENABLE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PROFILE_RPC_CMD_RESET = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_DIAG_DUMP_RPC = (0x489) # type: ignore
|
|
NV0000_CTRL_DIAG_RPC_MAX_ENTRIES = (100) # type: ignore
|
|
NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID = (0x89) # type: ignore
|
|
NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION = (0x501) # type: ignore
|
|
NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS = (0x502) # type: ignore
|
|
NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS = (0x201) # type: ignore
|
|
NV0000_CTRL_GPU_MAX_ATTACHED_GPUS = 32 # type: ignore
|
|
NV0000_CTRL_GPU_INVALID_ID = (0xffffffff) # type: ignore
|
|
NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_ID_INFO = (0x202) # type: ignore
|
|
NV0000_CTRL_GPU_MAX_SZNAME = 128 # type: ignore
|
|
NV0000_CTRL_NO_NUMA_NODE = (-1) # type: ignore
|
|
NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0000_CTRL_SLI_STATUS_OK = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SLI_STATUS_OS_NOT_SUPPORTED = (0x00000002) # type: ignore
|
|
NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED = (0x00000040) # type: ignore
|
|
NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 = (0x205) # type: ignore
|
|
NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_IN_USE = (0, 0) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE = (1, 1) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_MOBILE = (2, 2) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER = (3, 3) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_SOC = (5, 5) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_SOC_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_SOC_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED = (6, 6) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_INIT_STATUS = (0x203) # type: ignore
|
|
NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS = (0x204) # type: ignore
|
|
NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_PROBED_IDS = (0x214) # type: ignore
|
|
NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID = (0x14) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_PCI_INFO = (0x21b) # type: ignore
|
|
NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID = (0x1B) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_ATTACH_IDS = (0x215) # type: ignore
|
|
NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS = (0x0000ffff) # type: ignore
|
|
NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID = (0x15) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_DETACH_IDS = (0x216) # type: ignore
|
|
NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS = (0x0000ffff) # type: ignore
|
|
NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID = (0x16) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS = (0x219) # type: ignore
|
|
NV0000_CTRL_GPU_MAX_VIDEO_LINKS = 8 # type: ignore
|
|
NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID = (0x19) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_SVM_SIZE = (0x240) # type: ignore
|
|
NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID = (0x40) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO = (0x274) # type: ignore
|
|
NV0000_GPU_MAX_GID_LENGTH = (0x00000100) # type: ignore
|
|
NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID = (0x74) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT = (1, 0) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE = (2, 2) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID = (0x275) # type: ignore
|
|
NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID = (0x75) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT = (1, 0) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE = (2, 2) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE = (0x278) # type: ignore
|
|
NV0000_CTRL_GPU_DRAIN_STATE_DISABLED = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPU_DRAIN_STATE_ENABLED = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE = (0x00000002) # type: ignore
|
|
NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID = (0x78) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE = (0x279) # type: ignore
|
|
NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID = (0x79) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_DISCOVER = (0x27a) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE = (0x27b) # type: ignore
|
|
NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID = (0x7B) # type: ignore
|
|
NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT = (0x281) # type: ignore
|
|
NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID = (0x81) # type: ignore
|
|
NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA = 0x00000175 # type: ignore
|
|
NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN = 6 # type: ignore
|
|
NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT = 5 # type: ignore
|
|
NV0000_CTRL_CMD_GPU_LEGACY_CONFIG = (0x282) # type: ignore
|
|
NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID = (0x82) # type: ignore
|
|
NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX = (0x00000002) # type: ignore
|
|
NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX = (0x00000003) # type: ignore
|
|
NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED = (0x00000004) # type: ignore
|
|
NV0000_CTRL_CMD_IDLE_CHANNELS = (0x283) # type: ignore
|
|
NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID = (0x83) # type: ignore
|
|
NV0000_CTRL_GPU_IMAGE_TYPE_GSP = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG = (0x00000002) # type: ignore
|
|
NV0000_CTRL_GPU_IMAGE_TYPE_BINDATA_IMAGE = (0x00000003) # type: ignore
|
|
NV0000_CTRL_CMD_PUSH_UCODE_IMAGE = (0x285) # type: ignore
|
|
NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS_MESSAGE_ID = (0x85) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SETTING_LEGACY = (2, 0) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SETTING_LINK_COUNT = (7, 3) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL = (0x00) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF = (0x01) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN = (0x02) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF = (0x03) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER = (0x04) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_LINK_COUNT = (0x05) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_UNSET = (0x00) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_NODE = (0x01) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_GPU = (0x02) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE = (0x286) # type: ignore
|
|
NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID = (0x86) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE = (0x287) # type: ignore
|
|
NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID = (0x87) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS = (0x288) # type: ignore
|
|
NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES = 256 # type: ignore
|
|
NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID = (0x88) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID = (0x289) # type: ignore
|
|
NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID = (0x89) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID = (0x290) # type: ignore
|
|
NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID = (0x90) # type: ignore
|
|
NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE = (0xb01) # type: ignore
|
|
NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE = (0xb02) # type: ignore
|
|
NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO = (0xb03) # type: ignore
|
|
NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS = (0xb04) # type: ignore
|
|
NV0000_GPUACCT_PID_MAX_COUNT = 4000 # type: ignore
|
|
NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA = (0xb05) # type: ignore
|
|
NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS = (0x301) # type: ignore
|
|
NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0000_CTRL_GSYNC_INVALID_ID = (0xffffffff) # type: ignore
|
|
NV0000_CTRL_CMD_GSYNC_GET_ID_INFO = (0x302) # type: ignore
|
|
NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0000_CTRL_NVD_DUMP_COMPONENT_SYS = (0x400) # type: ignore
|
|
NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG = (0x800) # type: ignore
|
|
NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED = (0xB00) # type: ignore
|
|
NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE = (0x601) # type: ignore
|
|
NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0000_CTRL_NVD_MAX_DUMP_SIZE = (1000000) # type: ignore
|
|
NV0000_CTRL_CMD_NVD_GET_DUMP = (0x602) # type: ignore
|
|
NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT = (0x00000000) # type: ignore
|
|
NV0000_NVD_CPU_TIME_CLK_ID_OSTIME = (0x00000001) # type: ignore
|
|
NV0000_NVD_CPU_TIME_CLK_ID_TSC = (0x00000002) # type: ignore
|
|
NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API = (0x00000003) # type: ignore
|
|
NV0000_CTRL_CMD_NVD_GET_TIMESTAMP = (0x603) # type: ignore
|
|
NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO = (0x604) # type: ignore
|
|
NV0000_CTRL_NVD_MAX_RUNTIME_SIZES = (16) # type: ignore
|
|
NV0000_CTRL_NVD_SIGNATURE_SIZE = (4) # type: ignore
|
|
NV0000_CTRL_NVD_MAX_BUFFERS = (3840) # type: ignore
|
|
NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED = (0) # type: ignore
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_INT = (1) # type: ignore
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG = (2) # type: ignore
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_STRING = (3) # type: ignore
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_PTR = (4) # type: ignore
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR = (5) # type: ignore
|
|
NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT = (6) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_INFO = (7, 0) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE = (23, 8) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT = (0x00000004) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_RUNTIME_LEVEL = (28, 25) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP = (30, 29) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32 = (0x00000001) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64 = (0x00000002) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF = (0x00000003) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED = (31, 31) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO = (0x605) # type: ignore
|
|
NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE = (0, 0) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES = (0x00000001) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED = (0, 0) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES = (0x00000001) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE = (1, 1) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING = (0x00000000) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP = (0x00000001) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE = (2, 2) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES = (0x00000001) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED = (3, 3) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES = (0x00000001) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING = (5, 4) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL = (0x00000002) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA = (6, 6) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_NVD_GET_NVLOG = (0x606) # type: ignore
|
|
NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE = (4000) # type: ignore
|
|
NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV0000_CTRL_CMD_NVD_GET_RCERR_RPT = (0x607) # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES = 200 # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST = 0 # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS = 1 # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS = 2 # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS = 3 # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY = 0x00000000 # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED = 0x00000001 # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG = 0x0000000f # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST = 0x00000001 # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST = 0x00000002 # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID = 0x00000004 # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID = 0x00000008 # type: ignore
|
|
TPC_REG_ATTR = lambda gpcId,tpcId: ((gpcId << 8) | (tpcId)) # type: ignore
|
|
ROP_REG_ATTR = lambda gpcId,ropId: ((gpcId << 8) | (ropId)) # type: ignore
|
|
SM_REG_ATTR = lambda gpcId,tpcId,smId: ((((gpcId) << 16) | ((tpcId) << 8)) | (smId)) # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID = 0x00000000 # type: ignore
|
|
NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID = 0xFFFFFFFF # type: ignore
|
|
NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS = (0x608) # type: ignore
|
|
NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0000_CTRL_CMD_SET_SUB_PROCESS_ID = (0x901) # type: ignore
|
|
NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION = (0x902) # type: ignore
|
|
NV0000_SYNC_GPU_BOOST_MAX_GROUPS = (0x10) # type: ignore
|
|
NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID = 0xFFFFFFFF # type: ignore
|
|
NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO = (0xa01) # type: ignore
|
|
NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE = (0xa02) # type: ignore
|
|
NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY = (0xa03) # type: ignore
|
|
NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO = (0xa04) # type: ignore
|
|
NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_FEATURES = (0x1f0) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID = (0xF0) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_SLI = (0, 0) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT = (2, 2) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING = (3, 3) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED = (4, 4) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION = (0x101) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO = (0x102) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_FAMILY = (3, 0) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY = (11, 4) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_MODEL = (3, 0) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL = (7, 4) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY = 0xF # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY = 0xA # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL = 0x0 # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL = 0x4 # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY = 0x6 # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY = 0x0 # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL = 0x7 # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL = 0xA # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL = 0x9 # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P5 = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P55 = (0x00000002) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P6 = (0x00000003) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P2 = (0x00000004) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC = (0x00000005) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_CELA = (0x00000006) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P3 = (0x00000007) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 = (0x00000008) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_P4 = (0x00000009) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 = (0x00000010) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H = (0x00000011) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM = (0x00000012) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM = (0x00000013) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR = (0x00000014) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K5 = (0x00000030) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K6 = (0x00000031) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K62 = (0x00000032) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K63 = (0x00000033) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K7 = (0x00000034) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K8 = (0x00000035) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K10 = (0x00000036) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_K11 = (0x00000037) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN = (0x00000038) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_C6 = (0x00000060) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_C62 = (0x00000061) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_GX = (0x00000070) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_M1 = (0x00000071) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_M2 = (0x00000072) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_MGX = (0x00000073) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE = (0x00000080) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 = (0x00000090) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 = (0x00000091) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 = (0x00000092) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN = (0x00000093) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN = (0xA0000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 = (0xA0000009) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 = (0xA000000F) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 = (0xA0001000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 = (0xA0002000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC = (0xA00FF000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC = (0xA00FF001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_MMX = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_SSE = (0x00000002) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW = (0x00000004) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 = (0x00000008) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE = (0x00000010) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING = (0x00000020) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC = (0x00000040) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO = (0x00000080) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND = (0x00000100) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT = (0x00000200) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT = (0x00000400) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_CMOV = (0x00000800) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH = (0x00001000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 = (0x00002000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 = (0x00004000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 = (0x00008000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE = (0x00010000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 = (0x00020000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 = (0x00040000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_AVX = (0x00080000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CPU_CAP_ERMS = (0x00100000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO = (0x104) # type: ignore
|
|
NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH = (0x0000020) # type: ignore
|
|
NV0000_SYSTEM_CHIPSET_INVALID_ID = (0xffff) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE = (0, 0) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT = (0x107) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES = (0x109) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST = (0x108) # type: ignore
|
|
NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE = (32) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT = (0x110) # type: ignore
|
|
NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID = (0x10) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE = (0x00000002) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID = (0x00000003) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK = (0x00000004) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF = (0x00000002) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI = (0x00000003) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL = (0x00000004) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT = (0x5) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF = (0x00000002) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI = (0x00000003) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL = (0x00000004) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT = (0x5) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE = (0x111) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID = (0x11) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP = (0x000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC = (0x000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA = (0x000002) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC = (0x000003) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL = (0x121) # type: ignore
|
|
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE = 512 # type: ignore
|
|
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID = (0x21) # type: ignore
|
|
NV0000_CTRL_SYSTEM_HWBC_INVALID_ID = (0xFFFFFFFF) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO = (0x124) # type: ignore
|
|
NV0000_CTRL_SYSTEM_MAX_HWBCS = (0x00000080) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID = (0x24) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL = (0x122) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID = (0x22) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_INVALID = (0xFFFF) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT = (0x0000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC = (0x0001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC = (0x0002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS = (0x0003) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS = (0x0004) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC = (0x0005) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC = (0x0006) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE = (0x0007) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE = (0x0008) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT = (0x0009) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT = (0x000A) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE = (0x000B) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE = (0x000C) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER = (0x0100) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER = (0x0101) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET = (0x0102) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET = (0x0103) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD = (0x0104) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD = (0x0105) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET = (0x0106) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET = (0x0107) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT = (0x0108) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST = (0x0109) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST = (0x010A) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE = (0x010B) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE = (0x010C) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO = (0x010D) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS = (0x010E) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER = (0x0200) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA = (0x0201) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE = (0x0202) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG = (0x0203) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL = (0x0204) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN = (0x0205) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE = (0x0206) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS = (0x0210) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP = (0x0220) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA = (0x0221) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE = (0x0222) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE = (0x0240) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP = (0x0241) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN = (0x0242) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX = (0x0243) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION = (0x0244) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT = (0x0245) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE = (0x0250) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE = (0x0251) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA = (0x0252) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA = (0x0253) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK = (0x0320) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT = (0x0321) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID = (0xFFFF) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM = (0x0000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU = lambda i: (0x0100+((i)%0x100)) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU = lambda i: (0x0200+((i)%0x100)) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID = (0x80000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE = (0xFFFFFFFF) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS = (0x00000004) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC = (0x00000008) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC = (0x00000010) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB = (0x00000020) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS = (0x00000040) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT = (0x00000003) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 = (0x00000004) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 = (0x00000005) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM = (0x00000006) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM = (0x00000007) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL = (0x123) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX = (16) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID = (0x23) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS = (0x127) # type: ignore
|
|
NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS = 32 # type: ignore
|
|
NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED = 1024 # type: ignore
|
|
NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS = 8 # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER = 0xffffffff # type: ignore
|
|
NV0000_CTRL_P2P_CAPS_INDEX_READ = 0 # type: ignore
|
|
NV0000_CTRL_P2P_CAPS_INDEX_WRITE = 1 # type: ignore
|
|
NV0000_CTRL_P2P_CAPS_INDEX_NVLINK = 2 # type: ignore
|
|
NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS = 3 # type: ignore
|
|
NV0000_CTRL_P2P_CAPS_INDEX_PROP = 4 # type: ignore
|
|
NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK = 5 # type: ignore
|
|
NV0000_CTRL_P2P_CAPS_INDEX_PCI = 6 # type: ignore
|
|
NV0000_CTRL_P2P_CAPS_INDEX_C2C = 7 # type: ignore
|
|
NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 = 8 # type: ignore
|
|
NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE = 9 # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID = (0x27) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED = (0, 0) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED = (1, 1) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED = (2, 2) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED = (3, 3) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED = (4, 4) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED = (5, 5) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED = (6, 6) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED = (7, 7) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED = (8, 8) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED = (9, 9) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED = (10, 10) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED = (12, 12) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED = (13, 13) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE = (0x00000001) # type: ignore
|
|
NV0000_P2P_CAPS_STATUS_OK = (0x00) # type: ignore
|
|
NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED = (0x01) # type: ignore
|
|
NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED = (0x02) # type: ignore
|
|
NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED = (0x03) # type: ignore
|
|
NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY = (0x04) # type: ignore
|
|
NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED = (0x05) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 = (0x12b) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID = (0x2B) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX = (0x13a) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID = (0x3A) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CTRL = (0x12a) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID = (0x2A) # type: ignore
|
|
NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION = (0x00010000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT = (0x00000002) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_SENSOR_INDEX = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_MIN_LIMIT = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_MAX_LIMIT = (0x00000002) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE = (0x00000003) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT = (0x00000003) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA = (0x00000004) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA = (0x00000005) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA = (0x00000006) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA = (0x00000007) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA = (0x00000008) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA = (0x00000009) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000A) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000B) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000C) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000D) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS = (0x00000016) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS = (0x00000017) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM = (0x00000018) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM = (0x00000019) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR = (0x0000001A) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI = (0x0000001B) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_ACPI_CMD = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ = (0x00000002) # type: ignore
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO = (0x0000001C) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD = (0x00000026) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_PERIOD = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD = (0x00000027) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_PERIOD = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR = (0x00000028) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR = (0x00000029) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES = (0x0000002A) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES = (0x0000002B) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS = (0x0000002C) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS = (0x0000002D) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE = (0x0000002E) # type: ignore
|
|
NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE = (0x0000002F) # type: ignore
|
|
NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS = (0x00000044) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 = (0x00000001) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS = (0x00000045) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT = (0x00000046) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ = (0) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT = (0x00000047) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ = (0) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_PPM = (0x00000048) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX = (0) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK = (1) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_PPM = (0x00000049) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX = (0) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX = (2) # type: ignore
|
|
NV0000_CTRL_GPS_PPM_INDEX = (7, 0) # type: ignore
|
|
NV0000_CTRL_GPS_PPM_INDEX_MAXPERF = (0) # type: ignore
|
|
NV0000_CTRL_GPS_PPM_INDEX_BALANCED = (1) # type: ignore
|
|
NV0000_CTRL_GPS_PPM_INDEX_QUIET = (2) # type: ignore
|
|
NV0000_CTRL_GPS_PPM_INDEX_INVALID = (0xFF) # type: ignore
|
|
NV0000_CTRL_GPS_PPM_MASK = (15, 8) # type: ignore
|
|
NV0000_CTRL_GPS_PPM_MASK_INVALID = (0) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_PS_STATUS_OFF = (0) # type: ignore
|
|
NV0000_CTRL_GPS_CMD_PS_STATUS_ON = (1) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS = (0x129) # type: ignore
|
|
GPS_MAX_COUNTERS_PER_BLOCK = 32 # type: ignore
|
|
NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID = (0x29) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS = (0x12c) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x2C) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS = (0x12e) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x2E) # type: ignore
|
|
GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE = 288 # type: ignore
|
|
NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID = (0x2D) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI = (0x12d) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PARAM_TGPU = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PARAM_PDTS = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PARAM_SFAN = (0x00000002) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PARAM_SKNT = (0x00000003) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PARAM_CPUE = (0x00000004) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PARAM_TMP1 = (0x00000005) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PARAM_TMP2 = (0x00000006) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PARAM_CTGP = (0x00000007) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PARAM_PPMD = (0x00000008) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PARAM_COUNT = (0x00000009) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD = (0x130) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID = (0x30) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS = (0x00000002) # type: ignore
|
|
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY = (0x00000003) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS = (0x131) # type: ignore
|
|
NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID = (0x31) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ = (0x00000002) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH = (0x00000004) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF = (0x00000010) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG = (0x00000020) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS = (0x00000040) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER = (0x00000080) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP = (0x00000100) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI = (0x00000200) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR = (0x00000400) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK = (0x00000800) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL = (0x00001000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC = (0x00002000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM = (0x00004000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS = (0x00008000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE = (0x00010000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY = (0x00020000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA = (0x12f) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE = 64 # type: ignore
|
|
NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID = (0x2F) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA = (0x132) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID = (0x32) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE = 256 # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO = (0x133) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID = (0x33) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS = (0x134) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID = (0x34) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED = 0 # type: ignore
|
|
NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED = 1 # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS = (0x135) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID = (0x35) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG = (0x00000002) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG = (0x00000004) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS = (0x136) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID = (0x36) # type: ignore
|
|
NV0000_CTRL_VGPU_GET_VGPU_VERSION = (0x137) # type: ignore
|
|
NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID = (0x37) # type: ignore
|
|
NV0000_CTRL_VGPU_SET_VGPU_VERSION = (0x138) # type: ignore
|
|
NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID = (0x38) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID = (0x139) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID = (0x39) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO = (0x13b) # type: ignore
|
|
NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE = 1 # type: ignore
|
|
NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE = 32 # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT_MESSAGE_ID = (0x48) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID = (0x3B) # type: ignore
|
|
CONTROLLER_FILTER_TYPE_EMWA = 0 # type: ignore
|
|
CONTROLLER_FILTER_TYPE_MOVING_MAX = 1 # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE = 2 # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE = 3 # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE = 4 # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_CASE = 5 # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL_CASE = 6 # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED = (0x00000000) # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS = (0x00000002) # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED = (0, 0) # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES = 1 # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO = 0 # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION = (0x00000200) # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED = (0x00000000) # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES = (0x00000001) # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS = (0x00000002) # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE = (0x00000008) # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL = (0x00000009) # type: ignore
|
|
NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX = (255) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT = (0x13c) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID = (0x3C) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO = (0x13d) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID = (0x3D) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE = 256 # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 = (0x13e) # type: ignore
|
|
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID = (0x3E) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL = (0x13f) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID = (0x3F) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL = (0x140) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID = (0x40) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID = (0xFFFF) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT = (0x0000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC = (0x0001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC = (0x0002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS = (0x0003) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS = (0x0004) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC = (0x0005) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC = (0x0006) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE = (0x0007) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE = (0x0008) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT = (0x0009) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT = (0x000A) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE = (0x000B) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE = (0x000C) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER = (0x0100) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER = (0x0101) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET = (0x0102) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET = (0x0103) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD = (0x0104) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD = (0x0105) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET = (0x0106) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET = (0x0107) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT = (0x0108) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST = (0x0109) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST = (0x010A) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE = (0x010B) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE = (0x010C) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO = (0x010D) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS = (0x010E) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER = (0x0200) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA = (0x0201) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE = (0x0202) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG = (0x0203) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL = (0x0204) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN = (0x0205) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE = (0x0206) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS = (0x0210) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP = (0x0220) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA = (0x0221) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE = (0x0222) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE = (0x0240) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP = (0x0241) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN = (0x0242) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX = (0x0243) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION = (0x0244) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT = (0x0245) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE = (0x0250) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE = (0x0251) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA = (0x0252) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA = (0x0253) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK = (0x0320) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT = (0x0321) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID = (0xFFFF) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM = (0x0000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU = lambda i: (0x0100+((i)%0x100)) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU = lambda i: (0x0200+((i)%0x100)) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID = (0x80000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE = (0xFFFFFFFF) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS = (0x00000004) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC = (0x00000008) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC = (0x00000010) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB = (0x00000020) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS = (0x00000040) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING = (0x00000002) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT = (0x00000003) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 = (0x00000004) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 = (0x00000005) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM = (0x00000006) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM = (0x00000007) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF = (0x00000000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL = (0x141) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX = (16) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID = (0x41) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL = (0x142) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID = (0x42) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION = (0x00010000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT = (0x00000002) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT = (0x00000002) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE = (0x00000003) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT = (0x00000003) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA = (0x00000004) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA = (0x00000005) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA = (0x00000006) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA = (0x00000007) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA = (0x00000008) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA = (0x00000009) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000A) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000B) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000C) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000D) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS = (0x00000016) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS = (0x00000017) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM = (0x00000018) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM = (0x00000019) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR = (0x0000001A) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI = (0x0000001B) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ = (0x00000002) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO = (0x0000001C) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD = (0x00000026) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD = (0x00000027) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR = (0x00000028) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR = (0x00000029) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES = (0x0000002A) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES = (0x0000002B) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS = (0x0000002C) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS = (0x0000002D) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE = (0x0000002E) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE = (0x0000002F) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS = (0x00000044) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 = (0x00000001) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS = (0x00000045) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT = (0x00000046) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ = (0) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT = (0x00000047) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ = (0) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM = (0x00000048) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX = (0) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK = (1) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM = (0x00000049) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX = (0) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX = (2) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX = (7, 0) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF = (0) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED = (1) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET = (2) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID = (0xFF) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK = (15, 8) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID = (0) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF = (0) # type: ignore
|
|
NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON = (1) # type: ignore
|
|
PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK = 32 # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS = (0x146) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x46) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS = (0x147) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x47) # type: ignore
|
|
PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE = 288 # type: ignore
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID = (0x43) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI = (0x143) # type: ignore
|
|
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR = (0x00008000) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA = (0x144) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE = 64 # type: ignore
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID = (0x44) # type: ignore
|
|
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA = (0x145) # type: ignore
|
|
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID = (0x45) # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE = (0x3d02) # type: ignore
|
|
NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH = (0x00000001) # type: ignore
|
|
NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE = (0x00000002) # type: ignore
|
|
NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE = (0x00000003) # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR = (0x3d04) # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD = (0x3d05) # type: ignore
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD = (0, 0) # type: ignore
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE = (0x00000000) # type: ignore
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE = (0x00000001) # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD = (0x3d06) # type: ignore
|
|
NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV0000_CTRL_CMD_OS_GET_GPU_INFO = (0x3d07) # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO = (0x3d08) # type: ignore
|
|
NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE = 64 # type: ignore
|
|
NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST = (0x3d09) # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD = (0x3d0a) # type: ignore
|
|
NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE = NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE # type: ignore
|
|
NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID = (0xA) # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD = (0x3d0b) # type: ignore
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS = 512 # type: ignore
|
|
NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID = (0xB) # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD = (0x3d0c) # type: ignore
|
|
NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS = 128 # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE = 0 # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM = 1 # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM = 2 # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC = 3 # type: ignore
|
|
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC = 4 # type: ignore
|
|
NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID = (0xC) # type: ignore
|
|
NV0000_BUSDEVICE_DOMAIN = (31, 16) # type: ignore
|
|
NV0000_BUSDEVICE_BUS = (15, 8) # type: ignore
|
|
NV0000_BUSDEVICE_DEVICE = (7, 0) # type: ignore
|
|
NV0000_CTRL_CMD_VGPU_CREATE_DEVICE = (0xc02) # type: ignore
|
|
NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0000_CTRL_CMD_VGPU_GET_INSTANCES = (0xc03) # type: ignore
|
|
NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV0000_CTRL_CMD_VGPU_DELETE_DEVICE = (0xc04) # type: ignore
|
|
NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS = (0xc05) # type: ignore
|
|
NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV0000_CTRL_CMD_GPU_UPDATE_SYSFS_NODE = (0x206) # type: ignore
|
|
NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV0080_CTRL_RESERVED = (0x00) # type: ignore
|
|
NV0080_CTRL_BIF = (0x01) # type: ignore
|
|
NV0080_CTRL_GPU = (0x02) # type: ignore
|
|
NV0080_CTRL_CLK = (0x10) # type: ignore
|
|
NV0080_CTRL_GR = (0x11) # type: ignore
|
|
NV0080_CTRL_CIPHER = (0x12) # type: ignore
|
|
NV0080_CTRL_FB = (0x13) # type: ignore
|
|
NV0080_CTRL_HOST = (0x14) # type: ignore
|
|
NV0080_CTRL_VIDEO = (0x15) # type: ignore
|
|
NV0080_CTRL_FIFO = (0x17) # type: ignore
|
|
NV0080_CTRL_DMA = (0x18) # type: ignore
|
|
NV0080_CTRL_PERF = (0x19) # type: ignore
|
|
NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED = (0x99) # type: ignore
|
|
NV0080_CTRL_MSENC = (0x1B) # type: ignore
|
|
NV0080_CTRL_BSP = (0x1C) # type: ignore
|
|
NV0080_CTRL_RC = (0x1D) # type: ignore
|
|
NV0080_CTRL_OS_UNIX = (0x1E) # type: ignore
|
|
NV0080_CTRL_NVJPG = (0x1F) # type: ignore
|
|
NV0080_CTRL_INTERNAL = (0x20) # type: ignore
|
|
NV0080_CTRL_NVLINK = (0x21) # type: ignore
|
|
NV0080_CTRL_CMD_NULL = (0x800000) # type: ignore
|
|
NV0080_CTRL_CMD_BIF_RESET = (0x800102) # type: ignore
|
|
NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE = (4, 0) # type: ignore
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET = 0x1 # type: ignore
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR = 0x2 # type: ignore
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL = 0x3 # type: ignore
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE = 0x4 # type: ignore
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE = 0x5 # type: ignore
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX = 0x6 # type: ignore
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER = 0x7 # type: ignore
|
|
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE = 0x8 # type: ignore
|
|
NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE = (0x800104) # type: ignore
|
|
NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S = (0, 0) # type: ignore
|
|
NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED = 0x000000001 # type: ignore
|
|
NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED = 0x000000000 # type: ignore
|
|
NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1 = (1, 1) # type: ignore
|
|
NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED = 0x000000001 # type: ignore
|
|
NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED = 0x000000000 # type: ignore
|
|
NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE = (0x800105) # type: ignore
|
|
NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK = (0x800106) # type: ignore
|
|
NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV0080_CTRL_CMD_BSP_GET_CAPS = (0x801c01) # type: ignore
|
|
NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0080_CTRL_BSP_CAPS_TBL_SIZE = 8 # type: ignore
|
|
NV0080_CTRL_CMD_BSP_GET_CAPS_V2 = (0x801c02) # type: ignore
|
|
NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID = (0, 0) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED = (2, 1) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED = (0x00000002) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE = (6, 3) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY = (0x00000002) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY = (0x00000003) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS = (10, 7) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1 = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2 = (0x00000002) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4 = (0x00000004) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED = (12, 11) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED = (0x00000002) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS = (14, 13) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY = (0x00000002) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED = (0x00000003) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY = (15, 15) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC = (16, 16) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING = (17, 17) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED = (18, 18) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_CMD_DMA_GET_PTE_INFO = (0x801801) # type: ignore
|
|
NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS = 5 # type: ignore
|
|
NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0080_CTRL_CMD_DMA_SET_PTE_INFO = (0x80180a) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS = 5 # type: ignore
|
|
NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID = (0xA) # type: ignore
|
|
NV0080_CTRL_CMD_DMA_FILL_PTE_MEM = (0x801802) # type: ignore
|
|
NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0080_CTRL_CMD_DMA_FLUSH = (0x801805) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2 = (0, 0) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG = (1, 1) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB = (2, 2) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE = (4, 3) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM = (0x00000002) # type: ignore
|
|
NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS = (0x801806) # type: ignore
|
|
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS = (16) # type: ignore
|
|
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO = 0x1 # type: ignore
|
|
NV0080_CTRL_CMD_DMA_GET_PDE_INFO = (0x801809) # type: ignore
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY = (0x00000002) # type: ignore
|
|
NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS = 5 # type: ignore
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY = (0x00000002) # type: ignore
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL = 1 # type: ignore
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF = 2 # type: ignore
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER = 3 # type: ignore
|
|
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH = 4 # type: ignore
|
|
NV0080_CTRL_CMD_DMA_INVALIDATE_TLB = (0x80180c) # type: ignore
|
|
NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID = (0xC) # type: ignore
|
|
NV0080_CTRL_DMA_INVALIDATE_TLB_ALL = (0, 0) # type: ignore
|
|
NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_CMD_DMA_GET_CAPS = (0x80180d) # type: ignore
|
|
NV0080_CTRL_DMA_CAPS_TBL_SIZE = 8 # type: ignore
|
|
NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID = (0xD) # type: ignore
|
|
NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE = (0x80180e) # type: ignore
|
|
NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID = (0xE) # type: ignore
|
|
NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX = (0xFFFFFFFFFFFFFFFF) # type: ignore
|
|
NV0080_CTRL_CMD_DMA_UPDATE_PDE_2 = (0x80180f) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY = (0x00000002) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY = (0x00000003) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL = 0 # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG = 1 # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE = 2 # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID = (0xF) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE = (0, 0) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE = (1, 1) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE = (3, 2) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER = (0x00000002) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH = (0x00000003) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE = (4, 4) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE = (0x801810) # type: ignore
|
|
NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID = (0x10) # type: ignore
|
|
NV0080_CTRL_DMA_SET_DEFAULT_VASPACE = (0x801812) # type: ignore
|
|
NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID = (0x12) # type: ignore
|
|
NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY = (0x801813) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID = (0x13) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE = (1, 0) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH = (0x00000002) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES = (2, 2) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS = (3, 3) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY = (4, 4) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE = (5, 5) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY = (0x801814) # type: ignore
|
|
NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID = (0x14) # type: ignore
|
|
NV0080_CTRL_CMD_FB_GET_CAPS = (0x801301) # type: ignore
|
|
NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0080_CTRL_FB_CAPS_TBL_SIZE = 3 # type: ignore
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO = (0x801306) # type: ignore
|
|
NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN = 0 # type: ignore
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM = 1 # type: ignore
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM = 2 # type: ignore
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY = 0 # type: ignore
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1 = 1 # type: ignore
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4 = 2 # type: ignore
|
|
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE = 3 # type: ignore
|
|
NV0080_CTRL_CMD_FB_GET_CAPS_V2 = (0x801307) # type: ignore
|
|
NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY = (0x801308) # type: ignore
|
|
NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_GET_CAPS = (0x801701) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0080_CTRL_FIFO_CAPS_TBL_SIZE = 2 # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES = (0x801707) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID = (4, 0) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS = (0x00000000) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD = (0x00000001) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO = (0x00000002) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG = (0x00000003) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE = (0x00000004) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY = (0x00000005) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION = (0x00000006) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS = (0x00000007) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL = (0x00000008) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM = (0x00000009) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT = (0x0000000a) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT = (0x0000000b) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL = (0x0000000c) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL = (0x0000000d) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB = (0x0000000e) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV = (0x0000000f) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH = (0x00000010) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB = (0x00000011) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL = (0x00000012) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB = (0x00000013) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL = (0x00000014) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL = (0x00000015) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK = (0x00000016) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT = (0x00000017) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP = (0x00000018) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SETUP = (0x00000019) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT = (0x0000001a) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS = (0x801709) # type: ignore
|
|
NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS = (8) # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE = (0x80170b) # type: ignore
|
|
NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR = (12) # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST = (0x80170c) # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST = (0x80170d) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID = (0xD) # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE = (0x80170e) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0xE) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL = (0xffffffff) # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES = (0x80170f) # type: ignore
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID = (0xF) # type: ignore
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS = (0x00000000) # type: ignore
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS = (0x00000001) # type: ignore
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE = (0x00000002) # type: ignore
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE = (0x00000003) # type: ignore
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET = (0x00000004) # type: ignore
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT = (0x00000005) # type: ignore
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP = (0x00000007) # type: ignore
|
|
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT = (0x00000008) # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_STOP_RUNLIST = (0x801711) # type: ignore
|
|
NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID = (0x11) # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_START_RUNLIST = (0x801712) # type: ignore
|
|
NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID = (0x12) # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 = (0x801713) # type: ignore
|
|
NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x13) # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS = (0x801714) # type: ignore
|
|
NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS = 4096 # type: ignore
|
|
NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID = (0x14) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_GET_CLASSLIST = (0x800201) # type: ignore
|
|
NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES = (0x800280) # type: ignore
|
|
NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID = (0x80) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER = (0x800281) # type: ignore
|
|
NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID = (0x81) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER = (0x800282) # type: ignore
|
|
NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID = (0x82) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER = (0x800283) # type: ignore
|
|
NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID = (0x83) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_SET_VIDLINK = (0x800285) # type: ignore
|
|
NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID = (0x85) # type: ignore
|
|
NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS = 0 # type: ignore
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN = 1 # type: ignore
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP = 2 # type: ignore
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON = 0 # type: ignore
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN = 1 # type: ignore
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED = 2 # type: ignore
|
|
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP = 3 # type: ignore
|
|
NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE = (0x800287) # type: ignore
|
|
NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED = (0x00000000) # type: ignore
|
|
NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED = (0x00000001) # type: ignore
|
|
NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID = (0x87) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE = (0x800288) # type: ignore
|
|
NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID = (0x88) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE = (0x800289) # type: ignore
|
|
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE = (0x00000000) # type: ignore
|
|
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS = (0x00000001) # type: ignore
|
|
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX = (0x00000002) # type: ignore
|
|
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST = (0x00000003) # type: ignore
|
|
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU = NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST # type: ignore
|
|
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA = (0x00000004) # type: ignore
|
|
NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID = (0x89) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE = (0x80028c) # type: ignore
|
|
NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID = (0x8C) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE = (0x80028d) # type: ignore
|
|
NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID = (0x8D) # type: ignore
|
|
NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT = 0 # type: ignore
|
|
NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE = 1 # type: ignore
|
|
NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE = 2 # type: ignore
|
|
NV0080_CTRL_CMD_GPU_GET_VGX_CAPS = (0x80028e) # type: ignore
|
|
NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID = (0x8E) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS = (0x800291) # type: ignore
|
|
NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID = (0x91) # type: ignore
|
|
NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE = 100 # type: ignore
|
|
NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 = (0x800292) # type: ignore
|
|
NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID = (0x92) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE = (0x800293) # type: ignore
|
|
NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID = (0x93) # type: ignore
|
|
NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO = NVBIT(0) # type: ignore
|
|
NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS = NVBIT(1) # type: ignore
|
|
NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN = NVBIT(2) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS = (0x800294) # type: ignore
|
|
NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID = (0x94) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M = (1 << 6) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M = (1 << 7) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M = (1 << 8) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M = (1 << 9) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G = (1 << 10) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G = (1 << 11) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G = (1 << 12) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G = (1 << 13) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G = (1 << 14) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G = (1 << 15) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G = (1 << 16) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G = (1 << 17) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G = (1 << 18) # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN = NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX = NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G # type: ignore
|
|
NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID = 0x0 # type: ignore
|
|
NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE = (0x800296) # type: ignore
|
|
NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID = (0x96) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE = (0x800297) # type: ignore
|
|
NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0x97) # type: ignore
|
|
NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE = (0x800298) # type: ignore
|
|
NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0x98) # type: ignore
|
|
NV0080_CTRL_CMD_GR_GET_CAPS = (0x801102) # type: ignore
|
|
NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0080_CTRL_GR_CAPS_TBL_SIZE = 23 # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS = (0x00000000) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 = (0x00000001) # type: ignore
|
|
NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK = (0x00000002) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT = (0x00000003) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT = (0x00000004) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE = (0x00000005) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT = (0x00000006) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT = (0x00000007) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR = (0x00000008) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT = (0x00000009) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT = (0x0000000A) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT = (0x0000000B) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_SM_VERSION = (0x0000000C) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM = (0x0000000D) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP = (0x0000000E) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES = (0x0000000F) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES = (0x00000010) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY = (0x00000011) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY = (0x00000012) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM = (0x00000013) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS = (0x00000014) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS = (0x00000015) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS = (0x00000016) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC = (0x00000017) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS = (0x00000018) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS = (0x00000019) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED = (0x0000001A) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS = (0x0000001B) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC = (0x0000001C) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT = (0x0000001D) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES = (0x0000001E) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS = (0x0000001F) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC = (0x00000020) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS = (0x00000021) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT = (0x00000022) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT = (0x00000023) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS = (0x00000024) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS = (0x00000025) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES = (0x00000026) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC = (0x00000027) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP = (0x00000028) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC = (0x00000029) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC = (0x0000002A) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP = (0x0000002B) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT = (0x0000002C) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT = (0x0000002D) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT = (0x0000002E) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC = (0x00000032) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES = (0x00000033) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_DUMMY = (0x00000033) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES = (0x00000034) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES = (0x00000035) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS = (0x00000036) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG = (0x00000037) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET = (0x00000038) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET = (0x00000039) # type: ignore
|
|
NV0080_CTRL_GR_INFO_INDEX_MAX = (0x00000039) # type: ignore
|
|
NV0080_CTRL_GR_INFO_MAX_SIZE = (0x3a) # type: ignore
|
|
NV0080_CTRL_CMD_GR_GET_INFO = (0x801104) # type: ignore
|
|
NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE = (0x801107) # type: ignore
|
|
NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = (0x801108) # type: ignore
|
|
NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV0080_CTRL_CMD_GR_GET_CAPS_V2 = (0x801109) # type: ignore
|
|
NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV0080_CTRL_CMD_GR_GET_INFO_V2 = (0x801110) # type: ignore
|
|
NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x10) # type: ignore
|
|
NV0080_CTRL_CMD_HOST_GET_CAPS = (0x801401) # type: ignore
|
|
NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0080_CTRL_HOST_CAPS_TBL_SIZE = 3 # type: ignore
|
|
NV0080_CTRL_CMD_HOST_GET_CAPS_V2 = (0x801402) # type: ignore
|
|
NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE = (0x802002) # type: ignore
|
|
NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE = (0x802003) # type: ignore
|
|
NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL = (0x802009) # type: ignore
|
|
NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE = (0x802004) # type: ignore
|
|
NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL = (0x802007) # type: ignore
|
|
NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS = (0x802008) # type: ignore
|
|
NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS = 200 # type: ignore
|
|
NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID = (0x08) # type: ignore
|
|
NV0080_CTRL_CMD_MSENC_GET_CAPS = (0x801b01) # type: ignore
|
|
NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0080_CTRL_MSENC_CAPS_TBL_SIZE = 4 # type: ignore
|
|
NV0080_CTRL_CMD_MSENC_GET_CAPS_V2 = (0x801b02) # type: ignore
|
|
NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0080_CTRL_NVJPG_CAPS_TBL_SIZE = 9 # type: ignore
|
|
NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 = (0x801f02) # type: ignore
|
|
NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL = (0x801909) # type: ignore
|
|
NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH = (0x801e01) # type: ignore
|
|
NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE = (0x00000001) # type: ignore
|
|
NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE = (0x00000002) # type: ignore
|
|
NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED = (0x00000003) # type: ignore
|
|
NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO = (0x801e02) # type: ignore
|
|
NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_RESERVED = (0x00) # type: ignore
|
|
NV2080_CTRL_GPU = (0x01) # type: ignore
|
|
NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED = (0x81) # type: ignore
|
|
NV2080_CTRL_FUSE = (0x02) # type: ignore
|
|
NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED = (0x82) # type: ignore
|
|
NV2080_CTRL_EVENT = (0x03) # type: ignore
|
|
NV2080_CTRL_TIMER = (0x04) # type: ignore
|
|
NV2080_CTRL_THERMAL = (0x05) # type: ignore
|
|
NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED = (0xc5) # type: ignore
|
|
NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED = (0x85) # type: ignore
|
|
NV2080_CTRL_I2C = (0x06) # type: ignore
|
|
NV2080_CTRL_EXTI2C = (0x07) # type: ignore
|
|
NV2080_CTRL_BIOS = (0x08) # type: ignore
|
|
NV2080_CTRL_CIPHER = (0x09) # type: ignore
|
|
NV2080_CTRL_INTERNAL = (0x0A) # type: ignore
|
|
NV2080_CTRL_CLK_LEGACY_PRIVILEGED = (0xd0) # type: ignore
|
|
NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED = (0x90) # type: ignore
|
|
NV2080_CTRL_CLK = (0x10) # type: ignore
|
|
NV2080_CTRL_FIFO = (0x11) # type: ignore
|
|
NV2080_CTRL_GR = (0x12) # type: ignore
|
|
NV2080_CTRL_FB = (0x13) # type: ignore
|
|
NV2080_CTRL_MC = (0x17) # type: ignore
|
|
NV2080_CTRL_BUS = (0x18) # type: ignore
|
|
NV2080_CTRL_PERF_LEGACY_PRIVILEGED = (0xe0) # type: ignore
|
|
NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED = (0xa0) # type: ignore
|
|
NV2080_CTRL_PERF = (0x20) # type: ignore
|
|
NV2080_CTRL_NVIF = (0x21) # type: ignore
|
|
NV2080_CTRL_RC = (0x22) # type: ignore
|
|
NV2080_CTRL_GPIO = (0x23) # type: ignore
|
|
NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED = (0xa3) # type: ignore
|
|
NV2080_CTRL_NVD = (0x24) # type: ignore
|
|
NV2080_CTRL_DMA = (0x25) # type: ignore
|
|
NV2080_CTRL_PMGR = (0x26) # type: ignore
|
|
NV2080_CTRL_PMGR_LEGACY_PRIVILEGED = (0xe6) # type: ignore
|
|
NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED = (0xa6) # type: ignore
|
|
NV2080_CTRL_POWER = (0x27) # type: ignore
|
|
NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED = (0xa7) # type: ignore
|
|
NV2080_CTRL_LPWR = (0x28) # type: ignore
|
|
NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED = (0xa8) # type: ignore
|
|
NV2080_CTRL_LPWR_LEGACY_PRIVILEGED = (0xe8) # type: ignore
|
|
NV2080_CTRL_ACR = (0x29) # type: ignore
|
|
NV2080_CTRL_CE = (0x2A) # type: ignore
|
|
NV2080_CTRL_SPI = (0x2B) # type: ignore
|
|
NV2080_CTRL_NVLINK = (0x30) # type: ignore
|
|
NV2080_CTRL_FLCN = (0x31) # type: ignore
|
|
NV2080_CTRL_VOLT = (0x32) # type: ignore
|
|
NV2080_CTRL_VOLT_LEGACY_PRIVILEGED = (0xf2) # type: ignore
|
|
NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED = (0xb2) # type: ignore
|
|
NV2080_CTRL_FAS = (0x33) # type: ignore
|
|
NV2080_CTRL_ECC = (0x34) # type: ignore
|
|
NV2080_CTRL_ECC_NON_PRIVILEGED = (0xb4) # type: ignore
|
|
NV2080_CTRL_FLA = (0x35) # type: ignore
|
|
NV2080_CTRL_GSP = (0x36) # type: ignore
|
|
NV2080_CTRL_NNE = (0x37) # type: ignore
|
|
NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED = (0xb7) # type: ignore
|
|
NV2080_CTRL_GRMGR = (0x38) # type: ignore
|
|
NV2080_CTRL_UCODE_FUZZER = (0x39) # type: ignore
|
|
NV2080_CTRL_DMABUF = (0x3A) # type: ignore
|
|
NV2080_CTRL_BIF = (0x3B) # type: ignore
|
|
NV2080_CTRL_OS_WINDOWS = (0x3F) # type: ignore
|
|
NV2080_CTRL_OS_MACOS = (0x3E) # type: ignore
|
|
NV2080_CTRL_OS_UNIX = (0x3D) # type: ignore
|
|
NV2080_CTRL_CMD_NULL = (0x20800000) # type: ignore
|
|
NV2080_CTRL_BIOS_INFO_MAX_SIZE = (0x0000000F) # type: ignore
|
|
NV2080_CTRL_BIOS_INFO_INDEX_REVISION = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BIOS_GET_INFO = (0x20800802) # type: ignore
|
|
NV2080_CTRL_CMD_BIOS_GET_INFO_V2 = (0x20800810) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x10) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH = (0x00000100) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_ROOT = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_RM = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_CPL = (0x00000004) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_D3D = (0x00000005) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_OGL = (0x00000006) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_PMU = (0x00000007) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_MODE = (0x00000008) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_NUM_MODULES = (0x00000009) # type: ignore
|
|
NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN = (0x80000000) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_NBSI_SUCCESS = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH = (0xFFFFFFFA) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS = (0xFFFFFFFB) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE = (0xFFFFFFFC) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE = (0xFFFFFFFD) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE = (0xFFFFFFFE) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND = (0xFFFFFFFF) # type: ignore
|
|
NV2080_CTRL_CMD_BIOS_GET_NBSI = (0x20800803) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_BIOS_GET_NBSI_V2 = (0x2080080e) # type: ignore
|
|
NV2080_BIOS_GET_NBSI_MAX_RET_SIZE = (0x100) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID = (0xE) # type: ignore
|
|
NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ = (0x20800806) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
GLOB_TYPE_GET_NBSI_DIR = 0xfffe # type: ignore
|
|
GLOB_TYPE_APITEST = 0xffff # type: ignore
|
|
GLOB_TYPE_GET_NBSI_ACPI_RAW = 0xfffd # type: ignore
|
|
NV2080_CTRL_CMD_BIOS_GET_SKU_INFO = (0x20800808) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV2080_CTRL_CMD_BIOS_GET_POST_TIME = (0x20800809) # type: ignore
|
|
NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT = (0x2080080b) # type: ignore
|
|
NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID = (0xB) # type: ignore
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE = (1, 0) # type: ignore
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING = (2, 2) # type: ignore
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT = (3, 3) # type: ignore
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCI_INFO = (0x20801801) # type: ignore
|
|
NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_TYPE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_INTLINE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_CAPS = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS = (0x00000004) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS = (0x00000005) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS = (0x00000006) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS = (0x00000007) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS = (0x00000008) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS = (0x00000009) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS = (0x0000000A) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS = (0x0000000B) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS = (0x0000000C) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE = (0x0000000D) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS = (0x0000000E) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER = (0x0000000F) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER = (0x00000010) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS = (0x00000011) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS = (0x00000012) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE = (0x00000013) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO = (0x00000014) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER = (0x00000015) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS = (0x00000016) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS = (0x00000017) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS = (0x00000018) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT = (0x00000019) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT = (0x0000001A) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM = (0x0000001B) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS = (0x0000001C) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS = (0x0000001D) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED = (0x0000001E) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS = (0x0000001F) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR = (0x00000020) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR = (0x00000021) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR = (0x00000022) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR = (0x00000023) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS = (0x00000024) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS = (0x00000025) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS = (0x00000026) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS = (0x00000027) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR = (0x00000028) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR = (0x00000029) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR = (0x0000002A) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR = (0x0000002B) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER = (0x0000002C) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO = (0x0000002D) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE = (0x0000002E) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO = (0x0000002F) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO = (0x00000030) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO = (0x00000031) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI = (0x00000032) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE = (0x00000033) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_MAX = NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE # type: ignore
|
|
NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE = (0x00000034) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_TYPE_PCI = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_TYPE_FPCI = (0x00000004) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_TYPE_AXI = (0x00000008) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED = (3, 0) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS = (0x00000004) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS = (0x00000005) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS = (0x00000006) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_WIDTH = (9, 4) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM = (11, 10) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN = (15, 12) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6 = (0x00000005) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL = (19, 16) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6 = (0x00000005) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN = (23, 20) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6 = (0x00000005) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES = (24, 24) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM = (1, 0) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED = (19, 16) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS = (0x00000004) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS = (0x00000005) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS = (0x00000006) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH = (25, 20) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8 = (0x00000008) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12 = (0x0000000C) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16 = (0x00000010) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32 = (0x00000020) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA = (0, 0) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART = (2, 2) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA = (0, 0) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART = (2, 2) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE = (3, 3) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH = (0, 0) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED = (1, 1) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR = (0x00000004) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST = (0x00000008) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY = (0x00000010) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP = (0, 0) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL = (1, 1) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP = (0x00000004) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR = (0x00000008) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT = (0x00000010) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT = (0x00000020) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL = (0x00000040) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW = (0x00000080) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP = (0x00000100) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR = (0x00000200) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ = (0x00000400) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR = (0x00010000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP = (0x00020000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP = (0x00040000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER = (0x00080000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT = (0x00100000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL = (0x00200000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE = (0, 0) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED = (1, 1) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE = (2, 2) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED = (3, 3) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04 = (4, 4) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID = (0, 0) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM = (2, 1) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_MSI_STATUS = (0, 0) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED = (0, 0) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED = (1, 1) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED = (2, 2) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED = (3, 3) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED = (4, 4) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_RESERVED = (7, 5) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PORT_RESTORE_TIME = (15, 8) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_SCALE = (17, 16) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_VALUE = (23, 19) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED = (0, 0) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED = (1, 1) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED = (2, 2) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED = (3, 3) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_COMMON_MODE_RESTORE_TIME = (15, 8) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_VALUE = (25, 16) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_SCALE = (31, 29) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_SCALE = (1, 0) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_VALUE = (7, 3) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C = (0x00000002) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_INFO = (0x20801802) # type: ignore
|
|
NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_INFO_V2 = (0x20801823) # type: ignore
|
|
NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x23) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO = (0x20801803) # type: ignore
|
|
NV2080_CTRL_BUS_MAX_PCI_BARS = (8) # type: ignore
|
|
NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH = (0x20801804) # type: ignore
|
|
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING = (0x00000004) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED = (0x20801805) # type: ignore
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS = (0x00000002) # type: ignore
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS = (0x00000003) # type: ignore
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS = (0x00000004) # type: ignore
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS = (0x00000005) # type: ignore
|
|
NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS = (0x00000006) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_MAP_BAR2 = (0x20801809) # type: ignore
|
|
NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_UNMAP_BAR2 = (0x2080180a) # type: ignore
|
|
NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID = (0xA) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_VERIFY_BAR2 = (0x2080180b) # type: ignore
|
|
NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID = (0xB) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE = (0x20801812) # type: ignore
|
|
NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID = (0x12) # type: ignore
|
|
NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE = (0x00000002) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS = (0x20801813) # type: ignore
|
|
NV2080_CTRL_PEX_MAX_COUNTER_TYPES = 31 # type: ignore
|
|
NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x13) # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_TYPE = 0x00000000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS = 0x00000001 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT = 0x00000002 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT = 0x00000004 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT = 0x00000008 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT = 0x00000010 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT = 0x00000020 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT = 0x00000040 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT = 0x00000080 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT = 0x00000100 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT = 0x00000200 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT = 0x00000400 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS = 0x00000800 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT = 0x00001000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT = 0x00002000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT = 0x00004000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT = 0x00008000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT = 0x00010000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT = 0x00020000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT = 0x00040000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT = 0x00080000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT = 0x00100000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT = 0x00200000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT = 0x00400000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT = 0x00800000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT = 0x01000000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT = 0x02000000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT = 0x04000000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT = 0x08000000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT = 0x10000000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT = 0x20000000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT = 0x40000000 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS = (0x20801814) # type: ignore
|
|
NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x14) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS = (0x20801815) # type: ignore
|
|
NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x15) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS = (0x20801816) # type: ignore
|
|
NV2080_CTRL_PEX_MAX_LANES = 16 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID = (0x16) # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE = 0x00000000 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR = 0x00000001 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR = 0x00000002 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR = 0x00000004 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR = 0x00000008 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR = 0x00000010 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW = 0x00000020 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW = 0x00000040 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR = 0x00000080 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR = 0x00000100 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY = (0x20801817) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID = (0x17) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY = (0x20801818) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID = (0x18) # type: ignore
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES = 0x00000001 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES = 0x00000002 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0 = 0x00000004 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0 = 0x00000008 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S = 0x00000010 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S = 0x00000020 # type: ignore
|
|
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S = 0x00000040 # type: ignore
|
|
NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES = 7 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS = (0x20801819) # type: ignore
|
|
NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID = (0x19) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS = (0x20801820) # type: ignore
|
|
NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID = (0x20) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_BFD = (0x20801821) # type: ignore
|
|
NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID = (0x21) # type: ignore
|
|
NV2080_CTRL_ASPM_DISABLE_FLAGS_L1_MASK_REGKEY_OVERRIDE = 0x00000000 # type: ignore
|
|
NV2080_CTRL_ASPM_DISABLE_FLAGS_OS_RM_MAKES_POLICY_DECISIONS = 0x00000001 # type: ignore
|
|
NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_BEHIND_BRIDGE = 0x00000002 # type: ignore
|
|
NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_UNSUPPORTED = 0x00000003 # type: ignore
|
|
NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED = 0x00000004 # type: ignore
|
|
NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY = 0x00000005 # type: ignore
|
|
NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_DISABLED = 0x00000006 # type: ignore
|
|
NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY = 0x00000007 # type: ignore
|
|
NV2080_CTRL_ASPM_DISABLE_FLAGS_BIF_ENABLE_ASPM_DT_L1 = 0x00000008 # type: ignore
|
|
NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS = 9 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS = (0x20801822) # type: ignore
|
|
NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID = (0x22) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS = (0x20801824) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID = (0x24) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK = (0x20801825) # type: ignore
|
|
NV2080_CTRL_BUS_MAX_NUM_GPUS = 32 # type: ignore
|
|
NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID = (0x25) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS = (0x20801826) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID = (0x26) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE = (0x20801827) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID = (0x27) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_EOM_STATUS = (0x20801828) # type: ignore
|
|
NV2080_CTRL_BUS_MAX_NUM_LANES = 32 # type: ignore
|
|
NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID = (0x28) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS = (0x20801829) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID = (0x29) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM = 0x0 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU = 0x1 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P = 0x2 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32 = (0, 0) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64 = (1, 1) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32 = (2, 2) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64 = (3, 3) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32 = (4, 4) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64 = (5, 5) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128 = (6, 6) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS = (0x2080182a) # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD = 0 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN = 1 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX = 2 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC = 3 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC = 4 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND = 5 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR = 6 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR = 7 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH = 8 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS = 9 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD = 10 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN = 11 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX = 12 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT = 13 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID = (0x2A) # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR = (0, 0) # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES = 1 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO = 0 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR = (1, 1) # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES = 1 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO = 0 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION = (2, 2) # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES = 1 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO = 0 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32 = (3, 3) # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES = 1 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO = 0 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64 = (4, 4) # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES = 1 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO = 0 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128 = (5, 5) # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES = 1 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO = 0 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED = (6, 6) # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES = 1 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO = 0 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED = (7, 7) # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES = 1 # type: ignore
|
|
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO = 0 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_INFO = (0x2080182b) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID = (0x2B) # type: ignore
|
|
NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU = 1 # type: ignore
|
|
NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU = 2 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS = (0x2080182c) # type: ignore
|
|
NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID = (0x2C) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING = (0x2080182e) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID = 0 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK = 1 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE = 2 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 = 3 # type: ignore
|
|
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C = 4 # type: ignore
|
|
NV2080_SET_P2P_MAPPING_UUID_LEN = 16 # type: ignore
|
|
NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID = (0x2E) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING = (0x2080182f) # type: ignore
|
|
NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID = (0x2F) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS = (0x20801830) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID = (0x30) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32 = (0, 0) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64 = (1, 1) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32 = (2, 2) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64 = (3, 3) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32 = (4, 4) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64 = (5, 5) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128 = (6, 6) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_CE_GET_CAPS = (0x20802a01) # type: ignore
|
|
NV2080_CTRL_CE_CAPS_TBL_SIZE = 2 # type: ignore
|
|
NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_CMD_CE_GET_CAPS_V2 = (0x20802a03) # type: ignore
|
|
NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK = (0x20802a02) # type: ignore
|
|
NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG = (0x20802a04) # type: ignore
|
|
NV2080_CTRL_MAX_PCES = 32 # type: ignore
|
|
NV2080_CTRL_MAX_GRCES = 4 # type: ignore
|
|
NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS = (0x20802a05) # type: ignore
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE = 0xf # type: ignore
|
|
NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB = (0x20802a06) # type: ignore
|
|
NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS = (0x20802a07) # type: ignore
|
|
NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE = (0x20802a08) # type: ignore
|
|
NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK = (0x20802a09) # type: ignore
|
|
NV2080_CTRL_CE_MAX_HSHUBS = 32 # type: ignore
|
|
NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV2080_CTRL_CMD_CE_GET_ALL_CAPS = (0x20802a0a) # type: ignore
|
|
NV2080_CTRL_MAX_CES = 64 # type: ignore
|
|
NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID = (0xa) # type: ignore
|
|
NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS = (0x20802a0b) # type: ignore
|
|
NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID = (0xb) # type: ignore
|
|
NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO = (0x20802a0c) # type: ignore
|
|
NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID = (0xc) # type: ignore
|
|
NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS_V2 = (0x20802a0d) # type: ignore
|
|
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID = (0xd) # type: ignore
|
|
NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_V2 = (0x20802a0e) # type: ignore
|
|
NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID = (0xe) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE = (0x20802a0f) # type: ignore
|
|
NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID = (0xf) # type: ignore
|
|
NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK = (0x20802a11) # type: ignore
|
|
NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID = (0x11) # type: ignore
|
|
NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED = (0x20802a12) # type: ignore
|
|
NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID = (0x12) # type: ignore
|
|
NV2080_CTRL_CMD_DMA_INVALIDATE_TLB = (0x20802502) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS = (0, 0) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO = (1, 1) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY = (2, 2) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE = (3, 3) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB = (4, 4) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV = (5, 5) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG = (6, 6) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD = (7, 7) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION = (8, 8) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON = (9, 9) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS = (10, 10) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR = (11, 11) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE = (0x000000000) # type: ignore
|
|
NV2080_CTRL_DMA_INFO_INDEX_MAX = NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE # type: ignore
|
|
NV2080_CTRL_CMD_DMA_GET_INFO = (0x20802503) # type: ignore
|
|
NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES = (256) # type: ignore
|
|
NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD = (0x20803a01) # type: ignore
|
|
NV2080_CTRL_DMABUF_MAX_HANDLES = 128 # type: ignore
|
|
NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT = (0x00000000) # type: ignore
|
|
NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS = (0x20803400) # type: ignore
|
|
NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID = (0x0) # type: ignore
|
|
NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS = (0x20803401) # type: ignore
|
|
NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION = (0x20800301) # type: ignore
|
|
NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT = (0x00000002) # type: ignore
|
|
NV2080_EVENT_DSTATE_XUSB_D0 = (0x00000000) # type: ignore
|
|
NV2080_EVENT_DSTATE_XUSB_D3 = (0x00000003) # type: ignore
|
|
NV2080_EVENT_DSTATE_XUSB_INVALID = (0xFFFFFFFF) # type: ignore
|
|
NV2080_EVENT_DSTATE_PPC_D0 = (0x00000000) # type: ignore
|
|
NV2080_EVENT_DSTATE_PPC_D3 = (0x00000003) # type: ignore
|
|
NV2080_EVENT_DSTATE_PPC_INVALID = (0xFFFFFFFF) # type: ignore
|
|
NV2080_CTRL_CMD_EVENT_SET_TRIGGER = (0x20800302) # type: ignore
|
|
NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES = (0x20800303) # type: ignore
|
|
NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED = 0 # type: ignore
|
|
NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING = 1 # type: ignore
|
|
NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR = 2 # type: ignore
|
|
NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY = (0x20800304) # type: ignore
|
|
NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI = (0x20800305) # type: ignore
|
|
NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION = (0x20800306) # type: ignore
|
|
NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO = (0x20800308) # type: ignore
|
|
NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF = (0x20800309) # type: ignore
|
|
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF = (0x2080030a) # type: ignore
|
|
NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0xA) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT = (0x00000003) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT = (0x00000004) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE = (0x00000005) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT = (0x00000006) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE = (0x00000007) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE = (0x00000008) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE = (0x00000009) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE = (0x0000000A) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH = (0x0000000B) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_RAM_CFG = (0x0000000C) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE = (0x0000000D) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT = (0x0000000E) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT = (0x0000000F) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB = (0x0000000F) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB = (0x0000000F) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB = (0x0000000F) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW = (0x0000000F) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB = (0x00000010) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB = (0x00000011) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB = (0x00000012) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB = (0x00000013) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK = (0x00000014) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE = (0x00000015) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE = (0x00000016) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION = (0x00000017) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN = (0x00000018) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT = (0x00000019) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_FBP_MASK = (0x0000001A) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE = (0x0000001B) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID = (0x0000001C) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE = (0x0000001D) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_HEAP_START = (0x0000001E) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE = (0x0000001F) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE = (0x00000020) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T = (0x00000021) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT = (0x00000022) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT = (0x00000023) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE = (0x00000024) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE = (0x00000025) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE = (0x00000026) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE = (0x00000027) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED = (0x00000028) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE = (0x00000029) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT = (0x0000002A) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK = (0x0000002B) # type: ignore
|
|
NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED = (0x0000002C) # type: ignore
|
|
NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED = (0x0000002D) # type: ignore
|
|
NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED = (0x0000002E) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED = (0x0000002F) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE = (0x00000030) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT = (0x00000031) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB = (0x00000032) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB = (0x00000033) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB = (0x00000034) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE = (0x00000035) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB = (0x00000036) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0 = (NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1 = (0x00000037) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0 = (NV2080_CTRL_FB_INFO_INDEX_LTC_MASK) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 = (0x00000038) # type: ignore
|
|
NV2080_CTRL_FB_INFO_MAX_LIST_SIZE = (0x00000039) # type: ignore
|
|
NV2080_CTRL_FB_INFO_INDEX_MAX = (0x38) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 = NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 = (0x00000005) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 = (0x00000006) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 = (0x00000007) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 = NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 = (0x00000008) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 = (0x00000009) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 = (0x0000000C) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 = (0x0000000D) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 = (0x0000000E) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 = (0x0000000F) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X = (0x00000010) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 = (0x00000011) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X = (0x00000012) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 = (0x00000013) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 = (0x00000014) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7 = (0x00000015) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA = (0x00000003) # type: ignore
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON = (0x00000004) # type: ignore
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA = (0x00000005) # type: ignore
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX = (0x00000006) # type: ignore
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL = (0x00000007) # type: ignore
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND = (0x00000008) # type: ignore
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT = (0x00000009) # type: ignore
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON = (0x0000000F) # type: ignore
|
|
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN = (0xFFFFFFFF) # type: ignore
|
|
NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED = (0x00000002) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_INFO = (0x20801301) # type: ignore
|
|
NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_INFO_V2 = (0x20801303) # type: ignore
|
|
NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET = (0x20801310) # type: ignore
|
|
NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID = (0x10) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED = (0x2080130c) # type: ignore
|
|
NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID = (0xC) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL = (0x2080130d) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID = (0xD) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK = (0, 0) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE = (1, 1) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH = (2, 2) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE = (0x2080130e) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES = 500 # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID = (0xE) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE = (1, 0) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK = (2, 2) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE = (3, 3) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE = (4, 4) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH = (5, 5) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_FB_IS_KIND = (0x20801313) # type: ignore
|
|
NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID = (0x13) # type: ignore
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC = (0x00000005) # type: ignore
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 = (0x00000006) # type: ignore
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 = (0x00000007) # type: ignore
|
|
NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 = (0x00000008) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO = (0x20801315) # type: ignore
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID = (0x15) # type: ignore
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE = (0x00000003) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO = (0x20801320) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES = 17 # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES = 16 # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID = (0x20) # type: ignore
|
|
NV2080_CTRL_CMD_FB_OFFLINE_PAGES = (0x20801321) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES = (0x00000040) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS = (0xffffffffffffffff) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE = (0x00000004) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL = (0x00000003) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR = (0x00000004) # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE = NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE # type: ignore
|
|
NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE = NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE # type: ignore
|
|
NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID = (0x21) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES = (0x20801322) # type: ignore
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE = (0, 0) # type: ignore
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE = 0 # type: ignore
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE = 1 # type: ignore
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE = (1, 1) # type: ignore
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE = 0 # type: ignore
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE = 1 # type: ignore
|
|
NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x22) # type: ignore
|
|
NV2080_CTRL_CMD_FB_QUERY_ACR_REGION = (0x20801325) # type: ignore
|
|
NV2080_CTRL_CMD_FB_ACR_CLIENT_ID = 2 # type: ignore
|
|
NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID = (0x25) # type: ignore
|
|
NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES = (0x20801326) # type: ignore
|
|
NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x26) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO = (0x20801327) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID = (0x27) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP = (0x20801328) # type: ignore
|
|
NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID = (0x28) # type: ignore
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT = (0x20801329) # type: ignore
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS = (0x2080132a) # type: ignore
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS = (0x2080132b) # type: ignore
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB = (0x2080132c) # type: ignore
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB = (0x2080132d) # type: ignore
|
|
NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 = (0x20801335) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_AMAP_CONF = (0x20801336) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID = (0x36) # type: ignore
|
|
NV2080_CTRL_CMD_FB_CBC_OP = (0x20801337) # type: ignore
|
|
NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID = (0x37) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION = (0x20801338) # type: ignore
|
|
NV2080_MAX_CTAGS_FOR_CBC_EVICTION = 0x7F # type: ignore
|
|
NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID = (0x38) # type: ignore
|
|
NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE = (0x20801339) # type: ignore
|
|
NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID = (0x39) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FREE_TILE = (0x2080133a) # type: ignore
|
|
NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID = (0x3A) # type: ignore
|
|
NV2080_CTRL_CMD_FB_SETUP_VPR_REGION = (0x2080133b) # type: ignore
|
|
NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID = (0x3B) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES = (0x2080133c) # type: ignore
|
|
NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x3C) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO = (0x2080133d) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID = (0x3D) # type: ignore
|
|
NV2080_CTRL_CMD_FB_SET_RRD = (0x2080133e) # type: ignore
|
|
NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID = (0x3E) # type: ignore
|
|
NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE = (0xff) # type: ignore
|
|
NV2080_CTRL_CMD_FB_SET_READ_LIMIT = (0x2080133f) # type: ignore
|
|
NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE = NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE # type: ignore
|
|
NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID = (0x3F) # type: ignore
|
|
NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT = (0x20801340) # type: ignore
|
|
NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE = NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE # type: ignore
|
|
NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID = (0x40) # type: ignore
|
|
NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING = (0x20801341) # type: ignore
|
|
NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID = (0x41) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT = (0x20801342) # type: ignore
|
|
NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS = (4) # type: ignore
|
|
NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID = (0x42) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR = (0x20801343) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x43) # type: ignore
|
|
NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING = (0, 0) # type: ignore
|
|
NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE = 0 # type: ignore
|
|
NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE = 1 # type: ignore
|
|
NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD = (0x00000003) # type: ignore
|
|
NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS = (0x00000200) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS = (0x20801344) # type: ignore
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING = NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING # type: ignore
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE = NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE # type: ignore
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE = NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE # type: ignore
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE = (1, 1) # type: ignore
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE = 0 # type: ignore
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE = 1 # type: ignore
|
|
NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID = (0x44) # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE = 24 # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_INVALID_QUERY = 0x0 # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_FBP_MASK = 0x1 # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_LTC_MASK = 0x2 # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_LTS_MASK = 0x3 # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_FBPA_MASK = 0x4 # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_ROP_MASK = 0x5 # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK = 0x6 # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK = 0x7 # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK = 0x8 # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK = 0x9 # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK = 0xA # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK = 0xB # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP = 0xC # type: ignore
|
|
NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK = 0xD # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_PAC_MASK = 0xE # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK = 0xF # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK = 0x10 # type: ignore
|
|
NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK = 0x11 # type: ignore
|
|
NV2080_CTRL_FB_FS_INFO_MAX_QUERIES = 120 # type: ignore
|
|
NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID = (0x46) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_FS_INFO = (0x20801346) # type: ignore
|
|
NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS = (0x0) # type: ignore
|
|
NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW = (0x1) # type: ignore
|
|
NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS = (0x2) # type: ignore
|
|
NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW = (0x3) # type: ignore
|
|
NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS = (0x4) # type: ignore
|
|
NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID = (0x47) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM = (0x20801347) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES = (0x20801348) # type: ignore
|
|
NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES = 512 # type: ignore
|
|
NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES = 64 # type: ignore
|
|
NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x48) # type: ignore
|
|
NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO = (0x20801349) # type: ignore
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE = (4, 0) # type: ignore
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM = 0 # type: ignore
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM = 1 # type: ignore
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED = (5, 5) # type: ignore
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE = 0 # type: ignore
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE = 1 # type: ignore
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER = (6, 6) # type: ignore
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE = 0 # type: ignore
|
|
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE = 1 # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID = (0x49) # type: ignore
|
|
NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS = (0x20801350) # type: ignore
|
|
NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID = (0x50) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_NUMA_INFO = (0x20801351) # type: ignore
|
|
NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES = 64 # type: ignore
|
|
NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID = (0x51) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT = (0x20801352) # type: ignore
|
|
NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID = (0x52) # type: ignore
|
|
NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE = (0x20801353) # type: ignore
|
|
NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID = (0x53) # type: ignore
|
|
NV2080_CTRL_CMD_FB_STATS_MAX_OWNER = 200 # type: ignore
|
|
NV2080_CTRL_CMD_FB_STATS_GET = (0x2080132a) # type: ignore
|
|
NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID = (0x2A) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO = (0x20801354) # type: ignore
|
|
NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID = (0x54) # type: ignore
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION = (0x20801355) # type: ignore
|
|
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID = (0x55) # type: ignore
|
|
NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION = (0x20801356) # type: ignore
|
|
NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_DISABLE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_ENABLE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID = (0x56) # type: ignore
|
|
NV2080_CTRL_CMD_FB_GET_STATUS = (0x20801357) # type: ignore
|
|
NV2080_CTRL_FB_STATUS_FAILED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FB_STATUS_READY = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_STATUS_PENDING = (0x00000002) # type: ignore
|
|
NV2080_CTRL_FB_STATUS_NOT_APPLICABLE = (0x00000003) # type: ignore
|
|
NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID = (0x57) # type: ignore
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT = (0x20801358) # type: ignore
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID = (0x58) # type: ignore
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS = (0x20801359) # type: ignore
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID = (0x59) # type: ignore
|
|
NV2080_CTRL_CMD_SET_GPFIFO = (0x20801102) # type: ignore
|
|
NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS = (16) # type: ignore
|
|
NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_BIND_ENGINES = (0x20801103) # type: ignore
|
|
NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES = (0x20801104) # type: ignore
|
|
NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE = (0, 0) # type: ignore
|
|
NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT = (0x20801108) # type: ignore
|
|
NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL = (0x000000000) # type: ignore
|
|
NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS = (0x000000001) # type: ignore
|
|
NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP = (0x000000002) # type: ignore
|
|
NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP = (0x000000003) # type: ignore
|
|
NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET = (0x000000004) # type: ignore
|
|
NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE = (0x000000005) # type: ignore
|
|
NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE = (0x000000006) # type: ignore
|
|
NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED = (0x000000007) # type: ignore
|
|
NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE = (0x000000008) # type: ignore
|
|
NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE = (0x000000009) # type: ignore
|
|
NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT = (0x00000000a) # type: ignore
|
|
NV2080_CTRL_FIFO_INFO_INDEX_MAX = NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT # type: ignore
|
|
NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT = (12) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_INFO = (0x20801109) # type: ignore
|
|
NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES = (256) # type: ignore
|
|
NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL = (0x2080110a) # type: ignore
|
|
NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID = (0xA) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS = (0x2080110b) # type: ignore
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES = (64) # type: ignore
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID = (0xB) # type: ignore
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT = 0x2 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO = (0x2080110c) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID = (0xC) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID = 0x00000000 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM = 0x00000001 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH = 0x00000002 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH = 0x00000003 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION = (0x2080110d) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID = (0xD) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM = 0x00000000 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM = 0x00000001 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED = 0x00000000 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED = 0X00000001 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED = 0X00000002 # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN = 0 # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER = 1 # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT = 2 # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE = 3 # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE = 4 # type: ignore
|
|
NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT = 3 # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT = 0 # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE = 1 # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE = 2 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG = (0x2080110e) # type: ignore
|
|
NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT = 32 # type: ignore
|
|
NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS = 8 # type: ignore
|
|
NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES = 200 # type: ignore
|
|
NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID = (0xE) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE = (0x20801112) # type: ignore
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES = 256 # type: ignore
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES = 32 # type: ignore
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES = 16 # type: ignore
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA = 2 # type: ignore
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN = 16 # type: ignore
|
|
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID = (0x12) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT = (0x20801113) # type: ignore
|
|
NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE = 0x00000001 # type: ignore
|
|
NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA = 0x00000002 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID = (0x13) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY = (0x20801115) # type: ignore
|
|
NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT = 0x0 # type: ignore
|
|
NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED = 0x1 # type: ignore
|
|
NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM = 0x2 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE = (0, 0) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID = (0x15) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO = (0x20801116) # type: ignore
|
|
NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID = (0x16) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS = (0x20801117) # type: ignore
|
|
NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID = (0x17) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB = (0x20801118) # type: ignore
|
|
NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID = (0x18) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS = (0x20801119) # type: ignore
|
|
NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS = 4096 # type: ignore
|
|
NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID = (0x19) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION = (0x2080111a) # type: ignore
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES = (64) # type: ignore
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID = (0x1A) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 = (0x2080111b) # type: ignore
|
|
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID = (0x1B) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE = (0x20801120) # type: ignore
|
|
NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID = (0x20) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE = (0x20801121) # type: ignore
|
|
NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID = (0x21) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS = (0x20801122) # type: ignore
|
|
NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID = (0x22) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG = 128 # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO = (0x20801123) # type: ignore
|
|
NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID = (0x23) # type: ignore
|
|
NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID = (0x20801124) # type: ignore
|
|
NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID = (0x24) # type: ignore
|
|
NV2080_CTRL_CMD_FLA_RANGE = (0x20803501) # type: ignore
|
|
NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE = 0x00000000 # type: ignore
|
|
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE = NVBIT(0) # type: ignore
|
|
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY = NVBIT(1) # type: ignore
|
|
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE = NVBIT(2) # type: ignore
|
|
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY = NVBIT(3) # type: ignore
|
|
NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK = (0x20803502) # type: ignore
|
|
NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_FLA_GET_RANGE = (0x20803503) # type: ignore
|
|
NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS = (0x20803504) # type: ignore
|
|
NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
FALCON_ID_PMU = (NV2080_ENGINE_TYPE_PMU) # type: ignore
|
|
FALCON_ID_DPU = (NV2080_ENGINE_TYPE_DPU) # type: ignore
|
|
FALCON_ID_SEC2 = (NV2080_ENGINE_TYPE_SEC2) # type: ignore
|
|
FALCON_ID_FBFLCN = (NV2080_ENGINE_TYPE_FBFLCN) # type: ignore
|
|
NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE = (0x20803101) # type: ignore
|
|
NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE = 0x00 # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END = 0x01 # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN = 0x02 # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END = 0x03 # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK = 0x04 # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN = 0x05 # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END = 0x06 # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY = 0x07 # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT = 0x08 # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0 = 0x09 # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END = 0x0A # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN = 0x0B # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END = 0x0C # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY = 0x0D # type: ignore
|
|
NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID = 0xFF # type: ignore
|
|
NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH = (0x20803118) # type: ignore
|
|
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID = (0x18) # type: ignore
|
|
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT = 0x0 # type: ignore
|
|
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON = 0x1 # type: ignore
|
|
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV = 0x2 # type: ignore
|
|
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB = 0x3 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_FLAG = (31, 31) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_HEAD = (30, 30) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_VARIABLE = (29, 29) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EXTEND = (28, 28) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT = (27) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE = (20) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT = (28) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE = (24) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_LENGTH = (19, 8) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOAD = (7, 0) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT = (23, 0) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_HEAD_TIME = (29, 0) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_DATA_PAYLOAD = (30, 0) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_TASK_ID = (7, 0) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON = (10, 8) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD = 0x0 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0 = 0x1 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK = 0x2 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK = 0x3 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED = 0x4 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_ODP_MISS_COUNT = (23, 11) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TIMER_TICK_TIME_SLIP = (23, 0) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_TASK_ID = (7, 0) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_UNIT_ID = (15, 8) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE = (23, 16) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID = (7, 0) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CALLBACK_ID = (15, 8) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC = (15, 8) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE = 0xF0 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID = (23, 16) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT = 10 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_TASK_ID = (7, 0) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID = (23, 8) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED = 0x000000 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL = 0x000001 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT = 6 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID = (11, 0) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID = 0x000 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL = 0x001 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT = 0 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON = 1 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT = 2 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH = (0, 0) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED = 0 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED = 1 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH = (1, 1) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED = 0 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED = 1 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH = (2, 2) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED = 0 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED = 1 # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_THRESHOLD = (31, 8) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT = (0x20) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES = (0x120) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES = (0x24) # type: ignore
|
|
NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO = (0x20803120) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID = (0x20) # type: ignore
|
|
NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET = (0x20803122) # type: ignore
|
|
NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET = (0x20803123) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID = (0x22) # type: ignore
|
|
NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID = (0x23) # type: ignore
|
|
NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO = (0x20803124) # type: ignore
|
|
NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x24) # type: ignore
|
|
NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE = (0x20803125) # type: ignore
|
|
NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x25) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION = (0x20802300) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID = (0x00) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT = (0x20802301) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID = (0x01) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT = (0x20802302) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID = (0x02) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION = (0x20802303) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID = (0x03) # type: ignore
|
|
NV_GRID_LICENSE_INFO_MAX_LENGTH = (128) # type: ignore
|
|
NV_GRID_LICENSE_FEATURE_VPC_EDITION = "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" # type: ignore
|
|
NV_GRID_LICENSE_FEATURE_VAPPS_EDITION = "GRID-Virtual-Apps,3.0" # type: ignore
|
|
NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION = "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" # type: ignore
|
|
NV_GRID_LICENSE_FEATURE_GAMING_EDITION = "GRID-vGaming,8.0" # type: ignore
|
|
NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION = "NVIDIA-vComputeServer,9.0" # type: ignore
|
|
NV_GRID_LICENSED_PRODUCT_VWS = "NVIDIA RTX Virtual Workstation" # type: ignore
|
|
NV_GRID_LICENSED_PRODUCT_GAMING = "NVIDIA Cloud Gaming" # type: ignore
|
|
NV_GRID_LICENSED_PRODUCT_VPC = "NVIDIA Virtual PC" # type: ignore
|
|
NV_GRID_LICENSED_PRODUCT_VAPPS = "NVIDIA Virtual Applications" # type: ignore
|
|
NV_GRID_LICENSED_PRODUCT_COMPUTE = "NVIDIA Virtual Compute Server" # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_INDEX = (23, 0) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_ECID_LO32 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_ECID_HI32 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT = (0x00000004) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 = (0x00000012) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 = (0x00000013) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_ECID_EXTENDED = (0x0000001b) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS = (0x0000001f) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD = (0x00000022) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE = (0x00000025) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED = (0x00000027) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED = (0x00000028) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT = (0x00000029) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE = (0x0000002a) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM = (0x0000002b) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION = (0x0000002c) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY = (0x0000002d) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM = (0x0000002f) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY = (0x00000030) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE = (0x00000031) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED = (0x00000033) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED = (0x00000034) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED = (0x00000035) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY = (0x00000036) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY = (0x00000037) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY = (0x0000003a) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY = (0x0000003b) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU = (0x0000003c) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY = (0x0000003d) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED = (0x0000003f) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE = (0x00000041) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GROUP_ID = (30, 24) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_RESERVED = (31, 31) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV = (0x00000003) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING = (0x00000003) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING = (0x00000004) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_PEERID = (31, 1) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_INFO = (0x20800101) # type: ignore
|
|
NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_INFO_V2 = (0x20800102) # type: ignore
|
|
NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_NAME_STRING = (0x20800110) # type: ignore
|
|
NV2080_GPU_MAX_NAME_STRING_LENGTH = (0x0000040) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE = (31, 0) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID = (0x10) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING = (0x20800111) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID = (0x11) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_SET_POWER = (0x20800112) # type: ignore
|
|
NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID = (0x12) # type: ignore
|
|
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 = (0x00000007) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_SDM = (0x20800118) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID = (0x18) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_SET_SDM = (0x20800120) # type: ignore
|
|
NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID = (0x20) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO = (0x20800119) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID = (0x19) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL = (0x00000003) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL = (0x00000004) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU = (0x00000005) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER = (0x00000006) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA = (0x00000007) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL = (0x00000008) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL = (0x00000009) # type: ignore
|
|
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN = (0xFFFFFFFF) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_READ_32 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_WRITE_32 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_READ_64 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_WRITE_64 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_READ_08 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_WRITE_08 = (0x00000005) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM = (0x00000004) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP = (0x00000008) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP = (0x00000010) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_FB = (0x00000020) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD = (0x00000040) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE = (0x00000080) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS = (0x00) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP = (0x01) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE = (0x02) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET = (0x04) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP = (0x08) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK = (0x10) # type: ignore
|
|
NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS = (0x20) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_EXEC_REG_OPS = (0x20800122) # type: ignore
|
|
NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0x22) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINES = (0x20800123) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID = (0x23) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 = (0x20800170) # type: ignore
|
|
NV2080_GPU_MAX_ENGINES_LIST_SIZE = 0x54 # type: ignore
|
|
NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID = (0x70) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST = (0x20800124) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID = (0x24) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO = (0x20800125) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID = (0x25) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_QUERY_MODE = (0x20800128) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID = (0x28) # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN = 0 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM = 1 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH = 2 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB = 3 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL = 4 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB = 5 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL = 6 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL = 7 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK = 8 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT = 9 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP = 10 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP = 11 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP = 12 # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES = 16 # type: ignore
|
|
NV2080_CTRL_CMD_GPU_PROMOTE_CTX = (0x2080012b) # type: ignore
|
|
NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID = (0x2B) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_EVICT_CTX = (0x2080012c) # type: ignore
|
|
NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID = (0x2C) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_INITIALIZE_CTX = (0x2080012d) # type: ignore
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID = (0x2D) # type: ignore
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE = (1, 0) # type: ignore
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE = (2, 2) # type: ignore
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX = (3, 3) # type: ignore
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR = (0x2080012e) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS = (0x2080012f) # type: ignore
|
|
NV2080_CTRL_GPU_ECC_UNIT_GSP = (0x0000001D) # type: ignore
|
|
NV2080_CTRL_GPU_ECC_UNIT_COUNT = (0x00000024) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE = (0, 0) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE = 0 # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE = 1 # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE = 2 # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID = (0x2F) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES = (0x20800130) # type: ignore
|
|
NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS = (0x00000003) # type: ignore
|
|
NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID = (0x30) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES = (0x20800131) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID = (0x31) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION = (0x20800133) # type: ignore
|
|
NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID = (0x33) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION = (0x20800134) # type: ignore
|
|
NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID = (0x34) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS = (0x20800136) # type: ignore
|
|
NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE = (0, 0) # type: ignore
|
|
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE = 0 # type: ignore
|
|
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE = 1 # type: ignore
|
|
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID = (0x36) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO = (0x20800137) # type: ignore
|
|
NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID = (0x37) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO = (0x20800138) # type: ignore
|
|
NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID = (0x38) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO = (0x20800139) # type: ignore
|
|
NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x39) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO = (0x2080013f) # type: ignore
|
|
NV2080_GPU_MAX_MARKETING_NAME_LENGTH = (0x00000018) # type: ignore
|
|
NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH = (0x00000010) # type: ignore
|
|
NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH = (0x00000014) # type: ignore
|
|
NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH = (0x00000006) # type: ignore
|
|
NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH = (0x00000014) # type: ignore
|
|
NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID = (0x3F) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ID = (0x20800142) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID = (0x42) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE = (0x20800143) # type: ignore
|
|
NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID = (0x43) # type: ignore
|
|
NV2080_CTRL_GPU_DEBUG_MODE_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_DEBUG_MODE_DISABLED = (0x00000002) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE = (0x20800144) # type: ignore
|
|
NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID = (0x44) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST = (0x20800147) # type: ignore
|
|
NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS = (0x00000020) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID = (0x47) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_GID_INFO = (0x2080014a) # type: ignore
|
|
NV2080_GPU_MAX_GID_LENGTH = (0x000000100) # type: ignore
|
|
NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH = (0x000000010) # type: ignore
|
|
NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID = (0x4A) # type: ignore
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT = (1, 0) # type: ignore
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII = (0x00000000) # type: ignore
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY = (0x00000002) # type: ignore
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE = (2, 2) # type: ignore
|
|
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION = (0x2080014b) # type: ignore
|
|
NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN = 3 # type: ignore
|
|
NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID = (0x4B) # type: ignore
|
|
NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO = (0x2080014c) # type: ignore
|
|
NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID = (0x4C) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_IP_VERSION = (0x2080014d) # type: ignore
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID = (0x4D) # type: ignore
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC = (0x00000002) # type: ignore
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_PMGR = (0x00000003) # type: ignore
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU = (0x00000004) # type: ignore
|
|
NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON = (0x00000005) # type: ignore
|
|
NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS = 0 # type: ignore
|
|
NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS = 1 # type: ignore
|
|
NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT = (0x20800153) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID = (0x53) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ILLUM = (0x20800154) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID = (0x54) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_SET_ILLUM = (0x20800155) # type: ignore
|
|
NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID = (0x55) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION = (0x20800156) # type: ignore
|
|
NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN = 16 # type: ignore
|
|
NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID = (0x56) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT = (0x20800157) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO = (0x2080015a) # type: ignore
|
|
NV2080_CTRL_MAX_PHYSICAL_BRIDGE = (100) # type: ignore
|
|
NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID = (0x5A) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU = (0x2080015b) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID = (0x5B) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS = (0x2080015f) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID = (0x5F) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_VPR_CAPS = (0x20800160) # type: ignore
|
|
NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID = (0x60) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR = (0x20800167) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_PES_INFO = (0x20800168) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT = 10 # type: ignore
|
|
NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID = (0x68) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_OEM_INFO = (0x20800169) # type: ignore
|
|
NV2080_GPU_MAX_OEM_INFO_LENGTH = (0x000001F8) # type: ignore
|
|
NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID = (0x69) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_VPR_INFO = (0x2080016b) # type: ignore
|
|
NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID = (0x6B) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY = (0x2080016c) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID = (0x6C) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS = (0x2080016d) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID = (0x6D) # type: ignore
|
|
NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES = 0x200 # type: ignore
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID = (0x6E) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO = (0x2080016e) # type: ignore
|
|
NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x6F) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR = (0x2080016f) # type: ignore
|
|
NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID = (0x72) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT = (0x20800172) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID = (0x73) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS = (0x20800173) # type: ignore
|
|
NV_GI_UUID_LEN = 16 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_ID_INVALID = 0xFFFFFFFF # type: ignore
|
|
NV2080_CTRL_GPU_MAX_PARTITIONS = 0x00000008 # type: ignore
|
|
NV2080_CTRL_GPU_MAX_PARTITION_IDS = 0x00000009 # type: ignore
|
|
NV2080_CTRL_GPU_MAX_SMC_IDS = 0x00000008 # type: ignore
|
|
NV2080_CTRL_GPU_MAX_GPC_PER_SMC = 0x0000000c # type: ignore
|
|
NV2080_CTRL_GPU_MAX_CE_PER_SMC = 0x00000008 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE = (1, 0) # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL = 0x00000000 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF = 0x00000001 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER = 0x00000002 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH = 0x00000003 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE = 4 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE = (4, 2) # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL = 0x00000000 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF = 0x00000001 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF = 0x00000002 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER = 0x00000003 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER = 0x00000004 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH = 0x00000005 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_06 = 0x00000006 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07 = 0x00000007 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE = 8 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE = (7, 5) # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL = 0x00000001 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF = 0x00000002 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF = 0x00000003 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER = 0x00000004 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH = 0x00000005 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_06 = 0x00000006 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_07 = 0x00000007 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE = 0x00000000 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE = 8 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_MAX_TYPES = 40 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA = (30, 30) # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE = 0 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE = 1 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN = (31, 31) # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE = 0 # type: ignore
|
|
NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE = 1 # type: ignore
|
|
NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID = (0x74) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_SET_PARTITIONS = (0x20800174) # type: ignore
|
|
NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID = (0x75) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_PARTITIONS = (0x20800175) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION = (0x20800176) # type: ignore
|
|
NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID = (0x76) # type: ignore
|
|
NV2080_CTRL_GPU_FAULT_PACKET_SIZE = 32 # type: ignore
|
|
NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT = (0x20800177) # type: ignore
|
|
NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID = (0x77) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU = (0x20800178) # type: ignore
|
|
NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID = (0x78) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE = (0x20800179) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID = (0x79) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL = (0xFFFFFFFF) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR = (0xFFFFFFFB) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_INVALID = (0xFFFFFFFF) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_ERROR = (0xFFFFFFFB) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID = (0x2080017a) # type: ignore
|
|
NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID = (0x7A) # type: ignore
|
|
NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL = (0xFFFFFFFF) # type: ignore
|
|
NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR = (0xFFFFFFFB) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS = (0x2080017b) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID = (0x7B) # type: ignore
|
|
NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED = 0x00000001 # type: ignore
|
|
NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED = 0x00000002 # type: ignore
|
|
NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT = 0x00000004 # type: ignore
|
|
NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE = 0x00000008 # type: ignore
|
|
NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT = 0x00000010 # type: ignore
|
|
NV2080_GPU_NVFBC_MAX_SESSION_COUNT = 256 # type: ignore
|
|
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID = (0x7C) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO = (0x2080017c) # type: ignore
|
|
NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID = (0xe6) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX = (0x208001e6) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE = (0x2080017e) # type: ignore
|
|
NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID = (0x7E) # type: ignore
|
|
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB = 0x02000000 # type: ignore
|
|
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB = 0x04000000 # type: ignore
|
|
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB = 0x08000000 # type: ignore
|
|
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB = 0x10000000 # type: ignore
|
|
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB = 0x20000000 # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY = (0x20800181) # type: ignore
|
|
NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID = (0x81) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_CACHED_INFO = (0x20800182) # type: ignore
|
|
NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID = (0x82) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE = (0x20800183) # type: ignore
|
|
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING = (1, 0) # type: ignore
|
|
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY = 0 # type: ignore
|
|
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF = 1 # type: ignore
|
|
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG = 2 # type: ignore
|
|
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID = (0x83) # type: ignore
|
|
NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID = (0x85) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS = (0x20800185) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE = (0x20800188) # type: ignore
|
|
NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID = (0x88) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID = (0x8A) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC = (0x2080018a) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID = (0x8B) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS = (0x2080018b) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_PIDS = (0x2080018d) # type: ignore
|
|
NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT = 950 # type: ignore
|
|
NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID = (0x8D) # type: ignore
|
|
NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GPU_PID_INFO_INDEX_MAX = NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_PID_INFO = (0x2080018e) # type: ignore
|
|
NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT = 200 # type: ignore
|
|
NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID = (0x8E) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT = (0x20800192) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID = 0 # type: ignore
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1 = 1 # type: ignore
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2 = 2 # type: ignore
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL = 3 # type: ignore
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE = 4 # type: ignore
|
|
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID = (0x92) # type: ignore
|
|
NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE = 0 # type: ignore
|
|
NV2080_CTRL_GPU_COMPUTE_POLICY_MAX = 1 # type: ignore
|
|
NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID = (0x94) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG = (0x20800195) # type: ignore
|
|
NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX = 32 # type: ignore
|
|
NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID = (0x95) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_GFID = (0x20800196) # type: ignore
|
|
NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID = (0x96) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY = (0x20800197) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID = (0x97) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST = (0x20800198) # type: ignore
|
|
NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID = (0x98) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR = (0x20800199) # type: ignore
|
|
NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x99) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES = (0x2080019b) # type: ignore
|
|
NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS = 0xC8 # type: ignore
|
|
NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID = (0x9B) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING = (0x2080019c) # type: ignore
|
|
NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID = (0x9C) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS = (0x2080019d) # type: ignore
|
|
NV2080_CTRL_REG_OPS_ARRAY_MAX = 100 # type: ignore
|
|
NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID = (0x9D) # type: ignore
|
|
NV2080_GET_P2P_CAPS_UUID_LEN = 16 # type: ignore
|
|
NV2080_CTRL_CMD_GET_P2P_CAPS = (0x208001a0) # type: ignore
|
|
NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID = (0xA0) # type: ignore
|
|
NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xA2) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES = (0x208001a2) # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED = 0 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED = 1 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS = 2 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE = 3 # type: ignore
|
|
NV2080_GPU_FABRIC_CLUSTER_UUID_LEN = 16 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW = (1, 0) # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED = 0 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE = 1 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE = 2 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE = (3, 2) # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED = 0 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE = 1 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE = 2 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY = (5, 4) # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED = 0 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE = 1 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE = 2 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY = (7, 6) # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED = 0 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE = 1 # type: ignore
|
|
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE = 2 # type: ignore
|
|
NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xA3) # type: ignore
|
|
NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO = (0x208001a3) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS = (0x208001a4) # type: ignore
|
|
GPU_PART_NUMBER_FMT = "%4X-%s-%X%X" # type: ignore
|
|
NV2080_MAX_CHIP_SKU_LENGTH = 0x00000004 # type: ignore
|
|
NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID = (0xA4) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP = (0x208001a5) # type: ignore
|
|
NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID = (0xA5) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS = (0x208001a6) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP = (0x208001a7) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU = (0x208001a8) # type: ignore
|
|
NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX = 50 # type: ignore
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID = (0xA6) # type: ignore
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID = (0xA7) # type: ignore
|
|
NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID = (0xA8) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET = (0x208001a9) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET = (0x208001aa) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_RESET_STATUS = (0x208001ab) # type: ignore
|
|
NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID = (0xAB) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET = (0x208001ac) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET = (0x208001ad) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS = (0x208001ae) # type: ignore
|
|
NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID = (0xAE) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID = (0xAF) # type: ignore
|
|
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 = (0x208001af) # type: ignore
|
|
NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS = 0x40 # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO = (0x208001b0) # type: ignore
|
|
NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID = (0xB0) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_VF_CAPS = (0x208001b1) # type: ignore
|
|
NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID = (0xB1) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION = (0x208001b2) # type: ignore
|
|
NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID = (0xB2) # type: ignore
|
|
NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID = (0xe4) # type: ignore
|
|
NV2080_CTRL_GPU_GET_FIPS_STATUS = (0x208001e4) # type: ignore
|
|
NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU = 0x2 # type: ignore
|
|
NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU = 0xC # type: ignore
|
|
NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC = (0x18) # type: ignore
|
|
NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT = (0x1a) # type: ignore
|
|
NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID = (0xB3) # type: ignore
|
|
NV2080_CTRL_GPU_GET_RAFTS_FS_MASK = (0x208001b3) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILE_CAPACITY = (0x208001e5) # type: ignore
|
|
NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID = (0xe5) # type: ignore
|
|
NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK = (0x208001e7) # type: ignore
|
|
NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID = (0xe7) # type: ignore
|
|
NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS = 0x00000001 # type: ignore
|
|
NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL = 0x00000002 # type: ignore
|
|
NV2080_GPUMON_PID_INVALID = ((NvU32)(~0)) # type: ignore
|
|
NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE = (1, 0) # type: ignore
|
|
NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE = 0x0 # type: ignore
|
|
NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID = 0x1 # type: ignore
|
|
NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL = 0x2 # type: ignore
|
|
NV2080_CTRL_GR_ROUTE_INFO_DATA_CHANNEL_HANDLE = (31, 0) # type: ignore
|
|
NV2080_CTRL_GR_ROUTE_INFO_DATA_ENGID = (31, 0) # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS = NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 = NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 # type: ignore
|
|
NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK = NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT = NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT = NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE = NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT = NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT = NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR = NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT = NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT = NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT = NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_SM_VERSION = NV0080_CTRL_GR_INFO_INDEX_SM_VERSION # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM = NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP = NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES = NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES = NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY = NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY = NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM = NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED = NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT = NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT = NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT = NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT = NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT = NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT = NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_DUMMY = NV0080_CTRL_GR_INFO_INDEX_DUMMY # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES = NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES = NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS = NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG = NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET = NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET # type: ignore
|
|
NV2080_CTRL_GR_INFO_INDEX_MAX = NV0080_CTRL_GR_INFO_INDEX_MAX # type: ignore
|
|
NV2080_CTRL_GR_INFO_MAX_SIZE = NV0080_CTRL_GR_INFO_MAX_SIZE # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_NONE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_1_05 = (0x00000105) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_1_1 = (0x00000110) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_1_2 = (0x00000120) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_1_3 = (0x00000130) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_1_4 = (0x00000140) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_1_5 = (0x00000150) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_2_0 = (0x00000200) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_2_1 = (0x00000210) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_2_2 = (0x00000220) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_0 = (0x00000300) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_1 = (0x00000310) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_2 = (0x00000320) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_3 = (0x00000330) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_5 = (0x00000350) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_6 = (0x00000360) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_8 = (0x00000380) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_3_9 = (0x00000390) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_4_0 = (0x00000400) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_5_0 = (0x00000500) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_5_02 = (0x00000502) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_5_03 = (0x00000503) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_6_0 = (0x00000600) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_6_01 = (0x00000601) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_6_02 = (0x00000602) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_0 = (0x00000700) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_01 = (0x00000701) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_02 = (0x00000702) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_03 = (0x00000703) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_05 = (0x00000705) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_02 = (0x00000802) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_06 = (0x00000806) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_07 = (0x00000807) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_08 = (0x00000808) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_09 = (0x00000809) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_9_00 = (0x00000900) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_00 = (0x00000A00) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_01 = (0x00000A01) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_04 = (0x00000A04) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_5_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_5_02) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_5_3 = (NV2080_CTRL_GR_INFO_SM_VERSION_5_03) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_6_1 = (NV2080_CTRL_GR_INFO_SM_VERSION_6_01) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_6_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_6_02) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_1 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_01) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_02) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_3 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_03) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_7_5 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_05) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_02) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_6 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_06) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_7 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_07) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_8 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_08) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_8_9 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_09) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_9_0 = (NV2080_CTRL_GR_INFO_SM_VERSION_9_00) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_0 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_00) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_1 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_01) # type: ignore
|
|
NV2080_CTRL_GR_INFO_SM_VERSION_10_4 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_04) # type: ignore
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D = (0, 0) # type: ignore
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE = 0x0 # type: ignore
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE = 0x1 # type: ignore
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D = (1, 1) # type: ignore
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE = 0x0 # type: ignore
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE = 0x1 # type: ignore
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE = (2, 2) # type: ignore
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE = 0x0 # type: ignore
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE = 0x1 # type: ignore
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M = (3, 3) # type: ignore
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE = 0x0 # type: ignore
|
|
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE = 0x1 # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_INFO = (0x20801201) # type: ignore
|
|
NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE = (0x20801205) # type: ignore
|
|
NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER = (0x00000002) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_ZCULL_INFO = (0x20801206) # type: ignore
|
|
NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV2080_CTRL_CMD_GR_CTXSW_PM_MODE = (0x20801207) # type: ignore
|
|
NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CTXSW_PM_MODE_CTXSW = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW = (0x00000002) # type: ignore
|
|
NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND = (0x20801208) # type: ignore
|
|
NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV2080_CTRL_CMD_GR_CTXSW_PM_BIND = (0x20801209) # type: ignore
|
|
NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND = (0x2080123a) # type: ignore
|
|
NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID = (0x3A) # type: ignore
|
|
NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES = 128 # type: ignore
|
|
NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP = (0x2080120a) # type: ignore
|
|
NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID = (0xA) # type: ignore
|
|
NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE = (0x2080120e) # type: ignore
|
|
NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID = (0xE) # type: ignore
|
|
NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS = (0x2080120f) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT = 240 # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID = (0xF) # type: ignore
|
|
NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE = (0x20801210) # type: ignore
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID = (0x10) # type: ignore
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP = (0, 0) # type: ignore
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP = (1, 1) # type: ignore
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET = (0x00000001) # type: ignore
|
|
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI = (0x00000000) # type: ignore
|
|
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP = (0x00000001) # type: ignore
|
|
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL = (0x00000002) # type: ignore
|
|
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI = (0x00000000) # type: ignore
|
|
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA = (0x00000001) # type: ignore
|
|
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP = (0x00000002) # type: ignore
|
|
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND = (0x20801211) # type: ignore
|
|
NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID = (0x11) # type: ignore
|
|
NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE = (0x20801212) # type: ignore
|
|
NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID = (0x12) # type: ignore
|
|
NV2080_CTRL_PC_SAMPLING_MODE_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_PC_SAMPLING_MODE_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_ROP_INFO = (0x20801213) # type: ignore
|
|
NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x13) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_CTXSW_STATS = (0x20801215) # type: ignore
|
|
NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID = (0x15) # type: ignore
|
|
NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET = (0, 0) # type: ignore
|
|
NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE = (0x20801218) # type: ignore
|
|
NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x18) # type: ignore
|
|
NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT = 64 # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO = (0x20801219) # type: ignore
|
|
NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x19) # type: ignore
|
|
NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN = 0 # type: ignore
|
|
NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM = 1 # type: ignore
|
|
NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM = 2 # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER = (0x2080121b) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT = 512 # type: ignore
|
|
NV2080_CTRL_GR_DISABLED_SM_VGPC_ID = 0xFF # type: ignore
|
|
NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x1B) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL = (0x2080121c) # type: ignore
|
|
NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID = (0x1C) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT = 10 # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT = 10 # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA = (0x2080121d) # type: ignore
|
|
NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID = (0x1D) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE = (0x2080121e) # type: ignore
|
|
NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x1E) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE = (0x2080121f) # type: ignore
|
|
NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID = (0x1F) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE = (0x20801220) # type: ignore
|
|
NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID = (0x20) # type: ignore
|
|
NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS = 64 # type: ignore
|
|
NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS = (0x20801221) # type: ignore
|
|
NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID = (0x21) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS = (0x20801222) # type: ignore
|
|
NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID = (0x22) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_CAPS_V2 = (0x20801227) # type: ignore
|
|
NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x27) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_INFO_V2 = (0x20801228) # type: ignore
|
|
NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x28) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_GPC_MASK = (0x2080122a) # type: ignore
|
|
NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID = (0x2A) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_TPC_MASK = (0x2080122b) # type: ignore
|
|
NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID = (0x2B) # type: ignore
|
|
NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = (0x2080122c) # type: ignore
|
|
NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x2C) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES = (0x2080122d) # type: ignore
|
|
NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID = (0x2D) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER = (0x20801230) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED = (0x0) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2 = (0x1) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4 = (0x2) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8 = (0x3) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16 = (0x4) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32 = (0x5) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64 = (0x6) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED = (0x0) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2 = (0x1) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4 = (0x2) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8 = (0x3) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16 = (0x4) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32 = (0x5) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED = (0x0) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED = (0x1) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED = (0x0) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2 = (0x1) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4 = (0x2) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8 = (0x3) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16 = (0x4) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32 = (0x5) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED = (0x0) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2 = (0x1) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4 = (0x2) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8 = (0x3) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16 = (0x4) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32 = (0x5) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED = (0x0) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2 = (0x1) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4 = (0x2) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8 = (0x3) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16 = (0x4) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32 = (0x5) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64 = (0x6) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED = (0x0) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2 = (0x1) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4 = (0x2) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8 = (0x3) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16 = (0x4) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32 = (0x5) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64 = (0x6) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED = (0x0) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2 = (0x1) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4 = (0x2) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8 = (0x3) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16 = (0x4) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32 = (0x5) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64 = (0x6) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED = (0x0) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2 = (0x1) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4 = (0x2) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8 = (0x3) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16 = (0x4) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32 = (0x5) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64 = (0x6) # type: ignore
|
|
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x30) # type: ignore
|
|
NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID = (0x20801231) # type: ignore
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID = (0x31) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK = (0x20801232) # type: ignore
|
|
NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID = (0x32) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_PPC_MASK = (0x20801233) # type: ignore
|
|
NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID = (0x33) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC = (0x20801234) # type: ignore
|
|
NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID = (0x34) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_CTXSW_MODES = (0x20801235) # type: ignore
|
|
NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID = (0x35) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP = (0x20801236) # type: ignore
|
|
NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID = (0x36) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_ZCULL_MASK = (0x20801237) # type: ignore
|
|
NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID = (0x37) # type: ignore
|
|
NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 = (0x20801238) # type: ignore
|
|
NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID = (0x38) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO = (0x20801239) # type: ignore
|
|
NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID = (0x39) # type: ignore
|
|
NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK = (0x2080123b) # type: ignore
|
|
NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID = (0x3b) # type: ignore
|
|
NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO = (0x20803801) # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES = 96 # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE = 32 # type: ignore
|
|
NV2080_CTRL_GRMGR_MAX_SMC_IDS = 8 # type: ignore
|
|
NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID = 0 # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT = 1 # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP = 2 # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK = 3 # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK = 4 # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP = 5 # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK = 6 # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS = 7 # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK = 8 # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID = 9 # type: ignore
|
|
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK = 10 # type: ignore
|
|
NV2080_CTRL_CMD_GSP_GET_FEATURES = (0x20803601) # type: ignore
|
|
NV2080_GSP_MAX_BUILD_VERSION_LENGTH = (0x0000040) # type: ignore
|
|
NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED = (0, 0) # type: ignore
|
|
NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED = (1, 1) # type: ignore
|
|
NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS = (0x20803602) # type: ignore
|
|
NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS = (0x20803603) # type: ignore
|
|
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS = (0x20803604) # type: ignore
|
|
NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX = 64 # type: ignore
|
|
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK = (0x20804101) # type: ignore
|
|
NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE = (0x20804102) # type: ignore
|
|
NV2080_CTRL_I2C_VERSION_0 = 0x00 # type: ignore
|
|
NV2080_CTRL_I2C_MAX_ENTRIES = 256 # type: ignore
|
|
NV2080_CTRL_I2C_MAX_REG_LEN = 8 # type: ignore
|
|
NV2080_CTRL_I2C_MAX_ADDR_ENTRIES = 20 # type: ignore
|
|
NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC = (0x00000001) # type: ignore
|
|
NV2080_CTRL_I2C_FLAGS_PRIVILEGE = (0x00000002) # type: ignore
|
|
NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED = (0x00000004) # type: ignore
|
|
NV2080_CTRL_I2C_FLAGS_PX3540 = (0x00000010) # type: ignore
|
|
NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED = (0x00000008) # type: ignore
|
|
NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_CMD_I2C_READ_BUFFER = (0x20800601) # type: ignore
|
|
NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_I2C_WRITE_BUFFER = (0x20800602) # type: ignore
|
|
NV2080_CTRL_CMD_I2C_READ_REG = (0x20800603) # type: ignore
|
|
NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_I2C_WRITE_REG = (0x20800604) # type: ignore
|
|
NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV2080_CTRL_CMD_I2C_ACCESS = (0x20800610) # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID = (0x10) # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE = 0x1 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_RELEASE = 0x2 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE = 0x3 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE = 0x4 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_NULL = 0x5 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_RESET = 0x6 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT = 0x11 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE = 0x12 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE = 0x13 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER = 0x14 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER = 0x15 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_START = 0x17 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_STOP = 0x18 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE = 0x20 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_START = 0x1 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_STOP = 0x2 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_ACK = 0x4 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_RAB = 0x8 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS = 0x10 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE = 0x20 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED = 0x40 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_RESTART = 0x80 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT = 0x100 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT = 0x200 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT = 0x400 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT = 0x800 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT = 0x1000 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC = 0x0 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY = 0x1 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY = 0x2 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY = 0x3 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY = 0x4 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_1 = 0x1 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_2 = 0x2 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_3 = 0x3 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_4 = 0x4 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_5 = 0x5 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_6 = 0x6 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_7 = 0x7 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_8 = 0x8 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_9 = 0x9 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_PORT_10 = 0x10 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_NUM_PORTS = NV2080_CTRL_I2C_ACCESS_PORT_10 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS = 0x0 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_STATUS_ERROR = 0x1 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR = 0x2 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY = 0x3 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND = 0x4 # type: ignore
|
|
NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING = 0x5 # type: ignore
|
|
NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE = (0x20800620) # type: ignore
|
|
NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID = (0x20) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO = (0x20800a01) # type: ignore
|
|
NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID = (0x1C) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG = (0x20800a1c) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER = (0x20800a1d) # type: ignore
|
|
NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES = 64 # type: ignore
|
|
NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID = (0x1D) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER = (0x20800a1e) # type: ignore
|
|
NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID = (0x1E) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GR_MAX_ENGINES = 8 # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID = (0x20) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS = (0x20800a1f) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID = (0x1F) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GR_MAX_SM = 240 # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x23) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER = (0x20800a22) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x22) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MAX_BSPS = 8 # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS = 8 # type: ignore
|
|
NV2080_CTRL_INTERNAL_GR_MAX_GPC = 12 # type: ignore
|
|
NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT = 10 # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID = (0x27) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS = (0x20800a26) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID = (0x26) # type: ignore
|
|
NV2080_CTRL_KGR_MAX_BUFFER_PTES = 128 # type: ignore
|
|
NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES = (0x20800a28) # type: ignore
|
|
NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID = (0x28) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x2B) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO = (0x20800a2a) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID = (0x2A) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x2D) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO = (0x20800a2c) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x2C) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x2F) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO = (0x20800a2e) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x2E) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID = (0x31) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS = (0x20800a30) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID = (0x30) # type: ignore
|
|
NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT = 0x1a # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID = (0x33) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO = (0x20800a32) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID = (0x32) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x35) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER = (0x20800a34) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x34) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO = (0x20800a36) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX = 16 # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID = (0x36) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE = (0x20800a37) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE = (0x20800a38) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID = (0x37) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID = (0x38) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET = (0x20800a39) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET = (0x20800a3a) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET = (0x20800a3b) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID = (0x39) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID = (0x3A) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID = (0x3B) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE = (0x20800a3d) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID = (0x3C) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID = (0x3D) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID = (0x3E) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES = (0x20800a3f) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID = (0x3F) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES = 512 # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE = (0x20800a40) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID = (0x40) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP = (0x20800a41) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE = 4096 # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES = 4096 # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID = (0x41) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID = (0x43) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE = (0x20800a44) # type: ignore
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID = (0x44) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE = (0x20800a43) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID = (0x45) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR = (0x20800a46) # type: ignore
|
|
NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID = (0x46) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID = (0x47) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES = (0x20800a48) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID = (0x48) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM = (0x20800a49) # type: ignore
|
|
NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID = (0x49) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS = (0x20800a4a) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION = (0x20800a4b) # type: ignore
|
|
NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID = (0x4B) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE = (0x20800a4c) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID = (0x4C) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR = (0x20800a4d) # type: ignore
|
|
NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID = (0x4D) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES = 60 # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID = (0x4F) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM = (0x20800a51) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID = (0x51) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE = 4 # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID = (0x52) # type: ignore
|
|
NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS = 2 # type: ignore
|
|
NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID = 64 # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS = (0x20800a53) # type: ignore
|
|
NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID = (0x53) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO = (0x20800a54) # type: ignore
|
|
NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID = (0x54) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO = (0x20800a55) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID = (0x55) # type: ignore
|
|
NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM = (0x00000001) # type: ignore
|
|
NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR = (0x20800a70) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL = (0x20800a71) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID = (0x71) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE = (0x20800a72) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID = (0x72) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX = (0x20800a73) # type: ignore
|
|
NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID = (0x73) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING = (0x20800a74) # type: ignore
|
|
NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID = (0x74) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING = (0x20800a75) # type: ignore
|
|
NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID = (0x75) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES = (0x20800a57) # type: ignore
|
|
NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES = 128 # type: ignore
|
|
NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID = (0x57) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER = (0x20800a58) # type: ignore
|
|
NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID = (0x58) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO = (0x20800a59) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x59) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES = (0x20800a5a) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID = (0x5A) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE = (0x20800a5b) # type: ignore
|
|
NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID = (0x5B) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE = (0x20800a5c) # type: ignore
|
|
NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE = 128 # type: ignore
|
|
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID = (0x5C) # type: ignore
|
|
NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK = (0x20800a98) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID = (0x98) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET = (0x20800a99) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID = (0x99) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES = (0x20800a5d) # type: ignore
|
|
NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID = (0x5D) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES = (0x20800a60) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID = 15 # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID = (0x60) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS = (0x20800a61) # type: ignore
|
|
NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID = (0x61) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES = (0x20800a63) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID = (0x63) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES = (0x20800a65) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID = (0x65) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES = (0x20800a66) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID = (0x66) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG = (0x20800a68) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID = (0x68) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG = (0x20800a67) # type: ignore
|
|
NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID = (0x67) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE = (0x20800a6b) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE = 8 # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID = (0x6B) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT = (0x20800a6a) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE = (0x20800a7a) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR = (0x20800a7c) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE = (0x20800a81) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID = (0x81) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X = (0x20800a9a) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID = (0x9A) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE = 0 # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK = 1 # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST = NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL = (0x20800a7e) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID = (0x7E) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS = (0x20800a7f) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID = (0x7F) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO = (0x20800a80) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID = (0x80) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER = (0x20800a9b) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES = 256 # type: ignore
|
|
NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9B) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER = (0x20800a9c) # type: ignore
|
|
NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_FAULT_BUFFER_REPLAYABLE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER = (0x20800a9d) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES = 3000 # type: ignore
|
|
NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9D) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER = (0x20800a9e) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9E) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER = (0x20800a9f) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID = (0x9F) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X = (0x20800aa0) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID = (0xA0) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X = (0x20800aa1) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID = (0xA1) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO = (0x20800aa2) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES = 8 # type: ignore
|
|
NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS = 12 # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID = (0xA2) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE = (0x20800aa3) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID = (0xA3) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE = (0x20800aa4) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA4) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES = (0x20800aa5) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID = (0xA5) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES = (0x20800aa6) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID = (0xA6) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED = (0x20800a69) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID = (0x69) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE = (0x20800aa7) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE = (0x20800aa8) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE = (0x20800aa9) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE = (0x20800aaa) # type: ignore
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE = 4 # type: ignore
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA7) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA8) # type: ignore
|
|
NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA9) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xAA) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT = (0x20800a6c) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID = (0x6c) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL = (0x00000001) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST = (0x00000002) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST = (0x00000004) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL = (0x00000008) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN = (0x00000010) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL = (0x00000020) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES = (0x20800a6d) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO = (0x20800aac) # type: ignore
|
|
NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0xac) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG = (0x20800a88) # type: ignore
|
|
NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID = (0x88) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS = (0x20800a8a) # type: ignore
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE = 32 # type: ignore
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID = (0x8a) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS = (0x20800a8b) # type: ignore
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID = (0x8b) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID = (0x20800a8c) # type: ignore
|
|
NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID = (0x8c) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG = (0x20800a8d) # type: ignore
|
|
NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID = (0x8d) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR = (0x20800aad) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID = (0xae) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR = (0x20800aae) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS = (0x20800ab0) # type: ignore
|
|
NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID = (0xb0) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT = (0x20800ab1) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE = 32 # type: ignore
|
|
NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID = (0xB1) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS = (0x20800a6e) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE = (0x20800a6f) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID = (0x6f) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO = (0x20800ab2) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CCU_MAP = (0x20800ab3) # type: ignore
|
|
NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX = 1 # type: ignore
|
|
NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID = (0xB3) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP = (0x20800ab4) # type: ignore
|
|
NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID = (0xB4) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS = (0x20800ab5) # type: ignore
|
|
NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB5) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS = (0x20800ab6) # type: ignore
|
|
NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB6) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS = (0x20800ab8) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB8) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO = (0x20800ab9) # type: ignore
|
|
NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID = (0xB9) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE = (0x20800a76) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID = (0x76) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE = (0x20800a77) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID = (0x77) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xBB) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES = (0x20800aba) # type: ignore
|
|
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xBA) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE = (0x20800abd) # type: ignore
|
|
NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID = (0xBD) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT = (0x20800abe) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID = (0xBE) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS = (0x20800abf) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID = (0xBF) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS = (0x20800ac0) # type: ignore
|
|
NV2080_MAX_NUM_HEADS = 4 # type: ignore
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID = (0xC0) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC = (0x20800ac1) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID = (0xC1) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES = (0x20800ac4) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID = (0xC4) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID = (0x20800ac9) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID = (0xC9) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC = (0x20800aca) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID = (0xCA) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_FBSR_INIT = (0x20800ac2) # type: ignore
|
|
NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID = (0xC2) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING = (0x20800ac3) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID = (0xC3) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB = (0x20800ac5) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID = (0xC5) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD = (0x20800ac6) # type: ignore
|
|
NV2080_CTRL_ACPI_DSM_READ_SIZE = (0x1000) # type: ignore
|
|
NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID = (0xC6) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID = (0xC7) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL = (0x20800ac7) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID = (0xC8) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL = (0x20800ac8) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE = (0x20800acb) # type: ignore
|
|
NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID = (0xCB) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR = 0x00 # type: ignore
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM = 0x01 # type: ignore
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI = 0x02 # type: ignore
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD = 0x00 # type: ignore
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT = 0x01 # type: ignore
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR = 0x02 # type: ignore
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET = 0x03 # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC = (0x20800acc) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID = (0xCC) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC = (0x20800acd) # type: ignore
|
|
NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID = (0xCD) # type: ignore
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS = 0x00 # type: ignore
|
|
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS = 0x01 # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE = (0x20800ace) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID = (0xCE) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE = (0x20800acf) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID = (0xCF) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT = (0x20800ad0) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID = (0xD0) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT = (0x20800ad1) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID = (0xD1) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE = (0x20800ad2) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID = (0xD2) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 = (0x20800ad3) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID = (0xD3) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO = (0x20800ad4) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID = (0xD4) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING = (0x20800ad5) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID = (0xD5) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE = (0x20800ad6) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID = (0xD6) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE = (0x2080a7d7) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID = (0xD7) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT = (0x20800a7b) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS = (0x20800ad8) # type: ignore
|
|
NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0xD8) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS = (0x20800adb) # type: ignore
|
|
NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID = (0xDB) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS = (0x20800adc) # type: ignore
|
|
NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID = (0xDC) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE = (0x20800add) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL = (0x20800ade) # type: ignore
|
|
NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID = (0xDE) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA = (0x20800adf) # type: ignore
|
|
MAX_EDID_SIZE_FROM_SBIOS = 512 # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID = (0xDF) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED = (0x20800af0) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET = (0x20800af1) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET = (0x20800af2) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF4) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO = (0x208001f4) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF5) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE = (0x208001f5) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE = (0x208001f6) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE = (0x208001f7) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF8) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE = (0x208001f8) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE = (0x208001f9) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO = (0x20800af3) # type: ignore
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0xF3) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS = (0x20800ae1) # type: ignore
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE = 3 # type: ignore
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL = 0 # type: ignore
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER = 1 # type: ignore
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER = 2 # type: ignore
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT = 3 # type: ignore
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT = 6 # type: ignore
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID = (0xE1) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS = (0x20800ae2) # type: ignore
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID = (0xE2) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS = (0x20800ae5) # type: ignore
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID = (0xE5) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION = (0x20800ae6) # type: ignore
|
|
NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID = (0xE6) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE = (0x20800ae7) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID = (0xE7) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY = (0x20800ae8) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID = (0xE8) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID = (0x20800aef) # type: ignore
|
|
NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID = (0xEF) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP = (0x20800afa) # type: ignore
|
|
CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES = (0x10) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID = (0xFA) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG = (0x20800afb) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID = (0xFB) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG = (0x20800afc) # type: ignore
|
|
NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID = (0xFC) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO = (0x20800afd) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID = (0xFD) # type: ignore
|
|
NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID = (0xFE) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA = (0x20800afe) # type: ignore
|
|
NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID = (0xFF) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL = (0x20800aff) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID = (0xE3) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_OLDEST = 0x00 # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_NEWEST = 0x01 # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_STOP = 0x02 # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE = (0x208001e3) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID = (0xAF) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES = (0x20800aaf) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND = (0x20800ae4) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID = (0xE4) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID = (0xE9) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER = (0x20800ae9) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY = (0x20800aea) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID = (0xEA) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID = (0xEB) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP = (0x20800aeb) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID = (0xEC) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM = (0x20800aec) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID = (0xED) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR = (0x20800aed) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM = (0x20800a79) # type: ignore
|
|
NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID = (0x79) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID = (0x14) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE = (0x20800a14) # type: ignore
|
|
NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID = (0xEE) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_GPU_GET_PF_BAR1_SPA = (0x20800aee) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER = (0x20800a21) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x21) # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_OFF = 0x00 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_HS = 0x01 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAFE = 0x02 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAULT = 0x03 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RECOVERY = 0x04 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAIL = 0x05 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DETECT = 0x06 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESET = 0x07 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ENABLE_PM = 0x08 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_PM = 0x09 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SLEEP = 0x0A # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAVE_STATE = 0x0B # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESTORE_STATE = 0x0C # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_PRE_HS = 0x0E # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT = 0x0F # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_DISABLE = 0x10 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN = 0x11 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP = 0x12 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE1 = 0x13 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITNEGOTIATE = 0x14 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE = 0x15 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITOPTIMIZE = 0x16 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE = 0x17 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT = 0x18 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_CONTAIN = 0x19 # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITTL = 0x1A # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE5 = 0x1B # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ALI = 0x1C # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING = 0x1D # type: ignore
|
|
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INVALID = 0xFF # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS = 0x00 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE = 0x04 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER = 0x04 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN = 0x05 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE = 0x06 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF = 0x07 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE = 0x08 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE = 0x09 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY = 0x0A # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ = 0x0B # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN = 0x0C # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS = 0x0D # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS = 0x00 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE = 0x04 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER = 0x04 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN = 0x05 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE = 0x06 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF = 0x07 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL = 0x08 # type: ignore
|
|
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM = 0x09 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM = 6 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE = (0x7) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE = 0x00 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE = 0x01 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE = 0x02 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE = 0x03 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE = 0x04 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE = 0x05 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE = 0x06 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE = 0x07 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT = 0x08 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT = 0x09 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN = 0x0A # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN = 0x0B # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE = 0x0C # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD = 0x0D # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID = (0x24) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK = (0x20800a24) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID = (0x25) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID = (0x20800a25) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID = (0x29) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED = (0x20800a29) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM = 0x0 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET = 0x1 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID = (0x42) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX = (0x20800a42) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x4E) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER = (0x20800a4e) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x50) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER = (0x20800a50) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID = (0x20800a56) # type: ignore
|
|
NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE = (81) # type: ignore
|
|
NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID = (0x56) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM = 0x1 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER = 0x2 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID = (0x5F) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING = (0x20800a5f) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID = (0x62) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE = (0x20800a62) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET = (0x00000000) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE = (0x00000002) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID = (0x64) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY = (0x20800a64) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID = (0x78) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG = (0x20800a78) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID = (0x7D) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK = (0x20800a7d) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID = (0x82) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION = (0x20800a82) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID = (0x83) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY = (0x20800a83) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID = (0x84) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI = (0x20800a84) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE = 64 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID = (0x85) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET = (0x20800a85) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID = (0x86) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI = (0x20800a86) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x87) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO = (0x20800a87) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_MAX_LINKS_PER_IOCTRL_SW = 6 # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x8E) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO = (0x20800a8e) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID = (0x8F) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED = (0x20800a8f) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID = (0x90) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED = (0x20800a90) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_ASSERT = (0x00000000) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_DEASSERT = (0x00000001) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_TOGGLE = (0x00000002) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID = (0x91) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS = (0x20800a91) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID = (0x92) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS = (0x20800a92) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID = (0x93) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO = (0x20800a93) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID = (0x94) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM = (0x20800a94) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID = (0x95) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS = (0x20800a95) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID = (0x96) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS = (0x20800a96) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID = (0x97) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS = (0x20800a97) # type: ignore
|
|
NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID = (0xAB) # type: ignore
|
|
NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK = (0x20800aab) # type: ignore
|
|
NV2080_CTRL_CMD_LPWR_DIFR_CTRL = (0x20802801) # type: ignore
|
|
NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE = (0x00000002) # type: ignore
|
|
NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS = (0x00000003) # type: ignore
|
|
NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_LPWR_DIFR_SUPPORTED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED = (0x00000002) # type: ignore
|
|
NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE = (0x20802802) # type: ignore
|
|
NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS = (0x00000001) # type: ignore
|
|
NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED = (0x00000002) # type: ignore
|
|
NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE = (0x00000003) # type: ignore
|
|
NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR = (0x00000004) # type: ignore
|
|
NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_MC_GET_ARCH_INFO = (0x20801701) # type: ignore
|
|
NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X = (0xE0000023) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 = (0x00000160) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 = (0x00000170) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100 = (0x00000180) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 = (0x00000190) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100 = (0x000001A0) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200 = (0x000001B0) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D = (0x00000005) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106 = (0x00000006) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116 = (0x00000008) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117 = (0x00000007) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106 = (0x00000006) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107 = (0x00000007) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B = (0x0000000B) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC = (0x00000001) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106 = (0x00000006) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107 = (0x00000007) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD10B = (0x0000000B) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB204 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 = (0x00000005) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 = (0x00000006) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 = (0x00000007) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION = (0x00000000) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P = (0x00000001) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q = (0x00000002) # type: ignore
|
|
NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R = (0x00000003) # type: ignore
|
|
NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS = (0x20801702) # type: ignore
|
|
NV2080_CTRL_MC_ENGINE_ID_GRAPHICS = 0x00000001 # type: ignore
|
|
NV2080_CTRL_MC_ENGINE_ID_ALL = 0xFFFFFFFF # type: ignore
|
|
NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_MC_GET_MANUFACTURER = (0x20801703) # type: ignore
|
|
NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP = (0x2080170c) # type: ignore
|
|
NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID = (0xC) # type: ignore
|
|
NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS = (0x2080170d) # type: ignore
|
|
NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES = 256 # type: ignore
|
|
NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID = (0xD) # type: ignore
|
|
NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE = (0x2080170e) # type: ignore
|
|
NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX = 32 # type: ignore
|
|
NV2080_INTR_TYPE_NULL = (0x00000000) # type: ignore
|
|
NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT = (0x00000001) # type: ignore
|
|
NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR = (0x00000002) # type: ignore
|
|
NV2080_INTR_TYPE_INFO_FAULT = (0x00000003) # type: ignore
|
|
NV2080_INTR_TYPE_REPLAYABLE_FAULT = (0x00000004) # type: ignore
|
|
NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR = (0x00000005) # type: ignore
|
|
NV2080_INTR_TYPE_ACCESS_CNTR = (0x00000006) # type: ignore
|
|
NV2080_INTR_TYPE_TMR = (0x00000007) # type: ignore
|
|
NV2080_INTR_TYPE_CPU_DOORBELL = (0x00000008) # type: ignore
|
|
NV2080_INTR_TYPE_GR0_FECS_LOG = (0x00000009) # type: ignore
|
|
NV2080_INTR_TYPE_GR1_FECS_LOG = (0x0000000A) # type: ignore
|
|
NV2080_INTR_TYPE_GR2_FECS_LOG = (0x0000000B) # type: ignore
|
|
NV2080_INTR_TYPE_GR3_FECS_LOG = (0x0000000C) # type: ignore
|
|
NV2080_INTR_TYPE_GR4_FECS_LOG = (0x0000000D) # type: ignore
|
|
NV2080_INTR_TYPE_GR5_FECS_LOG = (0x0000000E) # type: ignore
|
|
NV2080_INTR_TYPE_GR6_FECS_LOG = (0x0000000F) # type: ignore
|
|
NV2080_INTR_TYPE_GR7_FECS_LOG = (0x00000010) # type: ignore
|
|
NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID = (0xE) # type: ignore
|
|
NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE = (0x20802401) # type: ignore
|
|
NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_CMD_NVD_GET_DUMP = (0x20802402) # type: ignore
|
|
NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL = (0x20802409) # type: ignore
|
|
NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER = 1024 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_MAX_STR_LEN = 65 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS = 10 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS = 32 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN = 0 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK = 1 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE = 2 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_TDR = 3 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_RC = 4 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT = 5 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_ANY = 6 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT = (0x7) # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX = 0 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX = 1 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX = 2 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX = 3 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX = 4 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATION_FAIL_IDX = 5 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX = 6 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX = 7 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX = 8 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX = 9 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX = 10 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX = 11 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX = 12 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX = 13 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX = 14 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX = 15 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX = 16 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX = 17 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX = 18 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX = 19 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX = 20 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX = 21 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX = 22 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX = 23 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX = 24 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX = 25 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX = 26 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX = 27 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX = 28 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX = 29 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX = 30 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX = 31 # type: ignore
|
|
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT = (0x20) # type: ignore
|
|
NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY = (0, 0) # type: ignore
|
|
NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES = 1 # type: ignore
|
|
NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO = 0 # type: ignore
|
|
NV2080_CTRL_NOCAT_GET_RESET_COUNTERS = (1, 1) # type: ignore
|
|
NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES = 1 # type: ignore
|
|
NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO = 0 # type: ignore
|
|
NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA = (0x2080240b) # type: ignore
|
|
NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY = 0 # type: ignore
|
|
NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON = 1 # type: ignore
|
|
NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG = 2 # type: ignore
|
|
NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG = 3 # type: ignore
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_NONE = 0 # type: ignore
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY = 1 # type: ignore
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP = 2 # type: ignore
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET = 3 # type: ignore
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET = 4 # type: ignore
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL = 5 # type: ignore
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET = 6 # type: ignore
|
|
NV2080_CTRL_NOCAT_TDR_TYPE_TEST = 7 # type: ignore
|
|
NV2080_CTRL_NOCAT_TAG_CLEAR = (0, 0) # type: ignore
|
|
NV2080_CTRL_NOCAT_TAG_CLEAR_YES = 1 # type: ignore
|
|
NV2080_CTRL_NOCAT_TAG_CLEAR_NO = 0 # type: ignore
|
|
NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID = (0xB) # type: ignore
|
|
NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD = (0x2080240c) # type: ignore
|
|
NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR = (0, 0) # type: ignore
|
|
NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES = 1 # type: ignore
|
|
NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO = 0 # type: ignore
|
|
NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER = (1, 1) # type: ignore
|
|
NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES = 1 # type: ignore
|
|
NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO = 0 # type: ignore
|
|
NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID = (0xC) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_TBL_SIZE = 2 # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 = (0x00000005) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 = (0x00000006) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 = (0x00000007) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0 = (0x00000008) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 = (0x00000005) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 = (0x00000006) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 = (0x00000007) # type: ignore
|
|
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0 = (0x00000008) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS = (0x20803001) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS = (31, 0) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID = (0x00000002) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU = (0x00000002) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH = (0x00000003) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE = (0x000000FF) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID = (0xFFFFFFFF) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED = (0, 0) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY = (1, 1) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_INACTIVE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_ACTIVE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG = (0x00000002) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE = (0x00000003) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP = (0x00000005) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY = (0x00000006) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC = (0x00000008) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX = (0x0000000a) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID = (0xFFFFFFFF) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING = (0x00000005) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE = (0x00000006) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF = (0x00000007) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST = (0x00000008) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT = (0x0000000e) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID = (0x000000FF) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING = (0x00000005) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE = (0x00000006) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF = (0x00000007) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST = (0x00000008) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT = (0x0000000e) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID = (0x000000FF) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_PHY_NVHS = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_PHY_GRS = (0x00000002) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_PHY_INVALID = (0x000000FF) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 = (0x00000005) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 = (0x00000006) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 = (0x00000007) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0 = (0x00000008) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID = (0x000000FF) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0 = (0x00000005) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 = (0x00000006) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 = (0x00000007) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0 = (0x00000008) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID = (0x000000FF) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID = (0x000000FF) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID = (0x000000FF) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT = (0x00000002) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID = (0x000000FF) # type: ignore
|
|
NV2080_CTRL_NVLINK_MAX_LINKS = 32 # type: ignore
|
|
NV2080_CTRL_NVLINK_MAX_ARR_SIZE = 64 # type: ignore
|
|
NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID = (0x00) # type: ignore
|
|
NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS = (0x01) # type: ignore
|
|
NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX = (0x02) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS = (0x20803002) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT = lambda intr,i: (((1 << i) & (intr)) >> i) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_TL_INTEN_BIT = lambda intr,i: NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i) # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_FALSE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN = 0 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN = 1 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN = 2 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN = 3 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN = 4 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN = 5 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN = 6 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN = 7 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN = 8 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN = 9 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN = 10 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN = 12 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN = 13 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX = 14 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR = 0 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR = 1 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR = 2 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR = 3 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR = 4 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR = 5 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR = 6 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR = 7 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR = 8 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR = 9 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR = 10 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR = 12 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR = 13 # type: ignore
|
|
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX = 14 # type: ignore
|
|
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN = (0x00000005) # type: ignore
|
|
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE = (0x00000006) # type: ignore
|
|
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF = (0x00000007) # type: ignore
|
|
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN = (0x00000005) # type: ignore
|
|
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE = (0x00000006) # type: ignore
|
|
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF = (0x00000007) # type: ignore
|
|
NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT = (0x0) # type: ignore
|
|
NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS = (0x1) # type: ignore
|
|
NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS = (0x2) # type: ignore
|
|
NV2080_CTRL_NVLINK_MAX_IOCTRLS = 3 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO = (0x20803003) # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_INVALID = 0x00000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TL_TX0 = 0x00000001 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TL_TX1 = 0x00000002 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TL_RX0 = 0x00000004 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TL_RX1 = 0x00000008 # type: ignore
|
|
NV2080_CTRL_NVLINK_LP_COUNTERS_DL = 0x00000010 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L = lambda i: (1 << (i + 8)) # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE = 4 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0 = 0x00000100 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1 = 0x00000200 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2 = 0x00000400 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3 = 0x00000800 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT = 0x00010000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L = lambda i: (1 << (i + 17)) # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE = 8 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 = 0x00020000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 = 0x00040000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 = 0x00080000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 = 0x00100000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 = 0x00200000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 = 0x00400000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 = 0x00800000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 = 0x01000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY = 0x02000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY = 0x04000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY = 0x08000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED = 0x10000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES = 32 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_COUNTERS = (0x20803004) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS = (0x20803005) # type: ignore
|
|
NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX0 = 0 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX1 = 1 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX0 = 2 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX1 = 3 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_SIZE = 4 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L0 = 4 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L1 = 5 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L2 = 6 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L3 = 7 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_SIZE = 8 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L0 = 8 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L1 = 9 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L2 = 10 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L3 = 11 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L4 = 12 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L5 = 13 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L6 = 14 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L7 = 15 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_RECOVERY = 16 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_REPLAY = 17 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_REPLAY = 18 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_MASKED = 19 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_FLIT = 20 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_DL = 21 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER = NV2080_CTRL_NVLINK_COUNTER_LP_DL # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_XMIT_PACKETS = 22 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_XMIT_BYTES = 23 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_PACKETS = 24 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_BYTES = 25 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LINK_ERROR_RECOVERY_COUNTER = 26 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LINK_DOWNED_COUNTER = 27 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LINK_RECOVERY_SUCCESSFUL_COUNTER = 28 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_ERRORS = 29 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_REMOTE_ERRORS = 30 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_GENERAL_ERRORS = 31 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_MALFORMED_PKT_ERROR = 32 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_BUFFER_OVERRUN_ERROR = 33 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RCV_VL15DROPPED_ERROR = 34 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LINK_INTEGRITY_ERRORS = 35 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_BUFFER_OVERRUN_ERRORS = 36 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_XMIT_WAIT_TIME = 37 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_XMIT_ERRORS = 38 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_SINGLE_ERROR_BLOCKS = 39 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BLOCKS = 40 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_UNCORRECTED_BLOCKS = 41 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_0 = 42 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_1 = 43 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_TOTAL = 44 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_0 = 45 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_1 = 46 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BITS = 47 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_0 = 48 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_1 = 49 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RAW_BER_TOTAL = 50 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_NO_ERROR_BLOCKS = 51 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_ERRORS = 52 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_BER = 53 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_SYMBOL_ERRORS = 54 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_SYMBOL_BER = 55 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_RECEIVED_BITS = 56 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_SYNC_HEADER_ERRORS = 57 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TIME_SINCE_LAST_CLEAR = 58 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS = 59 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_UNCORRECTABLE_ERRORS = 60 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_ERRORS = 61 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_BLOCKS = 62 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_BLOCKS = 63 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS = 64 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_PLR_BW_LOSS = 65 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_GOOD = 66 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_ERROR = 67 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_AUTH = 68 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_GOOD = 69 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_ERROR = 70 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_0 = 71 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_1 = 72 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_2 = 73 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_3 = 74 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_4 = 75 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_5 = 76 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_6 = 77 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_7 = 78 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_8 = 79 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_9 = 80 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_10 = 81 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_11 = 82 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_12 = 83 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_13 = 84 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_14 = 85 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_HISTORY_15 = 86 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_RX_DATA = 87 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_TX_DATA = 88 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_RX_RAW = 89 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_TP_TX_RAW = 90 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY = 91 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY_FORCE = 92 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_EXIT = 93 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_RECAL = 94 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_REMOTE = 95 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_LP_STEADY_STATE_TIME = 96 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_HIGH_SPEED_STEADY_STATE_TIME = 97 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_L1_OTHER_STATE_TIME = 98 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_ENTRY_TIME = 99 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_EXIT_TIME = 100 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_ENTRY_TIME = 101 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_EXIT_TIME = 102 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_ENTRY_TIME = 103 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_EXIT_TIME = 104 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_ENTRY_TIME = 105 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_EXIT_TIME = 106 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTERS_MAX = 107 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS = 2 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ = 28 # type: ignore
|
|
NV2080_CTRL_NVLINK_COUNTER_V2_GROUP = lambda i: ((i) / 64) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID = (0x50) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2 = (0x20803050) # type: ignore
|
|
NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID = (0x51) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2 = (0x20803051) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_INJECT_ERROR = (0x20803006) # type: ignore
|
|
NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV2080_CTRL_NVLINK_UNIT_DL = 0x01 # type: ignore
|
|
NV2080_CTRL_NVLINK_UNIT_TL = 0x02 # type: ignore
|
|
NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 = 0x03 # type: ignore
|
|
NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 = 0x04 # type: ignore
|
|
NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 = 0x05 # type: ignore
|
|
NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 = 0x06 # type: ignore
|
|
NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 = 0x07 # type: ignore
|
|
NV2080_CTRL_NVLINK_UNIT_MINION = 0x08 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE = (31, 28) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_NO_ERROR = 0x00000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_RAW_BER = 0x00000001 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_EFFECTIVE_BER = 0x00000002 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_ERR_INJECT_DURATION = (27, 12) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_MANTISSA = (11, 8) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_EXPONENT = (7, 0) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_INJECT_COUNT = (15, 0) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP = (16, 16) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_DIS = 0x00000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_EN = 0x00000001 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON = (17, 17) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_DIS = 0x00000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_EN = 0x00000001 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_CLEAR_COUNTERS = (18, 18) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_PIPE_INDEX = (3, 0) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR = (4, 4) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_DIS = 0x00000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_EN = 0x00000001 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN = (0, 0) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_DIS = 0x00000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_EN = 0x00000001 # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID = (0x81) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT = (0x20803081) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE = (1, 0) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_UP = 0x00000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_REQUEST = 0x00000001 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_HW_ERR = 0x00000002 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS = (0, 0) # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_NO_ERR_INJECT = 0x00000000 # type: ignore
|
|
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_PERFORMING_ERR_INJECT = 0x00000001 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID = (0x82) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT = (0x20803082) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES = (0x20803007) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE = (0x20803008) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS = (0x20803009) # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY = 0 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY = 1 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL = 2 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW = 3 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY = 4 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY = 5 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP = 6 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON = 7 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY = 8 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY = 9 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT = 10 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY = 11 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY = 12 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG = 13 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM = 14 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE = 15 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE = 16 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE = 17 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL = 18 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT = 19 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY = 0 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY = 1 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY = 4 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY = 5 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD = 7 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY = 8 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY = 9 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY = 11 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY = 20 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD = 21 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD = 22 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN = 23 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN = 24 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC = 25 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC = 26 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE = 27 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS = 28 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS = 29 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ = 30 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP = 31 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE = 32 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE = 33 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE = 34 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR = 35 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP = 36 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET = 37 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST = 38 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW = 39 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW = 40 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD = 41 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL = 42 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW = 43 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE = 44 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE = 45 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW = 46 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW = 47 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW = 48 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW = 49 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT = 50 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT = 51 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET = 52 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST = 53 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY = 54 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY = 55 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY = 56 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY = 57 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE = 58 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE = 59 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY = 60 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP = 61 # type: ignore
|
|
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN = 62 # type: ignore
|
|
NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES = 63 # type: ignore
|
|
NV2080_CTRL_NVLINK_IS_FATAL_ERROR_COUNT_VALID = lambda count,supportedCounts: ( not not ((supportedCounts) & NVBIT64(count))) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES = (0x2080300a) # type: ignore
|
|
NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES = 5 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID = (0xA) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE = (0x2080300b) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID = (0xB) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_SETUP_EOM = (0x2080300c) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID = (0xC) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE = (0x2080300d) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID = (0xD) # type: ignore
|
|
NV2080_CTRL_NVLINK_POWER_STATE_L0 = (0x00) # type: ignore
|
|
NV2080_CTRL_NVLINK_POWER_STATE_L1 = (0x01) # type: ignore
|
|
NV2080_CTRL_NVLINK_POWER_STATE_L2 = (0x02) # type: ignore
|
|
NV2080_CTRL_NVLINK_POWER_STATE_L3 = (0x03) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE = (0x2080300e) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID = (0xE) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR = (0x2080300f) # type: ignore
|
|
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID = (0xF) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES = (0x20803011) # type: ignore
|
|
NV2080_CTRL_NVLINK_MAX_LANES = 4 # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID = (0x11) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER = (0x20803012) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x12) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG = (0x20803013) # type: ignore
|
|
NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID = (0x13) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID = (0x14) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS = (0x20803014) # type: ignore
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX = 0 # type: ignore
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX = 1 # type: ignore
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX = 2 # type: ignore
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX = 3 # type: ignore
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX = 4 # type: ignore
|
|
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID = (0x15) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS = (0x20803015) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE = (0x20803016) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID = (0x16) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS = 0 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH = 1 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER = 2 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER = 3 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT = 4 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP = 5 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME = 6 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME = 7 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME = 8 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME = 9 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME = 10 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME = 11 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME = 12 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME = 13 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME = 14 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME = 15 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS = 16 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID = (0x18) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS = (0x20803018) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS = (0x20803052) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT = (0x00000000) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA = (0x00000001) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR = (0x00000002) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW = (0x00000003) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_REMOTE = (0x00000004) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_LOCAL = (0x00000005) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_EXT_LOCAL = (0x00000006) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID = (0x23) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE = (0x20803023) # type: ignore
|
|
NV2080_CTRL_NVLINK_MAX_LINK_COUNT = 32 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID = (0x28) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS = (0x20803028) # type: ignore
|
|
NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID = (0x29) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS = (0x20803029) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID = (0x38) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR = (0x20803038) # type: ignore
|
|
NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID = (0x39) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO = (0x20803039) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS = (0x2080303a) # type: ignore
|
|
NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID = (0x3b) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS = (0x2080303b) # type: ignore
|
|
NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID = (0x3c) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_EOM_CONTROL = (0x2080303c) # type: ignore
|
|
NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE = 5120 # type: ignore
|
|
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID = (0x3d) # type: ignore
|
|
NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE = (0x2080303d) # type: ignore
|
|
NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT = (0xFFFFFFFF) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID = (0x3e) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD = (0x2080303e) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID = (0x3f) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD = (0x2080303f) # type: ignore
|
|
NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID = (0x40) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA = (0x20803040) # type: ignore
|
|
NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID = (0x41) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED = (0x20803041) # type: ignore
|
|
NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID = (0x42) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK = (0x20803042) # type: ignore
|
|
NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID = (0x43) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP = (0x20803043) # type: ignore
|
|
NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE = 64 # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID = (0x44) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS = (0x20803044) # type: ignore
|
|
NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID = (0x45) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_CYCLE_LINK = (0x20803045) # type: ignore
|
|
NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID = (0x46) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG = (0x20803046) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH = 496 # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PAOS = (0x20803047) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS_MESSAGE_ID = (0x47) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY = (0x20803048) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLTC = (0x20803053) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID = (0x53) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLM = (0x20803054) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS_MESSAGE_ID = (0x54) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLC = (0x20803055) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID = (0x55) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCAM = (0x20803056) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID = (0x56) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTECR = (0x2080305c) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS_MESSAGE_ID = (0x5c) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEWE = (0x2080305e) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID = (0x5e) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSDE = (0x2080305f) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS_MESSAGE_ID = (0x5f) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTCAP = (0x20803061) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID = (0x61) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMTU = (0x20803062) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS_MESSAGE_ID = (0x62) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMLP = (0x20803064) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID = (0x64) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_GHPKT = (0x20803065) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID = (0x65) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PDDR = (0x20803066) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS_MESSAGE_ID = (0x66) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT = (0x20803068) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID = (0x68) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPCNT = (0x20803069) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS_MESSAGE_ID = (0x69) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MGIR = (0x2080306a) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS_MESSAGE_ID = (0x6a) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPAOS = (0x2080306b) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS_MESSAGE_ID = (0x6b) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPHCR = (0x2080306c) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID = (0x6c) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLTP = (0x2080306d) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS_MESSAGE_ID = (0x6d) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PGUID = (0x2080306e) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID = (0x6e) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRT = (0x2080306f) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS_MESSAGE_ID = (0x6f) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTYS = (0x20803070) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS_MESSAGE_ID = (0x70) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLRG = (0x20803071) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS_MESSAGE_ID = (0x71) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMAOS = (0x20803072) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS_MESSAGE_ID = (0x72) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLR = (0x20803073) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS_MESSAGE_ID = (0x73) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS = (0x20803074) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID = (0x74) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MORD = (0x20803075) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS_MESSAGE_ID = (0x75) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CAP = (0x20803076) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS_MESSAGE_ID = (0x76) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CONF = (0x20803077) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS_MESSAGE_ID = (0x77) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CTRL = (0x20803078) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS_MESSAGE_ID = (0x78) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEIM = (0x20803079) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS_MESSAGE_ID = (0x79) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIE = (0x2080307a) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS_MESSAGE_ID = (0x7a) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIM = (0x2080307b) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS_MESSAGE_ID = (0x7b) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MPSCR = (0x2080307c) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS_MESSAGE_ID = (0x7c) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR = (0x2080307d) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID = (0x7d) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLS = (0x2080307e) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS_MESSAGE_ID = (0x7e) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MLPC = (0x2080307f) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS_MESSAGE_ID = (0x7f) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLIB = (0x20803080) # type: ignore
|
|
NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS_MESSAGE_ID = (0x80) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO = (0x20803083) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID = (0x83) # type: ignore
|
|
NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS = 18 # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN = (0x20803084) # type: ignore
|
|
NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID = (0x84) # type: ignore
|
|
NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT = 23 # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE = (0x20803085) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID = (0x85) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_SET_BW_MODE = (0x20803086) # type: ignore
|
|
NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID = (0x86) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_BW_MODE = (0x20803087) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID = (0x87) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO = (0x20803088) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x88) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR = (0x20803089) # type: ignore
|
|
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID = (0x89) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY = (0x2080308a) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_CONFIGURE_L1_TOGGLE = (0x2080308e) # type: ignore
|
|
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID = (0x8E) # type: ignore
|
|
NV2080_CTRL_CMD_NVLINK_GET_L1_TOGGLE = (0x2080308f) # type: ignore
|
|
NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID = (0x8F) # type: ignore
|
|
NV_SUBPROC_NAME_MAX_LENGTH = 100 # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CMD = (1, 0) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR = (0x00000000) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL = (0x00000001) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX = (0x00000002) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA = (4, 4) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC = (5, 5) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO = (0x00000000) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES = (0x00000001) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY = (6, 6) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT = (0x00000000) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH = (0x00000001) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_DURATION_MAX = 3600 # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_DURATION_INFINITE = 0xffffffff # type: ignore
|
|
NV2080_CTRL_CMD_PERF_BOOST = (0x2080200a) # type: ignore
|
|
NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID = (0xA) # type: ignore
|
|
NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW = (0x20802093) # type: ignore
|
|
NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID = (0x93) # type: ignore
|
|
NV2080_CTRL_PERF_POWER_SOURCE_AC = (0x00000000) # type: ignore
|
|
NV2080_CTRL_PERF_POWER_SOURCE_BATTERY = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_PERF_SET_POWERSTATE = (0x2080205b) # type: ignore
|
|
NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID = (0x5B) # type: ignore
|
|
NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE = (0x20802092) # type: ignore
|
|
NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID = (0x92) # type: ignore
|
|
NV2080_CTRL_PERF_AUX_POWER_STATE_P0 = (0x00000000) # type: ignore
|
|
NV2080_CTRL_PERF_AUX_POWER_STATE_P1 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_PERF_AUX_POWER_STATE_P2 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_PERF_AUX_POWER_STATE_P3 = (0x00000003) # type: ignore
|
|
NV2080_CTRL_PERF_AUX_POWER_STATE_P4 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT = (0x00000005) # type: ignore
|
|
NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID = (0x6D) # type: ignore
|
|
NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL = (0x2080206e) # type: ignore
|
|
NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID = (0x6E) # type: ignore
|
|
NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL = (0x2080206f) # type: ignore
|
|
NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID = (0x6F) # type: ignore
|
|
NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID = (0x83) # type: ignore
|
|
NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL = 72 # type: ignore
|
|
NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 = (0x20802096) # type: ignore
|
|
NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID = (0x96) # type: ignore
|
|
NV2080_CTRL_CMD_PERF_GPU_IS_IDLE = (0x20802089) # type: ignore
|
|
NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID = (0x89) # type: ignore
|
|
NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE = (0x00000002) # type: ignore
|
|
NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY = (0x2080208f) # type: ignore
|
|
NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID = (0x8F) # type: ignore
|
|
NV2080_CTRL_PERF_CLK_MAX_DOMAINS = 32 # type: ignore
|
|
NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO = (0x20802002) # type: ignore
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2 = (0x2080200b) # type: ignore
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID = (0xB) # type: ignore
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE = (0, 0) # type: ignore
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT = (0x00000000) # type: ignore
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK = (0x00000001) # type: ignore
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE = (2, 1) # type: ignore
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP = (0x00000001) # type: ignore
|
|
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF = (0x00000002) # type: ignore
|
|
NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE = (0x20802087) # type: ignore
|
|
NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID = (0x87) # type: ignore
|
|
NV2080_CTRL_CMD_PERF_GET_POWERSTATE = (0x2080205a) # type: ignore
|
|
NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID = (0x5A) # type: ignore
|
|
NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT = (0x2080205d) # type: ignore
|
|
NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID = (0x5D) # type: ignore
|
|
NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK = (0x0000ffff) # type: ignore
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START = (0x00000001) # type: ignore
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP = (0x00000002) # type: ignore
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START = NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START # type: ignore
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP = NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP # type: ignore
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START = (0x00000003) # type: ignore
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP = (0x00000004) # type: ignore
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START = (0x00000005) # type: ignore
|
|
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP = (0x00000006) # type: ignore
|
|
NV2080_CTRL_PERF_VIDEOEVENT_OFA_START = (0x00000007) # type: ignore
|
|
NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP = (0x00000008) # type: ignore
|
|
NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE = (0x00010000) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_UNDEFINED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_MIN = (0x00000001) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P0 = (0x00000001) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P1 = (0x00000002) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P2 = (0x00000004) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P3 = (0x00000008) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P4 = (0x00000010) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P5 = (0x00000020) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P6 = (0x00000040) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P7 = (0x00000080) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P8 = (0x00000100) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P9 = (0x00000200) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P10 = (0x00000400) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P11 = (0x00000800) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P12 = (0x00001000) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P13 = (0x00002000) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P14 = (0x00004000) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_P15 = (0x00008000) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_MAX = NV2080_CTRL_PERF_PSTATES_P15 # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY = (0x10000) # type: ignore
|
|
NV2080_CTRL_PERF_PSTATES_ALL = (0xffff) # type: ignore
|
|
NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE = (0x20802068) # type: ignore
|
|
NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID = (0x68) # type: ignore
|
|
NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED = 0 # type: ignore
|
|
NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED = 1 # type: ignore
|
|
NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE = 2 # type: ignore
|
|
NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO = (0x20802609) # type: ignore
|
|
NV2080_CTRL_CMD_GC6_ENTRY = (0x2080270d) # type: ignore
|
|
NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID = (0xD) # type: ignore
|
|
NV2080_CTRL_CMD_GC6_EXIT = (0x2080270e) # type: ignore
|
|
NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID = (0xE) # type: ignore
|
|
NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM = (0x20802204) # type: ignore
|
|
NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV2080_CTRL_CMD_RC_GET_ERROR_COUNT = (0x20802205) # type: ignore
|
|
NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE = (0x2000) # type: ignore
|
|
NV2080_CTRL_CMD_RC_GET_ERROR = (0x20802206) # type: ignore
|
|
NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID = (0x13) # type: ignore
|
|
NV2080_CTRL_CMD_RC_GET_ERROR_V2 = (0x20802213) # type: ignore
|
|
NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY = (0x20802207) # type: ignore
|
|
NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO = (0x20802209) # type: ignore
|
|
NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING = (0x00000002) # type: ignore
|
|
NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED = (0x00000004) # type: ignore
|
|
NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG = (0x2080220a) # type: ignore
|
|
NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG = (0x2080220b) # type: ignore
|
|
NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS = (0x2080220c) # type: ignore
|
|
NV2080_CTRL_CMD_SET_RC_RECOVERY = (0x2080220d) # type: ignore
|
|
NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID = (0xD) # type: ignore
|
|
NV2080_CTRL_CMD_GET_RC_RECOVERY = (0x2080220e) # type: ignore
|
|
NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID = (0xE) # type: ignore
|
|
NV2080_CTRL_CMD_RC_RECOVERY_DISABLED = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_RC_RECOVERY_ENABLED = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE = (0x2080220f) # type: ignore
|
|
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID = (0xF) # type: ignore
|
|
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN = (0x00000000) # type: ignore
|
|
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END = (0x00000001) # type: ignore
|
|
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS = (0x00000000) # type: ignore
|
|
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG = (0x20802210) # type: ignore
|
|
NV2080_CTRL_CMD_SET_RC_INFO = (0x20802211) # type: ignore
|
|
NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID = (0x11) # type: ignore
|
|
NV2080_CTRL_CMD_GET_RC_INFO = (0x20802212) # type: ignore
|
|
NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID = (0x12) # type: ignore
|
|
NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE = (0x00000000) # type: ignore
|
|
NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE = (0x00000001) # type: ignore
|
|
RM_GSP_SPDM_CMD_ID_CC_INIT = (0x1) # type: ignore
|
|
RM_GSP_SPDM_CMD_ID_CC_DEINIT = (0x2) # type: ignore
|
|
RM_GSP_SPDM_CMD_ID_CC_CTRL = (0x3) # type: ignore
|
|
RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA = (0x4) # type: ignore
|
|
RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL = (0x5) # type: ignore
|
|
RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST = (0x6) # type: ignore
|
|
RM_GSP_SPDM_CMD_ID_INVALID_COMMAND = (0xFF) # type: ignore
|
|
SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE = 0x2400 # type: ignore
|
|
RSVD7_SIZE = 16 # type: ignore
|
|
RSVD8_SIZE = 2 # type: ignore
|
|
CE_FIPS_SELF_TEST_DATA_SIZE = 16 # type: ignore
|
|
CE_FIPS_SELF_TEST_AUTH_TAG_SIZE = 16 # type: ignore
|
|
CE_FIPS_SELF_TEST_IV_SIZE = 12 # type: ignore
|
|
RM_GSP_SPDM_MSG_ID_CC_INIT = (0x1) # type: ignore
|
|
RM_GSP_SPDM_MSG_ID_CC_DEINIT = (0x2) # type: ignore
|
|
RM_GSP_SPDM_MSG_ID_CC_CTRL = (0x3) # type: ignore
|
|
RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA = (0x4) # type: ignore
|
|
RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL = (0x5) # type: ignore
|
|
RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST = (0x6) # type: ignore
|
|
RM_GSP_SPDM_MSG_ID_INVALID_COMMAND = (0xFF) # type: ignore
|
|
NV2080_CTRL_INTERNAL_SPDM_PARTITION = (0x20800ad9) # type: ignore
|
|
NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID = (0xD9) # type: ignore
|
|
NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT = (0x20800ada) # type: ignore
|
|
NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID = (0xDA) # type: ignore
|
|
NV2080_CTRL_CMD_TIMER_SCHEDULE = (0x20800401) # type: ignore
|
|
NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME = (0, 0) # type: ignore
|
|
NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS = (0x00000000) # type: ignore
|
|
NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_TIMER_CANCEL = (0x20800402) # type: ignore
|
|
NV2080_CTRL_CMD_TIMER_GET_TIME = (0x20800403) # type: ignore
|
|
NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET = (0x20800404) # type: ignore
|
|
NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO = (0x20800406) # type: ignore
|
|
NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES = 16 # type: ignore
|
|
NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE = (3, 0) # type: ignore
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME = (0x00000001) # type: ignore
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC = (0x00000002) # type: ignore
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API = (0x00000003) # type: ignore
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS = (0x00000004) # type: ignore
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR = (7, 4) # type: ignore
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU = (0x00000000) # type: ignore
|
|
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP = (0x00000001) # type: ignore
|
|
NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ = (0x20800407) # type: ignore
|
|
NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT = (0x20803d01) # type: ignore
|
|
NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC = (0x00000001) # type: ignore
|
|
NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC = (0x00000002) # type: ignore
|
|
NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF = (0x20803d02) # type: ignore
|
|
NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW = (0x00000001) # type: ignore
|
|
NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW = (0x00000002) # type: ignore
|
|
NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER = (0x20803d03) # type: ignore
|
|
NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS = (0x20803d04) # type: ignore
|
|
NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER = (0x20803d05) # type: ignore
|
|
NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER = (0x20803d06) # type: ignore
|
|
NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS = (0x20803d07) # type: ignore
|
|
NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS = (0x20803d08) # type: ignore
|
|
NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK = (0x20804001) # type: ignore
|
|
NV2080_CTRL_MAX_VMMU_SEGMENTS = 384 # type: ignore
|
|
NV2080_GPU_MAX_ENGINES = 0x54 # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK = (0x20804002) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE = (0x20804003) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU = (0x20804004) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO = (0x20804005) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE = (0x20804006) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY = (0x20804007) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP = (0x20804008) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN = 8 # type: ignore
|
|
NV2080_CTRL_MAX_GPC_COUNT = 32 # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING = (0x20804009) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT = (0x2080400a) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID = (0xA) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG = (0x2080400b) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID = (0xB) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES = (0x2080400c) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID = (0xC) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS = (0x2080400d) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID = (0xD) # type: ignore
|
|
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE = (0x2080400e) # type: ignore
|
|
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0xE) # type: ignore
|
|
NV83DE_CTRL_RESERVED = (0x00) # type: ignore
|
|
NV83DE_CTRL_GR = (0x01) # type: ignore
|
|
NV83DE_CTRL_FIFO = (0x02) # type: ignore
|
|
NV83DE_CTRL_DEBUG = (0x03) # type: ignore
|
|
NV83DE_CTRL_INTERNAL = (0x04) # type: ignore
|
|
NV83DE_CTRL_CMD_NULL = (0x83de0000) # type: ignore
|
|
NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE = (0x83de0301) # type: ignore
|
|
NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE = (0x83de0302) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG = (0x83de0307) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE = (0x00000001) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE = (0x00000002) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS = (0x00000003) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG = (0x83de0308) # type: ignore
|
|
NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID = (0x8) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_ENABLED = (0x00000001) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_DISABLED = (0x00000002) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK = (0x83de0309) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL = (0x00000001) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP = (0x00000002) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP = (0x00000004) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT = (0x00000008) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP = (0x00000010) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED = (0x00000020) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE = (0x00000000) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL = (0x0000FFFF) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE = (0x83de030b) # type: ignore
|
|
NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID = (0xB) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES = (0x83de030c) # type: ignore
|
|
NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL = 100 # type: ignore
|
|
NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID = (0xC) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE = (0x83de030f) # type: ignore
|
|
NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID = (0xF) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES = (0x83de0310) # type: ignore
|
|
NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID = (0x10) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS_DEFINED = 1 # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_HAS_RESIDENT_CHANNEL = 1 # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE = (0x83de0313) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID = (0x13) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM = (0x00000001) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCSAT = (0x00000002) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING = (0x83de0314) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID = (0x14) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING = (0x00000001) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING = (0x00000002) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_READ_MEMORY = (0x83de0315) # type: ignore
|
|
NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID = (0x15) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY = (0x83de0316) # type: ignore
|
|
NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID = (0x16) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT = (0x83de0317) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID = (0x17) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT = (0x83de0318) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_GET_HANDLES = (0x83de0319) # type: ignore
|
|
NV83DE_CTRL_CMD_READ_SURFACE = (0x83de031a) # type: ignore
|
|
NV83DE_CTRL_CMD_WRITE_SURFACE = (0x83de031b) # type: ignore
|
|
MAX_ACCESS_OPS = 64 # type: ignore
|
|
NV83DE_CTRL_CMD_GET_MAPPINGS = (0x83de031c) # type: ignore
|
|
MAX_GET_MAPPINGS_OPS = 64 # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS = (0x83de031d) # type: ignore
|
|
NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS = 100 # type: ignore
|
|
NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0x1D) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG = (0x83de031f) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID = (0x1F) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_DISABLE = (0x00000000) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_ENABLE = (0x00000001) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG = (0x83de0320) # type: ignore
|
|
NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID = (0x20) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_DISABLED = (0x00000000) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_ENABLED = (0x00000001) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP = (0x83de0321) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID = (0x21) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER = (0x83de0322) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID = (0x22) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER = (0x83de0323) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID = (0x23) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT = (0x83de0324) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID = (0x24) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS = (0x83de0325) # type: ignore
|
|
NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID = (0x25) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY = (0x83de0326) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY = (0x83de0327) # type: ignore
|
|
MAX_ACCESS_MEMORY_OPS = 150 # type: ignore
|
|
NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES = 4 # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO = (0x83de0328) # type: ignore
|
|
NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID = (0x28) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_DROP_DEFERRED_RC = (0x83de0329) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS_MESSAGE_ID = (0x29) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG = (0x83de032a) # type: ignore
|
|
NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID = (0x2A) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_ENABLE = (0x00000001) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_DISABLE = (0x00000002) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_GCC_DEBUG_REQUESTS = (0x00000003) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG = (0x83de032b) # type: ignore
|
|
NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID = (0x2B) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_ENABLED = (0x00000001) # type: ignore
|
|
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_DISABLED = (0x00000002) # type: ignore
|
|
NVB0CC_CTRL_RESERVED = (0x00) # type: ignore
|
|
NVB0CC_CTRL_PROFILER = (0x01) # type: ignore
|
|
NVB0CC_CTRL_INTERNAL = (0x02) # type: ignore
|
|
NVB0CC_CTRL_CMD_NULL = (0xb0cc0000) # type: ignore
|
|
NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM = (0xb0cc0204) # type: ignore
|
|
NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS_MESSAGE_ID = (0x0) # type: ignore
|
|
NVB0CC_CTRL_CMD_INTERNAL_QUIESCE_PMA_CHANNEL = (0xb0cc0201) # type: ignore
|
|
NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NVB0CC_CTRL_CMD_INTERNAL_SRIOV_PROMOTE_PMA_STREAM = (0xb0cc0202) # type: ignore
|
|
NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT = (0xb0cc0203) # type: ignore
|
|
NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID = (0x4) # type: ignore
|
|
NVB0CC_CTRL_CMD_INTERNAL_FREE_PMA_STREAM = (0xb0cc0206) # type: ignore
|
|
NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS = (0xb0cc0207) # type: ignore
|
|
NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS_MESSAGE_ID = (0x7) # type: ignore
|
|
NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES = (0xb0cc0208) # type: ignore
|
|
NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES = (0xb0cc0209) # type: ignore
|
|
NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY = (0xb0cc020a) # type: ignore
|
|
NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID = (0xa) # type: ignore
|
|
NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES = (0xb0cc0301) # type: ignore
|
|
NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG = (1, 0) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG = (3, 2) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG = (5, 4) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG = (7, 6) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN = (9, 8) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT = (11, 10) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_IGNORE = (0x00000000) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_DISABLE = (0x00000001) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_ENABLE = (0x00000002) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_IGNORE = NVB0CC_CTRL_POWER_FEATURE_IGNORE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_DISABLE = NVB0CC_CTRL_POWER_FEATURE_DISABLE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_ENABLE = NVB0CC_CTRL_POWER_FEATURE_ENABLE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_IGNORE = NVB0CC_CTRL_POWER_FEATURE_IGNORE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_DISABLE = NVB0CC_CTRL_POWER_FEATURE_DISABLE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_ENABLE = NVB0CC_CTRL_POWER_FEATURE_ENABLE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_IGNORE = NVB0CC_CTRL_POWER_FEATURE_IGNORE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_DISABLE = NVB0CC_CTRL_POWER_FEATURE_DISABLE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_ENABLE = NVB0CC_CTRL_POWER_FEATURE_ENABLE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_IGNORE = NVB0CC_CTRL_POWER_FEATURE_IGNORE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_DISABLE = NVB0CC_CTRL_POWER_FEATURE_DISABLE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_ENABLE = NVB0CC_CTRL_POWER_FEATURE_ENABLE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_IGNORE = NVB0CC_CTRL_POWER_FEATURE_IGNORE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_DISABLE = NVB0CC_CTRL_POWER_FEATURE_DISABLE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_ENABLE = NVB0CC_CTRL_POWER_FEATURE_ENABLE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_IGNORE = NVB0CC_CTRL_POWER_FEATURE_IGNORE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_DISABLE = NVB0CC_CTRL_POWER_FEATURE_DISABLE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_ENABLE = NVB0CC_CTRL_POWER_FEATURE_ENABLE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED = (0x00000000) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED = (0x00000001) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED = (0x00000002) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED = (0x00000003) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FULFILLED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_REJECTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_NOT_SUPPORTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_REQUEST_FAILED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FULFILLED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_REJECTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_NOT_SUPPORTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_REQUEST_FAILED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FULFILLED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_REJECTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_NOT_SUPPORTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_REQUEST_FAILED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FULFILLED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_REJECTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_NOT_SUPPORTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_REQUEST_FAILED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FULFILLED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_REJECTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_NOT_SUPPORTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_REQUEST_FAILED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FULFILLED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FULFILLED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_REJECTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_REJECTED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_NOT_SUPPORTED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_NOT_SUPPORTED # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_REQUEST_FAILED = NVB0CC_CTRL_POWER_FEATURE_REQUEST_FAILED # type: ignore
|
|
NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES = (0xb0cc0302) # type: ignore
|
|
NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS_MESSAGE_ID = (0x2) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_RELEASE = (0x00000003) # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELCG_RELEASE = NVB0CC_CTRL_POWER_FEATURE_RELEASE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_BLCG_RELEASE = NVB0CC_CTRL_POWER_FEATURE_RELEASE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_SLCG_RELEASE = NVB0CC_CTRL_POWER_FEATURE_RELEASE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_ELPG_RELEASE = NVB0CC_CTRL_POWER_FEATURE_RELEASE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_IDLE_SLOWDOWN_RELEASE = NVB0CC_CTRL_POWER_FEATURE_RELEASE # type: ignore
|
|
NVB0CC_CTRL_POWER_FEATURE_MASK_VAT_RELEASE = NVB0CC_CTRL_POWER_FEATURE_RELEASE # type: ignore
|
|
NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY = (0xb0cc0101) # type: ignore
|
|
NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_MESSAGE_ID = (0x1) # type: ignore
|
|
NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY = (0xb0cc0102) # type: ignore
|
|
NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC = (0xb0cc0103) # type: ignore
|
|
NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_MESSAGE_ID = (0x3) # type: ignore
|
|
NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC = (0xb0cc0104) # type: ignore
|
|
NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM = (0xb0cc0105) # type: ignore
|
|
NVB0CC_PMA_BUFFER_SIZE_MAX = (0xffe00000) # type: ignore
|
|
NVB0CC_PMA_BYTES_AVAILABLE_SIZE = (0x1000) # type: ignore
|
|
NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_MESSAGE_ID = (0x5) # type: ignore
|
|
NVB0CC_CTRL_CMD_FREE_PMA_STREAM = (0xb0cc0106) # type: ignore
|
|
NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_MESSAGE_ID = (0x6) # type: ignore
|
|
NVB0CC_CTRL_CMD_BIND_PM_RESOURCES = (0xb0cc0107) # type: ignore
|
|
NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES = (0xb0cc0108) # type: ignore
|
|
NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT = (0xb0cc0109) # type: ignore
|
|
NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE = 0xFFFFFFFF # type: ignore
|
|
NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_MESSAGE_ID = (0x9) # type: ignore
|
|
NVB0CC_REGOPS_MAX_COUNT = (124) # type: ignore
|
|
NVB0CC_CTRL_CMD_EXEC_REG_OPS = (0xb0cc010a) # type: ignore
|
|
NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0xA) # type: ignore
|
|
NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER = (0xb0cc010b) # type: ignore
|
|
NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER = (0xb0cc010c) # type: ignore
|
|
NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS = (0xb0cc010d) # type: ignore
|
|
NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_MESSAGE_ID = (0xD) # type: ignore
|
|
NVB0CC_CTRL_CMD_SET_HS_CREDITS = (0xb0cc010e) # type: ignore
|
|
NVB0CC_MAX_CREDIT_INFO_ENTRIES = (63) # type: ignore
|
|
NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID = (0xE) # type: ignore
|
|
NVB0CC_CTRL_CMD_GET_HS_CREDITS = (0xb0cc010f) # type: ignore
|
|
NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_MESSAGE_ID = (0xF) # type: ignore
|
|
NVB0CC_CTRL_CMD_RESERVE_HES = (0xb0cc0113) # type: ignore
|
|
NVB0CC_CTRL_RESERVE_HES_PARAMS_MESSAGE_ID = (0x13) # type: ignore
|
|
NVB0CC_CTRL_CMD_RELEASE_HES = (0xb0cc0114) # type: ignore
|
|
NVB0CC_CTRL_RELEASE_HES_PARAMS_MESSAGE_ID = (0x14) # type: ignore
|
|
NVB0CC_CREDIT_POOL_MAX_COUNT = 30 # type: ignore
|
|
NVB0CC_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL = (0xb0cc0115) # type: ignore
|
|
NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL_MESSAGE_ID = (0x15) # type: ignore
|
|
NVB0CC_CTRL_CMD_GET_HS_CREDITS_MAPPING = (0xb0cc0116) # type: ignore
|
|
NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS_MESSAGE_ID = (0x16) # type: ignore
|
|
NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST = (0xb0cc0117) # type: ignore
|
|
NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID = (0x17) # type: ignore
|
|
NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS = (0xb0cc0118) # type: ignore
|
|
NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID = (0x18) # type: ignore
|
|
NVB0CC_CTRL_CMD_RESERVE_CCU_PROF = (0xb0cc0119) # type: ignore
|
|
NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_MESSAGE_ID = (0x19) # type: ignore
|
|
NVB0CC_CTRL_CMD_RELEASE_CCU_PROF = (0xb0cc011a) # type: ignore
|
|
NV_STATUS_LEVEL_OK = 0 # type: ignore
|
|
NV_STATUS_LEVEL_WARN = 1 # type: ignore
|
|
NV_STATUS_LEVEL_ERR = 3 # type: ignore
|
|
NV01_ROOT = (0x00000000) # type: ignore
|
|
NV1_ROOT = (0x00000000) # type: ignore
|
|
NV01_NULL_OBJECT = (0x00000000) # type: ignore
|
|
NV1_NULL_OBJECT = (0x00000000) # type: ignore
|
|
NV01_ROOT_NON_PRIV = (0x00000001) # type: ignore
|
|
NV1_ROOT_NON_PRIV = (0x00000001) # type: ignore
|
|
NV01_ROOT_CLIENT = (0x00000041) # type: ignore
|
|
FABRIC_MANAGER_SESSION = (0x0000000f) # type: ignore
|
|
NV0020_GPU_MANAGEMENT = (0x00000020) # type: ignore
|
|
NV01_DEVICE_0 = (0x00000080) # type: ignore
|
|
NV20_SUBDEVICE_0 = (0x00002080) # type: ignore
|
|
NV2081_BINAPI = (0x00002081) # type: ignore
|
|
NV2082_BINAPI_PRIVILEGED = (0x00002082) # type: ignore
|
|
NV20_SUBDEVICE_DIAG = (0x0000208f) # type: ignore
|
|
NV01_CONTEXT_DMA = (0x00000002) # type: ignore
|
|
NV01_MEMORY_SYSTEM = (0x0000003e) # type: ignore
|
|
NV1_MEMORY_SYSTEM = (0x0000003e) # type: ignore
|
|
NV01_MEMORY_LOCAL_PRIVILEGED = (0x0000003f) # type: ignore
|
|
NV1_MEMORY_LOCAL_PRIVILEGED = (0x0000003f) # type: ignore
|
|
NV01_MEMORY_PRIVILEGED = (0x0000003f) # type: ignore
|
|
NV1_MEMORY_PRIVILEGED = (0x0000003f) # type: ignore
|
|
NV01_MEMORY_LOCAL_USER = (0x00000040) # type: ignore
|
|
NV1_MEMORY_LOCAL_USER = (0x00000040) # type: ignore
|
|
NV01_MEMORY_USER = (0x00000040) # type: ignore
|
|
NV1_MEMORY_USER = (0x00000040) # type: ignore
|
|
NV_MEMORY_EXTENDED_USER = (0x00000042) # type: ignore
|
|
NV01_MEMORY_VIRTUAL = (0x00000070) # type: ignore
|
|
NV01_MEMORY_SYSTEM_DYNAMIC = (0x00000070) # type: ignore
|
|
NV1_MEMORY_SYSTEM_DYNAMIC = (0x00000070) # type: ignore
|
|
NV_MEMORY_MAPPER = (0x000000fe) # type: ignore
|
|
NV01_MEMORY_LOCAL_PHYSICAL = (0x000000c2) # type: ignore
|
|
NV01_MEMORY_SYNCPOINT = (0x000000c3) # type: ignore
|
|
NV01_MEMORY_SYSTEM_OS_DESCRIPTOR = (0x00000071) # type: ignore
|
|
NV01_MEMORY_DEVICELESS = (0x000090ce) # type: ignore
|
|
NV01_MEMORY_FRAMEBUFFER_CONSOLE = (0x00000076) # type: ignore
|
|
NV01_MEMORY_HW_RESOURCES = (0x000000b1) # type: ignore
|
|
NV01_MEMORY_LIST_SYSTEM = (0x00000081) # type: ignore
|
|
NV01_MEMORY_LIST_FBMEM = (0x00000082) # type: ignore
|
|
NV01_MEMORY_LIST_OBJECT = (0x00000083) # type: ignore
|
|
NV_IMEX_SESSION = (0x000000f1) # type: ignore
|
|
NV01_MEMORY_FLA = (0x000000f3) # type: ignore
|
|
NV_MEMORY_EXPORT = (0x000000e0) # type: ignore
|
|
NV_CE_UTILS = (0x00000050) # type: ignore
|
|
NV_MEMORY_FABRIC = (0x000000f8) # type: ignore
|
|
NV_MEMORY_FABRIC_IMPORT_V2 = (0x000000f9) # type: ignore
|
|
NV_MEMORY_FABRIC_IMPORTED_REF = (0x000000fb) # type: ignore
|
|
FABRIC_VASPACE_A = (0x000000fc) # type: ignore
|
|
NV_MEMORY_MULTICAST_FABRIC = (0x000000fd) # type: ignore
|
|
IO_VASPACE_A = (0x000000f2) # type: ignore
|
|
NV01_NULL = (0x00000030) # type: ignore
|
|
NV1_NULL = (0x00000030) # type: ignore
|
|
NV01_EVENT = (0x00000005) # type: ignore
|
|
NV1_EVENT = (0x00000005) # type: ignore
|
|
NV01_EVENT_KERNEL_CALLBACK = (0x00000078) # type: ignore
|
|
NV1_EVENT_KERNEL_CALLBACK = (0x00000078) # type: ignore
|
|
NV01_EVENT_OS_EVENT = (0x00000079) # type: ignore
|
|
NV1_EVENT_OS_EVENT = (0x00000079) # type: ignore
|
|
NV01_EVENT_WIN32_EVENT = (0x00000079) # type: ignore
|
|
NV1_EVENT_WIN32_EVENT = (0x00000079) # type: ignore
|
|
NV01_EVENT_KERNEL_CALLBACK_EX = (0x0000007e) # type: ignore
|
|
NV1_EVENT_KERNEL_CALLBACK_EX = (0x0000007e) # type: ignore
|
|
NV01_TIMER = (0x00000004) # type: ignore
|
|
NV1_TIMER = (0x00000004) # type: ignore
|
|
KERNEL_GRAPHICS_CONTEXT = (0x00000090) # type: ignore
|
|
LOCK_STRESS_OBJECT = (0x00000100) # type: ignore
|
|
NV50_CHANNEL_GPFIFO = (0x0000506f) # type: ignore
|
|
GF100_CHANNEL_GPFIFO = (0x0000906f) # type: ignore
|
|
KEPLER_CHANNEL_GPFIFO_A = (0x0000a06f) # type: ignore
|
|
UVM_CHANNEL_RETAINER = (0x0000c574) # type: ignore
|
|
KEPLER_CHANNEL_GPFIFO_B = (0x0000a16f) # type: ignore
|
|
MAXWELL_CHANNEL_GPFIFO_A = (0x0000b06f) # type: ignore
|
|
PASCAL_CHANNEL_GPFIFO_A = (0x0000c06f) # type: ignore
|
|
VOLTA_CHANNEL_GPFIFO_A = (0x0000c36f) # type: ignore
|
|
TURING_CHANNEL_GPFIFO_A = (0x0000c46f) # type: ignore
|
|
AMPERE_CHANNEL_GPFIFO_A = (0x0000c56f) # type: ignore
|
|
HOPPER_CHANNEL_GPFIFO_A = (0x0000c86f) # type: ignore
|
|
BLACKWELL_CHANNEL_GPFIFO_A = (0x0000c96f) # type: ignore
|
|
BLACKWELL_CHANNEL_GPFIFO_B = (0x0000ca6f) # type: ignore
|
|
NV04_SOFTWARE_TEST = (0x0000007d) # type: ignore
|
|
NV4_SOFTWARE_TEST = (0x0000007d) # type: ignore
|
|
NV30_GSYNC = (0x000030f1) # type: ignore
|
|
VOLTA_USERMODE_A = (0x0000c361) # type: ignore
|
|
TURING_USERMODE_A = (0x0000c461) # type: ignore
|
|
AMPERE_USERMODE_A = (0x0000c561) # type: ignore
|
|
HOPPER_USERMODE_A = (0x0000c661) # type: ignore
|
|
BLACKWELL_USERMODE_A = (0x0000c761) # type: ignore
|
|
NVC371_DISP_SF_USER = (0x0000c371) # type: ignore
|
|
NVC372_DISPLAY_SW = (0x0000c372) # type: ignore
|
|
NVC573_DISP_CAPABILITIES = (0x0000c573) # type: ignore
|
|
NVC673_DISP_CAPABILITIES = (0x0000c673) # type: ignore
|
|
NVC773_DISP_CAPABILITIES = (0x0000c773) # type: ignore
|
|
NVC973_DISP_CAPABILITIES = (0x0000c973) # type: ignore
|
|
NVCA73_DISP_CAPABILITIES = (0x0000ca73) # type: ignore
|
|
NV04_DISPLAY_COMMON = (0x00000073) # type: ignore
|
|
NV50_DEFERRED_API_CLASS = (0x00005080) # type: ignore
|
|
MPS_COMPUTE = (0x0000900e) # type: ignore
|
|
NVC570_DISPLAY = (0x0000c570) # type: ignore
|
|
NVC57A_CURSOR_IMM_CHANNEL_PIO = (0x0000c57a) # type: ignore
|
|
NVC57B_WINDOW_IMM_CHANNEL_DMA = (0x0000c57b) # type: ignore
|
|
NVC57D_CORE_CHANNEL_DMA = (0x0000c57d) # type: ignore
|
|
NVC57E_WINDOW_CHANNEL_DMA = (0x0000c57e) # type: ignore
|
|
NVC670_DISPLAY = (0x0000c670) # type: ignore
|
|
NVC671_DISP_SF_USER = (0x0000c671) # type: ignore
|
|
NVC67A_CURSOR_IMM_CHANNEL_PIO = (0x0000c67a) # type: ignore
|
|
NVC67B_WINDOW_IMM_CHANNEL_DMA = (0x0000c67b) # type: ignore
|
|
NVC67D_CORE_CHANNEL_DMA = (0x0000c67d) # type: ignore
|
|
NVC67E_WINDOW_CHANNEL_DMA = (0x0000c67e) # type: ignore
|
|
NVC77F_ANY_CHANNEL_DMA = (0x0000c77f) # type: ignore
|
|
NVC770_DISPLAY = (0x0000c770) # type: ignore
|
|
NVC771_DISP_SF_USER = (0x0000c771) # type: ignore
|
|
NVC77D_CORE_CHANNEL_DMA = (0x0000c77d) # type: ignore
|
|
NVC970_DISPLAY = (0x0000c970) # type: ignore
|
|
NVC971_DISP_SF_USER = (0x0000c971) # type: ignore
|
|
NVC97A_CURSOR_IMM_CHANNEL_PIO = (0x0000c97a) # type: ignore
|
|
NVC97B_WINDOW_IMM_CHANNEL_DMA = (0x0000c97b) # type: ignore
|
|
NVC97D_CORE_CHANNEL_DMA = (0x0000c97d) # type: ignore
|
|
NVC97E_WINDOW_CHANNEL_DMA = (0x0000c97e) # type: ignore
|
|
NVCA70_DISPLAY = (0x0000ca70) # type: ignore
|
|
NVCA71_DISP_SF_USER = (0x0000ca71) # type: ignore
|
|
NVCA7A_CURSOR_IMM_CHANNEL_PIO = (0x0000ca7a) # type: ignore
|
|
NVCA7B_WINDOW_IMM_CHANNEL_DMA = (0x0000ca7b) # type: ignore
|
|
NVCA7D_CORE_CHANNEL_DMA = (0x0000ca7d) # type: ignore
|
|
NVCA7E_WINDOW_CHANNEL_DMA = (0x0000ca7e) # type: ignore
|
|
NV9010_VBLANK_CALLBACK = (0x00009010) # type: ignore
|
|
GF100_PROFILER = (0x000090cc) # type: ignore
|
|
MAXWELL_PROFILER = (0x0000b0cc) # type: ignore
|
|
MAXWELL_PROFILER_CONTEXT = (0x0000b1cc) # type: ignore
|
|
MAXWELL_PROFILER_DEVICE = (0x0000b2cc) # type: ignore
|
|
GF100_SUBDEVICE_MASTER = (0x000090e6) # type: ignore
|
|
GF100_SUBDEVICE_INFOROM = (0x000090e7) # type: ignore
|
|
GF100_ZBC_CLEAR = (0x00009096) # type: ignore
|
|
GF100_DISP_SW = (0x00009072) # type: ignore
|
|
GF100_TIMED_SEMAPHORE_SW = (0x00009074) # type: ignore
|
|
G84_PERFBUFFER = (0x0000844c) # type: ignore
|
|
NV50_MEMORY_VIRTUAL = (0x000050a0) # type: ignore
|
|
NV50_P2P = (0x0000503b) # type: ignore
|
|
NV50_THIRD_PARTY_P2P = (0x0000503c) # type: ignore
|
|
FERMI_TWOD_A = (0x0000902d) # type: ignore
|
|
FERMI_VASPACE_A = (0x000090f1) # type: ignore
|
|
HOPPER_SEC2_WORK_LAUNCH_A = (0x0000cba2) # type: ignore
|
|
GF100_HDACODEC = (0x000090ec) # type: ignore
|
|
NVB8B0_VIDEO_DECODER = (0x0000b8b0) # type: ignore
|
|
NVC4B0_VIDEO_DECODER = (0x0000c4b0) # type: ignore
|
|
NVC6B0_VIDEO_DECODER = (0x0000c6b0) # type: ignore
|
|
NVC7B0_VIDEO_DECODER = (0x0000c7b0) # type: ignore
|
|
NVC9B0_VIDEO_DECODER = (0x0000c9b0) # type: ignore
|
|
NVCDB0_VIDEO_DECODER = (0x0000cdb0) # type: ignore
|
|
NVCFB0_VIDEO_DECODER = (0x0000cfb0) # type: ignore
|
|
NVC4B7_VIDEO_ENCODER = (0x0000c4b7) # type: ignore
|
|
NVB4B7_VIDEO_ENCODER = (0x0000b4b7) # type: ignore
|
|
NVC7B7_VIDEO_ENCODER = (0x0000c7b7) # type: ignore
|
|
NVC9B7_VIDEO_ENCODER = (0x0000c9b7) # type: ignore
|
|
NVCFB7_VIDEO_ENCODER = (0x0000cfb7) # type: ignore
|
|
NVB8D1_VIDEO_NVJPG = (0x0000b8d1) # type: ignore
|
|
NVC4D1_VIDEO_NVJPG = (0x0000c4d1) # type: ignore
|
|
NVC9D1_VIDEO_NVJPG = (0x0000c9d1) # type: ignore
|
|
NVCDD1_VIDEO_NVJPG = (0x0000cdd1) # type: ignore
|
|
NVCFD1_VIDEO_NVJPG = (0x0000cfd1) # type: ignore
|
|
NVB8FA_VIDEO_OFA = (0x0000b8fa) # type: ignore
|
|
NVC6FA_VIDEO_OFA = (0x0000c6fa) # type: ignore
|
|
NVC7FA_VIDEO_OFA = (0x0000c7fa) # type: ignore
|
|
NVC9FA_VIDEO_OFA = (0x0000c9fa) # type: ignore
|
|
NVCDFA_VIDEO_OFA = (0x0000cdfa) # type: ignore
|
|
NVCFFA_VIDEO_OFA = (0x0000cffa) # type: ignore
|
|
KEPLER_INLINE_TO_MEMORY_B = (0x0000a140) # type: ignore
|
|
FERMI_CONTEXT_SHARE_A = (0x00009067) # type: ignore
|
|
KEPLER_CHANNEL_GROUP_A = (0x0000a06c) # type: ignore
|
|
PASCAL_DMA_COPY_A = (0x0000c0b5) # type: ignore
|
|
TURING_DMA_COPY_A = (0x0000c5b5) # type: ignore
|
|
AMPERE_DMA_COPY_A = (0x0000c6b5) # type: ignore
|
|
AMPERE_DMA_COPY_B = (0x0000c7b5) # type: ignore
|
|
HOPPER_DMA_COPY_A = (0x0000c8b5) # type: ignore
|
|
BLACKWELL_DMA_COPY_A = (0x0000c9b5) # type: ignore
|
|
BLACKWELL_DMA_COPY_B = (0x0000cab5) # type: ignore
|
|
MAXWELL_DMA_COPY_A = (0x0000b0b5) # type: ignore
|
|
ACCESS_COUNTER_NOTIFY_BUFFER = (0x0000c365) # type: ignore
|
|
MMU_FAULT_BUFFER = (0x0000c369) # type: ignore
|
|
MMU_VIDMEM_ACCESS_BIT_BUFFER = (0x0000c763) # type: ignore
|
|
TURING_A = (0x0000c597) # type: ignore
|
|
TURING_COMPUTE_A = (0x0000c5c0) # type: ignore
|
|
AMPERE_A = (0x0000c697) # type: ignore
|
|
AMPERE_COMPUTE_A = (0x0000c6c0) # type: ignore
|
|
AMPERE_B = (0x0000c797) # type: ignore
|
|
AMPERE_COMPUTE_B = (0x0000c7c0) # type: ignore
|
|
ADA_A = (0x0000c997) # type: ignore
|
|
ADA_COMPUTE_A = (0x0000c9c0) # type: ignore
|
|
AMPERE_SMC_PARTITION_REF = (0x0000c637) # type: ignore
|
|
AMPERE_SMC_EXEC_PARTITION_REF = (0x0000c638) # type: ignore
|
|
AMPERE_SMC_CONFIG_SESSION = (0x0000c639) # type: ignore
|
|
NV0092_RG_LINE_CALLBACK = (0x00000092) # type: ignore
|
|
AMPERE_SMC_MONITOR_SESSION = (0x0000c640) # type: ignore
|
|
HOPPER_A = (0x0000cb97) # type: ignore
|
|
HOPPER_COMPUTE_A = (0x0000cbc0) # type: ignore
|
|
BLACKWELL_A = (0x0000cd97) # type: ignore
|
|
BLACKWELL_COMPUTE_A = (0x0000cdc0) # type: ignore
|
|
BLACKWELL_B = (0x0000ce97) # type: ignore
|
|
BLACKWELL_COMPUTE_B = (0x0000cec0) # type: ignore
|
|
BLACKWELL_INLINE_TO_MEMORY_A = (0x0000cd40) # type: ignore
|
|
NV40_DEBUG_BUFFER = (0x000000db) # type: ignore
|
|
RM_USER_SHARED_DATA = (0x000000de) # type: ignore
|
|
GT200_DEBUGGER = (0x000083de) # type: ignore
|
|
NV40_I2C = (0x0000402c) # type: ignore
|
|
KEPLER_DEVICE_VGPU = (0x0000a080) # type: ignore
|
|
NVA081_VGPU_CONFIG = (0x0000a081) # type: ignore
|
|
NVA084_KERNEL_HOST_VGPU_DEVICE = (0x0000a084) # type: ignore
|
|
NV0060_SYNC_GPU_BOOST = (0x00000060) # type: ignore
|
|
GP100_UVM_SW = (0x0000c076) # type: ignore
|
|
NVENC_SW_SESSION = (0x0000a0bc) # type: ignore
|
|
NV_EVENT_BUFFER = (0x000090cd) # type: ignore
|
|
NVFBC_SW_SESSION = (0x0000a0bd) # type: ignore
|
|
NV_CONFIDENTIAL_COMPUTE = (0x0000cb33) # type: ignore
|
|
NV_COUNTER_COLLECTION_UNIT = (0x0000cbca) # type: ignore
|
|
NV_SEMAPHORE_SURFACE = (0x000000da) # type: ignore |